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[binutils.git] / sim / m32r / cpu2.h
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16b47b25
NC		 1/* CPU family header for m32r2f.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
ecd75fc8 5Copyright 1996-2014 Free Software Foundation, Inc.
16b47b25
NC		 6
7This file is part of the GNU simulators.
8
e9c60591
DE		 9 This file is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
16b47b25 13
e9c60591
DE		 14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
16b47b25 18
e9c60591 19 You should have received a copy of the GNU General Public License along
51b318de 20 with this program; if not, see <http://www.gnu.org/licenses/>.
16b47b25
NC		 21
22*/
23
24#ifndef CPU_M32R2F_H
25#define CPU_M32R2F_H
26
27/* Maximum number of instructions that are fetched at a time.
28 This is for LIW type instructions sets (e.g. m32r). */
29#define MAX_LIW_INSNS 2
30
31/* Maximum number of instructions that can be executed in parallel. */
32#define MAX_PARALLEL_INSNS 2
33
197fa1aa
DE		 34/* The size of an "int" needed to hold an instruction word.
35 This is usually 32 bits, but some architectures needs 64 bits. */
36typedef CGEN_INSN_INT CGEN_INSN_WORD;
37
38#include "cgen-engine.h"
39
16b47b25
NC		 40/* CPU state information. */
41typedef struct {
42 /* Hardware elements. */
43 struct {
44 /* program counter */
45 USI h_pc;
46#define GET_H_PC() CPU (h_pc)
47#define SET_H_PC(x) (CPU (h_pc) = (x))
48 /* general registers */
49 SI h_gr[16];
50#define GET_H_GR(a1) CPU (h_gr)[a1]
51#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
52 /* control registers */
53 USI h_cr[16];
54#define GET_H_CR(index) m32r2f_h_cr_get_handler (current_cpu, index)
55#define SET_H_CR(index, x) \
56do { \
57m32r2f_h_cr_set_handler (current_cpu, (index), (x));\
58;} while (0)
59 /* accumulator */
60 DI h_accum;
61#define GET_H_ACCUM() m32r2f_h_accum_get_handler (current_cpu)
62#define SET_H_ACCUM(x) \
63do { \
64m32r2f_h_accum_set_handler (current_cpu, (x));\
65;} while (0)
66 /* accumulators */
67 DI h_accums[2];
68#define GET_H_ACCUMS(index) m32r2f_h_accums_get_handler (current_cpu, index)
69#define SET_H_ACCUMS(index, x) \
70do { \
71m32r2f_h_accums_set_handler (current_cpu, (index), (x));\
72;} while (0)
73 /* condition bit */
74 BI h_cond;
75#define GET_H_COND() CPU (h_cond)
76#define SET_H_COND(x) (CPU (h_cond) = (x))
77 /* psw part of psw */
78 UQI h_psw;
79#define GET_H_PSW() m32r2f_h_psw_get_handler (current_cpu)
80#define SET_H_PSW(x) \
81do { \
82m32r2f_h_psw_set_handler (current_cpu, (x));\
83;} while (0)
84 /* backup psw */
85 UQI h_bpsw;
86#define GET_H_BPSW() CPU (h_bpsw)
87#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
88 /* backup bpsw */
89 UQI h_bbpsw;
90#define GET_H_BBPSW() CPU (h_bbpsw)
91#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
92 /* lock */
93 BI h_lock;
94#define GET_H_LOCK() CPU (h_lock)
95#define SET_H_LOCK(x) (CPU (h_lock) = (x))
96 } hardware;
97#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
98} M32R2F_CPU_DATA;
99
100/* Cover fns for register access. */
101USI m32r2f_h_pc_get (SIM_CPU *);
102void m32r2f_h_pc_set (SIM_CPU *, USI);
103SI m32r2f_h_gr_get (SIM_CPU *, UINT);
104void m32r2f_h_gr_set (SIM_CPU *, UINT, SI);
105USI m32r2f_h_cr_get (SIM_CPU *, UINT);
106void m32r2f_h_cr_set (SIM_CPU *, UINT, USI);
107DI m32r2f_h_accum_get (SIM_CPU *);
108void m32r2f_h_accum_set (SIM_CPU *, DI);
109DI m32r2f_h_accums_get (SIM_CPU *, UINT);
110void m32r2f_h_accums_set (SIM_CPU *, UINT, DI);
111BI m32r2f_h_cond_get (SIM_CPU *);
112void m32r2f_h_cond_set (SIM_CPU *, BI);
113UQI m32r2f_h_psw_get (SIM_CPU *);
114void m32r2f_h_psw_set (SIM_CPU *, UQI);
115UQI m32r2f_h_bpsw_get (SIM_CPU *);
116void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
117UQI m32r2f_h_bbpsw_get (SIM_CPU *);
118void m32r2f_h_bbpsw_set (SIM_CPU *, UQI);
119BI m32r2f_h_lock_get (SIM_CPU *);
120void m32r2f_h_lock_set (SIM_CPU *, BI);
121
122/* These must be hand-written. */
123extern CPUREG_FETCH_FN m32r2f_fetch_register;
124extern CPUREG_STORE_FN m32r2f_store_register;
125
126typedef struct {
127 int empty;
128} MODEL_M32R2_DATA;
129
130/* Instruction argument buffer. */
131
132union sem_fields {
133 struct { /* no operands */
134 int empty;
2310652a 135 } sfmt_empty;
16b47b25
NC		 136 struct { /* */
137 UINT f_uimm8;
138 } sfmt_clrpsw;
139 struct { /* */
140 UINT f_uimm4;
141 } sfmt_trap;
142 struct { /* */
143 IADDR i_disp24;
144 unsigned char out_h_gr_SI_14;
145 } sfmt_bl24;
146 struct { /* */
147 IADDR i_disp8;
148 unsigned char out_h_gr_SI_14;
149 } sfmt_bl8;
150 struct { /* */
151 SI f_imm1;
152 UINT f_accd;
153 UINT f_accs;
154 } sfmt_rac_dsi;
155 struct { /* */
156 SI* i_dr;
157 UINT f_hi16;
158 UINT f_r1;
159 unsigned char out_dr;
160 } sfmt_seth;
161 struct { /* */
162 SI* i_src1;
163 UINT f_accs;
164 UINT f_r1;
165 unsigned char in_src1;
166 } sfmt_mvtachi_a;
167 struct { /* */
168 SI* i_dr;
169 UINT f_accs;
170 UINT f_r1;
171 unsigned char out_dr;
172 } sfmt_mvfachi_a;
173 struct { /* */
174 ADDR i_uimm24;
175 SI* i_dr;
176 UINT f_r1;
177 unsigned char out_dr;
178 } sfmt_ld24;
179 struct { /* */
180 SI* i_sr;
181 UINT f_r2;
182 unsigned char in_sr;
183 unsigned char out_h_gr_SI_14;
184 } sfmt_jl;
185 struct { /* */
186 SI* i_sr;
187 INT f_simm16;
188 UINT f_r2;
189 UINT f_uimm3;
190 unsigned char in_sr;
191 } sfmt_bset;
192 struct { /* */
193 SI* i_dr;
194 UINT f_r1;
195 UINT f_uimm5;
196 unsigned char in_dr;
197 unsigned char out_dr;
198 } sfmt_slli;
199 struct { /* */
200 SI* i_dr;
201 INT f_simm8;
202 UINT f_r1;
203 unsigned char in_dr;
204 unsigned char out_dr;
205 } sfmt_addi;
206 struct { /* */
207 SI* i_src1;
208 SI* i_src2;
209 UINT f_r1;
210 UINT f_r2;
211 unsigned char in_src1;
212 unsigned char in_src2;
213 unsigned char out_src2;
214 } sfmt_st_plus;
215 struct { /* */
216 SI* i_src1;
217 SI* i_src2;
218 INT f_simm16;
219 UINT f_r1;
220 UINT f_r2;
221 unsigned char in_src1;
222 unsigned char in_src2;
223 } sfmt_st_d;
224 struct { /* */
225 SI* i_src1;
226 SI* i_src2;
227 UINT f_acc;
228 UINT f_r1;
229 UINT f_r2;
230 unsigned char in_src1;
231 unsigned char in_src2;
232 } sfmt_machi_a;
233 struct { /* */
234 SI* i_dr;
235 SI* i_sr;
236 UINT f_r1;
237 UINT f_r2;
238 unsigned char in_sr;
239 unsigned char out_dr;
240 unsigned char out_sr;
241 } sfmt_ld_plus;
242 struct { /* */
243 IADDR i_disp16;
244 SI* i_src1;
245 SI* i_src2;
246 UINT f_r1;
247 UINT f_r2;
248 unsigned char in_src1;
249 unsigned char in_src2;
250 } sfmt_beq;
251 struct { /* */
252 SI* i_dr;
253 SI* i_sr;
254 UINT f_r1;
255 UINT f_r2;
256 UINT f_uimm16;
257 unsigned char in_sr;
258 unsigned char out_dr;
259 } sfmt_and3;
260 struct { /* */
261 SI* i_dr;
262 SI* i_sr;
263 INT f_simm16;
264 UINT f_r1;
265 UINT f_r2;
266 unsigned char in_sr;
267 unsigned char out_dr;
268 } sfmt_add3;
269 struct { /* */
270 SI* i_dr;
271 SI* i_sr;
272 UINT f_r1;
273 UINT f_r2;
274 unsigned char in_dr;
275 unsigned char in_sr;
276 unsigned char out_dr;
277 } sfmt_add;
278#if WITH_SCACHE_PBB
279 /* Writeback handler. */
280 struct {
281 /* Pointer to argbuf entry for insn whose results need writing back. */
282 const struct argbuf *abuf;
283 } write;
284 /* x-before handler */
285 struct {
286 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
287 int first_p;
288 } before;
289 /* x-after handler */
290 struct {
291 int empty;
292 } after;
293 /* This entry is used to terminate each pbb. */
294 struct {
295 /* Number of insns in pbb. */
296 int insn_count;
297 /* Next pbb to execute. */
298 SCACHE *next;
299 SCACHE *branch_target;
300 } chain;
301#endif
302};
303
304/* The ARGBUF struct. */
305struct argbuf {
306 /* These are the baseclass definitions. */
307 IADDR addr;
308 const IDESC *idesc;
309 char trace_p;
310 char profile_p;
311 /* ??? Temporary hack for skip insns. */
312 char skip_count;
313 char unused;
314 /* cpu specific data follows */
315 union sem semantic;
316 int written;
317 union sem_fields fields;
318};
319
320/* A cached insn.
321
322 ??? SCACHE used to contain more than just argbuf. We could delete the
323 type entirely and always just use ARGBUF, but for future concerns and as
324 a level of abstraction it is left in. */
325
326struct scache {
327 struct argbuf argbuf;
328};
329
330/* Macros to simplify extraction, reading and semantic code.
331 These define and assign the local vars that contain the insn's fields. */
332
333#define EXTRACT_IFMT_EMPTY_VARS \
334 unsigned int length;
335#define EXTRACT_IFMT_EMPTY_CODE \
336 length = 0; \
337
338#define EXTRACT_IFMT_ADD_VARS \
339 UINT f_op1; \
340 UINT f_r1; \
341 UINT f_op2; \
342 UINT f_r2; \
343 unsigned int length;
344#define EXTRACT_IFMT_ADD_CODE \
345 length = 2; \
346 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
347 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
348 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
349 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
350
351#define EXTRACT_IFMT_ADD3_VARS \
352 UINT f_op1; \
353 UINT f_r1; \
354 UINT f_op2; \
355 UINT f_r2; \
356 INT f_simm16; \
357 unsigned int length;
358#define EXTRACT_IFMT_ADD3_CODE \
359 length = 4; \
360 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
361 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
362 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
363 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 364 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
16b47b25
NC		 365
366#define EXTRACT_IFMT_AND3_VARS \
367 UINT f_op1; \
368 UINT f_r1; \
369 UINT f_op2; \
370 UINT f_r2; \
371 UINT f_uimm16; \
372 unsigned int length;
373#define EXTRACT_IFMT_AND3_CODE \
374 length = 4; \
375 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
376 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
377 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
378 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
379 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
380
381#define EXTRACT_IFMT_OR3_VARS \
382 UINT f_op1; \
383 UINT f_r1; \
384 UINT f_op2; \
385 UINT f_r2; \
386 UINT f_uimm16; \
387 unsigned int length;
388#define EXTRACT_IFMT_OR3_CODE \
389 length = 4; \
390 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
391 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
392 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
393 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
394 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
395
396#define EXTRACT_IFMT_ADDI_VARS \
397 UINT f_op1; \
398 UINT f_r1; \
399 INT f_simm8; \
400 unsigned int length;
401#define EXTRACT_IFMT_ADDI_CODE \
402 length = 2; \
403 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
404 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
62836bf4 405 f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
16b47b25
NC		 406
407#define EXTRACT_IFMT_ADDV3_VARS \
408 UINT f_op1; \
409 UINT f_r1; \
410 UINT f_op2; \
411 UINT f_r2; \
412 INT f_simm16; \
413 unsigned int length;
414#define EXTRACT_IFMT_ADDV3_CODE \
415 length = 4; \
416 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
417 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
418 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
419 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 420 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
16b47b25
NC		 421
422#define EXTRACT_IFMT_BC8_VARS \
423 UINT f_op1; \
424 UINT f_r1; \
425 SI f_disp8; \
426 unsigned int length;
427#define EXTRACT_IFMT_BC8_CODE \
428 length = 2; \
429 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
430 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
62836bf4 431 f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
16b47b25
NC		 432
433#define EXTRACT_IFMT_BC24_VARS \
434 UINT f_op1; \
435 UINT f_r1; \
436 SI f_disp24; \
437 unsigned int length;
438#define EXTRACT_IFMT_BC24_CODE \
439 length = 4; \
440 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
441 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
62836bf4 442 f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
16b47b25
NC		 443
444#define EXTRACT_IFMT_BEQ_VARS \
445 UINT f_op1; \
446 UINT f_r1; \
447 UINT f_op2; \
448 UINT f_r2; \
449 SI f_disp16; \
450 unsigned int length;
451#define EXTRACT_IFMT_BEQ_CODE \
452 length = 4; \
453 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
454 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
455 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
456 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 457 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
16b47b25
NC		 458
459#define EXTRACT_IFMT_BEQZ_VARS \
460 UINT f_op1; \
461 UINT f_r1; \
462 UINT f_op2; \
463 UINT f_r2; \
464 SI f_disp16; \
465 unsigned int length;
466#define EXTRACT_IFMT_BEQZ_CODE \
467 length = 4; \
468 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
469 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
470 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
471 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 472 f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
16b47b25
NC		 473
474#define EXTRACT_IFMT_CMP_VARS \
475 UINT f_op1; \
476 UINT f_r1; \
477 UINT f_op2; \
478 UINT f_r2; \
479 unsigned int length;
480#define EXTRACT_IFMT_CMP_CODE \
481 length = 2; \
482 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
483 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
484 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
485 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
486
487#define EXTRACT_IFMT_CMPI_VARS \
488 UINT f_op1; \
489 UINT f_r1; \
490 UINT f_op2; \
491 UINT f_r2; \
492 INT f_simm16; \
493 unsigned int length;
494#define EXTRACT_IFMT_CMPI_CODE \
495 length = 4; \
496 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
497 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
498 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
499 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 500 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
16b47b25
NC		 501
502#define EXTRACT_IFMT_CMPZ_VARS \
503 UINT f_op1; \
504 UINT f_r1; \
505 UINT f_op2; \
506 UINT f_r2; \
507 unsigned int length;
508#define EXTRACT_IFMT_CMPZ_CODE \
509 length = 2; \
510 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
511 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
512 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
513 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
514
515#define EXTRACT_IFMT_DIV_VARS \
516 UINT f_op1; \
517 UINT f_r1; \
518 UINT f_op2; \
519 UINT f_r2; \
520 INT f_simm16; \
521 unsigned int length;
522#define EXTRACT_IFMT_DIV_CODE \
523 length = 4; \
524 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
525 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
526 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
527 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 528 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
16b47b25
NC		 529
530#define EXTRACT_IFMT_JC_VARS \
531 UINT f_op1; \
532 UINT f_r1; \
533 UINT f_op2; \
534 UINT f_r2; \
535 unsigned int length;
536#define EXTRACT_IFMT_JC_CODE \
537 length = 2; \
538 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
539 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
540 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
541 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
542
543#define EXTRACT_IFMT_LD24_VARS \
544 UINT f_op1; \
545 UINT f_r1; \
546 UINT f_uimm24; \
547 unsigned int length;
548#define EXTRACT_IFMT_LD24_CODE \
549 length = 4; \
550 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
551 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
552 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
553
554#define EXTRACT_IFMT_LDI16_VARS \
555 UINT f_op1; \
556 UINT f_r1; \
557 UINT f_op2; \
558 UINT f_r2; \
559 INT f_simm16; \
560 unsigned int length;
561#define EXTRACT_IFMT_LDI16_CODE \
562 length = 4; \
563 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
564 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
565 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
566 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 567 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
16b47b25
NC		 568
569#define EXTRACT_IFMT_MACHI_A_VARS \
570 UINT f_op1; \
571 UINT f_r1; \
572 UINT f_acc; \
573 UINT f_op23; \
574 UINT f_r2; \
575 unsigned int length;
576#define EXTRACT_IFMT_MACHI_A_CODE \
577 length = 2; \
578 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
579 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
580 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
581 f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
582 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
583
584#define EXTRACT_IFMT_MVFACHI_A_VARS \
585 UINT f_op1; \
586 UINT f_r1; \
587 UINT f_op2; \
588 UINT f_accs; \
589 UINT f_op3; \
590 unsigned int length;
591#define EXTRACT_IFMT_MVFACHI_A_CODE \
592 length = 2; \
593 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
594 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
595 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
596 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
597 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
598
599#define EXTRACT_IFMT_MVFC_VARS \
600 UINT f_op1; \
601 UINT f_r1; \
602 UINT f_op2; \
603 UINT f_r2; \
604 unsigned int length;
605#define EXTRACT_IFMT_MVFC_CODE \
606 length = 2; \
607 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
608 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
609 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
610 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
611
612#define EXTRACT_IFMT_MVTACHI_A_VARS \
613 UINT f_op1; \
614 UINT f_r1; \
615 UINT f_op2; \
616 UINT f_accs; \
617 UINT f_op3; \
618 unsigned int length;
619#define EXTRACT_IFMT_MVTACHI_A_CODE \
620 length = 2; \
621 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
622 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
623 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
624 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
625 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
626
627#define EXTRACT_IFMT_MVTC_VARS \
628 UINT f_op1; \
629 UINT f_r1; \
630 UINT f_op2; \
631 UINT f_r2; \
632 unsigned int length;
633#define EXTRACT_IFMT_MVTC_CODE \
634 length = 2; \
635 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
636 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
637 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
638 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
639
640#define EXTRACT_IFMT_NOP_VARS \
641 UINT f_op1; \
642 UINT f_r1; \
643 UINT f_op2; \
644 UINT f_r2; \
645 unsigned int length;
646#define EXTRACT_IFMT_NOP_CODE \
647 length = 2; \
648 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
649 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
650 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
651 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
652
653#define EXTRACT_IFMT_RAC_DSI_VARS \
654 UINT f_op1; \
655 UINT f_accd; \
656 UINT f_bits67; \
657 UINT f_op2; \
658 UINT f_accs; \
659 UINT f_bit14; \
660 SI f_imm1; \
661 unsigned int length;
662#define EXTRACT_IFMT_RAC_DSI_CODE \
663 length = 2; \
664 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
665 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
666 f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
667 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
668 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
669 f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
670 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
671
672#define EXTRACT_IFMT_SETH_VARS \
673 UINT f_op1; \
674 UINT f_r1; \
675 UINT f_op2; \
676 UINT f_r2; \
677 UINT f_hi16; \
678 unsigned int length;
679#define EXTRACT_IFMT_SETH_CODE \
680 length = 4; \
681 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
682 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
683 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
684 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
685 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
686
687#define EXTRACT_IFMT_SLLI_VARS \
688 UINT f_op1; \
689 UINT f_r1; \
690 UINT f_shift_op2; \
691 UINT f_uimm5; \
692 unsigned int length;
693#define EXTRACT_IFMT_SLLI_CODE \
694 length = 2; \
695 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
696 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
697 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
698 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
699
700#define EXTRACT_IFMT_ST_D_VARS \
701 UINT f_op1; \
702 UINT f_r1; \
703 UINT f_op2; \
704 UINT f_r2; \
705 INT f_simm16; \
706 unsigned int length;
707#define EXTRACT_IFMT_ST_D_CODE \
708 length = 4; \
709 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
710 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
711 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
712 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 713 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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NC		 714
715#define EXTRACT_IFMT_TRAP_VARS \
716 UINT f_op1; \
717 UINT f_r1; \
718 UINT f_op2; \
719 UINT f_uimm4; \
720 unsigned int length;
721#define EXTRACT_IFMT_TRAP_CODE \
722 length = 2; \
723 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
724 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
725 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
726 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
727
728#define EXTRACT_IFMT_SATB_VARS \
729 UINT f_op1; \
730 UINT f_r1; \
731 UINT f_op2; \
732 UINT f_r2; \
733 UINT f_uimm16; \
734 unsigned int length;
735#define EXTRACT_IFMT_SATB_CODE \
736 length = 4; \
737 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
738 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
739 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
740 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
741 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
742
743#define EXTRACT_IFMT_CLRPSW_VARS \
744 UINT f_op1; \
745 UINT f_r1; \
746 UINT f_uimm8; \
747 unsigned int length;
748#define EXTRACT_IFMT_CLRPSW_CODE \
749 length = 2; \
750 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
751 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
752 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
753
754#define EXTRACT_IFMT_BSET_VARS \
755 UINT f_op1; \
756 UINT f_bit4; \
757 UINT f_uimm3; \
758 UINT f_op2; \
759 UINT f_r2; \
760 INT f_simm16; \
761 unsigned int length;
762#define EXTRACT_IFMT_BSET_CODE \
763 length = 4; \
764 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
765 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
766 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
767 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
768 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
62836bf4 769 f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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NC		 770
771#define EXTRACT_IFMT_BTST_VARS \
772 UINT f_op1; \
773 UINT f_bit4; \
774 UINT f_uimm3; \
775 UINT f_op2; \
776 UINT f_r2; \
777 unsigned int length;
778#define EXTRACT_IFMT_BTST_CODE \
779 length = 2; \
780 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
781 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
782 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
783 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
784 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
785
786/* Queued output values of an instruction. */
787
788struct parexec {
789 union {
790 struct { /* empty sformat for unspecified field list */
791 int empty;
792 } sfmt_empty;
793 struct { /* e.g. add $dr,$sr */
794 SI dr;
795 } sfmt_add;
796 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
797 SI dr;
798 } sfmt_add3;
799 struct { /* e.g. and3 $dr,$sr,$uimm16 */
800 SI dr;
801 } sfmt_and3;
802 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
803 SI dr;
804 } sfmt_or3;
805 struct { /* e.g. addi $dr,$simm8 */
806 SI dr;
807 } sfmt_addi;
808 struct { /* e.g. addv $dr,$sr */
809 BI condbit;
810 SI dr;
811 } sfmt_addv;
812 struct { /* e.g. addv3 $dr,$sr,$simm16 */
813 BI condbit;
814 SI dr;
815 } sfmt_addv3;
816 struct { /* e.g. addx $dr,$sr */
817 BI condbit;
818 SI dr;
819 } sfmt_addx;
820 struct { /* e.g. bc.s $disp8 */
821 USI pc;
822 } sfmt_bc8;
823 struct { /* e.g. bc.l $disp24 */
824 USI pc;
825 } sfmt_bc24;
826 struct { /* e.g. beq $src1,$src2,$disp16 */
827 USI pc;
828 } sfmt_beq;
829 struct { /* e.g. beqz $src2,$disp16 */
830 USI pc;
831 } sfmt_beqz;
832 struct { /* e.g. bl.s $disp8 */
833 SI h_gr_SI_14;
834 USI pc;
835 } sfmt_bl8;
836 struct { /* e.g. bl.l $disp24 */
837 SI h_gr_SI_14;
838 USI pc;
839 } sfmt_bl24;
840 struct { /* e.g. bcl.s $disp8 */
841 SI h_gr_SI_14;
842 USI pc;
843 } sfmt_bcl8;
844 struct { /* e.g. bcl.l $disp24 */
845 SI h_gr_SI_14;
846 USI pc;
847 } sfmt_bcl24;
848 struct { /* e.g. bra.s $disp8 */
849 USI pc;
850 } sfmt_bra8;
851 struct { /* e.g. bra.l $disp24 */
852 USI pc;
853 } sfmt_bra24;
854 struct { /* e.g. cmp $src1,$src2 */
855 BI condbit;
856 } sfmt_cmp;
857 struct { /* e.g. cmpi $src2,$simm16 */
858 BI condbit;
859 } sfmt_cmpi;
860 struct { /* e.g. cmpz $src2 */
861 BI condbit;
862 } sfmt_cmpz;
863 struct { /* e.g. div $dr,$sr */
864 SI dr;
865 } sfmt_div;
866 struct { /* e.g. jc $sr */
867 USI pc;
868 } sfmt_jc;
869 struct { /* e.g. jl $sr */
870 SI h_gr_SI_14;
871 USI pc;
872 } sfmt_jl;
873 struct { /* e.g. jmp $sr */
874 USI pc;
875 } sfmt_jmp;
876 struct { /* e.g. ld $dr,@$sr */
877 SI dr;
878 } sfmt_ld;
879 struct { /* e.g. ld $dr,@($slo16,$sr) */
880 SI dr;
881 } sfmt_ld_d;
882 struct { /* e.g. ldb $dr,@$sr */
883 SI dr;
884 } sfmt_ldb;
885 struct { /* e.g. ldb $dr,@($slo16,$sr) */
886 SI dr;
887 } sfmt_ldb_d;
888 struct { /* e.g. ldh $dr,@$sr */
889 SI dr;
890 } sfmt_ldh;
891 struct { /* e.g. ldh $dr,@($slo16,$sr) */
892 SI dr;
893 } sfmt_ldh_d;
894 struct { /* e.g. ld $dr,@$sr+ */
895 SI dr;
896 SI sr;
897 } sfmt_ld_plus;
898 struct { /* e.g. ld24 $dr,$uimm24 */
899 SI dr;
900 } sfmt_ld24;
901 struct { /* e.g. ldi8 $dr,$simm8 */
902 SI dr;
903 } sfmt_ldi8;
904 struct { /* e.g. ldi16 $dr,$hash$slo16 */
905 SI dr;
906 } sfmt_ldi16;
907 struct { /* e.g. lock $dr,@$sr */
908 SI dr;
909 BI h_lock_BI;
910 } sfmt_lock;
911 struct { /* e.g. machi $src1,$src2,$acc */
912 DI acc;
913 } sfmt_machi_a;
914 struct { /* e.g. mulhi $src1,$src2,$acc */
915 DI acc;
916 } sfmt_mulhi_a;
917 struct { /* e.g. mv $dr,$sr */
918 SI dr;
919 } sfmt_mv;
920 struct { /* e.g. mvfachi $dr,$accs */
921 SI dr;
922 } sfmt_mvfachi_a;
923 struct { /* e.g. mvfc $dr,$scr */
924 SI dr;
925 } sfmt_mvfc;
926 struct { /* e.g. mvtachi $src1,$accs */
927 DI accs;
928 } sfmt_mvtachi_a;
929 struct { /* e.g. mvtc $sr,$dcr */
930 USI dcr;
931 } sfmt_mvtc;
932 struct { /* e.g. nop */
933 int empty;
934 } sfmt_nop;
935 struct { /* e.g. rac $accd,$accs,$imm1 */
936 DI accd;
937 } sfmt_rac_dsi;
938 struct { /* e.g. rte */
939 UQI h_bpsw_UQI;
940 USI h_cr_USI_6;
941 UQI h_psw_UQI;
942 USI pc;
943 } sfmt_rte;
944 struct { /* e.g. seth $dr,$hash$hi16 */
945 SI dr;
946 } sfmt_seth;
947 struct { /* e.g. sll3 $dr,$sr,$simm16 */
948 SI dr;
949 } sfmt_sll3;
950 struct { /* e.g. slli $dr,$uimm5 */
951 SI dr;
952 } sfmt_slli;
953 struct { /* e.g. st $src1,@$src2 */
954 SI h_memory_SI_src2;
955 USI h_memory_SI_src2_idx;
956 } sfmt_st;
957 struct { /* e.g. st $src1,@($slo16,$src2) */
e9c60591
DE		 958 SI h_memory_SI_add__SI_src2_slo16;
959 USI h_memory_SI_add__SI_src2_slo16_idx;
16b47b25
NC		 960 } sfmt_st_d;
961 struct { /* e.g. stb $src1,@$src2 */
962 QI h_memory_QI_src2;
963 USI h_memory_QI_src2_idx;
964 } sfmt_stb;
965 struct { /* e.g. stb $src1,@($slo16,$src2) */
e9c60591
DE		 966 QI h_memory_QI_add__SI_src2_slo16;
967 USI h_memory_QI_add__SI_src2_slo16_idx;
16b47b25
NC		 968 } sfmt_stb_d;
969 struct { /* e.g. sth $src1,@$src2 */
970 HI h_memory_HI_src2;
971 USI h_memory_HI_src2_idx;
972 } sfmt_sth;
973 struct { /* e.g. sth $src1,@($slo16,$src2) */
e9c60591
DE		 974 HI h_memory_HI_add__SI_src2_slo16;
975 USI h_memory_HI_add__SI_src2_slo16_idx;
16b47b25
NC		 976 } sfmt_sth_d;
977 struct { /* e.g. st $src1,@+$src2 */
978 SI h_memory_SI_new_src2;
979 USI h_memory_SI_new_src2_idx;
980 SI src2;
981 } sfmt_st_plus;
982 struct { /* e.g. sth $src1,@$src2+ */
983 HI h_memory_HI_new_src2;
984 USI h_memory_HI_new_src2_idx;
985 SI src2;
986 } sfmt_sth_plus;
987 struct { /* e.g. stb $src1,@$src2+ */
988 QI h_memory_QI_new_src2;
989 USI h_memory_QI_new_src2_idx;
990 SI src2;
991 } sfmt_stb_plus;
992 struct { /* e.g. trap $uimm4 */
993 UQI h_bbpsw_UQI;
994 UQI h_bpsw_UQI;
995 USI h_cr_USI_14;
996 USI h_cr_USI_6;
997 UQI h_psw_UQI;
e9c60591 998 USI pc;
16b47b25
NC		 999 } sfmt_trap;
1000 struct { /* e.g. unlock $src1,@$src2 */
1001 BI h_lock_BI;
1002 SI h_memory_SI_src2;
1003 USI h_memory_SI_src2_idx;
1004 } sfmt_unlock;
1005 struct { /* e.g. satb $dr,$sr */
1006 SI dr;
1007 } sfmt_satb;
1008 struct { /* e.g. sat $dr,$sr */
1009 SI dr;
1010 } sfmt_sat;
1011 struct { /* e.g. sadd */
1012 DI h_accums_DI_0;
1013 } sfmt_sadd;
1014 struct { /* e.g. macwu1 $src1,$src2 */
1015 DI h_accums_DI_1;
1016 } sfmt_macwu1;
1017 struct { /* e.g. msblo $src1,$src2 */
1018 DI accum;
1019 } sfmt_msblo;
1020 struct { /* e.g. mulwu1 $src1,$src2 */
1021 DI h_accums_DI_1;
1022 } sfmt_mulwu1;
1023 struct { /* e.g. sc */
1024 int empty;
1025 } sfmt_sc;
1026 struct { /* e.g. clrpsw $uimm8 */
1027 USI h_cr_USI_0;
1028 } sfmt_clrpsw;
1029 struct { /* e.g. setpsw $uimm8 */
1030 USI h_cr_USI_0;
1031 } sfmt_setpsw;
1032 struct { /* e.g. bset $uimm3,@($slo16,$sr) */
e9c60591
DE		 1033 QI h_memory_QI_add__SI_sr_slo16;
1034 USI h_memory_QI_add__SI_sr_slo16_idx;
16b47b25
NC		 1035 } sfmt_bset;
1036 struct { /* e.g. btst $uimm3,$sr */
1037 BI condbit;
1038 } sfmt_btst;
1039 } operands;
1040 /* For conditionally written operands, bitmask of which ones were. */
1041 int written;
1042};
1043
1044/* Collection of various things for the trace handler to use. */
1045
1046typedef struct trace_record {
1047 IADDR pc;
1048 /* FIXME:wip */
1049} TRACE_RECORD;
1050
1051#endif /* CPU_M32R2F_H */
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