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f6bcefef | 1 | # Simulator main loop for CRIS. -*- C -*- |
ecd75fc8 | 2 | # Copyright (C) 2004-2014 Free Software Foundation, Inc. |
f6bcefef HPN |
3 | # Contributed by Axis Communications. |
4 | # | |
5 | # This file is part of the GNU simulators. | |
6 | # | |
7 | # This program is free software; you can redistribute it and/or modify | |
8 | # it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | # the Free Software Foundation; either version 3 of the License, or |
10 | # (at your option) any later version. | |
f6bcefef HPN |
11 | # |
12 | # This program is distributed in the hope that it will be useful, | |
13 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | # GNU General Public License for more details. | |
16 | # | |
4744ac1b JB |
17 | # You should have received a copy of the GNU General Public License |
18 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
f6bcefef HPN |
19 | |
20 | # Based on the fr30 file. | |
21 | ||
22 | # Syntax: | |
23 | # /bin/sh mainloop.in command | |
24 | # | |
25 | # Command is one of: | |
26 | # | |
27 | # init | |
28 | # support | |
29 | # extract-{simple,scache,pbb} | |
30 | # {full,fast}-exec-{simple,scache,pbb} | |
31 | # | |
32 | # A target need only provide a "full" version of one of simple,scache,pbb. | |
33 | # If the target wants it can also provide a fast version of same. | |
34 | # It can't provide more than this, however for illustration's sake the CRIS | |
35 | # port provides examples of all. | |
36 | ||
37 | # ??? After a few more ports are done, revisit. | |
38 | # Will eventually need to machine generate a lot of this. | |
39 | ||
40 | case "x$1" in | |
41 | ||
42 | xsupport) | |
43 | ||
44 | cat <<EOF | |
45 | /* It seems we don't have a templated header file corresponding to | |
46 | cris-tmpl.c, so we have to get out declarations the hackish way. */ | |
47 | extern void @cpu@_specific_init (SIM_CPU *current_cpu); | |
48 | ||
49 | static INLINE const IDESC * | |
50 | extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf, | |
51 | int fast_p) | |
52 | { | |
53 | const IDESC *id = @cpu@_decode (current_cpu, pc, insn, | |
54 | #if CGEN_INT_INSN_P | |
55 | insn, | |
56 | #endif | |
57 | abuf); | |
58 | @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p); | |
59 | if (! fast_p) | |
60 | { | |
61 | int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); | |
62 | int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); | |
63 | @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p); | |
64 | } | |
65 | return id; | |
66 | } | |
67 | ||
68 | static INLINE SEM_PC | |
69 | execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p) | |
70 | { | |
71 | SEM_PC vpc; | |
72 | ||
73 | if (fast_p) | |
74 | { | |
75 | #if ! WITH_SEM_SWITCH_FAST | |
76 | #if WITH_SCACHE | |
77 | vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc); | |
78 | #else | |
79 | vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf); | |
80 | #endif | |
81 | #else | |
82 | abort (); | |
83 | #endif /* WITH_SEM_SWITCH_FAST */ | |
84 | } | |
85 | else | |
86 | { | |
87 | #if ! WITH_SEM_SWITCH_FULL | |
88 | ARGBUF *abuf = &sc->argbuf; | |
89 | const IDESC *idesc = abuf->idesc; | |
90 | #if WITH_SCACHE_PBB | |
91 | int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL); | |
92 | #else | |
93 | int virtual_p = 0; | |
94 | #endif | |
95 | ||
96 | if (! virtual_p) | |
97 | { | |
98 | /* FIXME: call x-before */ | |
99 | if (ARGBUF_PROFILE_P (abuf)) | |
100 | PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num); | |
101 | /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */ | |
102 | if (PROFILE_MODEL_P (current_cpu) | |
103 | && ARGBUF_PROFILE_P (abuf)) | |
104 | @cpu@_model_insn_before (current_cpu, 1 /*first_p*/); | |
105 | TRACE_INSN_INIT (current_cpu, abuf, 1); | |
106 | TRACE_INSN (current_cpu, idesc->idata, | |
107 | (const struct argbuf *) abuf, abuf->addr); | |
108 | } | |
109 | #if WITH_SCACHE | |
110 | vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc); | |
111 | #else | |
112 | vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf); | |
113 | #endif | |
114 | if (! virtual_p) | |
115 | { | |
116 | /* FIXME: call x-after */ | |
117 | if (PROFILE_MODEL_P (current_cpu) | |
118 | && ARGBUF_PROFILE_P (abuf)) | |
119 | { | |
120 | int cycles; | |
121 | ||
122 | cycles = (*idesc->timing->model_fn) (current_cpu, sc); | |
123 | @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles); | |
124 | } | |
125 | TRACE_INSN_FINI (current_cpu, abuf, 1); | |
126 | } | |
127 | #else | |
128 | abort (); | |
129 | #endif /* WITH_SEM_SWITCH_FULL */ | |
130 | } | |
131 | ||
132 | return vpc; | |
133 | } | |
134 | ||
135 | EOF | |
136 | ||
137 | ;; | |
138 | ||
139 | xinit) | |
140 | ||
141 | cat <<EOF | |
142 | /* This seemed the only sane location to emit a call to a | |
143 | model-specific init function. It may not work for all simulator | |
144 | types. FIXME: Introduce a model-init hook. */ | |
145 | ||
146 | /* We use the same condition as the code that's expected to follow, so | |
147 | GCC can consolidate the code with only one conditional. */ | |
148 | if (! CPU_IDESC_SEM_INIT_P (current_cpu)) | |
149 | @cpu@_specific_init (current_cpu); | |
150 | EOF | |
151 | ||
152 | ;; | |
153 | ||
154 | xextract-simple | xextract-scache) | |
155 | ||
156 | # Inputs: current_cpu, vpc, sc, FAST_P | |
157 | # Outputs: sc filled in | |
158 | ||
159 | cat <<EOF | |
160 | { | |
161 | CGEN_INSN_INT insn = GETIMEMUHI (current_cpu, vpc); | |
162 | extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P); | |
163 | } | |
164 | EOF | |
165 | ||
166 | ;; | |
167 | ||
168 | xextract-pbb) | |
169 | ||
170 | # Inputs: current_cpu, pc, sc, max_insns, FAST_P | |
171 | # Outputs: sc, pc | |
172 | # sc must be left pointing past the last created entry. | |
173 | # pc must be left pointing past the last created entry. | |
174 | # If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called | |
175 | # to record the vpc of the cti insn. | |
176 | # SET_INSN_COUNT(n) must be called to record number of real insns. | |
177 | ||
178 | cat <<EOF | |
179 | { | |
180 | const IDESC *idesc; | |
181 | int icount = 0; | |
182 | ||
183 | /* Make sure the buffer doesn't overflow for profiled insns if | |
184 | max_insns happens to not be a multiple of 3. */ | |
185 | if (!FAST_P) | |
186 | max_insns -= 2 + 3; | |
187 | else | |
188 | /* There might be two real insns handled per loop. */ | |
189 | max_insns--; | |
190 | ||
191 | while (max_insns > 0) | |
192 | { | |
193 | UHI insn = GETIMEMUHI (current_cpu, pc); | |
194 | int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); | |
195 | int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); | |
196 | int befaft_p = profile_p || trace_p; | |
197 | ||
198 | if (befaft_p) | |
199 | { | |
200 | @cpu@_emit_before (current_cpu, sc, pc, 1); | |
201 | ++sc; | |
202 | sc->argbuf.trace_p = trace_p; | |
203 | sc->argbuf.profile_p = profile_p; | |
204 | --max_insns; | |
205 | } | |
206 | ||
207 | idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P); | |
208 | ++sc; | |
209 | --max_insns; | |
210 | ++icount; | |
211 | ||
212 | if (befaft_p) | |
213 | { | |
214 | @cpu@_emit_after (current_cpu, sc, pc); | |
215 | ++sc; | |
216 | --max_insns; | |
217 | } | |
218 | ||
219 | pc += idesc->length; | |
220 | ||
221 | if (IDESC_CTI_P (idesc)) | |
222 | { | |
223 | SET_CTI_VPC (sc - 1); | |
224 | ||
225 | /* Delay slot? Ignore for zero-instructions (bcc .+2) since | |
226 | those are treated as exit insns to avoid runaway sessions | |
227 | for invalid programs. */ | |
228 | if (insn != 0 && CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT)) | |
229 | { | |
230 | UHI insn; | |
231 | trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc); | |
232 | profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc); | |
233 | befaft_p = profile_p || trace_p; | |
234 | ||
235 | if (befaft_p) | |
236 | { | |
237 | @cpu@_emit_before (current_cpu, sc, pc, 1); | |
238 | ++sc; | |
239 | sc->argbuf.trace_p = trace_p; | |
240 | sc->argbuf.profile_p = profile_p; | |
241 | --max_insns; | |
242 | } | |
243 | ||
244 | insn = GETIMEMUHI (current_cpu, pc); | |
245 | idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P); | |
246 | ++sc; | |
247 | --max_insns; | |
248 | ++icount; | |
249 | ||
250 | if (befaft_p) | |
251 | { | |
252 | @cpu@_emit_after (current_cpu, sc, pc); | |
253 | ++sc; | |
254 | --max_insns; | |
255 | } | |
256 | pc += idesc->length; | |
257 | } | |
258 | break; | |
259 | } | |
260 | } | |
261 | ||
262 | Finish: | |
263 | SET_INSN_COUNT (icount); | |
264 | } | |
265 | EOF | |
266 | ||
267 | ;; | |
268 | ||
269 | xfull-exec-* | xfast-exec-*) | |
270 | ||
271 | # Inputs: current_cpu, sc, FAST_P | |
272 | # Outputs: vpc | |
273 | # vpc contains the address of the next insn to execute | |
274 | ||
275 | cat <<EOF | |
276 | { | |
277 | #if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST) | |
278 | #define DEFINE_SWITCH | |
279 | #include "sem@[email protected]" | |
280 | #else | |
281 | vpc = execute (current_cpu, vpc, FAST_P); | |
282 | #endif | |
283 | } | |
284 | EOF | |
285 | ||
286 | ;; | |
287 | ||
288 | *) | |
289 | echo "Invalid argument to mainloop.in: $1" >&2 | |
290 | exit 1 | |
291 | ;; | |
292 | ||
293 | esac |