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* config/e-criself.c: Fix typo in last change.
[binutils.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
8a104df9 3 2000, 2001, 2002
252b5132
RH		 4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
252b5132
RH		 36/* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40#if defined (TE_SVR4) || defined (TE_DELTA)
41const char *m68k_comment_chars = "|#";
42#else
43const char *m68k_comment_chars = "|";
44#endif
45
46/* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49/* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
92774660
KH		 51 #NO_APP at the beginning of its output. */
52/* Also note that comments like this one will always work. */
252b5132
RH		 53const char line_comment_chars[] = "#*";
54
63a0b638 55const char line_separator_chars[] = ";";
252b5132
RH		 56
57/* Chars that can be used to separate mant from exp in floating point nums */
5a38dc70 58const char EXP_CHARS[] = "eE";
252b5132
RH		 59
60/* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
62
5a38dc70 63const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 64
65/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
68
69const int md_reloc_size = 8; /* Size of relocation record */
70
71/* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
92774660 73 references. Not implemented. For ELF there are other means
252b5132
RH		 74 to denote pic relocations. */
75int flag_want_pic;
76
77static int flag_short_refs; /* -l option */
78static int flag_long_jumps; /* -S option */
28e7409f 79static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 80
81#ifdef REGISTER_PREFIX_OPTIONAL
82int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83#else
84int flag_reg_prefix_optional;
85#endif
86
87/* Whether --register-prefix-optional was used on the command line. */
88static int reg_prefix_optional_seen;
89
90/* The floating point coprocessor to use by default. */
91static enum m68k_register m68k_float_copnum = COP1;
92
93/* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95static int m68k_abspcadd;
96
97/* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99static int m68k_quick = 1;
100
101/* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
103 be 32 bits. */
104static int m68k_rel32 = 1;
105
106/* This is non-zero if m68k_rel32 was set from the command line. */
107static int m68k_rel32_from_cmdline;
108
109/* The default width to use for an index register when using a base
110 displacement. */
111static enum m68k_size m68k_index_width_default = SIZE_LONG;
112
113/* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
115 label. */
116
117struct label_line
118{
119 struct label_line *next;
120 symbolS *label;
121 char *file;
122 unsigned int line;
123 int text;
124};
125
126/* The list of labels. */
127
128static struct label_line *labels;
129
130/* The current label. */
131
132static struct label_line *current_label;
133
134/* Its an arbitrary name: This means I don't approve of it */
135/* See flames below */
136static struct obstack robyn;
137
252b5132
RH		 138struct m68k_incant
139 {
140 const char *m_operands;
141 unsigned long m_opcode;
142 short m_opnum;
143 short m_codenum;
144 int m_arch;
145 struct m68k_incant *m_next;
146 };
147
148#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149#define gettwo(x) (((x)->m_opcode)&0xffff)
150
151static const enum m68k_register m68000_control_regs[] = { 0 };
152static const enum m68k_register m68010_control_regs[] = {
153 SFC, DFC, USP, VBR,
154 0
155};
156static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 0
159};
160static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 0
164};
165static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
168 0
169};
6da466c7 170static const enum m68k_register mcf_control_regs[] = {
92774660 171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 172 RAMBAR0, RAMBAR1, MBAR,
173 0
174};
175#define cpu32_control_regs m68010_control_regs
176
177static const enum m68k_register *control_regs;
178
179/* internal form of a 68020 instruction */
180struct m68k_it
181{
182 const char *error;
183 const char *args; /* list of opcode info */
184 int numargs;
185
186 int numo; /* Number of shorts in opcode */
187 short opcode[11];
188
189 struct m68k_op operands[6];
190
191 int nexp; /* number of exprs in use */
192 struct m68k_exp exprs[4];
193
194 int nfrag; /* Number of frags we have to produce */
195 struct
196 {
197 int fragoff; /* Where in the current opcode the frag ends */
198 symbolS *fadd;
199 offsetT foff;
200 int fragty;
201 }
202 fragb[4];
203
204 int nrel; /* Num of reloc strucs in use */
205 struct
206 {
207 int n;
208 expressionS exp;
209 char wid;
210 char pcrel;
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
217 example). */
218 int pcrel_fix;
219#ifdef OBJ_ELF
220 /* Whether this expression needs special pic relocation, and if
221 so, which. */
222 enum pic_relocation pic_reloc;
223#endif
224 }
225 reloc[5]; /* Five is enough??? */
226};
227
6da466c7 228#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 229#define float_of_arch(x) ((x) & mfloat)
230#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 231#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 232
233/* Macros for determining if cpu supports a specific addressing mode */
dc84e067 234#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
252b5132
RH		 235
236static struct m68k_it the_ins; /* the instruction being assembled */
237
238#define op(ex) ((ex)->exp.X_op)
239#define adds(ex) ((ex)->exp.X_add_symbol)
240#define subs(ex) ((ex)->exp.X_op_symbol)
241#define offs(ex) ((ex)->exp.X_add_number)
242
243/* Macros for adding things to the m68k_it struct */
244
245#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246
247/* Static functions. */
248
249static void insop PARAMS ((int, const struct m68k_incant *));
250static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
251static void add_frag PARAMS ((symbolS *, offsetT, int));
252
253/* Like addword, but goes BEFORE general operands */
254static void
255insop (w, opcode)
256 int w;
257 const struct m68k_incant *opcode;
258{
259 int z;
07726851 260 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 261 the_ins.opcode[z] = the_ins.opcode[z - 1];
262 for (z = 0; z < the_ins.nrel; z++)
263 the_ins.reloc[z].n += 2;
252b5132
RH		 264 for (z = 0; z < the_ins.nfrag; z++)
265 the_ins.fragb[z].fragoff++;
8a104df9 266 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 267 the_ins.numo++;
268}
269
270/* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 Blecch. */
272static void
273add_fix (width, exp, pc_rel, pc_fix)
274 int width;
275 struct m68k_exp *exp;
276 int pc_rel;
277 int pc_fix;
278{
279 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
280 ? (the_ins.numo*2-1)
281 : (((width)=='b')
282 ? (the_ins.numo*2+1)
283 : (the_ins.numo*2)));
284 the_ins.reloc[the_ins.nrel].exp = exp->exp;
285 the_ins.reloc[the_ins.nrel].wid = width;
286 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287#ifdef OBJ_ELF
288 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289#endif
290 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291}
292
293/* Cause an extra frag to be generated here, inserting up to 10 bytes
294 (that value is chosen in the frag_var call in md_assemble). TYPE
295 is the subtype of the frag to be generated; its primary type is
296 rs_machine_dependent.
297
298 The TYPE parameter is also used by md_convert_frag_1 and
299 md_estimate_size_before_relax. The appropriate type of fixup will
300 be emitted by md_convert_frag_1.
301
302 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303static void
304add_frag (add, off, type)
305 symbolS *add;
306 offsetT off;
307 int type;
308{
8a104df9
KH		 309 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
310 the_ins.fragb[the_ins.nfrag].fadd = add;
311 the_ins.fragb[the_ins.nfrag].foff = off;
312 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 313}
314
315#define isvar(ex) \
316 (op (ex) != O_constant && op (ex) != O_big)
317
318static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
319static int get_num PARAMS ((struct m68k_exp *exp, int ok));
320static void m68k_ip PARAMS ((char *));
321static void insert_reg PARAMS ((const char *, int));
322static void select_control_regs PARAMS ((void));
323static void init_regtable PARAMS ((void));
324static int reverse_16_bits PARAMS ((int in));
325static int reverse_8_bits PARAMS ((int in));
326static void install_gen_operand PARAMS ((int mode, int val));
327static void install_operand PARAMS ((int mode, int val));
328static void s_bss PARAMS ((int));
329static void s_data1 PARAMS ((int));
330static void s_data2 PARAMS ((int));
331static void s_even PARAMS ((int));
332static void s_proc PARAMS ((int));
333static void mri_chip PARAMS ((void));
334static void s_chip PARAMS ((int));
335static void s_fopt PARAMS ((int));
336static void s_opt PARAMS ((int));
337static void s_reg PARAMS ((int));
338static void s_restore PARAMS ((int));
339static void s_save PARAMS ((int));
340static void s_mri_if PARAMS ((int));
341static void s_mri_else PARAMS ((int));
342static void s_mri_endi PARAMS ((int));
343static void s_mri_break PARAMS ((int));
344static void s_mri_next PARAMS ((int));
345static void s_mri_for PARAMS ((int));
346static void s_mri_endf PARAMS ((int));
347static void s_mri_repeat PARAMS ((int));
348static void s_mri_until PARAMS ((int));
349static void s_mri_while PARAMS ((int));
350static void s_mri_endw PARAMS ((int));
252b5132
RH		 351static void md_convert_frag_1 PARAMS ((fragS *));
352
353static int current_architecture;
354
dc84e067
NC		 355struct m68k_cpu
356 {
357 unsigned long arch;
358 const char *name;
359 int alias;
360 };
252b5132 361
dc84e067
NC		 362static const struct m68k_cpu archs[] =
363 {
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
378 cpus. */
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
407 };
252b5132
RH		 408
409static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410
151337e8
NC		 411/* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
252b5132 413
151337e8
NC		 414/* Macros used in the relaxation code. */
415#define TAB(x,y) (((x) << 2) + (y))
416#define TABTYPE(x) ((x) >> 2)
417
418/* Relaxation states. */
419#define BYTE 0
420#define SHORT 1
421#define LONG 2
422#define SZ_UNDEF 3
423
424/* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
433
ac62c346
AM		 434#define BRANCHBWL 0 /* branch byte, word, or long */
435#define BRABSJUNC 1 /* absolute jump for LONG, unconditional */
436#define BRABSJCOND 2 /* absolute jump for LONG, conditional */
437#define BRANCHBW 3 /* branch byte or word */
151337e8
NC		 438
439/* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
446
ac62c346
AM		 447#define FBRANCH 4 /* coprocessor branch */
448#define DBCCLBR 5 /* DBcc relaxable with a long branch */
449#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */
151337e8
NC		 450
451/* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
461
ac62c346
AM		 462#define PCREL1632 7 /* 16-bit or 32-bit PC-relative */
463#define PCINDEX 8 /* PC+displacement+index */
464#define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 465
466/* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
468
469/* The fields are:
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 474
475 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 476relax_typeS md_relax_table[] =
477{
ac62c346
AM		 478 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
479 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
480 { 0, 0, 4, 0 },
481 { 1, 1, 0, 0 },
482
483 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
484 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
485 { 0, 0, 4, 0 },
486 { 1, 1, 0, 0 },
487
488 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
489 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
490 { 0, 0, 6, 0 },
491 { 1, 1, 0, 0 },
492
493 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
494 { 0, 0, 2, 0 },
495 { 1, 1, 0, 0 },
496 { 1, 1, 0, 0 },
497
498 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
499 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
500 { 0, 0, 4, 0 },
501 { 1, 1, 0, 0 },
502
503 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
504 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
505 { 0, 0, 10, 0 },
506 { 1, 1, 0, 0 },
507
508 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
509 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
510 { 0, 0, 10, 0 },
511 { 1, 1, 0, 0 },
512
513 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */
514 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
515 { 0, 0, 6, 0 },
516 { 1, 1, 0, 0 },
517
518 { 125, -130, 0, TAB (PCINDEX, SHORT) },
519 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
520 { 0, 0, 4, 0 },
521 { 1, 1, 0, 0 },
522
523 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */
524 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
525 { 0, 0, 4, 0 },
526 { 1, 1, 0, 0 },
252b5132
RH		 527};
528
529/* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
531 generates these.
532 */
533
534/* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
539 */
540const pseudo_typeS md_pseudo_table[] =
541{
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
544 {"bss", s_bss, 0},
545 {"even", s_even, 0},
546 {"skip", s_space, 0},
547 {"proc", s_proc, 0},
548#if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
550#endif
551#ifdef OBJ_ELF
552 {"swbeg", s_ignore, 0},
553#endif
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
556
f27a3839
AS		 557#ifdef OBJ_ELF
558 /* Dwarf2 support for Gcc. */
9f1838ed 559 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
f27a3839
AS		 560 {"loc", dwarf2_directive_loc, 0},
561#endif
562
252b5132
RH		 563 /* The following pseudo-ops are supported for MRI compatibility. */
564 {"chip", s_chip, 0},
565 {"comline", s_space, 1},
566 {"fopt", s_fopt, 0},
567 {"mask2", s_ignore, 0},
568 {"opt", s_opt, 0},
569 {"reg", s_reg, 0},
570 {"restore", s_restore, 0},
571 {"save", s_save, 0},
572
573 {"if", s_mri_if, 0},
574 {"if.b", s_mri_if, 'b'},
575 {"if.w", s_mri_if, 'w'},
576 {"if.l", s_mri_if, 'l'},
577 {"else", s_mri_else, 0},
578 {"else.s", s_mri_else, 's'},
579 {"else.l", s_mri_else, 'l'},
580 {"endi", s_mri_endi, 0},
581 {"break", s_mri_break, 0},
582 {"break.s", s_mri_break, 's'},
583 {"break.l", s_mri_break, 'l'},
584 {"next", s_mri_next, 0},
585 {"next.s", s_mri_next, 's'},
586 {"next.l", s_mri_next, 'l'},
587 {"for", s_mri_for, 0},
588 {"for.b", s_mri_for, 'b'},
589 {"for.w", s_mri_for, 'w'},
590 {"for.l", s_mri_for, 'l'},
591 {"endf", s_mri_endf, 0},
592 {"repeat", s_mri_repeat, 0},
593 {"until", s_mri_until, 0},
594 {"until.b", s_mri_until, 'b'},
595 {"until.w", s_mri_until, 'w'},
596 {"until.l", s_mri_until, 'l'},
597 {"while", s_mri_while, 0},
598 {"while.b", s_mri_while, 'b'},
599 {"while.w", s_mri_while, 'w'},
600 {"while.l", s_mri_while, 'l'},
601 {"endw", s_mri_endw, 0},
602
603 {0, 0, 0}
604};
605
252b5132
RH		 606/* The mote pseudo ops are put into the opcode table, since they
607 don't start with a . they look like opcodes to gas.
608 */
609
610#ifdef M68KCOFF
611extern void obj_coff_section PARAMS ((int));
612#endif
613
5a38dc70 614const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 615{
616
617 {"dcl", cons, 4},
618 {"dc", cons, 2},
619 {"dcw", cons, 2},
620 {"dcb", cons, 1},
621
622 {"dsl", s_space, 4},
623 {"ds", s_space, 2},
624 {"dsw", s_space, 2},
625 {"dsb", s_space, 1},
626
627 {"xdef", s_globl, 0},
628#ifdef OBJ_ELF
629 {"align", s_align_bytes, 0},
630#else
631 {"align", s_align_ptwo, 0},
632#endif
633#ifdef M68KCOFF
634 {"sect", obj_coff_section, 0},
635 {"section", obj_coff_section, 0},
636#endif
637 {0, 0, 0}
638};
639
640#define issbyte(x) ((x)>=-128 && (x)<=127)
641#define isubyte(x) ((x)>=0 && (x)<=255)
642#define issword(x) ((x)>=-32768 && (x)<=32767)
643#define isuword(x) ((x)>=0 && (x)<=65535)
644
645#define isbyte(x) ((x)>= -255 && (x)<=255)
646#define isword(x) ((x)>=-65536 && (x)<=65535)
647#define islong(x) (1)
648
649extern char *input_line_pointer;
650
252b5132
RH		 651static char notend_table[256];
652static char alt_notend_table[256];
653#define notend(s) \
654 (! (notend_table[(unsigned char) *s] \
655 || (*s == ':' \
656 && alt_notend_table[(unsigned char) s[1]])))
657
658#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
659
660#ifdef NO_PCREL_RELOCS
661
662int
663make_pcrel_absolute(fixP, add_number)
664 fixS *fixP;
665 long *add_number;
666{
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
668
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
672 */
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 {
675 opcode[0] = 0x4e;
676 opcode[1] = 0xf9;
677 }
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
679 {
680 opcode[0] = 0x4e;
681 opcode[1] = 0xb9;
682 }
683 else
684 as_fatal (_("Unknown PC relative instruction"));
685 *add_number -= 4;
686 return 0;
687}
688
689#endif /* NO_PCREL_RELOCS */
690
691short
692tc_coff_fix2rtype (fixP)
693 fixS *fixP;
694{
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697#ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
701 : R_DIR32);
702#else
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
706 R_PCRLONG) :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
709 R_RELLONG));
710#endif
711}
712
713#endif
714
715#ifdef OBJ_ELF
716
c801568a
AM		 717/* Return zero if the reference to SYMBOL from within the same segment may
718 be relaxed. */
719
720/* On an ELF system, we can't relax an externally visible symbol,
721 because it may be overridden by a shared library. However, if
722 TARGET_OS is "elf", then we presume that we are assembling for an
723 embedded system, in which case we don't have to worry about shared
724 libraries, and we can relax any external sym. */
725
726#define relaxable_symbol(symbol) \
727 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
728 || S_IS_WEAK (symbol)))
729
252b5132
RH		 730/* Compute the relocation code for a fixup of SIZE bytes, using pc
731 relative relocation if PCREL is non-zero. PIC says whether a special
732 pic relocation was requested. */
733
734static bfd_reloc_code_real_type get_reloc_code
735 PARAMS ((int, int, enum pic_relocation));
736
737static bfd_reloc_code_real_type
738get_reloc_code (size, pcrel, pic)
739 int size;
740 int pcrel;
741 enum pic_relocation pic;
742{
743 switch (pic)
744 {
745 case pic_got_pcrel:
746 switch (size)
747 {
748 case 1:
749 return BFD_RELOC_8_GOT_PCREL;
750 case 2:
751 return BFD_RELOC_16_GOT_PCREL;
752 case 4:
753 return BFD_RELOC_32_GOT_PCREL;
754 }
755 break;
756
757 case pic_got_off:
758 switch (size)
759 {
760 case 1:
761 return BFD_RELOC_8_GOTOFF;
762 case 2:
763 return BFD_RELOC_16_GOTOFF;
764 case 4:
765 return BFD_RELOC_32_GOTOFF;
766 }
767 break;
768
769 case pic_plt_pcrel:
770 switch (size)
771 {
772 case 1:
773 return BFD_RELOC_8_PLT_PCREL;
774 case 2:
775 return BFD_RELOC_16_PLT_PCREL;
776 case 4:
777 return BFD_RELOC_32_PLT_PCREL;
778 }
779 break;
780
781 case pic_plt_off:
782 switch (size)
783 {
784 case 1:
785 return BFD_RELOC_8_PLTOFF;
786 case 2:
787 return BFD_RELOC_16_PLTOFF;
788 case 4:
789 return BFD_RELOC_32_PLTOFF;
790 }
791 break;
792
793 case pic_none:
794 if (pcrel)
795 {
796 switch (size)
797 {
798 case 1:
799 return BFD_RELOC_8_PCREL;
800 case 2:
801 return BFD_RELOC_16_PCREL;
802 case 4:
803 return BFD_RELOC_32_PCREL;
804 }
805 }
806 else
807 {
808 switch (size)
809 {
810 case 1:
811 return BFD_RELOC_8;
812 case 2:
813 return BFD_RELOC_16;
814 case 4:
815 return BFD_RELOC_32;
816 }
817 }
818 }
819
820 if (pcrel)
821 {
822 if (pic == pic_none)
823 as_bad (_("Can not do %d byte pc-relative relocation"), size);
824 else
825 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
826 }
827 else
828 {
829 if (pic == pic_none)
830 as_bad (_("Can not do %d byte relocation"), size);
831 else
832 as_bad (_("Can not do %d byte pic relocation"), size);
833 }
834
835 return BFD_RELOC_NONE;
836}
837
838/* Here we decide which fixups can be adjusted to make them relative
839 to the beginning of the section instead of the symbol. Basically
840 we need to make sure that the dynamic relocations are done
841 correctly, so in some cases we force the original symbol to be
842 used. */
843int
844tc_m68k_fix_adjustable (fixP)
845 fixS *fixP;
846{
252b5132
RH		 847 /* adjust_reloc_syms doesn't know about the GOT */
848 switch (fixP->fx_r_type)
849 {
850 case BFD_RELOC_8_GOT_PCREL:
851 case BFD_RELOC_16_GOT_PCREL:
852 case BFD_RELOC_32_GOT_PCREL:
853 case BFD_RELOC_8_GOTOFF:
854 case BFD_RELOC_16_GOTOFF:
855 case BFD_RELOC_32_GOTOFF:
856 case BFD_RELOC_8_PLT_PCREL:
857 case BFD_RELOC_16_PLT_PCREL:
858 case BFD_RELOC_32_PLT_PCREL:
859 case BFD_RELOC_8_PLTOFF:
860 case BFD_RELOC_16_PLTOFF:
861 case BFD_RELOC_32_PLTOFF:
862 return 0;
863
864 case BFD_RELOC_VTABLE_INHERIT:
865 case BFD_RELOC_VTABLE_ENTRY:
866 return 0;
867
868 default:
869 return 1;
870 }
871}
872
873#else /* !OBJ_ELF */
874
875#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
876
c801568a
AM		 877#define relaxable_symbol(symbol) 1
878
252b5132
RH		 879#endif /* OBJ_ELF */
880
881#ifdef BFD_ASSEMBLER
882
883arelent *
884tc_gen_reloc (section, fixp)
f1f5ef86 885 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 886 fixS *fixp;
887{
888 arelent *reloc;
889 bfd_reloc_code_real_type code;
890
8ec6253e
NC		 891 /* If the tcbit is set, then this was a fixup of a negative value
892 that was never resolved. We do not have a reloc to handle this,
893 so just return. We assume that other code will have detected this
894 situation and produced a helpful error message, so we just tell the
895 user that the reloc cannot be produced. */
252b5132 896 if (fixp->fx_tcbit)
8ec6253e
NC		 897 {
898 if (fixp->fx_addsy)
b091f402
AM		 899 as_bad_where (fixp->fx_file, fixp->fx_line,
900 _("Unable to produce reloc against symbol '%s'"),
901 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 902 return NULL;
903 }
252b5132
RH		 904
905 if (fixp->fx_r_type != BFD_RELOC_NONE)
906 {
907 code = fixp->fx_r_type;
908
909 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
910 that fixup_segment converted a non-PC relative reloc into a
911 PC relative reloc. In such a case, we need to convert the
912 reloc code. */
913 if (fixp->fx_pcrel)
914 {
915 switch (code)
916 {
917 case BFD_RELOC_8:
918 code = BFD_RELOC_8_PCREL;
919 break;
920 case BFD_RELOC_16:
921 code = BFD_RELOC_16_PCREL;
922 break;
923 case BFD_RELOC_32:
924 code = BFD_RELOC_32_PCREL;
925 break;
926 case BFD_RELOC_8_PCREL:
927 case BFD_RELOC_16_PCREL:
928 case BFD_RELOC_32_PCREL:
929 case BFD_RELOC_8_GOT_PCREL:
930 case BFD_RELOC_16_GOT_PCREL:
931 case BFD_RELOC_32_GOT_PCREL:
932 case BFD_RELOC_8_GOTOFF:
933 case BFD_RELOC_16_GOTOFF:
934 case BFD_RELOC_32_GOTOFF:
935 case BFD_RELOC_8_PLT_PCREL:
936 case BFD_RELOC_16_PLT_PCREL:
937 case BFD_RELOC_32_PLT_PCREL:
938 case BFD_RELOC_8_PLTOFF:
939 case BFD_RELOC_16_PLTOFF:
940 case BFD_RELOC_32_PLTOFF:
941 break;
942 default:
943 as_bad_where (fixp->fx_file, fixp->fx_line,
944 _("Cannot make %s relocation PC relative"),
945 bfd_get_reloc_code_name (code));
946 }
947 }
948 }
949 else
950 {
951#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
952 switch (F (fixp->fx_size, fixp->fx_pcrel))
953 {
954#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
955 MAP (1, 0, BFD_RELOC_8);
956 MAP (2, 0, BFD_RELOC_16);
957 MAP (4, 0, BFD_RELOC_32);
958 MAP (1, 1, BFD_RELOC_8_PCREL);
959 MAP (2, 1, BFD_RELOC_16_PCREL);
960 MAP (4, 1, BFD_RELOC_32_PCREL);
961 default:
962 abort ();
963 }
964 }
965#undef F
966#undef MAP
967
968 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 969 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
970 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 971 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
972#ifndef OBJ_ELF
973 if (fixp->fx_pcrel)
974 reloc->addend = fixp->fx_addnumber;
975 else
976 reloc->addend = 0;
977#else
978 if (!fixp->fx_pcrel)
979 reloc->addend = fixp->fx_addnumber;
980 else
981 reloc->addend = (section->vma
8390138c
AS		 982 /* Explicit sign extension in case char is
983 unsigned. */
984 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 985 + fixp->fx_addnumber
986 + md_pcrel_from (fixp));
987#endif
988
989 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
990 assert (reloc->howto != 0);
991
992 return reloc;
993}
994
995#endif /* BFD_ASSEMBLER */
996
252b5132
RH		 997/* Handle of the OPCODE hash table. NULL means any use before
998 m68k_ip_begin() will crash. */
999static struct hash_control *op_hash;
1000\f
1001/* Assemble an m68k instruction. */
1002
1003static void
1004m68k_ip (instring)
1005 char *instring;
1006{
1007 register char *p;
1008 register struct m68k_op *opP;
1009 register const struct m68k_incant *opcode;
1010 register const char *s;
1011 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1012 char *pdot, *pdotmove;
1013 enum m68k_size siz1, siz2;
1014 char c;
1015 int losing;
1016 int opsfound;
1017 LITTLENUM_TYPE words[6];
1018 LITTLENUM_TYPE *wordp;
1019 unsigned long ok_arch = 0;
1020
1021 if (*instring == ' ')
1022 instring++; /* skip leading whitespace */
1023
1024 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1025 or exactly 1 space. */
252b5132
RH		 1026 pdot = 0;
1027 for (p = instring; *p != '\0'; p++)
1028 {
1029 if (*p == ' ')
1030 break;
1031 if (*p == '.')
1032 pdot = p;
1033 }
1034
1035 if (p == instring)
1036 {
1037 the_ins.error = _("No operator");
1038 return;
1039 }
1040
1041 /* p now points to the end of the opcode name, probably whitespace.
1042 Make sure the name is null terminated by clobbering the
1043 whitespace, look it up in the hash table, then fix it back.
1044 Remove a dot, first, since the opcode tables have none. */
1045 if (pdot != NULL)
1046 {
1047 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1048 *pdotmove = pdotmove[1];
1049 p--;
1050 }
1051
1052 c = *p;
1053 *p = '\0';
1054 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1055 *p = c;
1056
1057 if (pdot != NULL)
1058 {
1059 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1060 *pdotmove = pdotmove[-1];
1061 *pdot = '.';
1062 ++p;
1063 }
1064
1065 if (opcode == NULL)
1066 {
1067 the_ins.error = _("Unknown operator");
1068 return;
1069 }
1070
1071 /* found a legitimate opcode, start matching operands */
1072 while (*p == ' ')
1073 ++p;
1074
1075 if (opcode->m_operands == 0)
1076 {
1077 char *old = input_line_pointer;
1078 *old = '\n';
1079 input_line_pointer = p;
1080 /* Ahh - it's a motorola style psuedo op */
1081 mote_pseudo_table[opcode->m_opnum].poc_handler
1082 (mote_pseudo_table[opcode->m_opnum].poc_val);
1083 input_line_pointer = old;
1084 *old = 0;
1085
1086 return;
1087 }
1088
1089 if (flag_mri && opcode->m_opnum == 0)
1090 {
1091 /* In MRI mode, random garbage is allowed after an instruction
1092 which accepts no operands. */
1093 the_ins.args = opcode->m_operands;
1094 the_ins.numargs = opcode->m_opnum;
1095 the_ins.numo = opcode->m_codenum;
1096 the_ins.opcode[0] = getone (opcode);
1097 the_ins.opcode[1] = gettwo (opcode);
1098 return;
1099 }
1100
1101 for (opP = &the_ins.operands[0]; *p; opP++)
1102 {
1103 p = crack_operand (p, opP);
1104
1105 if (opP->error)
1106 {
1107 the_ins.error = opP->error;
1108 return;
1109 }
1110 }
1111
1112 opsfound = opP - &the_ins.operands[0];
1113
1114 /* This ugly hack is to support the floating pt opcodes in their
1115 standard form. Essentially, we fake a first enty of type COP#1 */
1116 if (opcode->m_operands[0] == 'I')
1117 {
1118 int n;
1119
1120 for (n = opsfound; n > 0; --n)
1121 the_ins.operands[n] = the_ins.operands[n - 1];
1122
1123 memset ((char *) (&the_ins.operands[0]), '\0',
1124 sizeof (the_ins.operands[0]));
1125 the_ins.operands[0].mode = CONTROL;
1126 the_ins.operands[0].reg = m68k_float_copnum;
1127 opsfound++;
1128 }
1129
1130 /* We've got the operands. Find an opcode that'll accept them */
1131 for (losing = 0;;)
1132 {
1133 /* If we didn't get the right number of ops, or we have no
92774660 1134 common model with this pattern then reject this pattern. */
252b5132
RH		 1135
1136 ok_arch |= opcode->m_arch;
1137 if (opsfound != opcode->m_opnum
1138 || ((opcode->m_arch & current_architecture) == 0))
1139 ++losing;
1140 else
1141 {
1142 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1143 *s && !losing;
1144 s += 2, opP++)
1145 {
1146 /* Warning: this switch is huge! */
1147 /* I've tried to organize the cases into this order:
1148 non-alpha first, then alpha by letter. Lower-case
1149 goes directly before uppercase counterpart. */
1150 /* Code with multiple case ...: gets sorted by the lowest
1151 case ... it belongs to. I hope this makes sense. */
1152 switch (*s)
1153 {
1154 case '!':
1155 switch (opP->mode)
1156 {
1157 case IMMED:
1158 case DREG:
1159 case AREG:
1160 case FPREG:
1161 case CONTROL:
1162 case AINC:
1163 case ADEC:
1164 case REGLST:
1165 losing++;
1166 break;
1167 default:
1168 break;
1169 }
1170 break;
1171
1172 case '<':
1173 switch (opP->mode)
1174 {
1175 case DREG:
1176 case AREG:
1177 case FPREG:
1178 case CONTROL:
1179 case IMMED:
1180 case ADEC:
1181 case REGLST:
1182 losing++;
1183 break;
1184 default:
1185 break;
1186 }
1187 break;
1188
1189 case '>':
1190 switch (opP->mode)
1191 {
1192 case DREG:
1193 case AREG:
1194 case FPREG:
1195 case CONTROL:
1196 case IMMED:
1197 case AINC:
1198 case REGLST:
1199 losing++;
1200 break;
1201 case ABSL:
1202 break;
1203 default:
1204 if (opP->reg == PC
1205 || opP->reg == ZPC)
1206 losing++;
1207 break;
1208 }
1209 break;
1210
1211 case 'm':
1212 switch (opP->mode)
1213 {
1214 case DREG:
1215 case AREG:
1216 case AINDR:
1217 case AINC:
1218 case ADEC:
1219 break;
1220 default:
1221 losing++;
1222 }
8a104df9 1223 break;
252b5132
RH		 1224
1225 case 'n':
1226 switch (opP->mode)
1227 {
1228 case DISP:
1229 break;
1230 default:
1231 losing++;
1232 }
8a104df9 1233 break;
252b5132
RH		 1234
1235 case 'o':
1236 switch (opP->mode)
1237 {
1238 case BASE:
1239 case ABSL:
1240 case IMMED:
1241 break;
1242 default:
1243 losing++;
1244 }
8a104df9 1245 break;
252b5132
RH		 1246
1247 case 'p':
1248 switch (opP->mode)
1249 {
1250 case DREG:
1251 case AREG:
1252 case AINDR:
1253 case AINC:
1254 case ADEC:
1255 break;
1256 case DISP:
1257 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1258 losing++;
252b5132
RH		 1259 break;
1260 default:
1261 losing++;
1262 }
8a104df9 1263 break;
252b5132
RH		 1264
1265 case 'q':
1266 switch (opP->mode)
1267 {
1268 case DREG:
1269 case AINDR:
1270 case AINC:
1271 case ADEC:
1272 break;
1273 case DISP:
1274 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1275 losing++;
252b5132
RH		 1276 break;
1277 default:
1278 losing++;
1279 break;
1280 }
8a104df9 1281 break;
252b5132
RH		 1282
1283 case 'v':
1284 switch (opP->mode)
1285 {
1286 case DREG:
1287 case AINDR:
1288 case AINC:
1289 case ADEC:
1290 case ABSL:
1291 break;
1292 case DISP:
1293 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1294 losing++;
252b5132
RH		 1295 break;
1296 default:
1297 losing++;
1298 break;
1299 }
1300 break;
1301
1302 case '#':
1303 if (opP->mode != IMMED)
1304 losing++;
1305 else if (s[1] == 'b'
1306 && ! isvar (&opP->disp)
1307 && (opP->disp.exp.X_op != O_constant
1308 || ! isbyte (opP->disp.exp.X_add_number)))
1309 losing++;
1310 else if (s[1] == 'B'
1311 && ! isvar (&opP->disp)
1312 && (opP->disp.exp.X_op != O_constant
1313 || ! issbyte (opP->disp.exp.X_add_number)))
1314 losing++;
1315 else if (s[1] == 'w'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! isword (opP->disp.exp.X_add_number)))
1319 losing++;
1320 else if (s[1] == 'W'
1321 && ! isvar (&opP->disp)
1322 && (opP->disp.exp.X_op != O_constant
1323 || ! issword (opP->disp.exp.X_add_number)))
1324 losing++;
1325 break;
1326
1327 case '^':
1328 case 'T':
1329 if (opP->mode != IMMED)
1330 losing++;
1331 break;
1332
1333 case '$':
1334 if (opP->mode == AREG
1335 || opP->mode == CONTROL
1336 || opP->mode == FPREG
1337 || opP->mode == IMMED
1338 || opP->mode == REGLST
1339 || (opP->mode != ABSL
1340 && (opP->reg == PC
1341 || opP->reg == ZPC)))
1342 losing++;
1343 break;
1344
1345 case '%':
1346 if (opP->mode == CONTROL
1347 || opP->mode == FPREG
1348 || opP->mode == REGLST
1349 || opP->mode == IMMED
1350 || (opP->mode != ABSL
1351 && (opP->reg == PC
1352 || opP->reg == ZPC)))
1353 losing++;
1354 break;
1355
1356 case '&':
1357 switch (opP->mode)
1358 {
1359 case DREG:
1360 case AREG:
1361 case FPREG:
1362 case CONTROL:
1363 case IMMED:
1364 case AINC:
1365 case ADEC:
1366 case REGLST:
1367 losing++;
1368 break;
1369 case ABSL:
1370 break;
1371 default:
1372 if (opP->reg == PC
1373 || opP->reg == ZPC)
1374 losing++;
1375 break;
1376 }
1377 break;
1378
1379 case '*':
1380 if (opP->mode == CONTROL
1381 || opP->mode == FPREG
1382 || opP->mode == REGLST)
1383 losing++;
1384 break;
1385
1386 case '+':
1387 if (opP->mode != AINC)
1388 losing++;
1389 break;
1390
1391 case '-':
1392 if (opP->mode != ADEC)
1393 losing++;
1394 break;
1395
1396 case '/':
1397 switch (opP->mode)
1398 {
1399 case AREG:
1400 case CONTROL:
1401 case FPREG:
1402 case AINC:
1403 case ADEC:
1404 case IMMED:
1405 case REGLST:
1406 losing++;
1407 break;
1408 default:
1409 break;
1410 }
1411 break;
1412
1413 case ';':
1414 switch (opP->mode)
1415 {
1416 case AREG:
1417 case CONTROL:
1418 case FPREG:
1419 case REGLST:
1420 losing++;
1421 break;
1422 default:
1423 break;
1424 }
1425 break;
1426
1427 case '?':
1428 switch (opP->mode)
1429 {
1430 case AREG:
1431 case CONTROL:
1432 case FPREG:
1433 case AINC:
1434 case ADEC:
1435 case IMMED:
1436 case REGLST:
1437 losing++;
1438 break;
1439 case ABSL:
1440 break;
1441 default:
1442 if (opP->reg == PC || opP->reg == ZPC)
1443 losing++;
1444 break;
1445 }
1446 break;
1447
1448 case '@':
1449 switch (opP->mode)
1450 {
1451 case AREG:
1452 case CONTROL:
1453 case FPREG:
1454 case IMMED:
1455 case REGLST:
1456 losing++;
1457 break;
1458 default:
1459 break;
1460 }
1461 break;
1462
1463 case '~': /* For now! (JF FOO is this right?) */
1464 switch (opP->mode)
1465 {
1466 case DREG:
1467 case AREG:
1468 case CONTROL:
1469 case FPREG:
1470 case IMMED:
1471 case REGLST:
1472 losing++;
1473 break;
1474 case ABSL:
1475 break;
1476 default:
1477 if (opP->reg == PC
1478 || opP->reg == ZPC)
1479 losing++;
1480 break;
1481 }
1482 break;
1483
1484 case '3':
1485 if (opP->mode != CONTROL
1486 || (opP->reg != TT0 && opP->reg != TT1))
1487 losing++;
1488 break;
1489
1490 case 'A':
1491 if (opP->mode != AREG)
1492 losing++;
1493 break;
1494
1495 case 'a':
1496 if (opP->mode != AINDR)
1497 ++losing;
1498 break;
1499
1500 case 'B': /* FOO */
1501 if (opP->mode != ABSL
1502 || (flag_long_jumps
1503 && strncmp (instring, "jbsr", 4) == 0))
1504 losing++;
1505 break;
1506
1507 case 'C':
1508 if (opP->mode != CONTROL || opP->reg != CCR)
1509 losing++;
1510 break;
1511
1512 case 'd':
1513 if (opP->mode != DISP
1514 || opP->reg < ADDR0
1515 || opP->reg > ADDR7)
1516 losing++;
1517 break;
1518
1519 case 'D':
1520 if (opP->mode != DREG)
1521 losing++;
1522 break;
1523
6da466c7
ILT		 1524 case 'E':
1525 if (opP->reg != ACC)
1526 losing++;
1527 break;
1528
252b5132
RH		 1529 case 'F':
1530 if (opP->mode != FPREG)
1531 losing++;
1532 break;
1533
6da466c7
ILT		 1534 case 'G':
1535 if (opP->reg != MACSR)
1536 losing++;
1537 break;
1538
1539 case 'H':
1540 if (opP->reg != MASK)
1541 losing++;
1542 break;
1543
252b5132
RH		 1544 case 'I':
1545 if (opP->mode != CONTROL
1546 || opP->reg < COP0
1547 || opP->reg > COP7)
1548 losing++;
1549 break;
1550
1551 case 'J':
1552 if (opP->mode != CONTROL
1553 || opP->reg < USP
1554 || opP->reg > last_movec_reg)
1555 losing++;
1556 else
1557 {
1558 const enum m68k_register *rp;
1559 for (rp = control_regs; *rp; rp++)
1560 if (*rp == opP->reg)
1561 break;
1562 if (*rp == 0)
1563 losing++;
1564 }
1565 break;
1566
1567 case 'k':
1568 if (opP->mode != IMMED)
1569 losing++;
1570 break;
1571
1572 case 'l':
1573 case 'L':
1574 if (opP->mode == DREG
1575 || opP->mode == AREG
1576 || opP->mode == FPREG)
1577 {
1578 if (s[1] == '8')
1579 losing++;
1580 else
1581 {
1582 switch (opP->mode)
1583 {
1584 case DREG:
1585 opP->mask = 1 << (opP->reg - DATA0);
1586 break;
1587 case AREG:
1588 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1589 break;
1590 case FPREG:
1591 opP->mask = 1 << (opP->reg - FP0 + 16);
1592 break;
1593 default:
1594 abort ();
1595 }
1596 opP->mode = REGLST;
1597 }
1598 }
1599 else if (opP->mode == CONTROL)
1600 {
1601 if (s[1] != '8')
1602 losing++;
1603 else
1604 {
1605 switch (opP->reg)
1606 {
1607 case FPI:
1608 opP->mask = 1 << 24;
1609 break;
1610 case FPS:
1611 opP->mask = 1 << 25;
1612 break;
1613 case FPC:
1614 opP->mask = 1 << 26;
1615 break;
1616 default:
1617 losing++;
1618 break;
1619 }
1620 opP->mode = REGLST;
1621 }
1622 }
1623 else if (opP->mode != REGLST)
1624 losing++;
1625 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1626 losing++;
1627 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1628 losing++;
1629 break;
1630
1631 case 'M':
1632 if (opP->mode != IMMED)
1633 losing++;
1634 else if (opP->disp.exp.X_op != O_constant
1635 || ! issbyte (opP->disp.exp.X_add_number))
1636 losing++;
1637 else if (! m68k_quick
1638 && instring[3] != 'q'
1639 && instring[4] != 'q')
1640 losing++;
1641 break;
1642
1643 case 'O':
1644 if (opP->mode != DREG
1645 && opP->mode != IMMED
1646 && opP->mode != ABSL)
1647 losing++;
1648 break;
1649
1650 case 'Q':
1651 if (opP->mode != IMMED)
1652 losing++;
1653 else if (opP->disp.exp.X_op != O_constant
1654 || opP->disp.exp.X_add_number < 1
1655 || opP->disp.exp.X_add_number > 8)
1656 losing++;
1657 else if (! m68k_quick
1658 && (strncmp (instring, "add", 3) == 0
1659 || strncmp (instring, "sub", 3) == 0)
1660 && instring[3] != 'q')
1661 losing++;
1662 break;
1663
1664 case 'R':
1665 if (opP->mode != DREG && opP->mode != AREG)
1666 losing++;
1667 break;
1668
1669 case 'r':
1670 if (opP->mode != AINDR
1671 && (opP->mode != BASE
1672 || (opP->reg != 0
1673 && opP->reg != ZADDR0)
1674 || opP->disp.exp.X_op != O_absent
1675 || ((opP->index.reg < DATA0
1676 || opP->index.reg > DATA7)
1677 && (opP->index.reg < ADDR0
1678 || opP->index.reg > ADDR7))
1679 || opP->index.size != SIZE_UNSPEC
1680 || opP->index.scale != 1))
1681 losing++;
1682 break;
1683
1684 case 's':
1685 if (opP->mode != CONTROL
1686 || ! (opP->reg == FPI
1687 || opP->reg == FPS
1688 || opP->reg == FPC))
1689 losing++;
1690 break;
1691
1692 case 'S':
1693 if (opP->mode != CONTROL || opP->reg != SR)
1694 losing++;
1695 break;
1696
1697 case 't':
1698 if (opP->mode != IMMED)
1699 losing++;
1700 else if (opP->disp.exp.X_op != O_constant
1701 || opP->disp.exp.X_add_number < 0
1702 || opP->disp.exp.X_add_number > 7)
1703 losing++;
1704 break;
1705
1706 case 'U':
1707 if (opP->mode != CONTROL || opP->reg != USP)
1708 losing++;
1709 break;
1710
1711 /* JF these are out of order. We could put them
1712 in order if we were willing to put up with
1713 bunches of #ifdef m68851s in the code.
1714
1715 Don't forget that you need these operands
1716 to use 68030 MMU instructions. */
1717#ifndef NO_68851
1718 /* Memory addressing mode used by pflushr */
1719 case '|':
1720 if (opP->mode == CONTROL
1721 || opP->mode == FPREG
1722 || opP->mode == DREG
1723 || opP->mode == AREG
1724 || opP->mode == REGLST)
1725 losing++;
1726 /* We should accept immediate operands, but they
1727 supposedly have to be quad word, and we don't
1728 handle that. I would like to see what a Motorola
1729 assembler does before doing something here. */
1730 if (opP->mode == IMMED)
1731 losing++;
1732 break;
1733
1734 case 'f':
1735 if (opP->mode != CONTROL
1736 || (opP->reg != SFC && opP->reg != DFC))
1737 losing++;
1738 break;
1739
1740 case '0':
1741 if (opP->mode != CONTROL || opP->reg != TC)
1742 losing++;
1743 break;
1744
1745 case '1':
1746 if (opP->mode != CONTROL || opP->reg != AC)
1747 losing++;
1748 break;
1749
1750 case '2':
1751 if (opP->mode != CONTROL
1752 || (opP->reg != CAL
1753 && opP->reg != VAL
1754 && opP->reg != SCC))
1755 losing++;
1756 break;
1757
1758 case 'V':
1759 if (opP->mode != CONTROL
1760 || opP->reg != VAL)
1761 losing++;
1762 break;
1763
1764 case 'W':
1765 if (opP->mode != CONTROL
1766 || (opP->reg != DRP
1767 && opP->reg != SRP
1768 && opP->reg != CRP))
1769 losing++;
1770 break;
1771
1772 case 'X':
1773 if (opP->mode != CONTROL
1774 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1775 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1776 losing++;
1777 break;
1778
1779 case 'Y':
1780 if (opP->mode != CONTROL || opP->reg != PSR)
1781 losing++;
1782 break;
1783
1784 case 'Z':
1785 if (opP->mode != CONTROL || opP->reg != PCSR)
1786 losing++;
1787 break;
1788#endif
1789 case 'c':
1790 if (opP->mode != CONTROL
1791 || (opP->reg != NC
1792 && opP->reg != IC
1793 && opP->reg != DC
1794 && opP->reg != BC))
1795 {
1796 losing++;
92774660 1797 } /* not a cache specifier. */
252b5132
RH		 1798 break;
1799
1800 case '_':
1801 if (opP->mode != ABSL)
1802 ++losing;
1803 break;
1804
6da466c7
ILT		 1805 case 'u':
1806 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1807 losing++;
1808 /* FIXME: kludge instead of fixing parser:
1809 upper/lower registers are *not* CONTROL
92774660 1810 registers, but ordinary ones. */
6da466c7
ILT		 1811 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1812 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1813 opP->mode = DREG;
1814 else
1815 opP->mode = AREG;
1816 break;
1817
252b5132
RH		 1818 default:
1819 abort ();
1820 } /* switch on type of operand */
1821
1822 if (losing)
1823 break;
1824 } /* for each operand */
1825 } /* if immediately wrong */
1826
1827 if (!losing)
1828 {
1829 break;
92774660 1830 } /* got it. */
252b5132
RH		 1831
1832 opcode = opcode->m_next;
1833
1834 if (!opcode)
1835 {
1836 if (ok_arch
1837 && !(ok_arch & current_architecture))
1838 {
1839 char buf[200], *cp;
1840
1841 strcpy (buf,
1842 _("invalid instruction for this architecture; needs "));
1843 cp = buf + strlen (buf);
1844 switch (ok_arch)
1845 {
1846 case mfloat:
1847 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1848 break;
1849 case mmmu:
1850 strcpy (cp, _("mmu (68030 or 68851)"));
1851 break;
1852 case m68020up:
1853 strcpy (cp, _("68020 or higher"));
1854 break;
1855 case m68000up:
1856 strcpy (cp, _("68000 or higher"));
1857 break;
1858 case m68010up:
1859 strcpy (cp, _("68010 or higher"));
1860 break;
1861 default:
1862 {
1863 int got_one = 0, idx;
8fce3f5e
AM		 1864 for (idx = 0;
1865 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1866 idx++)
1867 {
1868 if ((archs[idx].arch & ok_arch)
1869 && ! archs[idx].alias)
1870 {
1871 if (got_one)
1872 {
1873 strcpy (cp, " or ");
1874 cp += strlen (cp);
1875 }
1876 got_one = 1;
1877 strcpy (cp, archs[idx].name);
1878 cp += strlen (cp);
1879 }
1880 }
1881 }
1882 }
1883 cp = xmalloc (strlen (buf) + 1);
1884 strcpy (cp, buf);
1885 the_ins.error = cp;
1886 }
1887 else
1888 the_ins.error = _("operands mismatch");
1889 return;
1890 } /* Fell off the end */
1891
1892 losing = 0;
1893 }
1894
1895 /* now assemble it */
1896
1897 the_ins.args = opcode->m_operands;
1898 the_ins.numargs = opcode->m_opnum;
1899 the_ins.numo = opcode->m_codenum;
1900 the_ins.opcode[0] = getone (opcode);
1901 the_ins.opcode[1] = gettwo (opcode);
1902
1903 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1904 {
1905 /* This switch is a doozy.
1906 Watch the first step; its a big one! */
1907 switch (s[0])
1908 {
1909
1910 case '*':
1911 case '~':
1912 case '%':
1913 case ';':
1914 case '@':
1915 case '!':
1916 case '&':
1917 case '$':
1918 case '?':
1919 case '/':
1920 case '<':
1921 case '>':
1922 case 'm':
1923 case 'n':
1924 case 'o':
1925 case 'p':
1926 case 'q':
1927 case 'v':
1928#ifndef NO_68851
1929 case '|':
1930#endif
1931 switch (opP->mode)
1932 {
1933 case IMMED:
1934 tmpreg = 0x3c; /* 7.4 */
1935 if (strchr ("bwl", s[1]))
1936 nextword = get_num (&opP->disp, 80);
1937 else
1938 nextword = get_num (&opP->disp, 0);
1939 if (isvar (&opP->disp))
1940 add_fix (s[1], &opP->disp, 0, 0);
1941 switch (s[1])
1942 {
1943 case 'b':
1944 if (!isbyte (nextword))
1945 opP->error = _("operand out of range");
1946 addword (nextword);
1947 baseo = 0;
1948 break;
1949 case 'w':
1950 if (!isword (nextword))
1951 opP->error = _("operand out of range");
1952 addword (nextword);
1953 baseo = 0;
1954 break;
1955 case 'W':
1956 if (!issword (nextword))
1957 opP->error = _("operand out of range");
1958 addword (nextword);
1959 baseo = 0;
1960 break;
1961 case 'l':
1962 addword (nextword >> 16);
1963 addword (nextword);
1964 baseo = 0;
1965 break;
1966
1967 case 'f':
1968 baseo = 2;
1969 outro = 8;
1970 break;
1971 case 'F':
1972 baseo = 4;
1973 outro = 11;
1974 break;
1975 case 'x':
1976 baseo = 6;
1977 outro = 15;
1978 break;
1979 case 'p':
1980 baseo = 6;
1981 outro = -1;
1982 break;
1983 default:
1984 abort ();
1985 }
1986 if (!baseo)
1987 break;
1988
1989 /* We gotta put out some float */
1990 if (op (&opP->disp) != O_big)
1991 {
1992 valueT val;
1993 int gencnt;
1994
1995 /* Can other cases happen here? */
1996 if (op (&opP->disp) != O_constant)
1997 abort ();
1998
1999 val = (valueT) offs (&opP->disp);
2000 gencnt = 0;
2001 do
2002 {
2003 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2004 val >>= LITTLENUM_NUMBER_OF_BITS;
2005 ++gencnt;
2006 }
2007 while (val != 0);
2008 offs (&opP->disp) = gencnt;
2009 }
2010 if (offs (&opP->disp) > 0)
2011 {
2012 if (offs (&opP->disp) > baseo)
2013 {
2014 as_warn (_("Bignum too big for %c format; truncated"),
2015 s[1]);
2016 offs (&opP->disp) = baseo;
2017 }
2018 baseo -= offs (&opP->disp);
2019 while (baseo--)
2020 addword (0);
2021 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2022 offs (&opP->disp)--;
2023 --wordp)
2024 addword (*wordp);
2025 break;
2026 }
2027 gen_to_words (words, baseo, (long) outro);
2028 for (wordp = words; baseo--; wordp++)
2029 addword (*wordp);
2030 break;
2031 case DREG:
2032 tmpreg = opP->reg - DATA; /* 0.dreg */
2033 break;
2034 case AREG:
2035 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2036 break;
2037 case AINDR:
2038 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2039 break;
2040 case ADEC:
2041 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2042 break;
2043 case AINC:
2044 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2045 break;
2046 case DISP:
2047
2048 nextword = get_num (&opP->disp, 80);
2049
2050 if (opP->reg == PC
2051 && ! isvar (&opP->disp)
2052 && m68k_abspcadd)
2053 {
2054 opP->disp.exp.X_op = O_symbol;
2055#ifndef BFD_ASSEMBLER
2056 opP->disp.exp.X_add_symbol = &abs_symbol;
2057#else
2058 opP->disp.exp.X_add_symbol =
2059 section_symbol (absolute_section);
2060#endif
2061 }
2062
2063 /* Force into index mode. Hope this works */
2064
2065 /* We do the first bit for 32-bit displacements, and the
2066 second bit for 16 bit ones. It is possible that we
2067 should make the default be WORD instead of LONG, but
2068 I think that'd break GCC, so we put up with a little
2069 inefficiency for the sake of working output. */
2070
2071 if (!issword (nextword)
2072 || (isvar (&opP->disp)
2073 && ((opP->disp.size == SIZE_UNSPEC
2074 && flag_short_refs == 0
2075 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2076 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2077 || opP->disp.size == SIZE_LONG)))
2078 {
2079 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2080 || arch_coldfire_p (current_architecture))
252b5132
RH		 2081 opP->error =
2082 _("displacement too large for this architecture; needs 68020 or higher");
2083 if (opP->reg == PC)
2084 tmpreg = 0x3B; /* 7.3 */
2085 else
2086 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2087 if (isvar (&opP->disp))
2088 {
2089 if (opP->reg == PC)
2090 {
2091 if (opP->disp.size == SIZE_LONG
2092#ifdef OBJ_ELF
2093 /* If the displacement needs pic
2094 relocation it cannot be relaxed. */
2095 || opP->disp.pic_reloc != pic_none
2096#endif
2097 )
2098 {
2099 addword (0x0170);
2100 add_fix ('l', &opP->disp, 1, 2);
2101 }
2102 else
2103 {
2104 add_frag (adds (&opP->disp),
2105 offs (&opP->disp),
151337e8 2106 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2107 break;
2108 }
2109 }
2110 else
2111 {
2112 addword (0x0170);
2113 add_fix ('l', &opP->disp, 0, 0);
2114 }
2115 }
2116 else
2117 addword (0x0170);
2118 addword (nextword >> 16);
2119 }
2120 else
2121 {
2122 if (opP->reg == PC)
2123 tmpreg = 0x3A; /* 7.2 */
2124 else
2125 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2126
2127 if (isvar (&opP->disp))
2128 {
2129 if (opP->reg == PC)
2130 {
2131 add_fix ('w', &opP->disp, 1, 0);
2132 }
2133 else
2134 add_fix ('w', &opP->disp, 0, 0);
2135 }
2136 }
2137 addword (nextword);
2138 break;
2139
2140 case POST:
2141 case PRE:
2142 case BASE:
2143 nextword = 0;
2144 baseo = get_num (&opP->disp, 80);
2145 if (opP->mode == POST || opP->mode == PRE)
2146 outro = get_num (&opP->odisp, 80);
2147 /* Figure out the `addressing mode'.
2148 Also turn on the BASE_DISABLE bit, if needed. */
2149 if (opP->reg == PC || opP->reg == ZPC)
2150 {
2151 tmpreg = 0x3b; /* 7.3 */
2152 if (opP->reg == ZPC)
2153 nextword |= 0x80;
2154 }
2155 else if (opP->reg == 0)
2156 {
2157 nextword |= 0x80;
2158 tmpreg = 0x30; /* 6.garbage */
2159 }
2160 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2161 {
2162 nextword |= 0x80;
2163 tmpreg = 0x30 + opP->reg - ZADDR0;
2164 }
2165 else
2166 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2167
2168 siz1 = opP->disp.size;
2169 if (opP->mode == POST || opP->mode == PRE)
2170 siz2 = opP->odisp.size;
2171 else
2172 siz2 = SIZE_UNSPEC;
2173
2174 /* Index register stuff */
2175 if (opP->index.reg != 0
2176 && opP->index.reg >= DATA
2177 && opP->index.reg <= ADDR7)
2178 {
2179 nextword |= (opP->index.reg - DATA) << 12;
2180
2181 if (opP->index.size == SIZE_LONG
2182 || (opP->index.size == SIZE_UNSPEC
2183 && m68k_index_width_default == SIZE_LONG))
2184 nextword |= 0x800;
2185
92774660 2186 if ((opP->index.scale != 1
252b5132 2187 && cpu_of_arch (current_architecture) < m68020)
92774660 2188 || (opP->index.scale == 8
6da466c7 2189 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2190 {
2191 opP->error =
2192 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2193 }
2194
6da466c7
ILT		 2195 if (arch_coldfire_p (current_architecture)
2196 && opP->index.size == SIZE_WORD)
2197 opP->error = _("invalid index size for coldfire");
2198
252b5132
RH		 2199 switch (opP->index.scale)
2200 {
2201 case 1:
2202 break;
2203 case 2:
2204 nextword |= 0x200;
2205 break;
2206 case 4:
2207 nextword |= 0x400;
2208 break;
2209 case 8:
2210 nextword |= 0x600;
2211 break;
2212 default:
2213 abort ();
2214 }
2215 /* IF its simple,
2216 GET US OUT OF HERE! */
2217
2218 /* Must be INDEX, with an index register. Address
2219 register cannot be ZERO-PC, and either :b was
2220 forced, or we know it will fit. For a 68000 or
2221 68010, force this mode anyways, because the
2222 larger modes aren't supported. */
2223 if (opP->mode == BASE
2224 && ((opP->reg >= ADDR0
2225 && opP->reg <= ADDR7)
2226 || opP->reg == PC))
2227 {
2228 if (siz1 == SIZE_BYTE
2229 || cpu_of_arch (current_architecture) < m68020
6da466c7 2230 || arch_coldfire_p (current_architecture)
252b5132
RH		 2231 || (siz1 == SIZE_UNSPEC
2232 && ! isvar (&opP->disp)
2233 && issbyte (baseo)))
2234 {
2235 nextword += baseo & 0xff;
2236 addword (nextword);
2237 if (isvar (&opP->disp))
2238 {
2239 /* Do a byte relocation. If it doesn't
2240 fit (possible on m68000) let the
2241 fixup processing complain later. */
2242 if (opP->reg == PC)
2243 add_fix ('B', &opP->disp, 1, 1);
2244 else
2245 add_fix ('B', &opP->disp, 0, 0);
2246 }
2247 else if (siz1 != SIZE_BYTE)
2248 {
2249 if (siz1 != SIZE_UNSPEC)
2250 as_warn (_("Forcing byte displacement"));
2251 if (! issbyte (baseo))
2252 opP->error = _("byte displacement out of range");
2253 }
2254
2255 break;
2256 }
2257 else if (siz1 == SIZE_UNSPEC
2258 && opP->reg == PC
2259 && isvar (&opP->disp)
2260 && subs (&opP->disp) == NULL
2261#ifdef OBJ_ELF
2262 /* If the displacement needs pic
2263 relocation it cannot be relaxed. */
2264 && opP->disp.pic_reloc == pic_none
2265#endif
2266 )
2267 {
2268 /* The code in md_convert_frag_1 needs to be
2269 able to adjust nextword. Call frag_grow
2270 to ensure that we have enough space in
2271 the frag obstack to make all the bytes
2272 contiguous. */
2273 frag_grow (14);
8a104df9
KH		 2274 nextword += baseo & 0xff;
2275 addword (nextword);
2276 add_frag (adds (&opP->disp), offs (&opP->disp),
2277 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2278
2279 break;
8a104df9 2280 }
252b5132
RH		 2281 }
2282 }
2283 else
2284 {
2285 nextword |= 0x40; /* No index reg */
2286 if (opP->index.reg >= ZDATA0
2287 && opP->index.reg <= ZDATA7)
2288 nextword |= (opP->index.reg - ZDATA0) << 12;
2289 else if (opP->index.reg >= ZADDR0
2290 || opP->index.reg <= ZADDR7)
2291 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2292 }
2293
2294 /* It isn't simple. */
2295
2296 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2297 || arch_coldfire_p (current_architecture))
252b5132
RH		 2298 opP->error =
2299 _("invalid operand mode for this architecture; needs 68020 or higher");
2300
2301 nextword |= 0x100;
2302 /* If the guy specified a width, we assume that it is
2303 wide enough. Maybe it isn't. If so, we lose. */
2304 switch (siz1)
2305 {
2306 case SIZE_UNSPEC:
2307 if (isvar (&opP->disp)
2308 ? m68k_rel32
2309 : ! issword (baseo))
2310 {
2311 siz1 = SIZE_LONG;
2312 nextword |= 0x30;
2313 }
2314 else if (! isvar (&opP->disp) && baseo == 0)
2315 nextword |= 0x10;
2316 else
2317 {
2318 nextword |= 0x20;
2319 siz1 = SIZE_WORD;
2320 }
2321 break;
2322 case SIZE_BYTE:
2323 as_warn (_(":b not permitted; defaulting to :w"));
2324 /* Fall through. */
2325 case SIZE_WORD:
2326 nextword |= 0x20;
2327 break;
2328 case SIZE_LONG:
2329 nextword |= 0x30;
2330 break;
2331 }
2332
2333 /* Figure out innner displacement stuff */
2334 if (opP->mode == POST || opP->mode == PRE)
2335 {
2336 if (cpu_of_arch (current_architecture) & cpu32)
2337 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2338 switch (siz2)
2339 {
2340 case SIZE_UNSPEC:
2341 if (isvar (&opP->odisp)
2342 ? m68k_rel32
2343 : ! issword (outro))
2344 {
2345 siz2 = SIZE_LONG;
2346 nextword |= 0x3;
2347 }
2348 else if (! isvar (&opP->odisp) && outro == 0)
2349 nextword |= 0x1;
2350 else
2351 {
2352 nextword |= 0x2;
2353 siz2 = SIZE_WORD;
2354 }
2355 break;
2356 case 1:
2357 as_warn (_(":b not permitted; defaulting to :w"));
2358 /* Fall through. */
2359 case 2:
2360 nextword |= 0x2;
2361 break;
2362 case 3:
2363 nextword |= 0x3;
2364 break;
2365 }
2366 if (opP->mode == POST
2367 && (nextword & 0x40) == 0)
2368 nextword |= 0x04;
2369 }
2370 addword (nextword);
2371
2372 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2373 {
2374 if (opP->reg == PC || opP->reg == ZPC)
2375 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2376 else
2377 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2378 }
2379 if (siz1 == SIZE_LONG)
2380 addword (baseo >> 16);
2381 if (siz1 != SIZE_UNSPEC)
2382 addword (baseo);
2383
2384 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2385 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2386 if (siz2 == SIZE_LONG)
2387 addword (outro >> 16);
2388 if (siz2 != SIZE_UNSPEC)
2389 addword (outro);
2390
2391 break;
2392
2393 case ABSL:
2394 nextword = get_num (&opP->disp, 80);
2395 switch (opP->disp.size)
2396 {
2397 default:
2398 abort ();
2399 case SIZE_UNSPEC:
2400 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2401 {
2402 tmpreg = 0x38; /* 7.0 */
2403 addword (nextword);
2404 break;
2405 }
252b5132
RH		 2406 if (isvar (&opP->disp)
2407 && !subs (&opP->disp)
2408 && adds (&opP->disp)
2409#ifdef OBJ_ELF
2410 /* If the displacement needs pic relocation it
2411 cannot be relaxed. */
2412 && opP->disp.pic_reloc == pic_none
2413#endif
252b5132
RH		 2414 && !flag_long_jumps
2415 && !strchr ("~%&$?", s[0]))
2416 {
2417 tmpreg = 0x3A; /* 7.2 */
2418 add_frag (adds (&opP->disp),
2419 offs (&opP->disp),
151337e8 2420 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2421 break;
2422 }
2423 /* Fall through into long */
2424 case SIZE_LONG:
2425 if (isvar (&opP->disp))
2426 add_fix ('l', &opP->disp, 0, 0);
2427
2428 tmpreg = 0x39;/* 7.1 mode */
2429 addword (nextword >> 16);
2430 addword (nextword);
2431 break;
2432
2433 case SIZE_BYTE:
2434 as_bad (_("unsupported byte value; use a different suffix"));
2435 /* Fall through. */
2436 case SIZE_WORD: /* Word */
2437 if (isvar (&opP->disp))
2438 add_fix ('w', &opP->disp, 0, 0);
2439
2440 tmpreg = 0x38;/* 7.0 mode */
2441 addword (nextword);
2442 break;
2443 }
2444 break;
2445 case CONTROL:
2446 case FPREG:
2447 default:
2448 as_bad (_("unknown/incorrect operand"));
bc805888 2449 /* abort (); */
252b5132
RH		 2450 }
2451 install_gen_operand (s[1], tmpreg);
2452 break;
2453
2454 case '#':
2455 case '^':
2456 switch (s[1])
2457 { /* JF: I hate floating point! */
2458 case 'j':
2459 tmpreg = 70;
2460 break;
2461 case '8':
2462 tmpreg = 20;
2463 break;
2464 case 'C':
2465 tmpreg = 50;
2466 break;
2467 case '3':
2468 default:
2469 tmpreg = 80;
2470 break;
2471 }
2472 tmpreg = get_num (&opP->disp, tmpreg);
2473 if (isvar (&opP->disp))
2474 add_fix (s[1], &opP->disp, 0, 0);
2475 switch (s[1])
2476 {
2477 case 'b': /* Danger: These do no check for
2478 certain types of overflow.
2479 user beware! */
2480 if (!isbyte (tmpreg))
2481 opP->error = _("out of range");
2482 insop (tmpreg, opcode);
2483 if (isvar (&opP->disp))
2484 the_ins.reloc[the_ins.nrel - 1].n =
2485 (opcode->m_codenum) * 2 + 1;
2486 break;
2487 case 'B':
2488 if (!issbyte (tmpreg))
2489 opP->error = _("out of range");
2490 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2491 if (isvar (&opP->disp))
2492 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2493 break;
2494 case 'w':
2495 if (!isword (tmpreg))
2496 opP->error = _("out of range");
2497 insop (tmpreg, opcode);
2498 if (isvar (&opP->disp))
2499 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2500 break;
2501 case 'W':
2502 if (!issword (tmpreg))
2503 opP->error = _("out of range");
2504 insop (tmpreg, opcode);
2505 if (isvar (&opP->disp))
2506 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2507 break;
2508 case 'l':
2509 /* Because of the way insop works, we put these two out
2510 backwards. */
2511 insop (tmpreg, opcode);
2512 insop (tmpreg >> 16, opcode);
2513 if (isvar (&opP->disp))
2514 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2515 break;
2516 case '3':
2517 tmpreg &= 0xFF;
2518 case '8':
2519 case 'C':
2520 case 'j':
2521 install_operand (s[1], tmpreg);
2522 break;
2523 default:
2524 abort ();
2525 }
2526 break;
2527
2528 case '+':
2529 case '-':
2530 case 'A':
2531 case 'a':
2532 install_operand (s[1], opP->reg - ADDR);
2533 break;
2534
2535 case 'B':
2536 tmpreg = get_num (&opP->disp, 80);
2537 switch (s[1])
2538 {
2539 case 'B':
8390138c 2540 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2541 break;
2542 case 'W':
2543 add_fix ('w', &opP->disp, 1, 0);
2544 addword (0);
2545 break;
2546 case 'L':
2547 long_branch:
151337e8 2548 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2549 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2550 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2551 add_fix ('l', &opP->disp, 1, 0);
2552 addword (0);
2553 addword (0);
2554 break;
2555 case 'g':
2556 if (subs (&opP->disp)) /* We can't relax it */
2557 goto long_branch;
2558
2559#ifdef OBJ_ELF
2560 /* If the displacement needs pic relocation it cannot be
2561 relaxed. */
2562 if (opP->disp.pic_reloc != pic_none)
2563 goto long_branch;
2564#endif
252b5132 2565 /* This could either be a symbol, or an absolute
151337e8
NC		 2566 address. If it's an absolute address, turn it into
2567 an absolute jump right here and keep it out of the
2568 relaxer. */
2569 if (adds (&opP->disp) == 0)
2570 {
2571 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2572 the_ins.opcode[0] = 0x4EF9;
151337e8 2573 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2574 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2575 else /* jCC */
2576 {
2577 the_ins.opcode[0] ^= 0x0100;
2578 the_ins.opcode[0] |= 0x0006;
18566f55 2579 addword (0x4EF9);
151337e8
NC		 2580 }
2581 add_fix ('l', &opP->disp, 0, 0);
2582 addword (0);
2583 addword (0);
2584 break;
2585 }
2586
2587 /* Now we know it's going into the relaxer. Now figure
2588 out which mode. We try in this order of preference:
2589 long branch, absolute jump, byte/word branches only. */
2590 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2591 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2592 TAB (BRANCHBWL, SZ_UNDEF));
2593 else if (! flag_keep_pcrel)
2594 {
2595 if ((the_ins.opcode[0] == 0x6000)
2596 || (the_ins.opcode[0] == 0x6100))
2597 add_frag (adds (&opP->disp), offs (&opP->disp),
2598 TAB (BRABSJUNC, SZ_UNDEF));
2599 else
2600 add_frag (adds (&opP->disp), offs (&opP->disp),
2601 TAB (BRABSJCOND, SZ_UNDEF));
2602 }
252b5132
RH		 2603 else
2604 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2605 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2606 break;
2607 case 'w':
2608 if (isvar (&opP->disp))
2609 {
151337e8
NC		 2610 /* Check for DBcc instructions. We can relax them,
2611 but only if we have long branches and/or absolute
2612 jumps. */
2613 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2614 && (HAVE_LONG_BRANCH (current_architecture)
2615 || (! flag_keep_pcrel)))
252b5132 2616 {
151337e8
NC		 2617 if (HAVE_LONG_BRANCH (current_architecture))
2618 add_frag (adds (&opP->disp), offs (&opP->disp),
2619 TAB (DBCCLBR, SZ_UNDEF));
2620 else
2621 add_frag (adds (&opP->disp), offs (&opP->disp),
2622 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2623 break;
2624 }
252b5132
RH		 2625 add_fix ('w', &opP->disp, 1, 0);
2626 }
2627 addword (0);
2628 break;
2629 case 'C': /* Fixed size LONG coproc branches */
2630 add_fix ('l', &opP->disp, 1, 0);
2631 addword (0);
2632 addword (0);
2633 break;
2634 case 'c': /* Var size Coprocesssor branches */
151337e8 2635 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2636 {
252b5132
RH		 2637 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2638 add_fix ('l', &opP->disp, 1, 0);
2639 addword (0);
2640 addword (0);
2641 }
151337e8
NC		 2642 else
2643 add_frag (adds (&opP->disp), offs (&opP->disp),
2644 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2645 break;
2646 default:
2647 abort ();
2648 }
2649 break;
2650
2651 case 'C': /* Ignore it */
2652 break;
2653
2654 case 'd': /* JF this is a kludge */
2655 install_operand ('s', opP->reg - ADDR);
2656 tmpreg = get_num (&opP->disp, 80);
2657 if (!issword (tmpreg))
2658 {
2659 as_warn (_("Expression out of range, using 0"));
2660 tmpreg = 0;
2661 }
2662 addword (tmpreg);
2663 break;
2664
2665 case 'D':
2666 install_operand (s[1], opP->reg - DATA);
2667 break;
2668
6da466c7
ILT		 2669 case 'E': /* Ignore it */
2670 break;
2671
252b5132
RH		 2672 case 'F':
2673 install_operand (s[1], opP->reg - FP0);
2674 break;
2675
6da466c7
ILT		 2676 case 'G': /* Ignore it */
2677 case 'H':
2678 break;
2679
252b5132
RH		 2680 case 'I':
2681 tmpreg = opP->reg - COP0;
2682 install_operand (s[1], tmpreg);
2683 break;
2684
2685 case 'J': /* JF foo */
2686 switch (opP->reg)
2687 {
2688 case SFC:
2689 tmpreg = 0x000;
2690 break;
2691 case DFC:
2692 tmpreg = 0x001;
2693 break;
2694 case CACR:
2695 tmpreg = 0x002;
2696 break;
2697 case TC:
2698 tmpreg = 0x003;
2699 break;
2700 case ITT0:
2701 tmpreg = 0x004;
2702 break;
2703 case ITT1:
2704 tmpreg = 0x005;
2705 break;
2706 case DTT0:
2707 tmpreg = 0x006;
2708 break;
2709 case DTT1:
2710 tmpreg = 0x007;
2711 break;
2712 case BUSCR:
2713 tmpreg = 0x008;
2714 break;
2715
2716 case USP:
2717 tmpreg = 0x800;
2718 break;
2719 case VBR:
2720 tmpreg = 0x801;
2721 break;
2722 case CAAR:
2723 tmpreg = 0x802;
2724 break;
2725 case MSP:
2726 tmpreg = 0x803;
2727 break;
2728 case ISP:
2729 tmpreg = 0x804;
2730 break;
2731 case MMUSR:
2732 tmpreg = 0x805;
2733 break;
2734 case URP:
2735 tmpreg = 0x806;
2736 break;
2737 case SRP:
2738 tmpreg = 0x807;
2739 break;
2740 case PCR:
2741 tmpreg = 0x808;
2742 break;
2743 case ROMBAR:
2744 tmpreg = 0xC00;
2745 break;
2746 case RAMBAR0:
2747 tmpreg = 0xC04;
2748 break;
2749 case RAMBAR1:
2750 tmpreg = 0xC05;
2751 break;
2752 case MBAR:
2753 tmpreg = 0xC0F;
2754 break;
2755 default:
2756 abort ();
2757 }
2758 install_operand (s[1], tmpreg);
2759 break;
2760
2761 case 'k':
2762 tmpreg = get_num (&opP->disp, 55);
2763 install_operand (s[1], tmpreg & 0x7f);
2764 break;
2765
2766 case 'l':
2767 tmpreg = opP->mask;
2768 if (s[1] == 'w')
2769 {
2770 if (tmpreg & 0x7FF0000)
2771 as_bad (_("Floating point register in register list"));
2772 insop (reverse_16_bits (tmpreg), opcode);
2773 }
2774 else
2775 {
2776 if (tmpreg & 0x700FFFF)
2777 as_bad (_("Wrong register in floating-point reglist"));
2778 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2779 }
2780 break;
2781
2782 case 'L':
2783 tmpreg = opP->mask;
2784 if (s[1] == 'w')
2785 {
2786 if (tmpreg & 0x7FF0000)
2787 as_bad (_("Floating point register in register list"));
2788 insop (tmpreg, opcode);
2789 }
2790 else if (s[1] == '8')
2791 {
2792 if (tmpreg & 0x0FFFFFF)
2793 as_bad (_("incorrect register in reglist"));
2794 install_operand (s[1], tmpreg >> 24);
2795 }
2796 else
2797 {
2798 if (tmpreg & 0x700FFFF)
2799 as_bad (_("wrong register in floating-point reglist"));
2800 else
2801 install_operand (s[1], tmpreg >> 16);
2802 }
2803 break;
2804
2805 case 'M':
2806 install_operand (s[1], get_num (&opP->disp, 60));
2807 break;
2808
2809 case 'O':
2810 tmpreg = ((opP->mode == DREG)
8fce3f5e 2811 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2812 : (get_num (&opP->disp, 40) & 0x1F));
2813 install_operand (s[1], tmpreg);
2814 break;
2815
2816 case 'Q':
2817 tmpreg = get_num (&opP->disp, 10);
2818 if (tmpreg == 8)
2819 tmpreg = 0;
2820 install_operand (s[1], tmpreg);
2821 break;
2822
2823 case 'R':
2824 /* This depends on the fact that ADDR registers are eight
2825 more than their corresponding DATA regs, so the result
2826 will have the ADDR_REG bit set */
2827 install_operand (s[1], opP->reg - DATA);
2828 break;
2829
2830 case 'r':
2831 if (opP->mode == AINDR)
2832 install_operand (s[1], opP->reg - DATA);
2833 else
2834 install_operand (s[1], opP->index.reg - DATA);
2835 break;
2836
2837 case 's':
2838 if (opP->reg == FPI)
2839 tmpreg = 0x1;
2840 else if (opP->reg == FPS)
2841 tmpreg = 0x2;
2842 else if (opP->reg == FPC)
2843 tmpreg = 0x4;
2844 else
2845 abort ();
2846 install_operand (s[1], tmpreg);
2847 break;
2848
2849 case 'S': /* Ignore it */
2850 break;
2851
2852 case 'T':
2853 install_operand (s[1], get_num (&opP->disp, 30));
2854 break;
2855
2856 case 'U': /* Ignore it */
2857 break;
2858
2859 case 'c':
2860 switch (opP->reg)
2861 {
2862 case NC:
2863 tmpreg = 0;
2864 break;
2865 case DC:
2866 tmpreg = 1;
2867 break;
2868 case IC:
2869 tmpreg = 2;
2870 break;
2871 case BC:
2872 tmpreg = 3;
2873 break;
2874 default:
2875 as_fatal (_("failed sanity check"));
2876 } /* switch on cache token */
2877 install_operand (s[1], tmpreg);
2878 break;
2879#ifndef NO_68851
92774660 2880 /* JF: These are out of order, I fear. */
252b5132
RH		 2881 case 'f':
2882 switch (opP->reg)
2883 {
2884 case SFC:
2885 tmpreg = 0;
2886 break;
2887 case DFC:
2888 tmpreg = 1;
2889 break;
2890 default:
2891 abort ();
2892 }
2893 install_operand (s[1], tmpreg);
2894 break;
2895
2896 case '0':
2897 case '1':
2898 case '2':
2899 switch (opP->reg)
2900 {
2901 case TC:
2902 tmpreg = 0;
2903 break;
2904 case CAL:
2905 tmpreg = 4;
2906 break;
2907 case VAL:
2908 tmpreg = 5;
2909 break;
2910 case SCC:
2911 tmpreg = 6;
2912 break;
2913 case AC:
2914 tmpreg = 7;
2915 break;
2916 default:
2917 abort ();
2918 }
2919 install_operand (s[1], tmpreg);
2920 break;
2921
2922 case 'V':
2923 if (opP->reg == VAL)
2924 break;
2925 abort ();
2926
2927 case 'W':
2928 switch (opP->reg)
2929 {
2930 case DRP:
2931 tmpreg = 1;
2932 break;
2933 case SRP:
2934 tmpreg = 2;
2935 break;
2936 case CRP:
2937 tmpreg = 3;
2938 break;
2939 default:
2940 abort ();
2941 }
2942 install_operand (s[1], tmpreg);
2943 break;
2944
2945 case 'X':
2946 switch (opP->reg)
2947 {
2948 case BAD:
2949 case BAD + 1:
2950 case BAD + 2:
2951 case BAD + 3:
2952 case BAD + 4:
2953 case BAD + 5:
2954 case BAD + 6:
2955 case BAD + 7:
2956 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2957 break;
2958
2959 case BAC:
2960 case BAC + 1:
2961 case BAC + 2:
2962 case BAC + 3:
2963 case BAC + 4:
2964 case BAC + 5:
2965 case BAC + 6:
2966 case BAC + 7:
2967 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2968 break;
2969
2970 default:
2971 abort ();
2972 }
2973 install_operand (s[1], tmpreg);
2974 break;
2975 case 'Y':
2976 know (opP->reg == PSR);
2977 break;
2978 case 'Z':
2979 know (opP->reg == PCSR);
2980 break;
2981#endif /* m68851 */
2982 case '3':
2983 switch (opP->reg)
2984 {
2985 case TT0:
2986 tmpreg = 2;
2987 break;
2988 case TT1:
2989 tmpreg = 3;
2990 break;
2991 default:
2992 abort ();
2993 }
2994 install_operand (s[1], tmpreg);
2995 break;
2996 case 't':
2997 tmpreg = get_num (&opP->disp, 20);
2998 install_operand (s[1], tmpreg);
2999 break;
3000 case '_': /* used only for move16 absolute 32-bit address */
3001 if (isvar (&opP->disp))
3002 add_fix ('l', &opP->disp, 0, 0);
3003 tmpreg = get_num (&opP->disp, 80);
3004 addword (tmpreg >> 16);
3005 addword (tmpreg & 0xFFFF);
3006 break;
6da466c7
ILT		 3007 case 'u':
3008 install_operand (s[1], opP->reg - DATA0L);
3009 opP->reg -= (DATA0L);
3010 opP->reg &= 0x0F; /* remove upper/lower bit */
3011 break;
252b5132
RH		 3012 default:
3013 abort ();
3014 }
3015 }
3016
3017 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3018 instruction, ready to be emitted. . . */
252b5132
RH		 3019}
3020
3021static int
3022reverse_16_bits (in)
3023 int in;
3024{
3025 int out = 0;
3026 int n;
3027
3028 static int mask[16] =
3029 {
3030 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3031 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3032 };
3033 for (n = 0; n < 16; n++)
3034 {
3035 if (in & mask[n])
3036 out |= mask[15 - n];
3037 }
3038 return out;
3039} /* reverse_16_bits() */
3040
3041static int
3042reverse_8_bits (in)
3043 int in;
3044{
3045 int out = 0;
3046 int n;
3047
3048 static int mask[8] =
3049 {
3050 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3051 };
3052
3053 for (n = 0; n < 8; n++)
3054 {
3055 if (in & mask[n])
3056 out |= mask[7 - n];
3057 }
3058 return out;
3059} /* reverse_8_bits() */
3060
3061/* Cause an extra frag to be generated here, inserting up to 10 bytes
3062 (that value is chosen in the frag_var call in md_assemble). TYPE
3063 is the subtype of the frag to be generated; its primary type is
3064 rs_machine_dependent.
3065
3066 The TYPE parameter is also used by md_convert_frag_1 and
3067 md_estimate_size_before_relax. The appropriate type of fixup will
3068 be emitted by md_convert_frag_1.
3069
3070 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3071static void
3072install_operand (mode, val)
3073 int mode;
3074 int val;
3075{
3076 switch (mode)
3077 {
3078 case 's':
3079 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3080 break;
3081 case 'd':
3082 the_ins.opcode[0] |= val << 9;
3083 break;
3084 case '1':
3085 the_ins.opcode[1] |= val << 12;
3086 break;
3087 case '2':
3088 the_ins.opcode[1] |= val << 6;
3089 break;
3090 case '3':
3091 the_ins.opcode[1] |= val;
3092 break;
3093 case '4':
3094 the_ins.opcode[2] |= val << 12;
3095 break;
3096 case '5':
3097 the_ins.opcode[2] |= val << 6;
3098 break;
3099 case '6':
3100 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3101 three words long! */
3102 the_ins.numo++;
3103 the_ins.opcode[2] |= val;
3104 break;
3105 case '7':
3106 the_ins.opcode[1] |= val << 7;
3107 break;
3108 case '8':
3109 the_ins.opcode[1] |= val << 10;
3110 break;
3111#ifndef NO_68851
3112 case '9':
3113 the_ins.opcode[1] |= val << 5;
3114 break;
3115#endif
3116
3117 case 't':
3118 the_ins.opcode[1] |= (val << 10) | (val << 7);
3119 break;
3120 case 'D':
3121 the_ins.opcode[1] |= (val << 12) | val;
3122 break;
3123 case 'g':
3124 the_ins.opcode[0] |= val = 0xff;
3125 break;
3126 case 'i':
3127 the_ins.opcode[0] |= val << 9;
3128 break;
3129 case 'C':
3130 the_ins.opcode[1] |= val;
3131 break;
3132 case 'j':
3133 the_ins.opcode[1] |= val;
3134 the_ins.numo++; /* What a hack */
3135 break;
3136 case 'k':
3137 the_ins.opcode[1] |= val << 4;
3138 break;
3139 case 'b':
3140 case 'w':
3141 case 'W':
3142 case 'l':
3143 break;
3144 case 'e':
3145 the_ins.opcode[0] |= (val << 6);
3146 break;
3147 case 'L':
3148 the_ins.opcode[1] = (val >> 16);
3149 the_ins.opcode[2] = val & 0xffff;
3150 break;
6da466c7
ILT		 3151 case 'm':
3152 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3153 the_ins.opcode[0] |= ((val & 0x7) << 9);
3154 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3155 break;
3156 case 'n':
3157 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3158 the_ins.opcode[0] |= ((val & 0x7) << 9);
3159 break;
3160 case 'o':
3161 the_ins.opcode[1] |= val << 12;
3162 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3163 break;
3164 case 'M':
3165 the_ins.opcode[0] |= (val & 0xF);
3166 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3167 break;
3168 case 'N':
3169 the_ins.opcode[1] |= (val & 0xF);
3170 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3171 break;
3172 case 'h':
3173 the_ins.opcode[1] |= ((val != 1) << 10);
3174 break;
252b5132
RH		 3175 case 'c':
3176 default:
3177 as_fatal (_("failed sanity check."));
3178 }
3179} /* install_operand() */
3180
3181static void
3182install_gen_operand (mode, val)
3183 int mode;
3184 int val;
3185{
3186 switch (mode)
3187 {
3188 case 's':
3189 the_ins.opcode[0] |= val;
3190 break;
3191 case 'd':
3192 /* This is a kludge!!! */
3193 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3194 break;
3195 case 'b':
3196 case 'w':
3197 case 'l':
3198 case 'f':
3199 case 'F':
3200 case 'x':
3201 case 'p':
3202 the_ins.opcode[0] |= val;
3203 break;
3204 /* more stuff goes here */
3205 default:
3206 as_fatal (_("failed sanity check."));
3207 }
3208} /* install_gen_operand() */
3209
3210/*
3211 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3212 * then deal with the bitfield hack.
3213 */
3214
3215static char *
3216crack_operand (str, opP)
3217 register char *str;
3218 register struct m68k_op *opP;
3219{
3220 register int parens;
3221 register int c;
3222 register char *beg_str;
3223 int inquote = 0;
3224
3225 if (!str)
3226 {
3227 return str;
3228 }
3229 beg_str = str;
3230 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3231 {
3232 if (! inquote)
3233 {
3234 if (*str == '(')
3235 parens++;
3236 else if (*str == ')')
3237 {
3238 if (!parens)
3239 { /* ERROR */
3240 opP->error = _("Extra )");
3241 return str;
3242 }
3243 --parens;
3244 }
3245 }
3246 if (flag_mri && *str == '\'')
3247 inquote = ! inquote;
3248 }
3249 if (!*str && parens)
3250 { /* ERROR */
3251 opP->error = _("Missing )");
3252 return str;
3253 }
3254 c = *str;
3255 *str = '\0';
3256 if (m68k_ip_op (beg_str, opP) != 0)
3257 {
3258 *str = c;
3259 return str;
3260 }
3261 *str = c;
3262 if (c == '}')
3263 c = *++str; /* JF bitfield hack */
3264 if (c)
3265 {
3266 c = *++str;
3267 if (!c)
3268 as_bad (_("Missing operand"));
3269 }
3270
3271 /* Detect MRI REG symbols and convert them to REGLSTs. */
3272 if (opP->mode == CONTROL && (int)opP->reg < 0)
3273 {
3274 opP->mode = REGLST;
3275 opP->mask = ~(int)opP->reg;
3276 opP->reg = 0;
3277 }
3278
3279 return str;
3280}
3281
3282/* This is the guts of the machine-dependent assembler. STR points to a
3283 machine dependent instruction. This function is supposed to emit
3284 the frags/bytes it assembles to.
3285 */
3286
3287static void
3288insert_reg (regname, regnum)
3289 const char *regname;
3290 int regnum;
3291{
3292 char buf[100];
3293 int i;
3294
3295#ifdef REGISTER_PREFIX
3296 if (!flag_reg_prefix_optional)
3297 {
3298 buf[0] = REGISTER_PREFIX;
3299 strcpy (buf + 1, regname);
3300 regname = buf;
3301 }
3302#endif
3303
3304 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3305 &zero_address_frag));
3306
3307 for (i = 0; regname[i]; i++)
3882b010 3308 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3309 buf[i] = '\0';
3310
3311 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3312 &zero_address_frag));
3313}
3314
3315struct init_entry
3316 {
3317 const char *name;
3318 int number;
3319 };
3320
3321static const struct init_entry init_table[] =
3322{
3323 { "d0", DATA0 },
3324 { "d1", DATA1 },
3325 { "d2", DATA2 },
3326 { "d3", DATA3 },
3327 { "d4", DATA4 },
3328 { "d5", DATA5 },
3329 { "d6", DATA6 },
3330 { "d7", DATA7 },
3331 { "a0", ADDR0 },
3332 { "a1", ADDR1 },
3333 { "a2", ADDR2 },
3334 { "a3", ADDR3 },
3335 { "a4", ADDR4 },
3336 { "a5", ADDR5 },
3337 { "a6", ADDR6 },
3338 { "fp", ADDR6 },
3339 { "a7", ADDR7 },
3340 { "sp", ADDR7 },
3341 { "ssp", ADDR7 },
3342 { "fp0", FP0 },
3343 { "fp1", FP1 },
3344 { "fp2", FP2 },
3345 { "fp3", FP3 },
3346 { "fp4", FP4 },
3347 { "fp5", FP5 },
3348 { "fp6", FP6 },
3349 { "fp7", FP7 },
3350 { "fpi", FPI },
3351 { "fpiar", FPI },
3352 { "fpc", FPI },
3353 { "fps", FPS },
3354 { "fpsr", FPS },
3355 { "fpc", FPC },
3356 { "fpcr", FPC },
3357 { "control", FPC },
3358 { "status", FPS },
3359 { "iaddr", FPI },
3360
3361 { "cop0", COP0 },
3362 { "cop1", COP1 },
3363 { "cop2", COP2 },
3364 { "cop3", COP3 },
3365 { "cop4", COP4 },
3366 { "cop5", COP5 },
3367 { "cop6", COP6 },
3368 { "cop7", COP7 },
3369 { "pc", PC },
3370 { "zpc", ZPC },
3371 { "sr", SR },
3372
3373 { "ccr", CCR },
3374 { "cc", CCR },
3375
6da466c7
ILT		 3376 { "acc", ACC },
3377 { "macsr", MACSR },
3378 { "mask", MASK },
3379
252b5132
RH		 3380 /* control registers */
3381 { "sfc", SFC }, /* Source Function Code */
3382 { "sfcr", SFC },
3383 { "dfc", DFC }, /* Destination Function Code */
3384 { "dfcr", DFC },
3385 { "cacr", CACR }, /* Cache Control Register */
3386 { "caar", CAAR }, /* Cache Address Register */
3387
3388 { "usp", USP }, /* User Stack Pointer */
3389 { "vbr", VBR }, /* Vector Base Register */
3390 { "msp", MSP }, /* Master Stack Pointer */
3391 { "isp", ISP }, /* Interrupt Stack Pointer */
3392
3393 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3394 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3395 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3396 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3397
3398 /* 68ec040 versions of same */
3399 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3400 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3401 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3402 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3403
3404 /* mcf5200 versions of same. The ColdFire programmer's reference
3405 manual indicated that the order is 2,3,0,1, but Ken Rose
3406 <[email protected]> says that 0,1,2,3 is the correct order. */
3407 { "acr0", ITT0 }, /* Access Control Unit 0 */
3408 { "acr1", ITT1 }, /* Access Control Unit 1 */
3409 { "acr2", DTT0 }, /* Access Control Unit 2 */
3410 { "acr3", DTT1 }, /* Access Control Unit 3 */
3411
3412 { "tc", TC }, /* MMU Translation Control Register */
3413 { "tcr", TC },
3414
3415 { "mmusr", MMUSR }, /* MMU Status Register */
3416 { "srp", SRP }, /* User Root Pointer */
3417 { "urp", URP }, /* Supervisor Root Pointer */
3418
3419 { "buscr", BUSCR },
3420 { "pcr", PCR },
3421
3422 { "rombar", ROMBAR }, /* ROM Base Address Register */
3423 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3424 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3425 { "mbar", MBAR }, /* Module Base Address Register */
3426 /* end of control registers */
3427
3428 { "ac", AC },
3429 { "bc", BC },
3430 { "cal", CAL },
3431 { "crp", CRP },
3432 { "drp", DRP },
3433 { "pcsr", PCSR },
3434 { "psr", PSR },
3435 { "scc", SCC },
3436 { "val", VAL },
3437 { "bad0", BAD0 },
3438 { "bad1", BAD1 },
3439 { "bad2", BAD2 },
3440 { "bad3", BAD3 },
3441 { "bad4", BAD4 },
3442 { "bad5", BAD5 },
3443 { "bad6", BAD6 },
3444 { "bad7", BAD7 },
3445 { "bac0", BAC0 },
3446 { "bac1", BAC1 },
3447 { "bac2", BAC2 },
3448 { "bac3", BAC3 },
3449 { "bac4", BAC4 },
3450 { "bac5", BAC5 },
3451 { "bac6", BAC6 },
3452 { "bac7", BAC7 },
3453
3454 { "ic", IC },
3455 { "dc", DC },
3456 { "nc", NC },
3457
3458 { "tt0", TT0 },
3459 { "tt1", TT1 },
3460 /* 68ec030 versions of same */
3461 { "ac0", TT0 },
3462 { "ac1", TT1 },
3463 /* 68ec030 access control unit, identical to 030 MMU status reg */
3464 { "acusr", PSR },
3465
3466 /* Suppressed data and address registers. */
3467 { "zd0", ZDATA0 },
3468 { "zd1", ZDATA1 },
3469 { "zd2", ZDATA2 },
3470 { "zd3", ZDATA3 },
3471 { "zd4", ZDATA4 },
3472 { "zd5", ZDATA5 },
3473 { "zd6", ZDATA6 },
3474 { "zd7", ZDATA7 },
3475 { "za0", ZADDR0 },
3476 { "za1", ZADDR1 },
3477 { "za2", ZADDR2 },
3478 { "za3", ZADDR3 },
3479 { "za4", ZADDR4 },
3480 { "za5", ZADDR5 },
3481 { "za6", ZADDR6 },
3482 { "za7", ZADDR7 },
3483
92774660 3484 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3485 { "d0l", DATA0L },
3486 { "d1l", DATA1L },
3487 { "d2l", DATA2L },
3488 { "d3l", DATA3L },
3489 { "d4l", DATA4L },
3490 { "d5l", DATA5L },
3491 { "d6l", DATA6L },
3492 { "d7l", DATA7L },
3493
3494 { "a0l", ADDR0L },
3495 { "a1l", ADDR1L },
3496 { "a2l", ADDR2L },
3497 { "a3l", ADDR3L },
3498 { "a4l", ADDR4L },
3499 { "a5l", ADDR5L },
3500 { "a6l", ADDR6L },
3501 { "a7l", ADDR7L },
3502
3503 { "d0u", DATA0U },
3504 { "d1u", DATA1U },
3505 { "d2u", DATA2U },
3506 { "d3u", DATA3U },
3507 { "d4u", DATA4U },
3508 { "d5u", DATA5U },
3509 { "d6u", DATA6U },
3510 { "d7u", DATA7U },
3511
3512 { "a0u", ADDR0U },
3513 { "a1u", ADDR1U },
3514 { "a2u", ADDR2U },
3515 { "a3u", ADDR3U },
3516 { "a4u", ADDR4U },
3517 { "a5u", ADDR5U },
3518 { "a6u", ADDR6U },
3519 { "a7u", ADDR7U },
3520
252b5132
RH		 3521 { 0, 0 }
3522};
3523
3524static void
3525init_regtable ()
3526{
3527 int i;
3528 for (i = 0; init_table[i].name; i++)
3529 insert_reg (init_table[i].name, init_table[i].number);
3530}
3531
3532static int no_68851, no_68881;
3533
3534#ifdef OBJ_AOUT
3535/* a.out machine type. Default to 68020. */
3536int m68k_aout_machtype = 2;
3537#endif
3538
3539void
3540md_assemble (str)
3541 char *str;
3542{
3543 const char *er;
3544 short *fromP;
3545 char *toP = NULL;
3546 int m, n = 0;
3547 char *to_beg_P;
3548 int shorts_this_frag;
3549 fixS *fixP;
3550
3551 /* In MRI mode, the instruction and operands are separated by a
3552 space. Anything following the operands is a comment. The label
3553 has already been removed. */
3554 if (flag_mri)
3555 {
3556 char *s;
3557 int fields = 0;
3558 int infield = 0;
3559 int inquote = 0;
3560
3561 for (s = str; *s != '\0'; s++)
3562 {
3563 if ((*s == ' ' || *s == '\t') && ! inquote)
3564 {
3565 if (infield)
3566 {
3567 ++fields;
3568 if (fields >= 2)
3569 {
3570 *s = '\0';
3571 break;
3572 }
3573 infield = 0;
3574 }
3575 }
3576 else
3577 {
3578 if (! infield)
3579 infield = 1;
3580 if (*s == '\'')
3581 inquote = ! inquote;
3582 }
3583 }
3584 }
3585
3586 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3587 m68k_ip (str);
3588 er = the_ins.error;
3589 if (!er)
3590 {
3591 for (n = 0; n < the_ins.numargs; n++)
3592 if (the_ins.operands[n].error)
3593 {
3594 er = the_ins.operands[n].error;
3595 break;
3596 }
3597 }
3598 if (er)
3599 {
3600 as_bad (_("%s -- statement `%s' ignored"), er, str);
3601 return;
3602 }
3603
3604 /* If there is a current label, record that it marks an instruction. */
3605 if (current_label != NULL)
3606 {
3607 current_label->text = 1;
3608 current_label = NULL;
3609 }
3610
f27a3839
AS		 3611#ifdef OBJ_ELF
3612 /* Tie dwarf2 debug info to the address at the start of the insn. */
3613 dwarf2_emit_insn (0);
3614#endif
3615
252b5132
RH		 3616 if (the_ins.nfrag == 0)
3617 {
3618 /* No frag hacking involved; just put it out */
3619 toP = frag_more (2 * the_ins.numo);
3620 fromP = &the_ins.opcode[0];
3621 for (m = the_ins.numo; m; --m)
3622 {
3623 md_number_to_chars (toP, (long) (*fromP), 2);
3624 toP += 2;
3625 fromP++;
3626 }
3627 /* put out symbol-dependent info */
3628 for (m = 0; m < the_ins.nrel; m++)
3629 {
3630 switch (the_ins.reloc[m].wid)
3631 {
3632 case 'B':
3633 n = 1;
3634 break;
3635 case 'b':
3636 n = 1;
3637 break;
3638 case '3':
3639 n = 1;
3640 break;
3641 case 'w':
3642 case 'W':
3643 n = 2;
3644 break;
3645 case 'l':
3646 n = 4;
3647 break;
3648 default:
3649 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3650 the_ins.reloc[m].wid);
3651 }
3652
3653 fixP = fix_new_exp (frag_now,
3654 ((toP - frag_now->fr_literal)
3655 - the_ins.numo * 2 + the_ins.reloc[m].n),
3656 n,
3657 &the_ins.reloc[m].exp,
3658 the_ins.reloc[m].pcrel,
3659 get_reloc_code (n, the_ins.reloc[m].pcrel,
3660 the_ins.reloc[m].pic_reloc));
3661 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3662 if (the_ins.reloc[m].wid == 'B')
3663 fixP->fx_signed = 1;
3664 }
3665 return;
3666 }
3667
3668 /* There's some frag hacking */
fbe572f9
AM		 3669 {
3670 /* Calculate the max frag size. */
3671 int wid;
3672
3673 wid = 2 * the_ins.fragb[0].fragoff;
3674 for (n = 1; n < the_ins.nfrag; n++)
3675 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3676 /* frag_var part. */
3677 wid += 10;
3678 /* Make sure the whole insn fits in one chunk, in particular that
3679 the var part is attached, as we access one byte before the
3680 variable frag for byte branches. */
3681 frag_grow (wid);
3682 }
3683
252b5132
RH		 3684 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3685 {
3686 int wid;
3687
3688 if (n == 0)
3689 wid = 2 * the_ins.fragb[n].fragoff;
3690 else
3691 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3692 toP = frag_more (wid);
3693 to_beg_P = toP;
3694 shorts_this_frag = 0;
3695 for (m = wid / 2; m; --m)
3696 {
3697 md_number_to_chars (toP, (long) (*fromP), 2);
3698 toP += 2;
3699 fromP++;
3700 shorts_this_frag++;
3701 }
3702 for (m = 0; m < the_ins.nrel; m++)
3703 {
3704 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3705 {
3706 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3707 break;
3708 }
3709 wid = the_ins.reloc[m].wid;
3710 if (wid == 0)
3711 continue;
3712 the_ins.reloc[m].wid = 0;
3713 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3714
3715 fixP = fix_new_exp (frag_now,
3716 ((toP - frag_now->fr_literal)
3717 - the_ins.numo * 2 + the_ins.reloc[m].n),
3718 wid,
3719 &the_ins.reloc[m].exp,
3720 the_ins.reloc[m].pcrel,
3721 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3722 the_ins.reloc[m].pic_reloc));
3723 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3724 }
3725 (void) frag_var (rs_machine_dependent, 10, 0,
3726 (relax_substateT) (the_ins.fragb[n].fragty),
3727 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3728 }
3729 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3730 shorts_this_frag = 0;
3731 if (n)
3732 {
3733 toP = frag_more (n * sizeof (short));
3734 while (n--)
3735 {
3736 md_number_to_chars (toP, (long) (*fromP), 2);
3737 toP += 2;
3738 fromP++;
3739 shorts_this_frag++;
3740 }
3741 }
3742 for (m = 0; m < the_ins.nrel; m++)
3743 {
3744 int wid;
3745
3746 wid = the_ins.reloc[m].wid;
3747 if (wid == 0)
3748 continue;
3749 the_ins.reloc[m].wid = 0;
3750 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3751
3752 fixP = fix_new_exp (frag_now,
3753 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3754 - shorts_this_frag * 2),
3755 wid,
3756 &the_ins.reloc[m].exp,
3757 the_ins.reloc[m].pcrel,
3758 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3759 the_ins.reloc[m].pic_reloc));
3760 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3761 }
3762}
3763
3764void
3765md_begin ()
3766{
3767 /*
3768 * md_begin -- set up hash tables with 68000 instructions.
3769 * similar to what the vax assembler does. ---phr
3770 */
3771 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3772 a copy of it at runtime, adding in the information we want but isn't
3773 there. I think it'd be better to have an awk script hack the table
3774 at compile time. Or even just xstr the table and use it as-is. But
3775 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3776 names. */
3777
94f592af
NC		 3778 const struct m68k_opcode *ins;
3779 struct m68k_incant *hack, *slak;
3780 const char *retval = 0; /* empty string, or error msg text */
3781 int i;
252b5132
RH		 3782
3783 if (flag_mri)
3784 {
3785 flag_reg_prefix_optional = 1;
3786 m68k_abspcadd = 1;
3787 if (! m68k_rel32_from_cmdline)
3788 m68k_rel32 = 0;
3789 }
3790
3791 op_hash = hash_new ();
3792
3793 obstack_begin (&robyn, 4000);
3794 for (i = 0; i < m68k_numopcodes; i++)
3795 {
3796 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3797 do
3798 {
3799 ins = &m68k_opcodes[i];
3800 /* We *could* ignore insns that don't match our arch here
92774660 3801 but just leaving them out of the hash. */
252b5132
RH		 3802 slak->m_operands = ins->args;
3803 slak->m_opnum = strlen (slak->m_operands) / 2;
3804 slak->m_arch = ins->arch;
3805 slak->m_opcode = ins->opcode;
3806 /* This is kludgey */
3807 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3808 if (i + 1 != m68k_numopcodes
3809 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3810 {
3811 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3812 i++;
3813 }
3814 else
3815 slak->m_next = 0;
3816 slak = slak->m_next;
3817 }
3818 while (slak);
3819
3820 retval = hash_insert (op_hash, ins->name, (char *) hack);
3821 if (retval)
3822 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3823 }
3824
3825 for (i = 0; i < m68k_numaliases; i++)
3826 {
3827 const char *name = m68k_opcode_aliases[i].primary;
3828 const char *alias = m68k_opcode_aliases[i].alias;
3829 PTR val = hash_find (op_hash, name);
3830 if (!val)
3831 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3832 retval = hash_insert (op_hash, alias, val);
3833 if (retval)
3834 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3835 }
3836
3837 /* In MRI mode, all unsized branches are variable sized. Normally,
3838 they are word sized. */
3839 if (flag_mri)
3840 {
3841 static struct m68k_opcode_alias mri_aliases[] =
3842 {
3843 { "bhi", "jhi", },
3844 { "bls", "jls", },
3845 { "bcc", "jcc", },
3846 { "bcs", "jcs", },
3847 { "bne", "jne", },
3848 { "beq", "jeq", },
3849 { "bvc", "jvc", },
3850 { "bvs", "jvs", },
3851 { "bpl", "jpl", },
3852 { "bmi", "jmi", },
3853 { "bge", "jge", },
3854 { "blt", "jlt", },
3855 { "bgt", "jgt", },
3856 { "ble", "jle", },
3857 { "bra", "jra", },
3858 { "bsr", "jbsr", },
3859 };
3860
8fce3f5e
AM		 3861 for (i = 0;
3862 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3863 i++)
252b5132
RH		 3864 {
3865 const char *name = mri_aliases[i].primary;
3866 const char *alias = mri_aliases[i].alias;
3867 PTR val = hash_find (op_hash, name);
3868 if (!val)
3869 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3870 retval = hash_jam (op_hash, alias, val);
3871 if (retval)
3872 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3873 }
3874 }
3875
8fce3f5e 3876 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3877 {
3878 notend_table[i] = 0;
3879 alt_notend_table[i] = 0;
3880 }
3881 notend_table[','] = 1;
3882 notend_table['{'] = 1;
3883 notend_table['}'] = 1;
3884 alt_notend_table['a'] = 1;
3885 alt_notend_table['A'] = 1;
3886 alt_notend_table['d'] = 1;
3887 alt_notend_table['D'] = 1;
3888 alt_notend_table['#'] = 1;
3889 alt_notend_table['&'] = 1;
3890 alt_notend_table['f'] = 1;
3891 alt_notend_table['F'] = 1;
3892#ifdef REGISTER_PREFIX
3893 alt_notend_table[REGISTER_PREFIX] = 1;
3894#endif
3895
3896 /* We need to put '(' in alt_notend_table to handle
3897 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3898 */
3899 alt_notend_table['('] = 1;
3900
3901 /* We need to put '@' in alt_notend_table to handle
3902 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3903 */
3904 alt_notend_table['@'] = 1;
3905
3906 /* We need to put digits in alt_notend_table to handle
3907 bfextu %d0{24:1},%d0
3908 */
3909 alt_notend_table['0'] = 1;
3910 alt_notend_table['1'] = 1;
3911 alt_notend_table['2'] = 1;
3912 alt_notend_table['3'] = 1;
3913 alt_notend_table['4'] = 1;
3914 alt_notend_table['5'] = 1;
3915 alt_notend_table['6'] = 1;
3916 alt_notend_table['7'] = 1;
3917 alt_notend_table['8'] = 1;
3918 alt_notend_table['9'] = 1;
3919
3920#ifndef MIT_SYNTAX_ONLY
3921 /* Insert pseudo ops, these have to go into the opcode table since
3922 gas expects pseudo ops to start with a dot */
3923 {
3924 int n = 0;
3925 while (mote_pseudo_table[n].poc_name)
3926 {
3927 hack = (struct m68k_incant *)
3928 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3929 hash_insert (op_hash,
3930 mote_pseudo_table[n].poc_name, (char *) hack);
3931 hack->m_operands = 0;
3932 hack->m_opnum = n;
3933 n++;
3934 }
3935 }
3936#endif
3937
3938 init_regtable ();
3939
3940#ifdef OBJ_ELF
3941 record_alignment (text_section, 2);
3942 record_alignment (data_section, 2);
3943 record_alignment (bss_section, 2);
3944#endif
3945}
3946
3947static void
3948select_control_regs ()
3949{
3950 /* Note which set of "movec" control registers is available. */
3951 switch (cpu_of_arch (current_architecture))
3952 {
4f2a7c9e
NC		 3953 case 0:
3954 as_warn (_("architecture not yet selected: defaulting to 68020"));
3955 control_regs = m68020_control_regs;
3956 break;
3957
252b5132
RH		 3958 case m68000:
3959 control_regs = m68000_control_regs;
3960 break;
3961 case m68010:
3962 control_regs = m68010_control_regs;
3963 break;
3964 case m68020:
3965 case m68030:
3966 control_regs = m68020_control_regs;
3967 break;
3968 case m68040:
3969 control_regs = m68040_control_regs;
3970 break;
3971 case m68060:
3972 control_regs = m68060_control_regs;
3973 break;
3974 case cpu32:
3975 control_regs = cpu32_control_regs;
3976 break;
3977 case mcf5200:
6da466c7
ILT		 3978 case mcf5206e:
3979 case mcf5307:
dc84e067 3980 case mcf5407:
6da466c7 3981 control_regs = mcf_control_regs;
252b5132
RH		 3982 break;
3983 default:
3984 abort ();
3985 }
3986}
3987
3988void
3989m68k_init_after_args ()
3990{
3991 if (cpu_of_arch (current_architecture) == 0)
3992 {
3993 int i;
3994 const char *default_cpu = TARGET_CPU;
3995
3996 if (*default_cpu == 'm')
3997 default_cpu++;
3998 for (i = 0; i < n_archs; i++)
3999 if (strcasecmp (default_cpu, archs[i].name) == 0)
4000 break;
4001 if (i == n_archs)
4002 {
4003 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4004 current_architecture |= m68020;
4005 }
4006 else
4007 current_architecture |= archs[i].arch;
4008 }
4009 /* Permit m68881 specification with all cpus; those that can't work
4010 with a coprocessor could be doing emulation. */
4011 if (current_architecture & m68851)
4012 {
4013 if (current_architecture & m68040)
4014 {
4015 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4016 }
4017 }
4018 /* What other incompatibilities could we check for? */
4019
4020 /* Toss in some default assumptions about coprocessors. */
4021 if (!no_68881
4022 && (cpu_of_arch (current_architecture)
4023 /* Can CPU32 have a 68881 coprocessor?? */
4024 & (m68020 | m68030 | cpu32)))
4025 {
4026 current_architecture |= m68881;
4027 }
4028 if (!no_68851
4029 && (cpu_of_arch (current_architecture) & m68020up) != 0
4030 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4031 {
4032 current_architecture |= m68851;
4033 }
4034 if (no_68881 && (current_architecture & m68881))
4035 as_bad (_("options for 68881 and no-68881 both given"));
4036 if (no_68851 && (current_architecture & m68851))
4037 as_bad (_("options for 68851 and no-68851 both given"));
4038
4039#ifdef OBJ_AOUT
4040 /* Work out the magic number. This isn't very general. */
4041 if (current_architecture & m68000)
4042 m68k_aout_machtype = 0;
4043 else if (current_architecture & m68010)
4044 m68k_aout_machtype = 1;
4045 else if (current_architecture & m68020)
4046 m68k_aout_machtype = 2;
4047 else
4048 m68k_aout_machtype = 2;
4049#endif
4050
4051 /* Note which set of "movec" control registers is available. */
4052 select_control_regs ();
4053
4054 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4055 || arch_coldfire_p (current_architecture))
252b5132
RH		 4056 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4057}
4058\f
4059/* This is called when a label is defined. */
4060
4061void
4062m68k_frob_label (sym)
4063 symbolS *sym;
4064{
4065 struct label_line *n;
4066
4067 n = (struct label_line *) xmalloc (sizeof *n);
4068 n->next = labels;
4069 n->label = sym;
4070 as_where (&n->file, &n->line);
4071 n->text = 0;
4072 labels = n;
4073 current_label = n;
4074}
4075
4076/* This is called when a value that is not an instruction is emitted. */
4077
4078void
4079m68k_flush_pending_output ()
4080{
4081 current_label = NULL;
4082}
4083
4084/* This is called at the end of the assembly, when the final value of
4085 the label is known. We warn if this is a text symbol aligned at an
4086 odd location. */
4087
4088void
4089m68k_frob_symbol (sym)
4090 symbolS *sym;
4091{
4092 if (S_GET_SEGMENT (sym) == reg_section
4093 && (int) S_GET_VALUE (sym) < 0)
4094 {
4095 S_SET_SEGMENT (sym, absolute_section);
4096 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4097 }
4098 else if ((S_GET_VALUE (sym) & 1) != 0)
4099 {
4100 struct label_line *l;
4101
4102 for (l = labels; l != NULL; l = l->next)
4103 {
4104 if (l->label == sym)
4105 {
4106 if (l->text)
4107 as_warn_where (l->file, l->line,
4108 _("text label `%s' aligned to odd boundary"),
4109 S_GET_NAME (sym));
4110 break;
4111 }
4112 }
4113 }
4114}
4115\f
4116/* This is called if we go in or out of MRI mode because of the .mri
4117 pseudo-op. */
4118
4119void
4120m68k_mri_mode_change (on)
4121 int on;
4122{
4123 if (on)
4124 {
4125 if (! flag_reg_prefix_optional)
4126 {
4127 flag_reg_prefix_optional = 1;
4128#ifdef REGISTER_PREFIX
4129 init_regtable ();
4130#endif
4131 }
4132 m68k_abspcadd = 1;
4133 if (! m68k_rel32_from_cmdline)
4134 m68k_rel32 = 0;
4135 }
4136 else
4137 {
4138 if (! reg_prefix_optional_seen)
4139 {
4140#ifdef REGISTER_PREFIX_OPTIONAL
4141 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4142#else
4143 flag_reg_prefix_optional = 0;
4144#endif
4145#ifdef REGISTER_PREFIX
4146 init_regtable ();
4147#endif
4148 }
4149 m68k_abspcadd = 0;
4150 if (! m68k_rel32_from_cmdline)
4151 m68k_rel32 = 1;
4152 }
4153}
4154
4155/* Equal to MAX_PRECISION in atof-ieee.c */
4156#define MAX_LITTLENUMS 6
4157
4158/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4159 of type TYPE, and store the appropriate bytes in *LITP. The number
4160 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4161 returned, or NULL on OK. */
4162
4163char *
4164md_atof (type, litP, sizeP)
4165 char type;
4166 char *litP;
4167 int *sizeP;
4168{
4169 int prec;
4170 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4171 LITTLENUM_TYPE *wordP;
4172 char *t;
4173
4174 switch (type)
4175 {
4176 case 'f':
4177 case 'F':
4178 case 's':
4179 case 'S':
4180 prec = 2;
4181 break;
4182
4183 case 'd':
4184 case 'D':
4185 case 'r':
4186 case 'R':
4187 prec = 4;
4188 break;
4189
4190 case 'x':
4191 case 'X':
4192 prec = 6;
4193 break;
4194
4195 case 'p':
4196 case 'P':
4197 prec = 6;
4198 break;
4199
4200 default:
4201 *sizeP = 0;
4202 return _("Bad call to MD_ATOF()");
4203 }
4204 t = atof_ieee (input_line_pointer, type, words);
4205 if (t)
4206 input_line_pointer = t;
4207
4208 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4209 for (wordP = words; prec--;)
4210 {
4211 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4212 litP += sizeof (LITTLENUM_TYPE);
4213 }
4214 return 0;
4215}
4216
4217void
4218md_number_to_chars (buf, val, n)
4219 char *buf;
4220 valueT val;
4221 int n;
4222{
4223 number_to_chars_bigendian (buf, val, n);
4224}
4225
94f592af
NC		 4226void
4227md_apply_fix3 (fixP, valP, seg)
252b5132 4228 fixS *fixP;
bbe8ef22 4229 valueT *valP;
94f592af 4230 segT seg ATTRIBUTE_UNUSED;
252b5132 4231{
bbe8ef22 4232 offsetT val = *valP;
252b5132
RH		 4233 addressT upper_limit;
4234 offsetT lower_limit;
4235
4236 /* This is unnecessary but it convinces the native rs6000 compiler
4237 to generate the code we want. */
4238 char *buf = fixP->fx_frag->fr_literal;
4239 buf += fixP->fx_where;
4240 /* end ibm compiler workaround */
4241
c801568a 4242 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
252b5132 4243
94f592af
NC		 4244 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4245 fixP->fx_done = 1;
4246
252b5132
RH		 4247#ifdef OBJ_ELF
4248 if (fixP->fx_addsy)
4249 {
4250 memset (buf, 0, fixP->fx_size);
4251 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4252
4253 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4254 && !S_IS_DEFINED (fixP->fx_addsy)
4255 && !S_IS_WEAK (fixP->fx_addsy))
4256 S_SET_WEAK (fixP->fx_addsy);
4257 return;
4258 }
4259#endif
4260
4261#ifdef BFD_ASSEMBLER
4262 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4263 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4264 return;
4265#endif
4266
4267 switch (fixP->fx_size)
4268 {
94f592af
NC		 4269 /* The cast to offsetT below are necessary to make code
4270 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4271 case 1:
4272 *buf++ = val;
4273 upper_limit = 0x7f;
4274 lower_limit = - (offsetT) 0x80;
4275 break;
4276 case 2:
4277 *buf++ = (val >> 8);
4278 *buf++ = val;
4279 upper_limit = 0x7fff;
4280 lower_limit = - (offsetT) 0x8000;
4281 break;
4282 case 4:
4283 *buf++ = (val >> 24);
4284 *buf++ = (val >> 16);
4285 *buf++ = (val >> 8);
4286 *buf++ = val;
4287 upper_limit = 0x7fffffff;
4288 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4289 break;
4290 default:
4291 BAD_CASE (fixP->fx_size);
4292 }
4293
4294 /* Fix up a negative reloc. */
4295 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4296 {
4297 fixP->fx_addsy = fixP->fx_subsy;
4298 fixP->fx_subsy = NULL;
4299 fixP->fx_tcbit = 1;
4300 }
4301
4302 /* For non-pc-relative values, it's conceivable we might get something
4303 like "0xff" for a byte field. So extend the upper part of the range
4304 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4305 so that we can do any range checking at all. */
4306 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4307 upper_limit = upper_limit * 2 + 1;
4308
4309 if ((addressT) val > upper_limit
4310 && (val > 0 || val < lower_limit))
4311 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4312
4313 /* A one byte PC-relative reloc means a short branch. We can't use
4314 a short branch with a value of 0 or -1, because those indicate
4315 different opcodes (branches with longer offsets). fixup_segment
4316 in write.c may have clobbered fx_pcrel, so we need to examine the
4317 reloc type. */
4318 if ((fixP->fx_pcrel
4319#ifdef BFD_ASSEMBLER
4320 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4321#endif
4322 )
4323 && fixP->fx_size == 1
4324 && (fixP->fx_addsy == NULL
4325 || S_IS_DEFINED (fixP->fx_addsy))
4326 && (val == 0 || val == -1))
4327 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4328}
4329
252b5132
RH		 4330/* *fragP has been relaxed to its final size, and now needs to have
4331 the bytes inside it modified to conform to the new size There is UGLY
4332 MAGIC here. ..
4333 */
4334static void
4335md_convert_frag_1 (fragP)
4336 register fragS *fragP;
4337{
4338 long disp;
252b5132
RH		 4339 fixS *fixP;
4340
4341 /* Address in object code of the displacement. */
4342 register int object_address = fragP->fr_fix + fragP->fr_address;
4343
4344 /* Address in gas core of the place to store the displacement. */
4345 /* This convinces the native rs6000 compiler to generate the code we
92774660 4346 want. */
252b5132
RH		 4347 register char *buffer_address = fragP->fr_literal;
4348 buffer_address += fragP->fr_fix;
4349 /* end ibm compiler workaround */
4350
4351 /* The displacement of the address, from current location. */
4352 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4353 disp = (disp + fragP->fr_offset) - object_address;
4354
252b5132
RH		 4355 switch (fragP->fr_subtype)
4356 {
151337e8
NC		 4357 case TAB (BRANCHBWL, BYTE):
4358 case TAB (BRABSJUNC, BYTE):
4359 case TAB (BRABSJCOND, BYTE):
4360 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4361 know (issbyte (disp));
4362 if (disp == 0)
b091f402
AM		 4363 as_bad_where (fragP->fr_file, fragP->fr_line,
4364 _("short branch with zero offset: use :w"));
151337e8 4365 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4366 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4367 fixP->fx_pcrel_adjust = -1;
252b5132 4368 break;
151337e8
NC		 4369 case TAB (BRANCHBWL, SHORT):
4370 case TAB (BRABSJUNC, SHORT):
4371 case TAB (BRABSJCOND, SHORT):
4372 case TAB (BRANCHBW, SHORT):
252b5132 4373 fragP->fr_opcode[1] = 0x00;
151337e8 4374 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4375 1, RELAX_RELOC_PC16);
151337e8
NC		 4376 fragP->fr_fix += 2;
4377 break;
4378 case TAB (BRANCHBWL, LONG):
4379 fragP->fr_opcode[1] = (char) 0xFF;
4380 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4381 1, RELAX_RELOC_PC32);
151337e8 4382 fragP->fr_fix += 4;
252b5132 4383 break;
151337e8
NC		 4384 case TAB (BRABSJUNC, LONG):
4385 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4386 {
151337e8
NC		 4387 fragP->fr_opcode[0] = 0x4E;
4388 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4389 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4390 0, RELAX_RELOC_ABS32);
151337e8
NC		 4391 fragP->fr_fix += 4;
4392 }
4393 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4394 {
4395 fragP->fr_opcode[0] = 0x4E;
4396 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4397 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4398 0, RELAX_RELOC_ABS32);
151337e8 4399 fragP->fr_fix += 4;
252b5132
RH		 4400 }
4401 else
4402 {
151337e8
NC		 4403 /* This cannot happen, because jbsr and jbra are the only two
4404 unconditional branches. */
4405 abort ();
252b5132
RH		 4406 }
4407 break;
151337e8
NC		 4408 case TAB (BRABSJCOND, LONG):
4409 /* Only Bcc 68000 instructions can come here. */
4410 /* Change bcc into b!cc/jmp absl long. */
92774660 4411
252b5132
RH		 4412 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4413 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4414
4415 /* JF: these used to be fr_opcode[2,3], but they may be in a
4416 different frag, in which case refering to them is a no-no.
92774660 4417 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4418 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4419 *buffer_address++ = (char) 0xf9;
4420 fragP->fr_fix += 2; /* account for jmp instruction */
4421 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4422 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4423 fragP->fr_fix += 4;
4424 break;
4425 case TAB (FBRANCH, SHORT):
4426 know ((fragP->fr_opcode[1] & 0x40) == 0);
4427 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4428 1, RELAX_RELOC_PC16);
151337e8
NC		 4429 fragP->fr_fix += 2;
4430 break;
4431 case TAB (FBRANCH, LONG):
4432 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4433 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4434 1, RELAX_RELOC_PC32);
252b5132 4435 fragP->fr_fix += 4;
252b5132 4436 break;
151337e8
NC		 4437 case TAB (DBCCLBR, SHORT):
4438 case TAB (DBCCABSJ, SHORT):
4439 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4440 1, RELAX_RELOC_PC16);
151337e8
NC		 4441 fragP->fr_fix += 2;
4442 break;
4443 case TAB (DBCCLBR, LONG):
4444 /* only DBcc instructions can come here */
28e7409f 4445 /* Change dbcc into dbcc/bral. */
28e7409f 4446
252b5132
RH		 4447 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4448 *buffer_address++ = 0x00; /* branch offset = 4 */
4449 *buffer_address++ = 0x04;
4450 *buffer_address++ = 0x60; /* put in bra pc+6 */
4451 *buffer_address++ = 0x06;
151337e8
NC		 4452 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4453 *buffer_address++ = (char) 0xff;
252b5132
RH		 4454
4455 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4456 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4457 RELAX_RELOC_PC32);
252b5132 4458 fragP->fr_fix += 4;
252b5132 4459 break;
151337e8
NC		 4460 case TAB (DBCCABSJ, LONG):
4461 /* only DBcc instructions can come here */
4462 /* Change dbcc into dbcc/jmp. */
4463
4464 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4465 *buffer_address++ = 0x00; /* branch offset = 4 */
4466 *buffer_address++ = 0x04;
4467 *buffer_address++ = 0x60; /* put in bra pc+6 */
4468 *buffer_address++ = 0x06;
4469 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4470 *buffer_address++ = (char) 0xf9;
4471
4472 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4473 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4474 RELAX_RELOC_ABS32);
252b5132 4475 fragP->fr_fix += 4;
252b5132 4476 break;
151337e8 4477 case TAB (PCREL1632, SHORT):
252b5132
RH		 4478 fragP->fr_opcode[1] &= ~0x3F;
4479 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4480 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4481 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4482 fragP->fr_fix += 2;
252b5132 4483 break;
151337e8 4484 case TAB (PCREL1632, LONG):
252b5132
RH		 4485 /* Already set to mode 7.3; this indicates: PC indirect with
4486 suppressed index, 32-bit displacement. */
4487 *buffer_address++ = 0x01;
4488 *buffer_address++ = 0x70;
4489 fragP->fr_fix += 2;
151337e8 4490 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4491 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4492 fixP->fx_pcrel_adjust = 2;
4493 fragP->fr_fix += 4;
252b5132 4494 break;
252b5132 4495 case TAB (PCINDEX, BYTE):
252b5132
RH		 4496 assert (fragP->fr_fix >= 2);
4497 buffer_address[-2] &= ~1;
151337e8 4498 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4499 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4500 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4501 break;
4502 case TAB (PCINDEX, SHORT):
252b5132
RH		 4503 assert (fragP->fr_fix >= 2);
4504 buffer_address[-2] |= 0x1;
4505 buffer_address[-1] = 0x20;
4506 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4507 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4508 fixP->fx_pcrel_adjust = 2;
151337e8 4509 fragP->fr_fix += 2;
252b5132
RH		 4510 break;
4511 case TAB (PCINDEX, LONG):
252b5132
RH		 4512 assert (fragP->fr_fix >= 2);
4513 buffer_address[-2] |= 0x1;
4514 buffer_address[-1] = 0x30;
151337e8 4515 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4516 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4517 fixP->fx_pcrel_adjust = 2;
4518 fragP->fr_fix += 4;
4519 break;
4520 case TAB (ABSTOPCREL, SHORT):
4521 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4522 1, RELAX_RELOC_PC16);
151337e8
NC		 4523 fragP->fr_fix += 2;
4524 break;
4525 case TAB (ABSTOPCREL, LONG):
4526 /* The thing to do here is force it to ABSOLUTE LONG, since
4527 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4528 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4529 abort ();
4530 fragP->fr_opcode[1] &= ~0x3F;
4531 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4532 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4533 0, RELAX_RELOC_ABS32);
151337e8 4534 fragP->fr_fix += 4;
252b5132 4535 break;
252b5132
RH		 4536 }
4537}
4538
4539#ifndef BFD_ASSEMBLER
4540
4541void
4542md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4543 object_headers *headers ATTRIBUTE_UNUSED;
4544 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4545 fragS *fragP;
4546{
4547 md_convert_frag_1 (fragP);
4548}
4549
4550#else
4551
4552void
4553md_convert_frag (abfd, sec, fragP)
36823076
AS		 4554 bfd *abfd ATTRIBUTE_UNUSED;
4555 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4556 fragS *fragP;
4557{
4558 md_convert_frag_1 (fragP);
4559}
4560#endif
4561
4562/* Force truly undefined symbols to their maximum size, and generally set up
4563 the frag list to be relaxed
4564 */
4565int
4566md_estimate_size_before_relax (fragP, segment)
4567 register fragS *fragP;
4568 segT segment;
4569{
151337e8 4570 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4571 switch (fragP->fr_subtype)
4572 {
151337e8
NC		 4573 case TAB (BRANCHBWL, SZ_UNDEF):
4574 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4575 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4576 {
151337e8
NC		 4577 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4578 && relaxable_symbol (fragP->fr_symbol))
252b5132 4579 {
151337e8
NC		 4580 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4581 }
4582 else if (flag_short_refs)
4583 {
4584 /* Symbol is undefined and we want short ref. */
4585 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4586 }
4587 else
4588 {
151337e8
NC		 4589 /* Symbol is still undefined. Make it LONG. */
4590 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4591 }
4592 break;
151337e8 4593 }
252b5132 4594
151337e8 4595 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4596 {
151337e8
NC		 4597 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4598 && relaxable_symbol (fragP->fr_symbol))
252b5132 4599 {
151337e8 4600 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4601 }
4602 else
4603 {
151337e8
NC		 4604 /* Symbol is undefined and we don't have long branches. */
4605 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4606 }
4607 break;
151337e8 4608 }
252b5132 4609
151337e8 4610 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4611 case TAB (DBCCLBR, SZ_UNDEF):
4612 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4613 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4614 {
8ec6253e
NC		 4615 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4616 && relaxable_symbol (fragP->fr_symbol))
151337e8 4617 || flag_short_refs)
252b5132 4618 {
151337e8 4619 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4620 }
4621 else
4622 {
151337e8 4623 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4624 }
4625 break;
151337e8 4626 }
81d4177b 4627
252b5132
RH		 4628 case TAB (PCINDEX, SZ_UNDEF):
4629 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4630 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4631 {
4632 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4633 }
4634 else
4635 {
4636 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4637 }
4638 break;
4639
151337e8
NC		 4640 case TAB (ABSTOPCREL, SZ_UNDEF):
4641 {
4642 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4643 && relaxable_symbol (fragP->fr_symbol)))
4644 {
4645 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4646 }
4647 else
4648 {
4649 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4650 }
4651 break;
4652 }
4653
252b5132
RH		 4654 default:
4655 break;
4656 }
4657
151337e8 4658 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4659 switch (fragP->fr_subtype)
4660 {
151337e8
NC		 4661 case TAB (BRANCHBWL, BYTE):
4662 case TAB (BRABSJUNC, BYTE):
4663 case TAB (BRABSJCOND, BYTE):
4664 case TAB (BRANCHBW, BYTE):
252b5132 4665 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4666 case we force word mode. If the symbol is at the start of a
4667 frag, and it is the next frag with any data in it (usually
4668 this is just the next frag, but assembler listings may
4669 introduce empty frags), we must use word mode. */
4670 if (fragP->fr_symbol)
252b5132 4671 {
ac62c346 4672 fragS *sym_frag;
252b5132 4673
ac62c346
AM		 4674 sym_frag = symbol_get_frag (fragP->fr_symbol);
4675 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4676 {
ac62c346
AM		 4677 fragS *l;
4678
23b7f870 4679 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4680 if (l->fr_fix != 0)
4681 break;
4682 if (l == sym_frag)
4683 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4684 }
4685 }
4686 break;
4687 default:
4688 break;
4689 }
ac62c346 4690 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4691}
4692
4693#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4694/* the bit-field entries in the relocation_info struct plays hell
4695 with the byte-order problems of cross-assembly. So as a hack,
4696 I added this mach. dependent ri twiddler. Ugly, but it gets
4697 you there. -KWK */
4698/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4699 are symbolnum, most sig. byte first. Last byte is broken up with
4700 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4701 nibble as nuthin. (on Sun 3 at least) */
4702/* Translate the internal relocation information into target-specific
92774660 4703 format. */
252b5132
RH		 4704#ifdef comment
4705void
4706md_ri_to_chars (the_bytes, ri)
4707 char *the_bytes;
4708 struct reloc_info_generic *ri;
4709{
4710 /* this is easy */
4711 md_number_to_chars (the_bytes, ri->r_address, 4);
4712 /* now the fun stuff */
4713 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4714 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4715 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4716 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4717 ((ri->r_extern << 4) & 0x10));
4718}
4719
4720#endif /* comment */
4721
4722#ifndef BFD_ASSEMBLER
4723void
4724tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4725 char *where;
4726 fixS *fixP;
4727 relax_addressT segment_address_in_file;
4728{
4729 /*
4730 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4731 * Out: GNU LD relocation length code: 0, 1, or 2.
4732 */
4733
5a38dc70 4734 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
252b5132
RH		 4735 long r_symbolnum;
4736
4737 know (fixP->fx_addsy != NULL);
4738
4739 md_number_to_chars (where,
4740 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4741 4);
4742
4743 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4744 ? S_GET_TYPE (fixP->fx_addsy)
4745 : fixP->fx_addsy->sy_number);
4746
4747 where[4] = (r_symbolnum >> 16) & 0x0ff;
4748 where[5] = (r_symbolnum >> 8) & 0x0ff;
4749 where[6] = r_symbolnum & 0x0ff;
4750 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4751 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4752}
4753#endif
4754
4755#endif /* OBJ_AOUT or OBJ_BOUT */
4756
4757#ifndef WORKING_DOT_WORD
5a38dc70
AM		 4758const int md_short_jump_size = 4;
4759const int md_long_jump_size = 6;
252b5132
RH		 4760
4761void
4762md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4763 char *ptr;
4764 addressT from_addr, to_addr;
36823076
AS		 4765 fragS *frag ATTRIBUTE_UNUSED;
4766 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4767{
4768 valueT offset;
4769
4770 offset = to_addr - (from_addr + 2);
4771
4772 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4773 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4774}
4775
4776void
4777md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4778 char *ptr;
4779 addressT from_addr, to_addr;
4780 fragS *frag;
4781 symbolS *to_symbol;
4782{
4783 valueT offset;
4784
4785 if (!HAVE_LONG_BRANCH(current_architecture))
4786 {
4787 offset = to_addr - S_GET_VALUE (to_symbol);
4788 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4789 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4790 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4791 0, NO_RELOC);
4792 }
4793 else
4794 {
4795 offset = to_addr - (from_addr + 2);
4796 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4797 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4798 }
4799}
4800
4801#endif
4802
4803/* Different values of OK tell what its OK to return. Things that
4804 aren't OK are an error (what a shock, no?)
4805
4806 0: Everything is OK
4807 10: Absolute 1:8 only
4808 20: Absolute 0:7 only
4809 30: absolute 0:15 only
4810 40: Absolute 0:31 only
4811 50: absolute 0:127 only
4812 55: absolute -64:63 only
4813 60: absolute -128:127 only
4814 70: absolute 0:4095 only
4815 80: No bignums
4816
4817 */
4818
4819static int
4820get_num (exp, ok)
4821 struct m68k_exp *exp;
4822 int ok;
4823{
4824 if (exp->exp.X_op == O_absent)
4825 {
4826 /* Do the same thing the VAX asm does */
4827 op (exp) = O_constant;
4828 adds (exp) = 0;
4829 subs (exp) = 0;
4830 offs (exp) = 0;
4831 if (ok == 10)
4832 {
4833 as_warn (_("expression out of range: defaulting to 1"));
4834 offs (exp) = 1;
4835 }
4836 }
4837 else if (exp->exp.X_op == O_constant)
4838 {
4839 switch (ok)
4840 {
4841 case 10:
4842 if (offs (exp) < 1 || offs (exp) > 8)
4843 {
4844 as_warn (_("expression out of range: defaulting to 1"));
4845 offs (exp) = 1;
4846 }
4847 break;
4848 case 20:
4849 if (offs (exp) < 0 || offs (exp) > 7)
4850 goto outrange;
4851 break;
4852 case 30:
4853 if (offs (exp) < 0 || offs (exp) > 15)
4854 goto outrange;
4855 break;
4856 case 40:
4857 if (offs (exp) < 0 || offs (exp) > 32)
4858 goto outrange;
4859 break;
4860 case 50:
4861 if (offs (exp) < 0 || offs (exp) > 127)
4862 goto outrange;
4863 break;
4864 case 55:
4865 if (offs (exp) < -64 || offs (exp) > 63)
4866 goto outrange;
4867 break;
4868 case 60:
4869 if (offs (exp) < -128 || offs (exp) > 127)
4870 goto outrange;
4871 break;
4872 case 70:
4873 if (offs (exp) < 0 || offs (exp) > 4095)
4874 {
4875 outrange:
4876 as_warn (_("expression out of range: defaulting to 0"));
4877 offs (exp) = 0;
4878 }
4879 break;
4880 default:
4881 break;
4882 }
4883 }
4884 else if (exp->exp.X_op == O_big)
4885 {
4886 if (offs (exp) <= 0 /* flonum */
4887 && (ok == 80 /* no bignums */
4888 || (ok > 10 /* small-int ranges including 0 ok */
4889 /* If we have a flonum zero, a zero integer should
4890 do as well (e.g., in moveq). */
4891 && generic_floating_point_number.exponent == 0
4892 && generic_floating_point_number.low[0] == 0)))
4893 {
4894 /* HACK! Turn it into a long */
4895 LITTLENUM_TYPE words[6];
4896
4897 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4898 op (exp) = O_constant;
4899 adds (exp) = 0;
4900 subs (exp) = 0;
4901 offs (exp) = words[1] | (words[0] << 16);
4902 }
4903 else if (ok != 0)
4904 {
4905 op (exp) = O_constant;
4906 adds (exp) = 0;
4907 subs (exp) = 0;
4908 offs (exp) = (ok == 10) ? 1 : 0;
4909 as_warn (_("Can't deal with expression; defaulting to %ld"),
4910 offs (exp));
4911 }
4912 }
4913 else
4914 {
4915 if (ok >= 10 && ok <= 70)
4916 {
4917 op (exp) = O_constant;
4918 adds (exp) = 0;
4919 subs (exp) = 0;
4920 offs (exp) = (ok == 10) ? 1 : 0;
4921 as_warn (_("Can't deal with expression; defaulting to %ld"),
4922 offs (exp));
4923 }
4924 }
4925
4926 if (exp->size != SIZE_UNSPEC)
4927 {
4928 switch (exp->size)
4929 {
4930 case SIZE_UNSPEC:
4931 case SIZE_LONG:
4932 break;
4933 case SIZE_BYTE:
4934 if (!isbyte (offs (exp)))
4935 as_warn (_("expression doesn't fit in BYTE"));
4936 break;
4937 case SIZE_WORD:
4938 if (!isword (offs (exp)))
4939 as_warn (_("expression doesn't fit in WORD"));
4940 break;
4941 }
4942 }
4943
4944 return offs (exp);
4945}
4946
4947/* These are the back-ends for the various machine dependent pseudo-ops. */
4948
4949static void
4950s_data1 (ignore)
36823076 4951 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4952{
4953 subseg_set (data_section, 1);
4954 demand_empty_rest_of_line ();
4955}
4956
4957static void
4958s_data2 (ignore)
36823076 4959 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4960{
4961 subseg_set (data_section, 2);
4962 demand_empty_rest_of_line ();
4963}
4964
4965static void
4966s_bss (ignore)
36823076 4967 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4968{
4969 /* We don't support putting frags in the BSS segment, we fake it
4970 by marking in_bss, then looking at s_skip for clues. */
4971
4972 subseg_set (bss_section, 0);
4973 demand_empty_rest_of_line ();
4974}
4975
4976static void
4977s_even (ignore)
36823076 4978 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4979{
4980 register int temp;
4981 register long temp_fill;
4982
4983 temp = 1; /* JF should be 2? */
4984 temp_fill = get_absolute_expression ();
92774660 4985 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 4986 frag_align (temp, (int) temp_fill, 0);
4987 demand_empty_rest_of_line ();
4988 record_alignment (now_seg, temp);
4989}
4990
4991static void
4992s_proc (ignore)
36823076 4993 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4994{
4995 demand_empty_rest_of_line ();
4996}
4997\f
4998/* Pseudo-ops handled for MRI compatibility. */
4999
5000/* This function returns non-zero if the argument is a conditional
5001 pseudo-op. This is called when checking whether a pending
5002 alignment is needed. */
5003
5004int
5005m68k_conditional_pseudoop (pop)
5006 pseudo_typeS *pop;
5007{
5008 return (pop->poc_handler == s_mri_if
5009 || pop->poc_handler == s_mri_else);
5010}
5011
5012/* Handle an MRI style chip specification. */
5013
5014static void
5015mri_chip ()
5016{
5017 char *s;
5018 char c;
5019 int i;
5020
5021 s = input_line_pointer;
5022 /* We can't use get_symbol_end since the processor names are not proper
5023 symbols. */
5024 while (is_part_of_name (c = *input_line_pointer++))
5025 ;
5026 *--input_line_pointer = 0;
5027 for (i = 0; i < n_archs; i++)
5028 if (strcasecmp (s, archs[i].name) == 0)
5029 break;
5030 if (i >= n_archs)
5031 {
5032 as_bad (_("%s: unrecognized processor name"), s);
5033 *input_line_pointer = c;
5034 ignore_rest_of_line ();
5035 return;
5036 }
5037 *input_line_pointer = c;
5038
5039 if (*input_line_pointer == '/')
5040 current_architecture = 0;
5041 else
5042 current_architecture &= m68881 | m68851;
5043 current_architecture |= archs[i].arch;
5044
5045 while (*input_line_pointer == '/')
5046 {
5047 ++input_line_pointer;
5048 s = input_line_pointer;
5049 /* We can't use get_symbol_end since the processor names are not
5050 proper symbols. */
5051 while (is_part_of_name (c = *input_line_pointer++))
5052 ;
5053 *--input_line_pointer = 0;
5054 if (strcmp (s, "68881") == 0)
5055 current_architecture |= m68881;
5056 else if (strcmp (s, "68851") == 0)
5057 current_architecture |= m68851;
5058 *input_line_pointer = c;
5059 }
5060
5061 /* Update info about available control registers. */
5062 select_control_regs ();
5063}
5064
5065/* The MRI CHIP pseudo-op. */
5066
5067static void
5068s_chip (ignore)
36823076 5069 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5070{
5071 char *stop = NULL;
5072 char stopc;
5073
5074 if (flag_mri)
5075 stop = mri_comment_field (&stopc);
5076 mri_chip ();
5077 if (flag_mri)
5078 mri_comment_end (stop, stopc);
5079 demand_empty_rest_of_line ();
5080}
5081
5082/* The MRI FOPT pseudo-op. */
5083
5084static void
5085s_fopt (ignore)
36823076 5086 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5087{
5088 SKIP_WHITESPACE ();
5089
5090 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5091 {
5092 int temp;
5093
5094 input_line_pointer += 3;
5095 temp = get_absolute_expression ();
5096 if (temp < 0 || temp > 7)
5097 as_bad (_("bad coprocessor id"));
5098 else
5099 m68k_float_copnum = COP0 + temp;
5100 }
5101 else
5102 {
5103 as_bad (_("unrecognized fopt option"));
5104 ignore_rest_of_line ();
5105 return;
5106 }
5107
5108 demand_empty_rest_of_line ();
5109}
5110
5111/* The structure used to handle the MRI OPT pseudo-op. */
5112
5113struct opt_action
5114{
5115 /* The name of the option. */
5116 const char *name;
5117
5118 /* If this is not NULL, just call this function. The first argument
5119 is the ARG field of this structure, the second argument is
5120 whether the option was negated. */
5121 void (*pfn) PARAMS ((int arg, int on));
5122
5123 /* If this is not NULL, and the PFN field is NULL, set the variable
5124 this points to. Set it to the ARG field if the option was not
5125 negated, and the NOTARG field otherwise. */
5126 int *pvar;
5127
5128 /* The value to pass to PFN or to assign to *PVAR. */
5129 int arg;
5130
5131 /* The value to assign to *PVAR if the option is negated. If PFN is
5132 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5133 the option may not be negated. */
5134 int notarg;
5135};
5136
5137/* The table used to handle the MRI OPT pseudo-op. */
5138
5139static void skip_to_comma PARAMS ((int, int));
5140static void opt_nest PARAMS ((int, int));
5141static void opt_chip PARAMS ((int, int));
5142static void opt_list PARAMS ((int, int));
5143static void opt_list_symbols PARAMS ((int, int));
5144
5145static const struct opt_action opt_table[] =
5146{
5147 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5148
5149 /* We do relaxing, so there is little use for these options. */
5150 { "b", 0, 0, 0, 0 },
5151 { "brs", 0, 0, 0, 0 },
5152 { "brb", 0, 0, 0, 0 },
5153 { "brl", 0, 0, 0, 0 },
5154 { "brw", 0, 0, 0, 0 },
5155
5156 { "c", 0, 0, 0, 0 },
5157 { "cex", 0, 0, 0, 0 },
5158 { "case", 0, &symbols_case_sensitive, 1, 0 },
5159 { "cl", 0, 0, 0, 0 },
5160 { "cre", 0, 0, 0, 0 },
5161 { "d", 0, &flag_keep_locals, 1, 0 },
5162 { "e", 0, 0, 0, 0 },
5163 { "f", 0, &flag_short_refs, 1, 0 },
5164 { "frs", 0, &flag_short_refs, 1, 0 },
5165 { "frl", 0, &flag_short_refs, 0, 1 },
5166 { "g", 0, 0, 0, 0 },
5167 { "i", 0, 0, 0, 0 },
5168 { "m", 0, 0, 0, 0 },
5169 { "mex", 0, 0, 0, 0 },
5170 { "mc", 0, 0, 0, 0 },
5171 { "md", 0, 0, 0, 0 },
5172 { "nest", opt_nest, 0, 0, 0 },
5173 { "next", skip_to_comma, 0, 0, 0 },
5174 { "o", 0, 0, 0, 0 },
5175 { "old", 0, 0, 0, 0 },
5176 { "op", skip_to_comma, 0, 0, 0 },
5177 { "pco", 0, 0, 0, 0 },
5178 { "p", opt_chip, 0, 0, 0 },
5179 { "pcr", 0, 0, 0, 0 },
5180 { "pcs", 0, 0, 0, 0 },
5181 { "r", 0, 0, 0, 0 },
5182 { "quick", 0, &m68k_quick, 1, 0 },
5183 { "rel32", 0, &m68k_rel32, 1, 0 },
5184 { "s", opt_list, 0, 0, 0 },
5185 { "t", opt_list_symbols, 0, 0, 0 },
5186 { "w", 0, &flag_no_warnings, 0, 1 },
5187 { "x", 0, 0, 0, 0 }
5188};
5189
8fce3f5e 5190#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5191
5192/* The MRI OPT pseudo-op. */
5193
5194static void
5195s_opt (ignore)
36823076 5196 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5197{
5198 do
5199 {
5200 int t;
5201 char *s;
5202 char c;
5203 int i;
5204 const struct opt_action *o;
5205
5206 SKIP_WHITESPACE ();
5207
5208 t = 1;
5209 if (*input_line_pointer == '-')
5210 {
5211 ++input_line_pointer;
5212 t = 0;
5213 }
5214 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5215 {
5216 input_line_pointer += 2;
5217 t = 0;
5218 }
5219
5220 s = input_line_pointer;
5221 c = get_symbol_end ();
5222
5223 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5224 {
5225 if (strcasecmp (s, o->name) == 0)
5226 {
5227 if (o->pfn)
5228 {
5229 /* Restore input_line_pointer now in case the option
5230 takes arguments. */
5231 *input_line_pointer = c;
5232 (*o->pfn) (o->arg, t);
5233 }
5234 else if (o->pvar != NULL)
5235 {
5236 if (! t && o->arg == o->notarg)
5237 as_bad (_("option `%s' may not be negated"), s);
5238 *input_line_pointer = c;
5239 *o->pvar = t ? o->arg : o->notarg;
5240 }
5241 else
5242 *input_line_pointer = c;
5243 break;
5244 }
5245 }
5246 if (i >= OPTCOUNT)
5247 {
5248 as_bad (_("option `%s' not recognized"), s);
5249 *input_line_pointer = c;
5250 }
5251 }
5252 while (*input_line_pointer++ == ',');
5253
5254 /* Move back to terminating character. */
5255 --input_line_pointer;
5256 demand_empty_rest_of_line ();
5257}
5258
5259/* Skip ahead to a comma. This is used for OPT options which we do
5260 not suppor tand which take arguments. */
5261
5262static void
5263skip_to_comma (arg, on)
36823076
AS		 5264 int arg ATTRIBUTE_UNUSED;
5265 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5266{
5267 while (*input_line_pointer != ','
5268 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5269 ++input_line_pointer;
5270}
5271
5272/* Handle the OPT NEST=depth option. */
5273
5274static void
5275opt_nest (arg, on)
36823076
AS		 5276 int arg ATTRIBUTE_UNUSED;
5277 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5278{
5279 if (*input_line_pointer != '=')
5280 {
5281 as_bad (_("bad format of OPT NEST=depth"));
5282 return;
5283 }
5284
5285 ++input_line_pointer;
5286 max_macro_nest = get_absolute_expression ();
5287}
5288
5289/* Handle the OPT P=chip option. */
5290
5291static void
5292opt_chip (arg, on)
36823076
AS		 5293 int arg ATTRIBUTE_UNUSED;
5294 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5295{
5296 if (*input_line_pointer != '=')
5297 {
5298 /* This is just OPT P, which we do not support. */
5299 return;
5300 }
5301
5302 ++input_line_pointer;
5303 mri_chip ();
5304}
5305
5306/* Handle the OPT S option. */
5307
5308static void
5309opt_list (arg, on)
36823076 5310 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5311 int on;
5312{
5313 listing_list (on);
5314}
5315
5316/* Handle the OPT T option. */
5317
5318static void
5319opt_list_symbols (arg, on)
36823076 5320 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5321 int on;
5322{
5323 if (on)
5324 listing |= LISTING_SYMBOLS;
5325 else
8a104df9 5326 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5327}
5328
5329/* Handle the MRI REG pseudo-op. */
5330
5331static void
5332s_reg (ignore)
36823076 5333 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5334{
5335 char *s;
5336 int c;
5337 struct m68k_op rop;
5338 int mask;
5339 char *stop = NULL;
5340 char stopc;
5341
5342 if (line_label == NULL)
5343 {
5344 as_bad (_("missing label"));
5345 ignore_rest_of_line ();
5346 return;
5347 }
5348
5349 if (flag_mri)
5350 stop = mri_comment_field (&stopc);
5351
5352 SKIP_WHITESPACE ();
5353
5354 s = input_line_pointer;
3882b010 5355 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5356#ifdef REGISTER_PREFIX
5357 || *input_line_pointer == REGISTER_PREFIX
5358#endif
5359 || *input_line_pointer == '/'
5360 || *input_line_pointer == '-')
5361 ++input_line_pointer;
5362 c = *input_line_pointer;
5363 *input_line_pointer = '\0';
5364
5365 if (m68k_ip_op (s, &rop) != 0)
5366 {
5367 if (rop.error == NULL)
5368 as_bad (_("bad register list"));
5369 else
5370 as_bad (_("bad register list: %s"), rop.error);
5371 *input_line_pointer = c;
5372 ignore_rest_of_line ();
5373 return;
5374 }
5375
5376 *input_line_pointer = c;
5377
5378 if (rop.mode == REGLST)
5379 mask = rop.mask;
5380 else if (rop.mode == DREG)
5381 mask = 1 << (rop.reg - DATA0);
5382 else if (rop.mode == AREG)
5383 mask = 1 << (rop.reg - ADDR0 + 8);
5384 else if (rop.mode == FPREG)
5385 mask = 1 << (rop.reg - FP0 + 16);
5386 else if (rop.mode == CONTROL
5387 && rop.reg == FPI)
5388 mask = 1 << 24;
5389 else if (rop.mode == CONTROL
5390 && rop.reg == FPS)
5391 mask = 1 << 25;
5392 else if (rop.mode == CONTROL
5393 && rop.reg == FPC)
5394 mask = 1 << 26;
5395 else
5396 {
5397 as_bad (_("bad register list"));
5398 ignore_rest_of_line ();
5399 return;
5400 }
5401
5402 S_SET_SEGMENT (line_label, reg_section);
5403 S_SET_VALUE (line_label, ~mask);
49309057 5404 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5405
5406 if (flag_mri)
5407 mri_comment_end (stop, stopc);
5408
5409 demand_empty_rest_of_line ();
5410}
5411
5412/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5413
5414struct save_opts
5415{
5416 struct save_opts *next;
5417 int abspcadd;
5418 int symbols_case_sensitive;
5419 int keep_locals;
5420 int short_refs;
5421 int architecture;
5422 int quick;
5423 int rel32;
5424 int listing;
5425 int no_warnings;
5426 /* FIXME: We don't save OPT S. */
5427};
5428
5429/* This variable holds the stack of saved options. */
5430
5431static struct save_opts *save_stack;
5432
5433/* The MRI SAVE pseudo-op. */
5434
5435static void
5436s_save (ignore)
36823076 5437 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5438{
5439 struct save_opts *s;
5440
5441 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5442 s->abspcadd = m68k_abspcadd;
5443 s->symbols_case_sensitive = symbols_case_sensitive;
5444 s->keep_locals = flag_keep_locals;
5445 s->short_refs = flag_short_refs;
5446 s->architecture = current_architecture;
5447 s->quick = m68k_quick;
5448 s->rel32 = m68k_rel32;
5449 s->listing = listing;
5450 s->no_warnings = flag_no_warnings;
5451
5452 s->next = save_stack;
5453 save_stack = s;
5454
5455 demand_empty_rest_of_line ();
5456}
5457
5458/* The MRI RESTORE pseudo-op. */
5459
5460static void
5461s_restore (ignore)
36823076 5462 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5463{
5464 struct save_opts *s;
5465
5466 if (save_stack == NULL)
5467 {
5468 as_bad (_("restore without save"));
5469 ignore_rest_of_line ();
5470 return;
5471 }
5472
5473 s = save_stack;
5474 save_stack = s->next;
5475
5476 m68k_abspcadd = s->abspcadd;
5477 symbols_case_sensitive = s->symbols_case_sensitive;
5478 flag_keep_locals = s->keep_locals;
5479 flag_short_refs = s->short_refs;
5480 current_architecture = s->architecture;
5481 m68k_quick = s->quick;
5482 m68k_rel32 = s->rel32;
5483 listing = s->listing;
5484 flag_no_warnings = s->no_warnings;
5485
5486 free (s);
5487
5488 demand_empty_rest_of_line ();
5489}
5490
5491/* Types of MRI structured control directives. */
5492
5493enum mri_control_type
5494{
5495 mri_for,
5496 mri_if,
5497 mri_repeat,
5498 mri_while
5499};
5500
5501/* This structure is used to stack the MRI structured control
5502 directives. */
5503
5504struct mri_control_info
5505{
5506 /* The directive within which this one is enclosed. */
5507 struct mri_control_info *outer;
5508
5509 /* The type of directive. */
5510 enum mri_control_type type;
5511
5512 /* Whether an ELSE has been in an IF. */
5513 int else_seen;
5514
5515 /* The add or sub statement at the end of a FOR. */
5516 char *incr;
5517
5518 /* The label of the top of a FOR or REPEAT loop. */
5519 char *top;
5520
5521 /* The label to jump to for the next iteration, or the else
5522 expression of a conditional. */
5523 char *next;
5524
5525 /* The label to jump to to break out of the loop, or the label past
5526 the end of a conditional. */
5527 char *bottom;
5528};
5529
5530/* The stack of MRI structured control directives. */
5531
5532static struct mri_control_info *mri_control_stack;
5533
5534/* The current MRI structured control directive index number, used to
5535 generate label names. */
5536
5537static int mri_control_index;
5538
5539/* Some function prototypes. */
5540
5541static void mri_assemble PARAMS ((char *));
5542static char *mri_control_label PARAMS ((void));
5543static struct mri_control_info *push_mri_control
5544 PARAMS ((enum mri_control_type));
5545static void pop_mri_control PARAMS ((void));
5546static int parse_mri_condition PARAMS ((int *));
5547static int parse_mri_control_operand
5548 PARAMS ((int *, char **, char **, char **, char **));
5549static int swap_mri_condition PARAMS ((int));
5550static int reverse_mri_condition PARAMS ((int));
5551static void build_mri_control_operand
5552 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5553 const char *, int));
5554static void parse_mri_control_expression
5555 PARAMS ((char *, int, const char *, const char *, int));
5556
5557/* Assemble an instruction for an MRI structured control directive. */
5558
5559static void
5560mri_assemble (str)
5561 char *str;
5562{
5563 char *s;
5564
5565 /* md_assemble expects the opcode to be in lower case. */
5566 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5567 *s = TOLOWER (*s);
252b5132
RH		 5568
5569 md_assemble (str);
5570}
5571
5572/* Generate a new MRI label structured control directive label name. */
5573
5574static char *
5575mri_control_label ()
5576{
5577 char *n;
5578
5579 n = (char *) xmalloc (20);
5580 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5581 ++mri_control_index;
5582 return n;
5583}
5584
5585/* Create a new MRI structured control directive. */
5586
5587static struct mri_control_info *
5588push_mri_control (type)
5589 enum mri_control_type type;
5590{
5591 struct mri_control_info *n;
5592
5593 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5594
5595 n->type = type;
5596 n->else_seen = 0;
5597 if (type == mri_if || type == mri_while)
5598 n->top = NULL;
5599 else
5600 n->top = mri_control_label ();
5601 n->next = mri_control_label ();
5602 n->bottom = mri_control_label ();
5603
5604 n->outer = mri_control_stack;
5605 mri_control_stack = n;
5606
5607 return n;
5608}
5609
5610/* Pop off the stack of MRI structured control directives. */
5611
5612static void
5613pop_mri_control ()
5614{
5615 struct mri_control_info *n;
5616
5617 n = mri_control_stack;
5618 mri_control_stack = n->outer;
5619 if (n->top != NULL)
5620 free (n->top);
5621 free (n->next);
5622 free (n->bottom);
5623 free (n);
5624}
5625
5626/* Recognize a condition code in an MRI structured control expression. */
5627
5628static int
5629parse_mri_condition (pcc)
5630 int *pcc;
5631{
5632 char c1, c2;
5633
5634 know (*input_line_pointer == '<');
5635
5636 ++input_line_pointer;
5637 c1 = *input_line_pointer++;
5638 c2 = *input_line_pointer++;
5639
5640 if (*input_line_pointer != '>')
5641 {
5642 as_bad (_("syntax error in structured control directive"));
5643 return 0;
5644 }
5645
5646 ++input_line_pointer;
5647 SKIP_WHITESPACE ();
5648
3882b010
L		 5649 c1 = TOLOWER (c1);
5650 c2 = TOLOWER (c2);
252b5132
RH		 5651
5652 *pcc = (c1 << 8) | c2;
5653
5654 return 1;
5655}
5656
5657/* Parse a single operand in an MRI structured control expression. */
5658
5659static int
5660parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5661 int *pcc;
5662 char **leftstart;
5663 char **leftstop;
5664 char **rightstart;
5665 char **rightstop;
5666{
5667 char *s;
5668
5669 SKIP_WHITESPACE ();
5670
5671 *pcc = -1;
5672 *leftstart = NULL;
5673 *leftstop = NULL;
5674 *rightstart = NULL;
5675 *rightstop = NULL;
5676
5677 if (*input_line_pointer == '<')
5678 {
5679 /* It's just a condition code. */
5680 return parse_mri_condition (pcc);
5681 }
5682
5683 /* Look ahead for the condition code. */
5684 for (s = input_line_pointer; *s != '\0'; ++s)
5685 {
5686 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5687 break;
5688 }
5689 if (*s == '\0')
5690 {
5691 as_bad (_("missing condition code in structured control directive"));
5692 return 0;
5693 }
5694
5695 *leftstart = input_line_pointer;
5696 *leftstop = s;
5697 if (*leftstop > *leftstart
5698 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5699 --*leftstop;
5700
5701 input_line_pointer = s;
5702 if (! parse_mri_condition (pcc))
5703 return 0;
5704
5705 /* Look ahead for AND or OR or end of line. */
5706 for (s = input_line_pointer; *s != '\0'; ++s)
5707 {
e1f44d10
NC		 5708 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5709 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5710 ^^^ ^^ */
8a104df9
KH		 5711 if ((s == input_line_pointer
5712 || *(s-1) == ' '
5713 || *(s-1) == '\t')
5714 && ((strncasecmp (s, "AND", 3) == 0
5715 && (s[3] == '.' || ! is_part_of_name (s[3])))
5716 || (strncasecmp (s, "OR", 2) == 0
5717 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5718 break;
252b5132
RH		 5719 }
5720
5721 *rightstart = input_line_pointer;
5722 *rightstop = s;
5723 if (*rightstop > *rightstart
5724 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5725 --*rightstop;
5726
5727 input_line_pointer = s;
5728
5729 return 1;
5730}
5731
5732#define MCC(b1, b2) (((b1) << 8) | (b2))
5733
5734/* Swap the sense of a condition. This changes the condition so that
5735 it generates the same result when the operands are swapped. */
5736
5737static int
5738swap_mri_condition (cc)
5739 int cc;
5740{
5741 switch (cc)
5742 {
5743 case MCC ('h', 'i'): return MCC ('c', 's');
5744 case MCC ('l', 's'): return MCC ('c', 'c');
e1f44d10
NC		 5745 /* <HS> is an alias for <CC> */
5746 case MCC ('h', 's'):
252b5132 5747 case MCC ('c', 'c'): return MCC ('l', 's');
e1f44d10
NC		 5748 /* <LO> is an alias for <CS> */
5749 case MCC ('l', 'o'):
252b5132
RH		 5750 case MCC ('c', 's'): return MCC ('h', 'i');
5751 case MCC ('p', 'l'): return MCC ('m', 'i');
5752 case MCC ('m', 'i'): return MCC ('p', 'l');
5753 case MCC ('g', 'e'): return MCC ('l', 'e');
5754 case MCC ('l', 't'): return MCC ('g', 't');
5755 case MCC ('g', 't'): return MCC ('l', 't');
5756 case MCC ('l', 'e'): return MCC ('g', 'e');
e1f44d10
NC		 5757 /* issue a warning for conditions we can not swap */
5758 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5759 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5760 case MCC ('v', 'c'):
5761 case MCC ('v', 's'):
5762 default :
5763 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5764 (char) (cc >> 8), (char) (cc));
5765 break;
252b5132
RH		 5766 }
5767 return cc;
5768}
5769
5770/* Reverse the sense of a condition. */
5771
5772static int
5773reverse_mri_condition (cc)
5774 int cc;
5775{
5776 switch (cc)
5777 {
5778 case MCC ('h', 'i'): return MCC ('l', 's');
5779 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5780 /* <HS> is an alias for <CC> */
5781 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5782 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5783 /* <LO> is an alias for <CS> */
5784 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5785 case MCC ('c', 's'): return MCC ('c', 'c');
5786 case MCC ('n', 'e'): return MCC ('e', 'q');
5787 case MCC ('e', 'q'): return MCC ('n', 'e');
5788 case MCC ('v', 'c'): return MCC ('v', 's');
5789 case MCC ('v', 's'): return MCC ('v', 'c');
5790 case MCC ('p', 'l'): return MCC ('m', 'i');
5791 case MCC ('m', 'i'): return MCC ('p', 'l');
5792 case MCC ('g', 'e'): return MCC ('l', 't');
5793 case MCC ('l', 't'): return MCC ('g', 'e');
5794 case MCC ('g', 't'): return MCC ('l', 'e');
5795 case MCC ('l', 'e'): return MCC ('g', 't');
5796 }
5797 return cc;
5798}
5799
5800/* Build an MRI structured control expression. This generates test
5801 and branch instructions. It goes to TRUELAB if the condition is
5802 true, and to FALSELAB if the condition is false. Exactly one of
5803 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5804 is the size qualifier for the expression. EXTENT is the size to
5805 use for the branch. */
5806
5807static void
5808build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5809 rightstop, truelab, falselab, extent)
5810 int qual;
5811 int cc;
5812 char *leftstart;
5813 char *leftstop;
5814 char *rightstart;
5815 char *rightstop;
5816 const char *truelab;
5817 const char *falselab;
5818 int extent;
5819{
5820 char *buf;
5821 char *s;
5822
5823 if (leftstart != NULL)
5824 {
5825 struct m68k_op leftop, rightop;
5826 char c;
5827
5828 /* Swap the compare operands, if necessary, to produce a legal
5829 m68k compare instruction. Comparing a register operand with
5830 a non-register operand requires the register to be on the
5831 right (cmp, cmpa). Comparing an immediate value with
5832 anything requires the immediate value to be on the left
5833 (cmpi). */
5834
5835 c = *leftstop;
5836 *leftstop = '\0';
5837 (void) m68k_ip_op (leftstart, &leftop);
5838 *leftstop = c;
5839
5840 c = *rightstop;
5841 *rightstop = '\0';
5842 (void) m68k_ip_op (rightstart, &rightop);
5843 *rightstop = c;
5844
5845 if (rightop.mode == IMMED
5846 || ((leftop.mode == DREG || leftop.mode == AREG)
5847 && (rightop.mode != DREG && rightop.mode != AREG)))
5848 {
5849 char *temp;
5850
e1f44d10
NC		 5851 /* Correct conditional handling:
5852 if #1 <lt> d0 then ;means if (1 < d0)
5853 ...
5854 endi
5855
5856 should assemble to:
5857
5858 cmp #1,d0 if we do *not* swap the operands
5859 bgt true we need the swapped condition!
5860 ble false
5861 true:
5862 ...
5863 false:
5864 */
252b5132
RH		 5865 temp = leftstart;
5866 leftstart = rightstart;
5867 rightstart = temp;
5868 temp = leftstop;
5869 leftstop = rightstop;
5870 rightstop = temp;
8a104df9
KH		 5871 }
5872 else
5873 {
e1f44d10 5874 cc = swap_mri_condition (cc);
252b5132
RH		 5875 }
5876 }
5877
5878 if (truelab == NULL)
5879 {
5880 cc = reverse_mri_condition (cc);
5881 truelab = falselab;
5882 }
92774660 5883
252b5132
RH		 5884 if (leftstart != NULL)
5885 {
5886 buf = (char *) xmalloc (20
5887 + (leftstop - leftstart)
5888 + (rightstop - rightstart));
5889 s = buf;
5890 *s++ = 'c';
5891 *s++ = 'm';
5892 *s++ = 'p';
5893 if (qual != '\0')
3882b010 5894 *s++ = TOLOWER (qual);
252b5132
RH		 5895 *s++ = ' ';
5896 memcpy (s, leftstart, leftstop - leftstart);
5897 s += leftstop - leftstart;
5898 *s++ = ',';
5899 memcpy (s, rightstart, rightstop - rightstart);
5900 s += rightstop - rightstart;
5901 *s = '\0';
5902 mri_assemble (buf);
5903 free (buf);
5904 }
92774660 5905
252b5132
RH		 5906 buf = (char *) xmalloc (20 + strlen (truelab));
5907 s = buf;
5908 *s++ = 'b';
5909 *s++ = cc >> 8;
5910 *s++ = cc & 0xff;
5911 if (extent != '\0')
3882b010 5912 *s++ = TOLOWER (extent);
252b5132
RH		 5913 *s++ = ' ';
5914 strcpy (s, truelab);
5915 mri_assemble (buf);
5916 free (buf);
5917}
5918
5919/* Parse an MRI structured control expression. This generates test
5920 and branch instructions. STOP is where the expression ends. It
5921 goes to TRUELAB if the condition is true, and to FALSELAB if the
5922 condition is false. Exactly one of TRUELAB and FALSELAB will be
5923 NULL, meaning to fall through. QUAL is the size qualifier for the
5924 expression. EXTENT is the size to use for the branch. */
5925
5926static void
5927parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5928 char *stop;
5929 int qual;
5930 const char *truelab;
5931 const char *falselab;
5932 int extent;
5933{
5934 int c;
5935 int cc;
5936 char *leftstart;
5937 char *leftstop;
5938 char *rightstart;
5939 char *rightstop;
5940
5941 c = *stop;
5942 *stop = '\0';
5943
5944 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5945 &rightstart, &rightstop))
5946 {
5947 *stop = c;
5948 return;
5949 }
5950
5951 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5952 {
5953 const char *flab;
5954
5955 if (falselab != NULL)
5956 flab = falselab;
5957 else
5958 flab = mri_control_label ();
5959
5960 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5961 rightstop, (const char *) NULL, flab, extent);
5962
5963 input_line_pointer += 3;
5964 if (*input_line_pointer != '.'
5965 || input_line_pointer[1] == '\0')
5966 qual = '\0';
5967 else
5968 {
5969 qual = input_line_pointer[1];
5970 input_line_pointer += 2;
5971 }
5972
5973 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5974 &rightstart, &rightstop))
5975 {
5976 *stop = c;
5977 return;
5978 }
5979
5980 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5981 rightstop, truelab, falselab, extent);
5982
5983 if (falselab == NULL)
5984 colon (flab);
5985 }
5986 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5987 {
5988 const char *tlab;
5989
5990 if (truelab != NULL)
5991 tlab = truelab;
5992 else
5993 tlab = mri_control_label ();
5994
5995 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5996 rightstop, tlab, (const char *) NULL, extent);
5997
5998 input_line_pointer += 2;
5999 if (*input_line_pointer != '.'
6000 || input_line_pointer[1] == '\0')
6001 qual = '\0';
6002 else
6003 {
6004 qual = input_line_pointer[1];
6005 input_line_pointer += 2;
6006 }
6007
6008 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6009 &rightstart, &rightstop))
6010 {
6011 *stop = c;
6012 return;
6013 }
6014
6015 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6016 rightstop, truelab, falselab, extent);
6017
6018 if (truelab == NULL)
6019 colon (tlab);
6020 }
6021 else
6022 {
6023 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6024 rightstop, truelab, falselab, extent);
6025 }
6026
6027 *stop = c;
6028 if (input_line_pointer != stop)
6029 as_bad (_("syntax error in structured control directive"));
6030}
6031
6032/* Handle the MRI IF pseudo-op. This may be a structured control
6033 directive, or it may be a regular assembler conditional, depending
6034 on its operands. */
6035
6036static void
6037s_mri_if (qual)
6038 int qual;
6039{
6040 char *s;
6041 int c;
6042 struct mri_control_info *n;
6043
6044 /* A structured control directive must end with THEN with an
6045 optional qualifier. */
6046 s = input_line_pointer;
e1f44d10
NC		 6047 /* We only accept '*' as introduction of comments if preceded by white space
6048 or at first column of a line (I think this can't actually happen here?)
6049 This is important when assembling:
6050 if d0 <ne> 12(a0,d0*2) then
6051 if d0 <ne> #CONST*20 then */
6052 while ( ! ( is_end_of_line[(unsigned char) *s]
6053 || ( flag_mri
6054 && *s == '*'
6055 && ( s == input_line_pointer
6056 || *(s-1) == ' '
6057 || *(s-1) == '\t'))))
252b5132
RH		 6058 ++s;
6059 --s;
6060 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6061 --s;
6062
6063 if (s - input_line_pointer > 1
6064 && s[-1] == '.')
6065 s -= 2;
6066
6067 if (s - input_line_pointer < 3
6068 || strncasecmp (s - 3, "THEN", 4) != 0)
6069 {
6070 if (qual != '\0')
6071 {
6072 as_bad (_("missing then"));
6073 ignore_rest_of_line ();
6074 return;
6075 }
6076
6077 /* It's a conditional. */
6078 s_if (O_ne);
6079 return;
6080 }
6081
6082 /* Since this might be a conditional if, this pseudo-op will be
6083 called even if we are supported to be ignoring input. Double
6084 check now. Clobber *input_line_pointer so that ignore_input
6085 thinks that this is not a special pseudo-op. */
6086 c = *input_line_pointer;
6087 *input_line_pointer = 0;
6088 if (ignore_input ())
6089 {
6090 *input_line_pointer = c;
6091 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6092 ++input_line_pointer;
6093 demand_empty_rest_of_line ();
6094 return;
6095 }
6096 *input_line_pointer = c;
6097
6098 n = push_mri_control (mri_if);
6099
6100 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6101 n->next, s[1] == '.' ? s[2] : '\0');
6102
6103 if (s[1] == '.')
6104 input_line_pointer = s + 3;
6105 else
6106 input_line_pointer = s + 1;
6107
6108 if (flag_mri)
6109 {
6110 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6111 ++input_line_pointer;
6112 }
6113
6114 demand_empty_rest_of_line ();
6115}
6116
6117/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6118 structured IF, associate the ELSE with the IF. Otherwise, assume
6119 it is a conditional else. */
6120
6121static void
6122s_mri_else (qual)
6123 int qual;
6124{
6125 int c;
6126 char *buf;
6127 char q[2];
6128
6129 if (qual == '\0'
6130 && (mri_control_stack == NULL
6131 || mri_control_stack->type != mri_if
6132 || mri_control_stack->else_seen))
6133 {
6134 s_else (0);
6135 return;
6136 }
6137
6138 c = *input_line_pointer;
6139 *input_line_pointer = 0;
6140 if (ignore_input ())
6141 {
6142 *input_line_pointer = c;
6143 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6144 ++input_line_pointer;
6145 demand_empty_rest_of_line ();
6146 return;
6147 }
6148 *input_line_pointer = c;
6149
6150 if (mri_control_stack == NULL
6151 || mri_control_stack->type != mri_if
6152 || mri_control_stack->else_seen)
6153 {
6154 as_bad (_("else without matching if"));
6155 ignore_rest_of_line ();
6156 return;
6157 }
6158
6159 mri_control_stack->else_seen = 1;
6160
6161 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6162 q[0] = TOLOWER (qual);
252b5132
RH		 6163 q[1] = '\0';
6164 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6165 mri_assemble (buf);
6166 free (buf);
6167
6168 colon (mri_control_stack->next);
6169
6170 if (flag_mri)
6171 {
6172 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6173 ++input_line_pointer;
6174 }
6175
6176 demand_empty_rest_of_line ();
6177}
6178
6179/* Handle the MRI ENDI pseudo-op. */
6180
6181static void
6182s_mri_endi (ignore)
36823076 6183 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6184{
6185 if (mri_control_stack == NULL
6186 || mri_control_stack->type != mri_if)
6187 {
6188 as_bad (_("endi without matching if"));
6189 ignore_rest_of_line ();
6190 return;
6191 }
6192
6193 /* ignore_input will not return true for ENDI, so we don't need to
6194 worry about checking it again here. */
6195
6196 if (! mri_control_stack->else_seen)
6197 colon (mri_control_stack->next);
6198 colon (mri_control_stack->bottom);
6199
6200 pop_mri_control ();
6201
6202 if (flag_mri)
6203 {
6204 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6205 ++input_line_pointer;
6206 }
6207
6208 demand_empty_rest_of_line ();
6209}
6210
6211/* Handle the MRI BREAK pseudo-op. */
6212
6213static void
6214s_mri_break (extent)
6215 int extent;
6216{
6217 struct mri_control_info *n;
6218 char *buf;
6219 char ex[2];
6220
6221 n = mri_control_stack;
6222 while (n != NULL
6223 && n->type != mri_for
6224 && n->type != mri_repeat
6225 && n->type != mri_while)
6226 n = n->outer;
6227 if (n == NULL)
6228 {
6229 as_bad (_("break outside of structured loop"));
6230 ignore_rest_of_line ();
6231 return;
6232 }
6233
6234 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6235 ex[0] = TOLOWER (extent);
252b5132
RH		 6236 ex[1] = '\0';
6237 sprintf (buf, "bra%s %s", ex, n->bottom);
6238 mri_assemble (buf);
6239 free (buf);
6240
6241 if (flag_mri)
6242 {
6243 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6244 ++input_line_pointer;
6245 }
6246
6247 demand_empty_rest_of_line ();
6248}
6249
6250/* Handle the MRI NEXT pseudo-op. */
6251
6252static void
6253s_mri_next (extent)
6254 int extent;
6255{
6256 struct mri_control_info *n;
6257 char *buf;
6258 char ex[2];
6259
6260 n = mri_control_stack;
6261 while (n != NULL
6262 && n->type != mri_for
6263 && n->type != mri_repeat
6264 && n->type != mri_while)
6265 n = n->outer;
6266 if (n == NULL)
6267 {
6268 as_bad (_("next outside of structured loop"));
6269 ignore_rest_of_line ();
6270 return;
6271 }
6272
6273 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6274 ex[0] = TOLOWER (extent);
252b5132
RH		 6275 ex[1] = '\0';
6276 sprintf (buf, "bra%s %s", ex, n->next);
6277 mri_assemble (buf);
6278 free (buf);
6279
6280 if (flag_mri)
6281 {
6282 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6283 ++input_line_pointer;
6284 }
6285
6286 demand_empty_rest_of_line ();
6287}
6288
6289/* Handle the MRI FOR pseudo-op. */
6290
6291static void
6292s_mri_for (qual)
6293 int qual;
6294{
6295 const char *varstart, *varstop;
6296 const char *initstart, *initstop;
6297 const char *endstart, *endstop;
6298 const char *bystart, *bystop;
6299 int up;
6300 int by;
6301 int extent;
6302 struct mri_control_info *n;
6303 char *buf;
6304 char *s;
6305 char ex[2];
6306
6307 /* The syntax is
6308 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6309 */
6310
6311 SKIP_WHITESPACE ();
6312 varstart = input_line_pointer;
6313
6314 /* Look for the '='. */
6315 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6316 && *input_line_pointer != '=')
6317 ++input_line_pointer;
6318 if (*input_line_pointer != '=')
6319 {
6320 as_bad (_("missing ="));
6321 ignore_rest_of_line ();
6322 return;
6323 }
6324
6325 varstop = input_line_pointer;
6326 if (varstop > varstart
6327 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6328 --varstop;
6329
6330 ++input_line_pointer;
6331
6332 initstart = input_line_pointer;
6333
6334 /* Look for TO or DOWNTO. */
6335 up = 1;
6336 initstop = NULL;
6337 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6338 {
6339 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6340 && ! is_part_of_name (input_line_pointer[2]))
6341 {
6342 initstop = input_line_pointer;
6343 input_line_pointer += 2;
6344 break;
6345 }
6346 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6347 && ! is_part_of_name (input_line_pointer[6]))
6348 {
6349 initstop = input_line_pointer;
6350 up = 0;
6351 input_line_pointer += 6;
6352 break;
6353 }
6354 ++input_line_pointer;
6355 }
6356 if (initstop == NULL)
6357 {
6358 as_bad (_("missing to or downto"));
6359 ignore_rest_of_line ();
6360 return;
6361 }
6362 if (initstop > initstart
6363 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6364 --initstop;
6365
6366 SKIP_WHITESPACE ();
6367 endstart = input_line_pointer;
6368
6369 /* Look for BY or DO. */
6370 by = 0;
6371 endstop = NULL;
6372 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6373 {
6374 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6375 && ! is_part_of_name (input_line_pointer[2]))
6376 {
6377 endstop = input_line_pointer;
6378 by = 1;
6379 input_line_pointer += 2;
6380 break;
6381 }
6382 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6383 && (input_line_pointer[2] == '.'
6384 || ! is_part_of_name (input_line_pointer[2])))
6385 {
6386 endstop = input_line_pointer;
6387 input_line_pointer += 2;
6388 break;
6389 }
6390 ++input_line_pointer;
6391 }
6392 if (endstop == NULL)
6393 {
6394 as_bad (_("missing do"));
6395 ignore_rest_of_line ();
6396 return;
6397 }
6398 if (endstop > endstart
6399 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6400 --endstop;
6401
6402 if (! by)
6403 {
6404 bystart = "#1";
6405 bystop = bystart + 2;
6406 }
6407 else
6408 {
6409 SKIP_WHITESPACE ();
6410 bystart = input_line_pointer;
6411
6412 /* Look for DO. */
6413 bystop = NULL;
6414 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6415 {
6416 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6417 && (input_line_pointer[2] == '.'
6418 || ! is_part_of_name (input_line_pointer[2])))
6419 {
6420 bystop = input_line_pointer;
6421 input_line_pointer += 2;
6422 break;
6423 }
6424 ++input_line_pointer;
6425 }
6426 if (bystop == NULL)
6427 {
6428 as_bad (_("missing do"));
6429 ignore_rest_of_line ();
6430 return;
6431 }
6432 if (bystop > bystart
6433 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6434 --bystop;
6435 }
6436
6437 if (*input_line_pointer != '.')
6438 extent = '\0';
6439 else
6440 {
6441 extent = input_line_pointer[1];
6442 input_line_pointer += 2;
6443 }
6444
6445 /* We have fully parsed the FOR operands. Now build the loop. */
6446
6447 n = push_mri_control (mri_for);
6448
6449 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6450
6451 /* move init,var */
6452 s = buf;
6453 *s++ = 'm';
6454 *s++ = 'o';
6455 *s++ = 'v';
6456 *s++ = 'e';
6457 if (qual != '\0')
3882b010 6458 *s++ = TOLOWER (qual);
252b5132
RH		 6459 *s++ = ' ';
6460 memcpy (s, initstart, initstop - initstart);
6461 s += initstop - initstart;
6462 *s++ = ',';
6463 memcpy (s, varstart, varstop - varstart);
6464 s += varstop - varstart;
6465 *s = '\0';
6466 mri_assemble (buf);
6467
6468 colon (n->top);
6469
6470 /* cmp end,var */
6471 s = buf;
6472 *s++ = 'c';
6473 *s++ = 'm';
6474 *s++ = 'p';
6475 if (qual != '\0')
3882b010 6476 *s++ = TOLOWER (qual);
252b5132
RH		 6477 *s++ = ' ';
6478 memcpy (s, endstart, endstop - endstart);
6479 s += endstop - endstart;
6480 *s++ = ',';
6481 memcpy (s, varstart, varstop - varstart);
6482 s += varstop - varstart;
6483 *s = '\0';
6484 mri_assemble (buf);
6485
6486 /* bcc bottom */
3882b010 6487 ex[0] = TOLOWER (extent);
252b5132
RH		 6488 ex[1] = '\0';
6489 if (up)
6490 sprintf (buf, "blt%s %s", ex, n->bottom);
6491 else
6492 sprintf (buf, "bgt%s %s", ex, n->bottom);
6493 mri_assemble (buf);
6494
6495 /* Put together the add or sub instruction used by ENDF. */
6496 s = buf;
6497 if (up)
6498 strcpy (s, "add");
6499 else
6500 strcpy (s, "sub");
6501 s += 3;
6502 if (qual != '\0')
3882b010 6503 *s++ = TOLOWER (qual);
252b5132
RH		 6504 *s++ = ' ';
6505 memcpy (s, bystart, bystop - bystart);
6506 s += bystop - bystart;
6507 *s++ = ',';
6508 memcpy (s, varstart, varstop - varstart);
6509 s += varstop - varstart;
6510 *s = '\0';
6511 n->incr = buf;
6512
6513 if (flag_mri)
6514 {
6515 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6516 ++input_line_pointer;
6517 }
6518
6519 demand_empty_rest_of_line ();
6520}
6521
6522/* Handle the MRI ENDF pseudo-op. */
6523
6524static void
6525s_mri_endf (ignore)
36823076 6526 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6527{
6528 if (mri_control_stack == NULL
6529 || mri_control_stack->type != mri_for)
6530 {
6531 as_bad (_("endf without for"));
6532 ignore_rest_of_line ();
6533 return;
6534 }
6535
6536 colon (mri_control_stack->next);
6537
6538 mri_assemble (mri_control_stack->incr);
6539
6540 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6541 mri_assemble (mri_control_stack->incr);
6542
6543 free (mri_control_stack->incr);
6544
6545 colon (mri_control_stack->bottom);
6546
6547 pop_mri_control ();
6548
6549 if (flag_mri)
6550 {
6551 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6552 ++input_line_pointer;
6553 }
6554
6555 demand_empty_rest_of_line ();
6556}
6557
6558/* Handle the MRI REPEAT pseudo-op. */
6559
6560static void
6561s_mri_repeat (ignore)
36823076 6562 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6563{
6564 struct mri_control_info *n;
6565
6566 n = push_mri_control (mri_repeat);
6567 colon (n->top);
6568 if (flag_mri)
6569 {
6570 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6571 ++input_line_pointer;
6572 }
6573 demand_empty_rest_of_line ();
6574}
6575
6576/* Handle the MRI UNTIL pseudo-op. */
6577
6578static void
6579s_mri_until (qual)
6580 int qual;
6581{
6582 char *s;
6583
6584 if (mri_control_stack == NULL
6585 || mri_control_stack->type != mri_repeat)
6586 {
6587 as_bad (_("until without repeat"));
6588 ignore_rest_of_line ();
6589 return;
6590 }
6591
6592 colon (mri_control_stack->next);
6593
6594 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6595 ;
6596
6597 parse_mri_control_expression (s, qual, (const char *) NULL,
6598 mri_control_stack->top, '\0');
6599
6600 colon (mri_control_stack->bottom);
6601
6602 input_line_pointer = s;
6603
6604 pop_mri_control ();
6605
6606 if (flag_mri)
6607 {
6608 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6609 ++input_line_pointer;
6610 }
6611
6612 demand_empty_rest_of_line ();
6613}
6614
6615/* Handle the MRI WHILE pseudo-op. */
6616
6617static void
6618s_mri_while (qual)
6619 int qual;
6620{
6621 char *s;
6622
6623 struct mri_control_info *n;
6624
6625 s = input_line_pointer;
e1f44d10
NC		 6626 /* We only accept '*' as introduction of comments if preceded by white space
6627 or at first column of a line (I think this can't actually happen here?)
6628 This is important when assembling:
6629 while d0 <ne> 12(a0,d0*2) do
6630 while d0 <ne> #CONST*20 do */
8a104df9
KH		 6631 while (! (is_end_of_line[(unsigned char) *s]
6632 || (flag_mri
6633 && *s == '*'
6634 && (s == input_line_pointer
6635 || *(s-1) == ' '
6636 || *(s-1) == '\t'))))
252b5132
RH		 6637 s++;
6638 --s;
6639 while (*s == ' ' || *s == '\t')
6640 --s;
6641 if (s - input_line_pointer > 1
6642 && s[-1] == '.')
6643 s -= 2;
6644 if (s - input_line_pointer < 2
6645 || strncasecmp (s - 1, "DO", 2) != 0)
6646 {
6647 as_bad (_("missing do"));
6648 ignore_rest_of_line ();
6649 return;
6650 }
6651
6652 n = push_mri_control (mri_while);
6653
6654 colon (n->next);
6655
6656 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6657 s[1] == '.' ? s[2] : '\0');
6658
6659 input_line_pointer = s + 1;
6660 if (*input_line_pointer == '.')
6661 input_line_pointer += 2;
6662
6663 if (flag_mri)
6664 {
6665 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6666 ++input_line_pointer;
6667 }
6668
6669 demand_empty_rest_of_line ();
6670}
6671
6672/* Handle the MRI ENDW pseudo-op. */
6673
6674static void
6675s_mri_endw (ignore)
36823076 6676 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6677{
6678 char *buf;
6679
6680 if (mri_control_stack == NULL
6681 || mri_control_stack->type != mri_while)
6682 {
6683 as_bad (_("endw without while"));
6684 ignore_rest_of_line ();
6685 return;
6686 }
6687
6688 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6689 sprintf (buf, "bra %s", mri_control_stack->next);
6690 mri_assemble (buf);
6691 free (buf);
6692
6693 colon (mri_control_stack->bottom);
6694
6695 pop_mri_control ();
6696
6697 if (flag_mri)
6698 {
6699 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6700 ++input_line_pointer;
6701 }
6702
6703 demand_empty_rest_of_line ();
6704}
6705\f
6706/*
6707 * md_parse_option
6708 * Invocation line includes a switch not recognized by the base assembler.
6709 * See if it's a processor-specific option. These are:
6710 *
6711 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6712 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6713 * Select the architecture. Instructions or features not
6714 * supported by the selected architecture cause fatal
6715 * errors. More than one may be specified. The default is
6716 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6717 * for -m68000, and -m68882 is a synonym for -m68881.
6718 * -[A]m[c]no-68851, -[A]m[c]no-68881
6719 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6720 * so don't use or document it, but that's the way the parsing
6721 * works).
6722 *
6723 * -pic Indicates PIC.
6724 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6725 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6726 *
6727 * --bitwise-or
6728 * Permit `|' to be used in expressions.
6729 *
6730 */
6731
6732#ifdef OBJ_ELF
5a38dc70 6733const char *md_shortopts = "lSA:m:kQ:V";
252b5132 6734#else
5a38dc70 6735const char *md_shortopts = "lSA:m:k";
252b5132
RH		 6736#endif
6737
6738struct option md_longopts[] = {
6739#define OPTION_PIC (OPTION_MD_BASE)
6740 {"pic", no_argument, NULL, OPTION_PIC},
6741#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6742 {"register-prefix-optional", no_argument, NULL,
6743 OPTION_REGISTER_PREFIX_OPTIONAL},
6744#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6745 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6746#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6747 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6748#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6749 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6750#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6751 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6752#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6753 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6754#define OPTION_PCREL (OPTION_MD_BASE + 7)
6755 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6756 {NULL, no_argument, NULL, 0}
6757};
bc805888 6758size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6759
6760int
6761md_parse_option (c, arg)
6762 int c;
6763 char *arg;
6764{
6765 switch (c)
6766 {
6767 case 'l': /* -l means keep external to 2 bit offset
6768 rather than 16 bit one */
6769 flag_short_refs = 1;
6770 break;
6771
6772 case 'S': /* -S means that jbsr's always turn into
6773 jsr's. */
6774 flag_long_jumps = 1;
6775 break;
6776
28e7409f
NC		 6777 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6778 branches into absolute jumps. */
6779 flag_keep_pcrel = 1;
6780 break;
6781
252b5132
RH		 6782 case 'A':
6783 if (*arg == 'm')
8a104df9 6784 arg++;
252b5132
RH		 6785 /* intentional fall-through */
6786 case 'm':
6787
6788 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6789 {
6790 int i;
6791 unsigned long arch;
6792 const char *oarg = arg;
6793
6794 arg += 3;
6795 if (*arg == 'm')
6796 {
6797 arg++;
6798 if (arg[0] == 'c' && arg[1] == '6')
6799 arg++;
6800 }
6801 for (i = 0; i < n_archs; i++)
6802 if (!strcmp (arg, archs[i].name))
6803 break;
6804 if (i == n_archs)
6805 {
6806 unknown:
6807 as_bad (_("unrecognized option `%s'"), oarg);
6808 return 0;
6809 }
6810 arch = archs[i].arch;
6811 if (arch == m68881)
6812 no_68881 = 1;
6813 else if (arch == m68851)
6814 no_68851 = 1;
6815 else
6816 goto unknown;
6817 }
6818 else
6819 {
6820 int i;
6821
6822 if (arg[0] == 'c' && arg[1] == '6')
6823 arg++;
6824
6825 for (i = 0; i < n_archs; i++)
6826 if (!strcmp (arg, archs[i].name))
6827 {
6828 unsigned long arch = archs[i].arch;
6829 if (cpu_of_arch (arch))
6830 /* It's a cpu spec. */
6831 {
6832 current_architecture &= ~m68000up;
6833 current_architecture |= arch;
6834 }
6835 else if (arch == m68881)
6836 {
6837 current_architecture |= m68881;
6838 no_68881 = 0;
6839 }
6840 else if (arch == m68851)
6841 {
6842 current_architecture |= m68851;
6843 no_68851 = 0;
6844 }
6845 else
6846 /* ??? */
6847 abort ();
6848 break;
6849 }
6850 if (i == n_archs)
6851 {
6852 as_bad (_("unrecognized architecture specification `%s'"), arg);
6853 return 0;
6854 }
6855 }
6856 break;
6857
6858 case OPTION_PIC:
6859 case 'k':
6860 flag_want_pic = 1;
6861 break; /* -pic, Position Independent Code */
6862
6863 case OPTION_REGISTER_PREFIX_OPTIONAL:
6864 flag_reg_prefix_optional = 1;
6865 reg_prefix_optional_seen = 1;
6866 break;
6867
6868 /* -V: SVR4 argument to print version ID. */
6869 case 'V':
6870 print_version_id ();
6871 break;
6872
6873 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6874 should be emitted or not. FIXME: Not implemented. */
6875 case 'Q':
6876 break;
6877
6878 case OPTION_BITWISE_OR:
6879 {
6880 char *n, *t;
6881 const char *s;
6882
6883 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6884 t = n;
6885 for (s = m68k_comment_chars; *s != '\0'; s++)
6886 if (*s != '|')
6887 *t++ = *s;
6888 *t = '\0';
6889 m68k_comment_chars = n;
6890 }
6891 break;
6892
6893 case OPTION_BASE_SIZE_DEFAULT_16:
6894 m68k_index_width_default = SIZE_WORD;
6895 break;
6896
6897 case OPTION_BASE_SIZE_DEFAULT_32:
6898 m68k_index_width_default = SIZE_LONG;
6899 break;
6900
6901 case OPTION_DISP_SIZE_DEFAULT_16:
6902 m68k_rel32 = 0;
6903 m68k_rel32_from_cmdline = 1;
6904 break;
6905
6906 case OPTION_DISP_SIZE_DEFAULT_32:
6907 m68k_rel32 = 1;
6908 m68k_rel32_from_cmdline = 1;
6909 break;
6910
6911 default:
6912 return 0;
6913 }
6914
6915 return 1;
6916}
6917
6918void
6919md_show_usage (stream)
6920 FILE *stream;
6921{
76f57f3a 6922 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 6923 int i;
6924 unsigned int default_arch;
76f57f3a 6925
8a104df9 6926 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 6927 if (*default_cpu == 'm')
6928 default_cpu++;
6929 for (i = 0; i < n_archs; i++)
6930 {
6931 if (strcasecmp (default_cpu, archs[i].name) == 0)
6932 {
6933 default_arch = archs[i].arch;
6934 for (i = 0; i < n_archs; i++)
6935 {
6936 if (archs[i].arch == default_arch
6937 && !archs[i].alias)
6938 {
6939 default_cpu = archs[i].name;
6940 break;
6941 }
6942 }
6943 }
6944 }
6945
bc805888 6946 fprintf (stream, _("\
252b5132
RH		 6947680X0 options:\n\
6948-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 6949-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6950-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6951-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
76f57f3a 6952 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 6953-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6954 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 6955 [default yes for 68020, 68030, and cpu32]\n"),
6956 default_cpu);
bc805888 6957 fprintf (stream, _("\
252b5132
RH		 6958-m68851 | -mno-68851\n\
6959 target has/lacks memory-management unit coprocessor\n\
6960 [default yes for 68020 and up]\n\
6961-pic, -k generate position independent code\n\
6962-S turn jbsr into jsr\n\
28e7409f 6963--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6964--register-prefix-optional\n\
6965 recognize register names without prefix character\n\
6966--bitwise-or do not treat `|' as a comment character\n"));
6967 fprintf (stream, _("\
6968--base-size-default-16 base reg without size is 16 bits\n\
6969--base-size-default-32 base reg without size is 32 bits (default)\n\
6970--disp-size-default-16 displacement with unknown size is 16 bits\n\
6971--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6972}
6973\f
6974#ifdef TEST2
6975
6976/* TEST2: Test md_assemble() */
6977/* Warning, this routine probably doesn't work anymore */
6978
6979main ()
6980{
6981 struct m68k_it the_ins;
6982 char buf[120];
6983 char *cp;
6984 int n;
6985
6986 m68k_ip_begin ();
6987 for (;;)
6988 {
6989 if (!gets (buf) || !*buf)
6990 break;
6991 if (buf[0] == '|' || buf[1] == '.')
6992 continue;
6993 for (cp = buf; *cp; cp++)
6994 if (*cp == '\t')
6995 *cp = ' ';
6996 if (is_label (buf))
6997 continue;
6998 memset (&the_ins, '\0', sizeof (the_ins));
6999 m68k_ip (&the_ins, buf);
7000 if (the_ins.error)
7001 {
7002 printf (_("Error %s in %s\n"), the_ins.error, buf);
7003 }
7004 else
7005 {
7006 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7007 for (n = 0; n < the_ins.numo; n++)
7008 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7009 printf (" ");
7010 print_the_insn (&the_ins.opcode[0], stdout);
7011 (void) putchar ('\n');
7012 }
7013 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7014 {
7015 if (the_ins.operands[n].error)
7016 {
7017 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7018 continue;
7019 }
7020 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7021 if (the_ins.operands[n].b_const)
7022 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7023 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7024 if (the_ins.operands[n].b_iadd)
7025 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7026 (void) putchar ('\n');
7027 }
7028 }
7029 m68k_ip_end ();
7030 return 0;
7031}
7032
7033is_label (str)
7034 char *str;
7035{
7036 while (*str == ' ')
7037 str++;
7038 while (*str && *str != ' ')
7039 str++;
7040 if (str[-1] == ':' || str[1] == '=')
7041 return 1;
7042 return 0;
7043}
7044
7045#endif
7046
7047/* Possible states for relaxation:
7048
7049 0 0 branch offset byte (bra, etc)
7050 0 1 word
7051 0 2 long
7052
7053 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7054 1 1 word
7055 1 2 long
7056
7057 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7058 2 1 word-long
7059 2 2 long-word
7060 2 3 long-long
7061
7062 */
7063
7064/* We have no need to default values of symbols. */
7065
252b5132
RH		 7066symbolS *
7067md_undefined_symbol (name)
36823076 7068 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7069{
7070 return 0;
7071}
7072
7073/* Round up a section size to the appropriate boundary. */
7074valueT
7075md_section_align (segment, size)
36823076 7076 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7077 valueT size;
7078{
7079#ifdef OBJ_AOUT
7080#ifdef BFD_ASSEMBLER
7081 /* For a.out, force the section size to be aligned. If we don't do
7082 this, BFD will align it for us, but it will not write out the
7083 final bytes of the section. This may be a bug in BFD, but it is
7084 easier to fix it here since that is how the other a.out targets
7085 work. */
7086 int align;
7087
7088 align = bfd_get_section_alignment (stdoutput, segment);
7089 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7090#endif
7091#endif
7092
7093 return size;
7094}
7095
7096/* Exactly what point is a PC-relative offset relative TO?
7097 On the 68k, it is relative to the address of the first extension
7098 word. The difference between the addresses of the offset and the
92774660 7099 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7100long
7101md_pcrel_from (fixP)
7102 fixS *fixP;
7103{
7104 int adjust;
7105
8390138c
AS		 7106 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7107 sign extend the value here. */
7108 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7109 if (adjust == 64)
7110 adjust = -1;
7111 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7112}
7113
7114#ifndef BFD_ASSEMBLER
7115#ifdef OBJ_COFF
7116
252b5132
RH		 7117void
7118tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7119 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7120{
7121}
7122
7123int
7124tc_coff_sizemachdep (frag)
7125 fragS *frag;
7126{
7127 switch (frag->fr_subtype & 0x3)
7128 {
7129 case BYTE:
7130 return 1;
7131 case SHORT:
7132 return 2;
7133 case LONG:
7134 return 4;
7135 default:
7136 abort ();
7137 return 0;
7138 }
7139}
7140
7141#endif
7142#endif
0d96863f 7143#ifdef OBJ_ELF
8a104df9
KH		 7144void
7145m68k_elf_final_processing ()
0d96863f 7146{
8a104df9
KH		 7147 /* Set file-specific flags if this is a cpu32 processor */
7148 if (cpu_of_arch (current_architecture) & cpu32)
7149 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7150 else if ((cpu_of_arch (current_architecture) & m68000up)
7151 && !(cpu_of_arch (current_architecture) & m68020up))
7152 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7153}
7154#endif
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