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* sym.h, symconst.h: Add comment stating these files are not part
[binutils.git] / include / opcode / i386.h
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ce868e5c
JG		 1/* i386-opcode.h -- Intel 80386 opcode table
2 Copyright 1989, 1991, 1992 Free Software Foundation.
3
4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
18Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
20static const template i386_optab[] = {
21
22#define _ None
23/* move instructions */
fc0d7441
ILT		 24{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } },
25{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
26{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } },
27{ "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } },
28{ "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, Reg16|Mem, 0 } },
ce868e5c 29/* move to/from control debug registers */
fc0d7441
ILT		 30{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} },
31{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} },
32{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} },
ce868e5c
JG		 33
34/* move with sign extend */
35/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
36 conflict with the "movs" string move instruction. Thus,
fc0d7441 37 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
ce868e5c 38 is not kosher; we must seperate the two instructions. */
fc0d7441
ILT		 39{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg32, 0} },
40{"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16, 0} },
41{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 42
43/* move with zero extend */
fc0d7441
ILT		 44{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
45{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 46
47/* push instructions */
fc0d7441
ILT		 48{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } },
49{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } },
50{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} },
51{"push", 1, 0x68, _, NoModrm, { Imm32, 0, 0} },
52{"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } },
53{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 54/* push all */
fc0d7441 55{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } },
ce868e5c
JG		 56
57/* pop instructions */
fc0d7441
ILT		 58{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } },
59{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } },
ce868e5c 60#define POP_SEG_SHORT 0x7
fc0d7441
ILT		 61{"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } },
62{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 63/* pop all */
fc0d7441 64{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } },
ce868e5c
JG		 65
66/* xchg exchange instructions
67 xchg commutes: we allow both operand orders */
fc0d7441
ILT		 68{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } },
69{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } },
70{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } },
71{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } },
ce868e5c
JG		 72
73/* in/out from ports */
fc0d7441
ILT		 74{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } },
75{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } },
76{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } },
77{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } },
78{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } },
79{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } },
80{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } },
81{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } },
82
83#if 0
84{"inb", 1, 0xe4, _, NoModrm, { Imm8, 0, 0 } },
85{"inb", 1, 0xec, _, NoModrm, { WordMem, 0, 0 } },
86{"inw", 1, 0x66e5, _, NoModrm, { Imm8, 0, 0 } },
87{"inw", 1, 0x66ed, _, NoModrm, { WordMem, 0, 0 } },
88{"outb", 1, 0xe6, _, NoModrm, { Imm8, 0, 0 } },
89{"outb", 1, 0xee, _, NoModrm, { WordMem, 0, 0 } },
90{"outw", 1, 0x66e7, _, NoModrm, { Imm8, 0, 0 } },
91{"outw", 1, 0x66ef, _, NoModrm, { WordMem, 0, 0 } },
92#endif
ce868e5c
JG		 93
94/* load effective address */
fc0d7441 95{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } },
ce868e5c
JG		 96
97/* load segment registers from memory */
fc0d7441
ILT		 98{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} },
99{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} },
100{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} },
101{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} },
102{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} },
ce868e5c
JG		 103
104/* flags register instructions */
fc0d7441
ILT		 105{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} },
106{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} },
107{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} },
108{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} },
109{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} },
110{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} },
111{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} },
112{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} },
113{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} },
114{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} },
115{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} },
116{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} },
117
118{"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} },
119{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} },
120{"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} },
121{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
122
123{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} },
124{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
125
126{"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} },
127{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} },
128{"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} },
129{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} },
130
131{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} },
132{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
133
134{"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} },
135{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} },
136{"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} },
137{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} },
138
139{"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} },
140{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} },
141{"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} },
142{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} },
143
144{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} },
145{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} },
146{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} },
147{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
148
149{"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} },
150{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} },
151{"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} },
152{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} },
153
154{"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} },
155{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} },
156{"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} },
157{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} },
158
159{"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} },
160{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} },
161{"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} },
162{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} },
163
164{"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} },
165{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} },
166{"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} },
167{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} },
168
169{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
170{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
171
172{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} },
173{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} },
174{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} },
175{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} },
176{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} },
177{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 178
179/* conversion insns */
180/* conversion: intel naming */
fc0d7441
ILT		 181{"cbw", 0, 0x6698, _, NoModrm, { 0, 0, 0} },
182{"cwd", 0, 0x6699, _, NoModrm, { 0, 0, 0} },
183{"cwde", 0, 0x98, _, NoModrm, { 0, 0, 0} },
184{"cdq", 0, 0x99, _, NoModrm, { 0, 0, 0} },
ce868e5c 185/* att naming */
fc0d7441
ILT		 186{"cbtw", 0, 0x6698, _, NoModrm, { 0, 0, 0} },
187{"cwtl", 0, 0x98, _, NoModrm, { 0, 0, 0} },
188{"cwtd", 0, 0x6699, _, NoModrm, { 0, 0, 0} },
189{"cltd", 0, 0x99, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 190
191/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
192 expanding 64-bit multiplies, and *cannot* be selected to accomplish
193 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
194 These multiplies can only be selected with single opearnd forms. */
fc0d7441
ILT		 195{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
196{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
ce868e5c
JG		 197
198
199
200
201/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
202 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
203 '%eax' in the reg field and '%ecx' in the regmem field if we did not
204 switch them. */
fc0d7441
ILT		 205{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
206{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} },
207{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} },
ce868e5c
JG		 208/*
209 imul with 2 operands mimicks imul with 3 by puting register both
210 in i.rm.reg & i.rm.regmem fields
211*/
fc0d7441
ILT		 212{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} },
213{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} },
214{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
215{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
216{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
217{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
218
219{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
220{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
221{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
222{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
223
224{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
225{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
226{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
227{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
228
229{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
230{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
231{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
232{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
233
234{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
235{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
236{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
237{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
238
239{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
240{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
241{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
242{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
243{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
244{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
245{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
246{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
247
248{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
249{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
250{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} },
251
252{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
253{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
254{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
255{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
256
257{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
258{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
259{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} },
260
261{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
262{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
263{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
264{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
ce868e5c
JG		 265
266/* control transfer instructions */
267#define CALL_PC_RELATIVE 0xe8
fc0d7441
ILT		 268{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} },
269{"call", 1, 0xff, 2, Modrm, { Reg|Mem|JumpAbsolute, 0, 0} },
ce868e5c 270#define CALL_FAR_IMMEDIATE 0x9a
fc0d7441
ILT		 271{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Abs32|Imm32, 0} },
272{"lcall", 1, 0xff, 3, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 273
274#define JUMP_PC_RELATIVE 0xeb
fc0d7441
ILT		 275{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} },
276{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
ce868e5c 277#define JUMP_FAR_IMMEDIATE 0xea
fc0d7441
ILT		 278{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} },
279{"ljmp", 1, 0xff, 5, Modrm, { Mem, 0, 0} },
ce868e5c 280
fc0d7441
ILT		 281{"ret", 0, 0xc3, _, NoModrm, { 0, 0, 0} },
282{"ret", 1, 0xc2, _, NoModrm, { Imm16, 0, 0} },
283{"lret", 0, 0xcb, _, NoModrm, { 0, 0, 0} },
284{"lret", 1, 0xca, _, NoModrm, { Imm16, 0, 0} },
285{"enter", 2, 0xc8, _, NoModrm, { Imm16, Imm8, 0} },
286{"leave", 0, 0xc9, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 287
288/* conditional jumps */
fc0d7441 289{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} },
ce868e5c 290
fc0d7441 291{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} },
ce868e5c 292
fc0d7441
ILT		 293{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} },
294{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} },
295{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} },
ce868e5c 296
fc0d7441
ILT		 297{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} },
298{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} },
299{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} },
ce868e5c 300
fc0d7441
ILT		 301{"je", 1, 0x74, _, Jump, { Disp, 0, 0} },
302{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} },
ce868e5c 303
fc0d7441
ILT		 304{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} },
305{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} },
ce868e5c 306
fc0d7441
ILT		 307{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} },
308{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} },
ce868e5c 309
fc0d7441
ILT		 310{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} },
311{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} },
ce868e5c 312
fc0d7441 313{"js", 1, 0x78, _, Jump, { Disp, 0, 0} },
ce868e5c 314
fc0d7441 315{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} },
ce868e5c 316
fc0d7441
ILT		 317{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} },
318{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} },
ce868e5c 319
fc0d7441
ILT		 320{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} },
321{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} },
ce868e5c 322
fc0d7441
ILT		 323{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} },
324{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} },
ce868e5c 325
fc0d7441
ILT		 326{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} },
327{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} },
ce868e5c 328
fc0d7441
ILT		 329{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} },
330{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} },
ce868e5c 331
fc0d7441
ILT		 332{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} },
333{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} },
ce868e5c
JG		 334
335/* these turn into pseudo operations when disp is larger than 8 bits */
336#define IS_JUMP_ON_CX_ZERO(o) \
337 (o == 0x67e3)
338#define IS_JUMP_ON_ECX_ZERO(o) \
339 (o == 0xe3)
340
fc0d7441
ILT		 341{"jcxz", 1, 0x67e3, _, JumpByte, { Disp, 0, 0} },
342{"jecxz", 1, 0xe3, _, JumpByte, { Disp, 0, 0} },
ce868e5c
JG		 343
344#define IS_LOOP_ECX_TIMES(o) \
345 (o == 0xe2 || o == 0xe1 || o == 0xe0)
346
fc0d7441 347{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} },
ce868e5c 348
fc0d7441
ILT		 349{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
350{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
ce868e5c 351
fc0d7441
ILT		 352{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
353{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
ce868e5c
JG		 354
355/* set byte on flag instructions */
fc0d7441 356{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 357
fc0d7441 358{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 359
fc0d7441
ILT		 360{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
361{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
362{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 363
fc0d7441
ILT		 364{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
365{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
366{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 367
fc0d7441
ILT		 368{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
369{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 370
fc0d7441
ILT		 371{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
372{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 373
fc0d7441
ILT		 374{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
375{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 376
fc0d7441
ILT		 377{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
378{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 379
fc0d7441 380{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 381
fc0d7441 382{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 383
fc0d7441
ILT		 384{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
385{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 386
fc0d7441
ILT		 387{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
388{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 389
fc0d7441
ILT		 390{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
391{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 392
fc0d7441
ILT		 393{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
394{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 395
fc0d7441
ILT		 396{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
397{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 398
fc0d7441
ILT		 399{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
400{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c
JG		 401
402#define IS_STRING_INSTRUCTION(o) \
403 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
404 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
405 (o) == 0xd7)
406
407/* string manipulation */
fc0d7441
ILT		 408{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
409{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
410{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} },
411{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} },
412{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
413{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
414{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
415{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
416{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
417{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
418{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
419{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
420{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 421
422/* bit manipulation */
fc0d7441
ILT		 423{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
424{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
425{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} },
426{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
427{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} },
428{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
429{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} },
430{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
431{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} },
432{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
ce868e5c
JG		 433
434/* interrupts & op. sys insns */
435/* See i386.c for conversion of 'int $3' into the special int 3 insn. */
436#define INT_OPCODE 0xcd
437#define INT3_OPCODE 0xcc
fc0d7441
ILT		 438{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} },
439{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} },
440{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} },
441{"iret", 0, 0xcf, _, NoModrm, { 0, 0, 0} },
ce868e5c 442
fc0d7441
ILT		 443{"boundl", 2, 0x62, _, Modrm, { Reg32, Mem, 0} },
444{"boundw", 2, 0x6662, _, Modrm, { Reg16, Mem, 0} },
ce868e5c 445
fc0d7441
ILT		 446{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} },
447{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
ce868e5c 448/* nop is actually 'xchgl %eax, %eax' */
fc0d7441 449{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 450
451/* protection control */
fc0d7441
ILT		 452{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} },
453{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
454{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
455{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
456{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
457{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
458{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
459{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
460
461{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
462{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
463{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
464{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
465{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
466
467{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
468{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
ce868e5c
JG		 469
470/* floating point instructions */
471
472/* load */
fc0d7441
ILT		 473{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
474{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */
475{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */
476{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
477{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */
478{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */
479{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
480{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
481{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */
482{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */
ce868e5c
JG		 483
484/* store (no pop) */
fc0d7441
ILT		 485{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
486{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
487{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
488{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
489{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
490{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
ce868e5c
JG		 491
492/* store (with pop) */
fc0d7441
ILT		 493{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
494{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
495{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
496{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
497{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
498{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
499{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
500{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
501{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */
502{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */
ce868e5c
JG		 503
504/* exchange %st<n> with %st0 */
fc0d7441 505{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} },
ce868e5c
JG		 506
507/* comparison (without pop) */
fc0d7441
ILT		 508{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
509{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
510{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
511{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
512{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
513{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
ce868e5c
JG		 514
515/* comparison (with pop) */
fc0d7441
ILT		 516{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
517{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
518{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
519{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
520{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
521{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
522{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
ce868e5c
JG		 523
524/* unordered comparison (with pop) */
fc0d7441
ILT		 525{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} },
526{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} },
527{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
ce868e5c 528
fc0d7441
ILT		 529{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */
530{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */
ce868e5c
JG		 531
532/* load constants into %st0 */
fc0d7441
ILT		 533{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */
534{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */
535{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */
536{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */
537{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */
538{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */
539{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */
ce868e5c
JG		 540
541/* arithmetic */
542
543/* add */
fc0d7441
ILT		 544{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} },
545{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
546{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
547{"faddp", 1, 0xdac0, _, ShortForm, { FloatReg, 0, 0} },
548{"faddp", 2, 0xdac0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
549{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
550{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
551{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
552{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
553{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 554
555/* sub */
556/* Note: intel has decided that certain of these operations are reversed
557 in assembler syntax. */
fc0d7441
ILT		 558{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} },
559{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 560#ifdef NON_BROKEN_OPCODES
fc0d7441 561{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 562#else
fc0d7441 563{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 564#endif
fc0d7441
ILT		 565{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} },
566{"fsubp", 1, 0xdae0, _, ShortForm, { FloatReg, 0, 0} },
567{"fsubp", 2, 0xdae0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 568#ifdef NON_BROKEN_OPCODES
fc0d7441 569{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 570#else
fc0d7441 571{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 572#endif
fc0d7441
ILT		 573{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} },
574{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
575{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
576{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
577{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 578
579/* sub reverse */
fc0d7441
ILT		 580{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} },
581{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 582#ifdef NON_BROKEN_OPCODES
fc0d7441 583{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 584#else
fc0d7441 585{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 586#endif
fc0d7441
ILT		 587{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} },
588{"fsubrp", 1, 0xdae8, _, ShortForm, { FloatReg, 0, 0} },
589{"fsubrp", 2, 0xdae8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 590#ifdef NON_BROKEN_OPCODES
fc0d7441 591{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 592#else
fc0d7441 593{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 594#endif
fc0d7441
ILT		 595{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} },
596{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
597{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
598{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
599{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 600
601/* mul */
fc0d7441
ILT		 602{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} },
603{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
604{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} },
605{"fmulp", 1, 0xdac8, _, ShortForm, { FloatReg, 0, 0} },
606{"fmulp", 2, 0xdac8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
607{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} },
608{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
609{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
610{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
611{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 612
613/* div */
614/* Note: intel has decided that certain of these operations are reversed
615 in assembler syntax. */
fc0d7441
ILT		 616{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} },
617{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 618#ifdef NON_BROKEN_OPCODES
fc0d7441 619{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 620#else
fc0d7441 621{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 622#endif
fc0d7441
ILT		 623{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} },
624{"fdivp", 1, 0xdaf0, _, ShortForm, { FloatReg, 0, 0} },
625{"fdivp", 2, 0xdaf0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 626#ifdef NON_BROKEN_OPCODES
fc0d7441 627{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 628#else
fc0d7441 629{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 630#endif
fc0d7441
ILT		 631{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} },
632{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
633{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
634{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
635{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 636
637/* div reverse */
fc0d7441
ILT		 638{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} },
639{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 640#ifdef NON_BROKEN_OPCODES
fc0d7441 641{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 642#else
fc0d7441 643{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 644#endif
fc0d7441
ILT		 645{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} },
646{"fdivrp", 1, 0xdaf8, _, ShortForm, { FloatReg, 0, 0} },
647{"fdivrp", 2, 0xdaf8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 648#ifdef NON_BROKEN_OPCODES
fc0d7441 649{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 650#else
fc0d7441 651{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 652#endif
fc0d7441
ILT		 653{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} },
654{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
655{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
656{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
657{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
658
659{"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} },
660{"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} },
661{"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} },
662{"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} },
663{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} },
664{"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} },
665{"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} },
666{"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} },
667{"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} },
668{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} },
669{"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} },
670{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} },
671{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} },
672{"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} },
673{"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} },
674{"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} },
675
676{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} },
677{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 678
679/* processor control */
fc0d7441
ILT		 680{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
681{"finit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
682{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
683{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
684{"fstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
685{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
686{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
687{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
688{"fstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
689{"fstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
690{"fstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
691{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
692{"fclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 693/*
694 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
695 instructions; i'm not sure how to add them or how they are different.
696 My 386/387 book offers no details about this.
697*/
fc0d7441
ILT		 698{"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
699{"fstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
700{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
701{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
702{"fsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
703{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
ce868e5c 704
fc0d7441
ILT		 705{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} },
706{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} },
707{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 708
709/*
710 opcode prefixes; we allow them as seperate insns too
711 (see prefix table below)
712*/
fc0d7441
ILT		 713{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} },
714{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} },
715{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} },
716{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} },
717{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} },
718{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} },
719{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} },
720{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} },
721{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} },
722{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} },
723{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} },
724{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
725{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
726{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
727{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
728{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
729
730/* 486 extensions */
731
732{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } },
733{"xadd", 2, 0x0fc0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
734{"cmpxchg", 2, 0x0fb0, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
735{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} },
736{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} },
737{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
738
739{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinal */
ce868e5c
JG		 740};
741#undef _
742
fc0d7441 743static const template *const i386_optab_end
ce868e5c
JG		 744 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
745
746/* 386 register table */
747
748static const reg_entry i386_regtab[] = {
749 /* 8 bit regs */
750 {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
751 {"bl", Reg8, 3},
752 {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
753 /* 16 bit regs */
754 {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
755 {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
756 /* 32 bit regs */
757 {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
758 {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
759 /* segment registers */
760 {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
761 {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
762 /* control registers */
763 {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
764 /* debug registers */
765 {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
766 {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
767 /* test registers */
768 {"tr6", Test, 6}, {"tr7", Test, 7},
769 /* float registers */
770 {"st(0)", FloatReg|FloatAcc, 0},
771 {"st", FloatReg|FloatAcc, 0},
772 {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
773 {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
774 {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
775};
776
777#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
778
fc0d7441 779static const reg_entry *const i386_regtab_end
ce868e5c
JG		 780 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
781
782/* segment stuff */
783static const seg_entry cs = { "cs", 0x2e };
784static const seg_entry ds = { "ds", 0x3e };
785static const seg_entry ss = { "ss", 0x36 };
786static const seg_entry es = { "es", 0x26 };
787static const seg_entry fs = { "fs", 0x64 };
788static const seg_entry gs = { "gs", 0x65 };
789static const seg_entry null = { "", 0x0 };
790
791/*
792 This table is used to store the default segment register implied by all
793 possible memory addressing modes.
794 It is indexed by the mode & modrm entries of the modrm byte as follows:
795 index = (mode<<3) | modrm;
796*/
fc0d7441 797static const seg_entry *const one_byte_segment_defaults[] = {
ce868e5c
JG		 798 /* mode 0 */
799 &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
800 /* mode 1 */
801 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
802 /* mode 2 */
803 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
804 /* mode 3 --- not a memory reference; never referenced */
805};
806
fc0d7441 807static const seg_entry *const two_byte_segment_defaults[] = {
ce868e5c
JG		 808 /* mode 0 */
809 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
810 /* mode 1 */
811 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
812 /* mode 2 */
813 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
814 /* mode 3 --- not a memory reference; never referenced */
815};
816
817static const prefix_entry i386_prefixtab[] = {
818 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
819 * (How is this useful?) */
820#define WORD_PREFIX_OPCODE 0x66
821 { "data16", 0x66 }, /* operand size prefix */
822 { "lock", 0xf0 }, /* bus lock prefix */
823 { "wait", 0x9b }, /* wait for coprocessor */
824 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
825 { "es", 0x26 }, { "fs", 0x64 },
826 { "gs", 0x65 }, { "ss", 0x36 },
827/* REPE & REPNE used to detect rep/repne with a non-string instruction */
828#define REPNE 0xf2
829#define REPE 0xf3
830 { "rep", 0xf3 }, /* repeat string instructions */
831 { "repe", 0xf3 }, { "repz", 0xf3 },
832 { "repne", 0xf2 }, { "repnz", 0xf2 }
833};
834
fc0d7441 835static const prefix_entry *const i386_prefixtab_end
ce868e5c
JG		 836 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
837
838/* end of i386-opcode.h */
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