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* readelf.c (guess_is_rela): AVR uses RELA relocations.
[binutils.git] / sim / mips / ChangeLog
CommitLineData
e30db738
AC		 1Mon Apr 10 00:07:09 2000 Andrew Cagney <[email protected]>
2
3 * interp.c (decode_coproc): Output long using %lx and not %s.
4
cb7450ea
FCE		 52000-03-21 Frank Ch. Eigler <[email protected]>
6
7 * interp.c (sim_open): Sort & extend dummy memory regions for
8 --board=jmr3904 for eCos.
9
a3027dd7
FCE		 102000-03-02 Frank Ch. Eigler <[email protected]>
11
12 * configure: Regenerated.
13
14Tue Feb 8 18:35:01 2000 Donald Lindsay <[email protected]>
15
16 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
17 calls, conditional on the simulator being in verbose mode.
18
dfcd3bfb
JM		 19Fri Feb 4 09:45:15 2000 Donald Lindsay <[email protected]>
20
21 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
22 cache don't get ReservedInstruction traps.
23
c2d11a7d
JM		 241999-11-29 Mark Salter <[email protected]>
25
26 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
27 to clear status bits in sdisr register. This is how the hardware works.
28
29 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
30 being used by cygmon.
31
4ce44c66
JM		 321999-11-11 Andrew Haley <[email protected]>
33
34 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
35 instructions.
36
cff3e48b
JM		 37Thu Sep 9 15:12:08 1999 Geoffrey Keating <[email protected]>
38
39 * mips.igen (MULT): Correct previous mis-applied patch.
40
d4f3574e
SS		 41Tue Sep 7 13:34:54 1999 Geoffrey Keating <[email protected]>
42
43 * mips.igen (delayslot32): Handle sequence like
44 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
45 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
46 (MULT): Actually pass the third register...
47
481999-09-03 Mark Salter <[email protected]>
49
50 * interp.c (sim_open): Added more memory aliases for additional
51 hardware being touched by cygmon on jmr3904 board.
52
53Thu Sep 2 18:15:53 1999 Andrew Cagney <[email protected]>
54
55 * configure: Regenerated to track ../common/aclocal.m4 changes.
56
a0b3c4fd
JM		 57Tue Jul 27 16:36:51 1999 Andrew Cagney <[email protected]>
58
59 * interp.c (sim_store_register): Handle case where client - GDB -
60 specifies that a 4 byte register is 8 bytes in size.
61 (sim_fetch_register): Ditto.
62
adf40b2e
JM		 631999-07-14 Frank Ch. Eigler <[email protected]>
64
65 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
66 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
67 (idt_monitor_base): Base address for IDT monitor traps.
68 (pmon_monitor_base): Ditto for PMON.
69 (lsipmon_monitor_base): Ditto for LSI PMON.
70 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
71 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
72 (sim_firmware_command): New function.
73 (mips_option_handler): Call it for OPTION_FIRMWARE.
74 (sim_open): Allocate memory for idt_monitor region. If "--board"
75 option was given, add no monitor by default. Add BREAK hooks only if
76 monitors are also there.
77
43e526b9
JM		 78Mon Jul 12 00:02:27 1999 Andrew Cagney <[email protected]>
79
80 * interp.c (sim_monitor): Flush output before reading input.
81
82Sun Jul 11 19:28:11 1999 Andrew Cagney <[email protected]>
83
84 * tconfig.in (SIM_HANDLES_LMA): Always define.
85
86Thu Jul 8 16:06:59 1999 Andrew Cagney <[email protected]>
87
88 From Mark Salter <[email protected]>:
89 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
90 (sim_open): Add setup for BSP board.
91
9846de1b
JM		 92Wed Jul 7 12:45:58 1999 Andrew Cagney <[email protected]>
93
94 * mips.igen (MULT, MULTU): Add syntax for two operand version.
95 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
96 them as unimplemented.
97
cd0fc7c3
SS		 981999-05-08 Felix Lee <[email protected]>
99
100 * configure: Regenerated to track ../common/aclocal.m4 changes.
101
7a292a7a
SS		 1021999-04-21 Frank Ch. Eigler <[email protected]>
103
104 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
105
106Thu Apr 15 14:15:17 1999 Andrew Cagney <[email protected]>
107
108 * configure.in: Any mips64vr5*-*-* target should have
109 -DTARGET_ENABLE_FR=1.
110 (default_endian): Any mips64vr*el-*-* target should default to
111 LITTLE_ENDIAN.
112 * configure: Re-generate.
113
1141999-02-19 Gavin Romig-Koch <[email protected]>
115
116 * mips.igen (ldl): Extend from _16_, not 32.
117
118Wed Jan 27 18:51:38 1999 Andrew Cagney <[email protected]>
119
120 * interp.c (sim_store_register): Force registers written to by GDB
121 into an un-interpreted state.
122
c906108c
SS		 1231999-02-05 Frank Ch. Eigler <[email protected]>
124
125 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
126 CPU, start periodic background I/O polls.
127 (tx3904sio_poll): New function: periodic I/O poller.
128
1291998-12-30 Frank Ch. Eigler <[email protected]>
130
131 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
132
133Tue Dec 29 16:03:53 1998 Rainer Orth <[email protected]>
134
135 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
136 case statement.
137
1381998-12-29 Frank Ch. Eigler <[email protected]>
139
140 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
141 (load_word): Call SIM_CORE_SIGNAL hook on error.
142 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
143 starting. For exception dispatching, pass PC instead of NULL_CIA.
144 (decode_coproc): Use COP0_BADVADDR to store faulting address.
145 * sim-main.h (COP0_BADVADDR): Define.
146 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
147 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
148 (_sim_cpu): Add exc_* fields to store register value snapshots.
149 * mips.igen (*): Replace memory-related SignalException* calls
150 with references to SIM_CORE_SIGNAL hook.
151
152 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
153 fix.
154 * sim-main.c (*): Minor warning cleanups.
155
1561998-12-24 Gavin Romig-Koch <[email protected]>
157
158 * m16.igen (DADDIU5): Correct type-o.
159
160Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
161
162 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
163 variables.
164
165Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
166
167 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
168 to include path.
169 (interp.o): Add dependency on itable.h
170 (oengine.c, gencode): Delete remaining references.
171 (BUILT_SRC_FROM_GEN): Clean up.
172
1731998-12-16 Gavin Romig-Koch <[email protected]>
174
175 * vr4run.c: New.
176 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
177 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
178 tmp-run-hack) : New.
179 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
180 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
181 Drop the "64" qualifier to get the HACK generator working.
182 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
183 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
184 qualifier to get the hack generator working.
185 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
186 (DSLL): Use do_dsll.
187 (DSLLV): Use do_dsllv.
188 (DSRA): Use do_dsra.
189 (DSRL): Use do_dsrl.
190 (DSRLV): Use do_dsrlv.
191 (BC1): Move *vr4100 to get the HACK generator working.
192 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
193 get the HACK generator working.
194 (MACC) Rename to get the HACK generator working.
195 (DMACC,MACCS,DMACCS): Add the 64.
196
1971998-12-12 Gavin Romig-Koch <[email protected]>
198
199 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
200 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
201
2021998-12-11 Gavin Romig-Koch <[email protected]>
203
204 * mips/interp.c (DEBUG): Cleanups.
205
2061998-12-10 Frank Ch. Eigler <[email protected]>
207
208 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
209 (tx3904sio_tickle): fflush after a stdout character output.
210
2111998-12-03 Frank Ch. Eigler <[email protected]>
212
213 * interp.c (sim_close): Uninstall modules.
214
215Wed Nov 25 13:41:03 1998 Andrew Cagney <[email protected]>
216
217 * sim-main.h, interp.c (sim_monitor): Change to global
218 function.
219
220Wed Nov 25 17:33:24 1998 Andrew Cagney <[email protected]>
221
222 * configure.in (vr4100): Only include vr4100 instructions in
223 simulator.
224 * configure: Re-generate.
225 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
226
227Mon Nov 23 18:20:36 1998 Andrew Cagney <[email protected]>
228
229 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
230 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
231 true alternative.
232
233 * configure.in (sim_default_gen, sim_use_gen): Replace with
234 sim_gen.
235 (--enable-sim-igen): Delete config option. Always using IGEN.
236 * configure: Re-generate.
237
238 * Makefile.in (gencode): Kill, kill, kill.
239 * gencode.c: Ditto.
240
241Mon Nov 23 18:07:36 1998 Andrew Cagney <[email protected]>
242
243 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
244 bit mips16 igen simulator.
245 * configure: Re-generate.
246
247 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
248 as part of vr4100 ISA.
249 * vr.igen: Mark all instructions as 64 bit only.
250
251Mon Nov 23 17:07:37 1998 Andrew Cagney <[email protected]>
252
253 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
254 Pacify GCC.
255
256Mon Nov 23 13:23:40 1998 Andrew Cagney <[email protected]>
257
258 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
259 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
260 * configure: Re-generate.
261
262 * m16.igen (BREAK): Define breakpoint instruction.
263 (JALX32): Mark instruction as mips16 and not r3900.
264 * mips.igen (C.cond.fmt): Fix typo in instruction format.
265
266 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
267
268Sat Nov 7 09:54:38 1998 Andrew Cagney <[email protected]>
269
270 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
271 insn as a debug breakpoint.
272
273 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
274 pending.slot_size.
275 (PENDING_SCHED): Clean up trace statement.
276 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
277 (PENDING_FILL): Delay write by only one cycle.
278 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
279
280 * sim-main.c (pending_tick): Clean up trace statements. Add trace
281 of pending writes.
282 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
283 32 & 64.
284 (pending_tick): Move incrementing of index to FOR statement.
285 (pending_tick): Only update PENDING_OUT after a write has occured.
286
287 * configure.in: Add explicit mips-lsi-* target. Use gencode to
288 build simulator.
289 * configure: Re-generate.
290
291 * interp.c (sim_engine_run OLD): Delete explicit call to
292 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
293
294Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <[email protected]>
295
296 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
297 interrupt level number to match changed SignalExceptionInterrupt
298 macro.
299
300Fri Oct 9 18:02:25 1998 Doug Evans <[email protected]>
301
302 * interp.c: #include "itable.h" if WITH_IGEN.
303 (get_insn_name): New function.
304 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
305 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
306
307Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <[email protected]>
308
309 * configure: Rebuilt to inhale new common/aclocal.m4.
310
311Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <[email protected]>
312
313 * dv-tx3904sio.c: Include sim-assert.h.
314
315Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <[email protected]>
316
317 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
318 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
319 Reorganize target-specific sim-hardware checks.
320 * configure: rebuilt.
321 * interp.c (sim_open): For tx39 target boards, set
322 OPERATING_ENVIRONMENT, add tx3904sio devices.
323 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
324 ROM executables. Install dv-sockser into sim-modules list.
325
326 * dv-tx3904irc.c: Compiler warning clean-up.
327 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
328 frequent hw-trace messages.
329
330Fri Jul 31 18:14:16 1998 Andrew Cagney <[email protected]>
331
332 * vr.igen (MulAcc): Identify as a vr4100 specific function.
333
334Sat Jul 25 16:03:14 1998 Andrew Cagney <[email protected]>
335
336 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
337
338 * vr.igen: New file.
339 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
340 * mips.igen: Define vr4100 model. Include vr.igen.
341Mon Jun 29 09:21:07 1998 Gavin Koch <[email protected]>
342
343 * mips.igen (check_mf_hilo): Correct check.
344
345Wed Jun 17 12:20:49 1998 Andrew Cagney <[email protected]>
346
347 * sim-main.h (interrupt_event): Add prototype.
348
349 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
350 register_ptr, register_value.
351 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
352
353 * sim-main.h (tracefh): Make extern.
354
355Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <[email protected]>
356
357 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
358 Reduce unnecessarily high timer event frequency.
359 * dv-tx3904cpu.c: Ditto for interrupt event.
360
361Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <[email protected]>
362
363 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
364 to allay warnings.
365 (interrupt_event): Made non-static.
366
367 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
368 interchange of configuration values for external vs. internal
369 clock dividers.
370
371Tue Jun 9 12:46:24 1998 Ian Carmichael <[email protected]>
372
373 * mips.igen (BREAK): Moved code to here for
374 simulator-reserved break instructions.
375 * gencode.c (build_instruction): Ditto.
376 * interp.c (signal_exception): Code moved from here. Non-
377 reserved instructions now use exception vector, rather
378 than halting sim.
379 * sim-main.h: Moved magic constants to here.
380
381Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <[email protected]>
382
383 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
384 register upon non-zero interrupt event level, clear upon zero
385 event value.
386 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
387 by passing zero event value.
388 (*_io_{read,write}_buffer): Endianness fixes.
389 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
390 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
391
392 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
393 serial I/O and timer module at base address 0xFFFF0000.
394
395Tue Jun 9 11:52:29 1998 Gavin Koch <[email protected]>
396
397 * mips.igen (SWC1) : Correct the handling of ReverseEndian
398 and BigEndianCPU.
399
400Tue Jun 9 11:40:57 1998 Gavin Koch <[email protected]>
401
402 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
403 parts.
404 * configure: Update.
405
406Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <[email protected]>
407
408 * dv-tx3904tmr.c: New file - implements tx3904 timer.
409 * dv-tx3904{irc,cpu}.c: Mild reformatting.
410 * configure.in: Include tx3904tmr in hw_device list.
411 * configure: Rebuilt.
412 * interp.c (sim_open): Instantiate three timer instances.
413 Fix address typo of tx3904irc instance.
414
415Tue Jun 2 15:48:02 1998 Ian Carmichael <[email protected]>
416
417 * interp.c (signal_exception): SystemCall exception now uses
418 the exception vector.
419
420Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <[email protected]>
421
422 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
423 to allay warnings.
424
425Fri May 29 11:40:39 1998 Andrew Cagney <[email protected]>
426
427 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
428
429Mon May 25 20:47:45 1998 Andrew Cagney <[email protected]>
430
431 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
432
433 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
434 sim-main.h. Declare a struct hw_descriptor instead of struct
435 hw_device_descriptor.
436
437Mon May 25 12:41:38 1998 Andrew Cagney <[email protected]>
438
439 * mips.igen (do_store_left, do_load_left): Compute nr of left and
440 right bits and then re-align left hand bytes to correct byte
441 lanes. Fix incorrect computation in do_store_left when loading
442 bytes from second word.
443
444Fri May 22 13:34:20 1998 Andrew Cagney <[email protected]>
445
446 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
447 * interp.c (sim_open): Only create a device tree when HW is
448 enabled.
449
450 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
451 * interp.c (signal_exception): Ditto.
452
453Thu May 21 14:24:11 1998 Gavin Koch <[email protected]>
454
455 * gencode.c: Mark BEGEZALL as LIKELY.
456
457Thu May 21 18:57:19 1998 Andrew Cagney <[email protected]>
458
459 * sim-main.h (ALU32_END): Sign extend 32 bit results.
460 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
461
462Mon May 18 18:22:42 1998 Frank Ch. Eigler <[email protected]>
463
464 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
465 modules. Recognize TX39 target with "mips*tx39" pattern.
466 * configure: Rebuilt.
467 * sim-main.h (*): Added many macros defining bits in
468 TX39 control registers.
469 (SignalInterrupt): Send actual PC instead of NULL.
470 (SignalNMIReset): New exception type.
471 * interp.c (board): New variable for future use to identify
472 a particular board being simulated.
473 (mips_option_handler,mips_options): Added "--board" option.
474 (interrupt_event): Send actual PC.
475 (sim_open): Make memory layout conditional on board setting.
476 (signal_exception): Initial implementation of hardware interrupt
477 handling. Accept another break instruction variant for simulator
478 exit.
479 (decode_coproc): Implement RFE instruction for TX39.
480 (mips.igen): Decode RFE instruction as such.
481 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
482 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
483 bbegin to implement memory map.
484 * dv-tx3904cpu.c: New file.
485 * dv-tx3904irc.c: New file.
486
487Wed May 13 14:40:11 1998 Gavin Koch <[email protected]>
488
489 * mips.igen (check_mt_hilo): Create a separate r3900 version.
490
491Wed May 13 14:11:46 1998 Gavin Koch <[email protected]>
492
493 * tx.igen (madd,maddu): Replace calls to check_op_hilo
494 with calls to check_div_hilo.
495
496Wed May 13 09:59:27 1998 Gavin Koch <[email protected]>
497
498 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
499 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
500 Add special r3900 version of do_mult_hilo.
501 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
502 with calls to check_mult_hilo.
503 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
504 with calls to check_div_hilo.
505
506Tue May 12 15:22:11 1998 Andrew Cagney <[email protected]>
507
508 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
509 Document a replacement.
510
511Fri May 8 17:48:19 1998 Ian Carmichael <[email protected]>
512
513 * interp.c (sim_monitor): Make mon_printf work.
514
515Wed May 6 19:42:19 1998 Doug Evans <[email protected]>
516
517 * sim-main.h (INSN_NAME): New arg `cpu'.
518
519Tue Apr 28 18:33:31 1998 Geoffrey Noer <[email protected]>
520
521 * configure: Regenerated to track ../common/aclocal.m4 changes.
522
523Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
524
525 * configure: Regenerated to track ../common/aclocal.m4 changes.
526 * config.in: Ditto.
527
528Sun Apr 26 15:20:01 1998 Tom Tromey <[email protected]>
529
530 * acconfig.h: New file.
531 * configure.in: Reverted change of Apr 24; use sinclude again.
532
533Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
534
535 * configure: Regenerated to track ../common/aclocal.m4 changes.
536 * config.in: Ditto.
537
538Fri Apr 24 11:19:20 1998 Tom Tromey <[email protected]>
539
540 * configure.in: Don't call sinclude.
541
542Fri Apr 24 11:35:01 1998 Andrew Cagney <[email protected]>
543
544 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
545
546Tue Apr 21 11:59:50 1998 Andrew Cagney <[email protected]>
547
548 * mips.igen (ERET): Implement.
549
550 * interp.c (decode_coproc): Return sign-extended EPC.
551
552 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
553
554 * interp.c (signal_exception): Do not ignore Trap.
555 (signal_exception): On TRAP, restart at exception address.
556 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
557 (signal_exception): Update.
558 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
559 so that TRAP instructions are caught.
560
561Mon Apr 20 11:26:55 1998 Andrew Cagney <[email protected]>
562
563 * sim-main.h (struct hilo_access, struct hilo_history): Define,
564 contains HI/LO access history.
565 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
566 (HIACCESS, LOACCESS): Delete, replace with
567 (HIHISTORY, LOHISTORY): New macros.
568 (CHECKHILO): Delete all, moved to mips.igen
569
570 * gencode.c (build_instruction): Do not generate checks for
571 correct HI/LO register usage.
572
573 * interp.c (old_engine_run): Delete checks for correct HI/LO
574 register usage.
575
576 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
577 check_mf_cycles): New functions.
578 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
579 do_divu, domultx, do_mult, do_multu): Use.
580
581 * tx.igen ("madd", "maddu"): Use.
582
583Wed Apr 15 18:31:54 1998 Andrew Cagney <[email protected]>
584
585 * mips.igen (DSRAV): Use function do_dsrav.
586 (SRAV): Use new function do_srav.
587
588 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
589 (B): Sign extend 11 bit immediate.
590 (EXT-B*): Shift 16 bit immediate left by 1.
591 (ADDIU*): Don't sign extend immediate value.
592
593Wed Apr 15 10:32:15 1998 Andrew Cagney <[email protected]>
594
595 * m16run.c (sim_engine_run): Restore CIA after handling an event.
596
597 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
598 functions.
599
600 * mips.igen (delayslot32, nullify_next_insn): New functions.
601 (m16.igen): Always include.
602 (do_*): Add more tracing.
603
604 * m16.igen (delayslot16): Add NIA argument, could be called by a
605 32 bit MIPS16 instruction.
606
607 * interp.c (ifetch16): Move function from here.
608 * sim-main.c (ifetch16): To here.
609
610 * sim-main.c (ifetch16, ifetch32): Update to match current
611 implementations of LH, LW.
612 (signal_exception): Don't print out incorrect hex value of illegal
613 instruction.
614
615Wed Apr 15 00:17:25 1998 Andrew Cagney <[email protected]>
616
617 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
618 instruction.
619
620 * m16.igen: Implement MIPS16 instructions.
621
622 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
623 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
624 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
625 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
626 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
627 bodies of corresponding code from 32 bit insn to these. Also used
628 by MIPS16 versions of functions.
629
630 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
631 (IMEM16): Drop NR argument from macro.
632
633Sat Apr 4 22:39:50 1998 Andrew Cagney <[email protected]>
634
635 * Makefile.in (SIM_OBJS): Add sim-main.o.
636
637 * sim-main.h (address_translation, load_memory, store_memory,
638 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
639 as INLINE_SIM_MAIN.
640 (pr_addr, pr_uword64): Declare.
641 (sim-main.c): Include when H_REVEALS_MODULE_P.
642
643 * interp.c (address_translation, load_memory, store_memory,
644 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
645 from here.
646 * sim-main.c: To here. Fix compilation problems.
647
648 * configure.in: Enable inlining.
649 * configure: Re-config.
650
651Sat Apr 4 20:36:25 1998 Andrew Cagney <[email protected]>
652
653 * configure: Regenerated to track ../common/aclocal.m4 changes.
654
655Fri Apr 3 04:32:35 1998 Andrew Cagney <[email protected]>
656
657 * mips.igen: Include tx.igen.
658 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
659 * tx.igen: New file, contains MADD and MADDU.
660
661 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
662 the hardwired constant `7'.
663 (store_memory): Ditto.
664 (LOADDRMASK): Move definition to sim-main.h.
665
666 mips.igen (MTC0): Enable for r3900.
667 (ADDU): Add trace.
668
669 mips.igen (do_load_byte): Delete.
670 (do_load, do_store, do_load_left, do_load_write, do_store_left,
671 do_store_right): New functions.
672 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
673
674 configure.in: Let the tx39 use igen again.
675 configure: Update.
676
677Thu Apr 2 10:59:39 1998 Andrew Cagney <[email protected]>
678
679 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
680 not an address sized quantity. Return zero for cache sizes.
681
682Wed Apr 1 23:47:53 1998 Andrew Cagney <[email protected]>
683
684 * mips.igen (r3900): r3900 does not support 64 bit integer
685 operations.
686
687Mon Mar 30 14:46:05 1998 Gavin Koch <[email protected]>
688
689 * configure.in (mipstx39*-*-*): Use gencode simulator rather
690 than igen one.
691 * configure : Rebuild.
692
693Fri Mar 27 16:15:52 1998 Andrew Cagney <[email protected]>
694
695 * configure: Regenerated to track ../common/aclocal.m4 changes.
696
697Fri Mar 27 15:01:50 1998 Andrew Cagney <[email protected]>
698
699 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
700
701Wed Mar 25 16:44:27 1998 Ian Carmichael <[email protected]>
702
703 * configure: Regenerated to track ../common/aclocal.m4 changes.
704 * config.in: Regenerated to track ../common/aclocal.m4 changes.
705
706Wed Mar 25 12:35:29 1998 Andrew Cagney <[email protected]>
707
708 * configure: Regenerated to track ../common/aclocal.m4 changes.
709
710Wed Mar 25 10:05:46 1998 Andrew Cagney <[email protected]>
711
712 * interp.c (Max, Min): Comment out functions. Not yet used.
713
714Wed Mar 18 12:38:12 1998 Andrew Cagney <[email protected]>
715
716 * configure: Regenerated to track ../common/aclocal.m4 changes.
717
718Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <[email protected]>
719
720 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
721 configurable settings for stand-alone simulator.
722
723 * configure.in: Added X11 search, just in case.
724
725 * configure: Regenerated.
726
727Wed Mar 11 14:09:10 1998 Andrew Cagney <[email protected]>
728
729 * interp.c (sim_write, sim_read, load_memory, store_memory):
730 Replace sim_core_*_map with read_map, write_map, exec_map resp.
731
732Tue Mar 3 13:58:43 1998 Andrew Cagney <[email protected]>
733
734 * sim-main.h (GETFCC): Return an unsigned value.
735
736Tue Mar 3 13:21:37 1998 Andrew Cagney <[email protected]>
737
738 * mips.igen (DIV): Fix check for -1 / MIN_INT.
739 (DADD): Result destination is RD not RT.
740
741Fri Feb 27 13:49:49 1998 Andrew Cagney <[email protected]>
742
743 * sim-main.h (HIACCESS, LOACCESS): Always define.
744
745 * mdmx.igen (Maxi, Mini): Rename Max, Min.
746
747 * interp.c (sim_info): Delete.
748
749Fri Feb 27 18:41:01 1998 Doug Evans <[email protected]>
750
751 * interp.c (DECLARE_OPTION_HANDLER): Use it.
752 (mips_option_handler): New argument `cpu'.
753 (sim_open): Update call to sim_add_option_table.
754
755Wed Feb 25 18:56:22 1998 Andrew Cagney <[email protected]>
756
757 * mips.igen (CxC1): Add tracing.
758
759Fri Feb 20 17:43:21 1998 Andrew Cagney <[email protected]>
760
761 * sim-main.h (Max, Min): Declare.
762
763 * interp.c (Max, Min): New functions.
764
765 * mips.igen (BC1): Add tracing.
766
767Thu Feb 19 14:50:00 1998 John Metzler <[email protected]>
768
769 * interp.c Added memory map for stack in vr4100
770
771Thu Feb 19 10:21:21 1998 Gavin Koch <[email protected]>
772
773 * interp.c (load_memory): Add missing "break"'s.
774
775Tue Feb 17 12:45:35 1998 Andrew Cagney <[email protected]>
776
777 * interp.c (sim_store_register, sim_fetch_register): Pass in
778 length parameter. Return -1.
779
780Tue Feb 10 11:57:40 1998 Ian Carmichael <[email protected]>
781
782 * interp.c: Added hardware init hook, fixed warnings.
783
784Sat Feb 7 17:16:20 1998 Andrew Cagney <[email protected]>
785
786 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
787
788Tue Feb 3 11:36:02 1998 Andrew Cagney <[email protected]>
789
790 * interp.c (ifetch16): New function.
791
792 * sim-main.h (IMEM32): Rename IMEM.
793 (IMEM16_IMMED): Define.
794 (IMEM16): Define.
795 (DELAY_SLOT): Update.
796
797 * m16run.c (sim_engine_run): New file.
798
799 * m16.igen: All instructions except LB.
800 (LB): Call do_load_byte.
801 * mips.igen (do_load_byte): New function.
802 (LB): Call do_load_byte.
803
804 * mips.igen: Move spec for insn bit size and high bit from here.
805 * Makefile.in (tmp-igen, tmp-m16): To here.
806
807 * m16.dc: New file, decode mips16 instructions.
808
809 * Makefile.in (SIM_NO_ALL): Define.
810 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
811
812Tue Feb 3 11:28:00 1998 Andrew Cagney <[email protected]>
813
814 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
815 point unit to 32 bit registers.
816 * configure: Re-generate.
817
818Sun Feb 1 15:47:14 1998 Andrew Cagney <[email protected]>
819
820 * configure.in (sim_use_gen): Make IGEN the default simulator
821 generator for generic 32 and 64 bit mips targets.
822 * configure: Re-generate.
823
824Sun Feb 1 16:52:37 1998 Andrew Cagney <[email protected]>
825
826 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
827 bitsize.
828
829 * interp.c (sim_fetch_register, sim_store_register): Read/write
830 FGR from correct location.
831 (sim_open): Set size of FGR's according to
832 WITH_TARGET_FLOATING_POINT_BITSIZE.
833
834 * sim-main.h (FGR): Store floating point registers in a separate
835 array.
836
837Sun Feb 1 16:47:51 1998 Andrew Cagney <[email protected]>
838
839 * configure: Regenerated to track ../common/aclocal.m4 changes.
840
841Tue Feb 3 00:10:50 1998 Andrew Cagney <[email protected]>
842
843 * interp.c (ColdReset): Call PENDING_INVALIDATE.
844
845 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
846
847 * interp.c (pending_tick): New function. Deliver pending writes.
848
849 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
850 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
851 it can handle mixed sized quantites and single bits.
852
853Mon Feb 2 17:43:15 1998 Andrew Cagney <[email protected]>
854
855 * interp.c (oengine.h): Do not include when building with IGEN.
856 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
857 (sim_info): Ditto for PROCESSOR_64BIT.
858 (sim_monitor): Replace ut_reg with unsigned_word.
859 (*): Ditto for t_reg.
860 (LOADDRMASK): Define.
861 (sim_open): Remove defunct check that host FP is IEEE compliant,
862 using software to emulate floating point.
863 (value_fpr, ...): Always compile, was conditional on HASFPU.
864
865Sun Feb 1 11:15:29 1998 Andrew Cagney <[email protected]>
866
867 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
868 size.
869
870 * interp.c (SD, CPU): Define.
871 (mips_option_handler): Set flags in each CPU.
872 (interrupt_event): Assume CPU 0 is the one being iterrupted.
873 (sim_close): Do not clear STATE, deleted anyway.
874 (sim_write, sim_read): Assume CPU zero's vm should be used for
875 data transfers.
876 (sim_create_inferior): Set the PC for all processors.
877 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
878 argument.
879 (mips16_entry): Pass correct nr of args to store_word, load_word.
880 (ColdReset): Cold reset all cpu's.
881 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
882 (sim_monitor, load_memory, store_memory, signal_exception): Use
883 `CPU' instead of STATE_CPU.
884
885
886 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
887 SD or CPU_.
888
889 * sim-main.h (signal_exception): Add sim_cpu arg.
890 (SignalException*): Pass both SD and CPU to signal_exception.
891 * interp.c (signal_exception): Update.
892
893 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
894 Ditto
895 (sync_operation, prefetch, cache_op, store_memory, load_memory,
896 address_translation): Ditto
897 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
898
899Sat Jan 31 18:15:41 1998 Andrew Cagney <[email protected]>
900
901 * configure: Regenerated to track ../common/aclocal.m4 changes.
902
903Sat Jan 31 14:49:24 1998 Andrew Cagney <[email protected]>
904
905 * interp.c (sim_engine_run): Add `nr_cpus' argument.
906
907 * mips.igen (model): Map processor names onto BFD name.
908
909 * sim-main.h (CPU_CIA): Delete.
910 (SET_CIA, GET_CIA): Define
911
912Wed Jan 21 16:16:27 1998 Andrew Cagney <[email protected]>
913
914 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
915 regiser.
916
917 * configure.in (default_endian): Configure a big-endian simulator
918 by default.
919 * configure: Re-generate.
920
921Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
922
923 * configure: Regenerated to track ../common/aclocal.m4 changes.
924
925Mon Jan 5 20:38:54 1998 Mark Alexander <[email protected]>
926
927 * interp.c (sim_monitor): Handle Densan monitor outbyte
928 and inbyte functions.
929
9301997-12-29 Felix Lee <[email protected]>
931
932 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
933
934Wed Dec 17 14:48:20 1997 Jeffrey A Law ([email protected])
935
936 * Makefile.in (tmp-igen): Arrange for $zero to always be
937 reset to zero after every instruction.
938
939Mon Dec 15 23:17:11 1997 Andrew Cagney <[email protected]>
940
941 * configure: Regenerated to track ../common/aclocal.m4 changes.
942 * config.in: Ditto.
943
944Wed Dec 10 17:10:45 1997 Jeffrey A Law ([email protected])
945
946 * mips.igen (MSUB): Fix to work like MADD.
947 * gencode.c (MSUB): Similarly.
948
949Thu Dec 4 09:21:05 1997 Doug Evans <[email protected]>
950
951 * configure: Regenerated to track ../common/aclocal.m4 changes.
952
953Wed Nov 26 11:00:23 1997 Andrew Cagney <[email protected]>
954
955 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
956
957Sun Nov 23 01:45:20 1997 Andrew Cagney <[email protected]>
958
959 * sim-main.h (sim-fpu.h): Include.
960
961 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
962 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
963 using host independant sim_fpu module.
964
965Thu Nov 20 19:56:22 1997 Andrew Cagney <[email protected]>
966
967 * interp.c (signal_exception): Report internal errors with SIGABRT
968 not SIGQUIT.
969
970 * sim-main.h (C0_CONFIG): New register.
971 (signal.h): No longer include.
972
973 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
974
975Tue Nov 18 15:33:48 1997 Doug Evans <[email protected]>
976
977 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
978
979Fri Nov 14 11:56:48 1997 Andrew Cagney <[email protected]>
980
981 * mips.igen: Tag vr5000 instructions.
982 (ANDI): Was missing mipsIV model, fix assembler syntax.
983 (do_c_cond_fmt): New function.
984 (C.cond.fmt): Handle mips I-III which do not support CC field
985 separatly.
986 (bc1): Handle mips IV which do not have a delaed FCC separatly.
987 (SDR): Mask paddr when BigEndianMem, not the converse as specified
988 in IV3.2 spec.
989 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
990 vr5000 which saves LO in a GPR separatly.
991
992 * configure.in (enable-sim-igen): For vr5000, select vr5000
993 specific instructions.
994 * configure: Re-generate.
995
996Wed Nov 12 14:42:52 1997 Andrew Cagney <[email protected]>
997
998 * Makefile.in (SIM_OBJS): Add sim-fpu module.
999
1000 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1001 fmt_uninterpreted_64 bit cases to switch. Convert to
1002 fmt_formatted,
1003
1004 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1005
1006 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1007 as specified in IV3.2 spec.
1008 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1009
1010Tue Nov 11 12:38:23 1997 Andrew Cagney <[email protected]>
1011
1012 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1013 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1014 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1015 PENDING_FILL versions of instructions. Simplify.
1016 (X): New function.
1017 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1018 instructions.
1019 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1020 a signed value.
1021 (MTHI, MFHI): Disable code checking HI-LO.
1022
1023 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1024 global.
1025 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1026
1027Thu Nov 6 16:36:35 1997 Andrew Cagney <[email protected]>
1028
1029 * gencode.c (build_mips16_operands): Replace IPC with cia.
1030
1031 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1032 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1033 IPC to `cia'.
1034 (UndefinedResult): Replace function with macro/function
1035 combination.
1036 (sim_engine_run): Don't save PC in IPC.
1037
1038 * sim-main.h (IPC): Delete.
1039
1040
1041 * interp.c (signal_exception, store_word, load_word,
1042 address_translation, load_memory, store_memory, cache_op,
1043 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1044 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1045 current instruction address - cia - argument.
1046 (sim_read, sim_write): Call address_translation directly.
1047 (sim_engine_run): Rename variable vaddr to cia.
1048 (signal_exception): Pass cia to sim_monitor
1049
1050 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1051 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1052 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1053
1054 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1055 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1056 SIM_ASSERT.
1057
1058 * interp.c (signal_exception): Pass restart address to
1059 sim_engine_restart.
1060
1061 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1062 idecode.o): Add dependency.
1063
1064 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1065 Delete definitions
1066 (DELAY_SLOT): Update NIA not PC with branch address.
1067 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1068
1069 * mips.igen: Use CIA not PC in branch calculations.
1070 (illegal): Call SignalException.
1071 (BEQ, ADDIU): Fix assembler.
1072
1073Wed Nov 5 12:19:56 1997 Andrew Cagney <[email protected]>
1074
1075 * m16.igen (JALX): Was missing.
1076
1077 * configure.in (enable-sim-igen): New configuration option.
1078 * configure: Re-generate.
1079
1080 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1081
1082 * interp.c (load_memory, store_memory): Delete parameter RAW.
1083 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1084 bypassing {load,store}_memory.
1085
1086 * sim-main.h (ByteSwapMem): Delete definition.
1087
1088 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1089
1090 * interp.c (sim_do_command, sim_commands): Delete mips specific
1091 commands. Handled by module sim-options.
1092
1093 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1094 (WITH_MODULO_MEMORY): Define.
1095
1096 * interp.c (sim_info): Delete code printing memory size.
1097
1098 * interp.c (mips_size): Nee sim_size, delete function.
1099 (power2): Delete.
1100 (monitor, monitor_base, monitor_size): Delete global variables.
1101 (sim_open, sim_close): Delete code creating monitor and other
1102 memory regions. Use sim-memopts module, via sim_do_commandf, to
1103 manage memory regions.
1104 (load_memory, store_memory): Use sim-core for memory model.
1105
1106 * interp.c (address_translation): Delete all memory map code
1107 except line forcing 32 bit addresses.
1108
1109Wed Nov 5 11:21:11 1997 Andrew Cagney <[email protected]>
1110
1111 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1112 trace options.
1113
1114 * interp.c (logfh, logfile): Delete globals.
1115 (sim_open, sim_close): Delete code opening & closing log file.
1116 (mips_option_handler): Delete -l and -n options.
1117 (OPTION mips_options): Ditto.
1118
1119 * interp.c (OPTION mips_options): Rename option trace to dinero.
1120 (mips_option_handler): Update.
1121
1122Wed Nov 5 09:35:59 1997 Andrew Cagney <[email protected]>
1123
1124 * interp.c (fetch_str): New function.
1125 (sim_monitor): Rewrite using sim_read & sim_write.
1126 (sim_open): Check magic number.
1127 (sim_open): Write monitor vectors into memory using sim_write.
1128 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1129 (sim_read, sim_write): Simplify - transfer data one byte at a
1130 time.
1131 (load_memory, store_memory): Clarify meaning of parameter RAW.
1132
1133 * sim-main.h (isHOST): Defete definition.
1134 (isTARGET): Mark as depreciated.
1135 (address_translation): Delete parameter HOST.
1136
1137 * interp.c (address_translation): Delete parameter HOST.
1138
1139Wed Oct 29 11:13:56 1997 Andrew Cagney <[email protected]>
1140
1141 * mips.igen:
1142
1143 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1144 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1145
1146Tue Oct 28 11:06:47 1997 Andrew Cagney <[email protected]>
1147
1148 * mips.igen: Add model filter field to records.
1149
1150Mon Oct 27 17:53:59 1997 Andrew Cagney <[email protected]>
1151
1152 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1153
1154 interp.c (sim_engine_run): Do not compile function sim_engine_run
1155 when WITH_IGEN == 1.
1156
1157 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1158 target architecture.
1159
1160 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1161 igen. Replace with configuration variables sim_igen_flags /
1162 sim_m16_flags.
1163
1164 * m16.igen: New file. Copy mips16 insns here.
1165 * mips.igen: From here.
1166
1167Mon Oct 27 13:53:59 1997 Andrew Cagney <[email protected]>
1168
1169 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1170 to top.
1171 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1172
1173Sat Oct 25 16:51:40 1997 Gavin Koch <[email protected]>
1174
1175 * gencode.c (build_instruction): Follow sim_write's lead in using
1176 BigEndianMem instead of !ByteSwapMem.
1177
1178Fri Oct 24 17:41:49 1997 Andrew Cagney <[email protected]>
1179
1180 * configure.in (sim_gen): Dependent on target, select type of
1181 generator. Always select old style generator.
1182
1183 configure: Re-generate.
1184
1185 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1186 targets.
1187 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1188 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1189 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1190 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1191 SIM_@sim_gen@_*, set by autoconf.
1192
1193Wed Oct 22 12:52:06 1997 Andrew Cagney <[email protected]>
1194
1195 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1196
1197 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1198 CURRENT_FLOATING_POINT instead.
1199
1200 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1201 (address_translation): Raise exception InstructionFetch when
1202 translation fails and isINSTRUCTION.
1203
1204 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1205 sim_engine_run): Change type of of vaddr and paddr to
1206 address_word.
1207 (address_translation, prefetch, load_memory, store_memory,
1208 cache_op): Change type of vAddr and pAddr to address_word.
1209
1210 * gencode.c (build_instruction): Change type of vaddr and paddr to
1211 address_word.
1212
1213Mon Oct 20 15:29:04 1997 Andrew Cagney <[email protected]>
1214
1215 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1216 macro to obtain result of ALU op.
1217
1218Tue Oct 21 17:39:14 1997 Andrew Cagney <[email protected]>
1219
1220 * interp.c (sim_info): Call profile_print.
1221
1222Mon Oct 20 13:31:20 1997 Andrew Cagney <[email protected]>
1223
1224 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1225
1226 * sim-main.h (WITH_PROFILE): Do not define, defined in
1227 common/sim-config.h. Use sim-profile module.
1228 (simPROFILE): Delete defintion.
1229
1230 * interp.c (PROFILE): Delete definition.
1231 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1232 (sim_close): Delete code writing profile histogram.
1233 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1234 Delete.
1235 (sim_engine_run): Delete code profiling the PC.
1236
1237Mon Oct 20 13:31:20 1997 Andrew Cagney <[email protected]>
1238
1239 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1240
1241 * interp.c (sim_monitor): Make register pointers of type
1242 unsigned_word*.
1243
1244 * sim-main.h: Make registers of type unsigned_word not
1245 signed_word.
1246
1247Thu Oct 16 10:31:39 1997 Andrew Cagney <[email protected]>
1248
1249 * interp.c (sync_operation): Rename from SyncOperation, make
1250 global, add SD argument.
1251 (prefetch): Rename from Prefetch, make global, add SD argument.
1252 (decode_coproc): Make global.
1253
1254 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1255
1256 * gencode.c (build_instruction): Generate DecodeCoproc not
1257 decode_coproc calls.
1258
1259 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1260 (SizeFGR): Move to sim-main.h
1261 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1262 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1263 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1264 sim-main.h.
1265 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1266 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1267 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1268 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1269 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1270 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1271
1272 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1273 exception.
1274 (sim-alu.h): Include.
1275 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1276 (sim_cia): Typedef to instruction_address.
1277
1278Thu Oct 16 10:31:41 1997 Andrew Cagney <[email protected]>
1279
1280 * Makefile.in (interp.o): Rename generated file engine.c to
1281 oengine.c.
1282
1283 * interp.c: Update.
1284
1285Thu Oct 16 10:31:40 1997 Andrew Cagney <[email protected]>
1286
1287 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1288
1289Thu Oct 16 10:31:39 1997 Andrew Cagney <[email protected]>
1290
1291 * gencode.c (build_instruction): For "FPSQRT", output correct
1292 number of arguments to Recip.
1293
1294Tue Oct 14 17:38:18 1997 Andrew Cagney <[email protected]>
1295
1296 * Makefile.in (interp.o): Depends on sim-main.h
1297
1298 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1299
1300 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1301 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1302 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1303 STATE, DSSTATE): Define
1304 (GPR, FGRIDX, ..): Define.
1305
1306 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1307 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1308 (GPR, FGRIDX, ...): Delete macros.
1309
1310 * interp.c: Update names to match defines from sim-main.h
1311
1312Tue Oct 14 15:11:45 1997 Andrew Cagney <[email protected]>
1313
1314 * interp.c (sim_monitor): Add SD argument.
1315 (sim_warning): Delete. Replace calls with calls to
1316 sim_io_eprintf.
1317 (sim_error): Delete. Replace calls with sim_io_error.
1318 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1319 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1320 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1321 argument.
1322 (mips_size): Rename from sim_size. Add SD argument.
1323
1324 * interp.c (simulator): Delete global variable.
1325 (callback): Delete global variable.
1326 (mips_option_handler, sim_open, sim_write, sim_read,
1327 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1328 sim_size,sim_monitor): Use sim_io_* not callback->*.
1329 (sim_open): ZALLOC simulator struct.
1330 (PROFILE): Do not define.
1331
1332Tue Oct 14 13:35:48 1997 Andrew Cagney <[email protected]>
1333
1334 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1335 support.h with corresponding code.
1336
1337 * sim-main.h (word64, uword64), support.h: Move definition to
1338 sim-main.h.
1339 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1340
1341 * support.h: Delete
1342 * Makefile.in: Update dependencies
1343 * interp.c: Do not include.
1344
1345Tue Oct 14 13:35:48 1997 Andrew Cagney <[email protected]>
1346
1347 * interp.c (address_translation, load_memory, store_memory,
1348 cache_op): Rename to from AddressTranslation et.al., make global,
1349 add SD argument
1350
1351 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1352 CacheOp): Define.
1353
1354 * interp.c (SignalException): Rename to signal_exception, make
1355 global.
1356
1357 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1358
1359 * sim-main.h (SignalException, SignalExceptionInterrupt,
1360 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1361 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1362 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1363 Define.
1364
1365 * interp.c, support.h: Use.
1366
1367Tue Oct 14 13:19:20 1997 Andrew Cagney <[email protected]>
1368
1369 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1370 to value_fpr / store_fpr. Add SD argument.
1371 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1372 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1373
1374 * sim-main.h (ValueFPR, StoreFPR): Define.
1375
1376Tue Oct 14 13:06:55 1997 Andrew Cagney <[email protected]>
1377
1378 * interp.c (sim_engine_run): Check consistency between configure
1379 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1380 and HASFPU.
1381
1382 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1383 (mips_fpu): Configure WITH_FLOATING_POINT.
1384 (mips_endian): Configure WITH_TARGET_ENDIAN.
1385 * configure: Update.
1386
1387Fri Oct 3 09:28:00 1997 Andrew Cagney <[email protected]>
1388
1389 * configure: Regenerated to track ../common/aclocal.m4 changes.
1390
1391Mon Sep 29 14:45:00 1997 Bob Manson <[email protected]>
1392
1393 * configure: Regenerated.
1394
1395Fri Sep 26 12:48:18 1997 Mark Alexander <[email protected]>
1396
1397 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1398
1399Thu Sep 25 11:15:22 1997 Andrew Cagney <[email protected]>
1400
1401 * gencode.c (print_igen_insn_models): Assume certain architectures
1402 include all mips* instructions.
1403 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1404 instruction.
1405
1406 * Makefile.in (tmp.igen): Add target. Generate igen input from
1407 gencode file.
1408
1409 * gencode.c (FEATURE_IGEN): Define.
1410 (main): Add --igen option. Generate output in igen format.
1411 (process_instructions): Format output according to igen option.
1412 (print_igen_insn_format): New function.
1413 (print_igen_insn_models): New function.
1414 (process_instructions): Only issue warnings and ignore
1415 instructions when no FEATURE_IGEN.
1416
1417Wed Sep 24 17:38:57 1997 Andrew Cagney <[email protected]>
1418
1419 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1420 MIPS targets.
1421
1422Tue Sep 23 11:04:38 1997 Andrew Cagney <[email protected]>
1423
1424 * configure: Regenerated to track ../common/aclocal.m4 changes.
1425
1426Tue Sep 23 10:19:51 1997 Andrew Cagney <[email protected]>
1427
1428 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1429 SIM_RESERVED_BITS): Delete, moved to common.
1430 (SIM_EXTRA_CFLAGS): Update.
1431
1432Mon Sep 22 11:46:20 1997 Andrew Cagney <[email protected]>
1433
1434 * configure.in: Configure non-strict memory alignment.
1435 * configure: Regenerated to track ../common/aclocal.m4 changes.
1436
1437Fri Sep 19 17:45:25 1997 Andrew Cagney <[email protected]>
1438
1439 * configure: Regenerated to track ../common/aclocal.m4 changes.
1440
1441Sat Sep 20 14:07:28 1997 Gavin Koch <[email protected]>
1442
1443 * gencode.c (SDBBP,DERET): Added (3900) insns.
1444 (RFE): Turn on for 3900.
1445 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1446 (dsstate): Made global.
1447 (SUBTARGET_R3900): Added.
1448 (CANCELDELAYSLOT): New.
1449 (SignalException): Ignore SystemCall rather than ignore and
1450 terminate. Add DebugBreakPoint handling.
1451 (decode_coproc): New insns RFE, DERET; and new registers Debug
1452 and DEPC protected by SUBTARGET_R3900.
1453 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1454 bits explicitly.
1455 * Makefile.in,configure.in: Add mips subtarget option.
1456 * configure: Update.
1457
1458Fri Sep 19 09:33:27 1997 Gavin Koch <[email protected]>
1459
1460 * gencode.c: Add r3900 (tx39).
1461
1462
1463Tue Sep 16 15:52:04 1997 Gavin Koch <[email protected]>
1464
1465 * gencode.c (build_instruction): Don't need to subtract 4 for
1466 JALR, just 2.
1467
1468Tue Sep 16 11:32:28 1997 Gavin Koch <[email protected]>
1469
1470 * interp.c: Correct some HASFPU problems.
1471
1472Mon Sep 15 17:36:15 1997 Andrew Cagney <[email protected]>
1473
1474 * configure: Regenerated to track ../common/aclocal.m4 changes.
1475
1476Fri Sep 12 12:01:39 1997 Andrew Cagney <[email protected]>
1477
1478 * interp.c (mips_options): Fix samples option short form, should
1479 be `x'.
1480
1481Thu Sep 11 09:35:29 1997 Andrew Cagney <[email protected]>
1482
1483 * interp.c (sim_info): Enable info code. Was just returning.
1484
1485Tue Sep 9 17:30:57 1997 Andrew Cagney <[email protected]>
1486
1487 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1488 MFC0.
1489
1490Tue Sep 9 16:28:28 1997 Andrew Cagney <[email protected]>
1491
1492 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1493 constants.
1494 (build_instruction): Ditto for LL.
1495
1496Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1497
1498 * configure: Regenerated to track ../common/aclocal.m4 changes.
1499
1500Wed Aug 27 18:13:22 1997 Andrew Cagney <[email protected]>
1501
1502 * configure: Regenerated to track ../common/aclocal.m4 changes.
1503 * config.in: Ditto.
1504
1505Wed Aug 27 14:12:27 1997 Andrew Cagney <[email protected]>
1506
1507 * interp.c (sim_open): Add call to sim_analyze_program, update
1508 call to sim_config.
1509
1510Tue Aug 26 10:40:07 1997 Andrew Cagney <[email protected]>
1511
1512 * interp.c (sim_kill): Delete.
1513 (sim_create_inferior): Add ABFD argument. Set PC from same.
1514 (sim_load): Move code initializing trap handlers from here.
1515 (sim_open): To here.
1516 (sim_load): Delete, use sim-hload.c.
1517
1518 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1519
1520Mon Aug 25 17:50:22 1997 Andrew Cagney <[email protected]>
1521
1522 * configure: Regenerated to track ../common/aclocal.m4 changes.
1523 * config.in: Ditto.
1524
1525Mon Aug 25 15:59:48 1997 Andrew Cagney <[email protected]>
1526
1527 * interp.c (sim_open): Add ABFD argument.
1528 (sim_load): Move call to sim_config from here.
1529 (sim_open): To here. Check return status.
1530
1531Fri Jul 25 15:00:45 1997 Gavin Koch <[email protected]>
1532
1533 * gencode.c (build_instruction): Two arg MADD should
1534 not assign result to $0.
1535
1536Thu Jun 26 12:13:17 1997 Angela Marie Thomas ([email protected])
1537
1538 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1539 * sim/mips/configure.in: Regenerate.
1540
1541Wed Jul 9 10:29:21 1997 Andrew Cagney <[email protected]>
1542
1543 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1544 signed8, unsigned8 et.al. types.
1545
1546 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1547 hosts when selecting subreg.
1548
1549Wed Jul 2 11:54:10 1997 Jeffrey A Law ([email protected])
1550
1551 * interp.c (sim_engine_run): Reset the ZERO register to zero
1552 regardless of FEATURE_WARN_ZERO.
1553 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1554
1555Wed Jun 4 10:43:14 1997 Andrew Cagney <[email protected]>
1556
1557 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1558 (SignalException): For BreakPoints ignore any mode bits and just
1559 save the PC.
1560 (SignalException): Always set the CAUSE register.
1561
1562Tue Jun 3 05:00:33 1997 Andrew Cagney <[email protected]>
1563
1564 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1565 exception has been taken.
1566
1567 * interp.c: Implement the ERET and mt/f sr instructions.
1568
1569Sat May 31 00:44:16 1997 Andrew Cagney <[email protected]>
1570
1571 * interp.c (SignalException): Don't bother restarting an
1572 interrupt.
1573
1574Fri May 30 23:41:48 1997 Andrew Cagney <[email protected]>
1575
1576 * interp.c (SignalException): Really take an interrupt.
1577 (interrupt_event): Only deliver interrupts when enabled.
1578
1579Tue May 27 20:08:06 1997 Andrew Cagney <[email protected]>
1580
1581 * interp.c (sim_info): Only print info when verbose.
1582 (sim_info) Use sim_io_printf for output.
1583
1584Tue May 27 14:22:23 1997 Andrew Cagney <[email protected]>
1585
1586 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1587 mips architectures.
1588
1589Tue May 27 14:22:23 1997 Andrew Cagney <[email protected]>
1590
1591 * interp.c (sim_do_command): Check for common commands if a
1592 simulator specific command fails.
1593
1594Thu May 22 09:32:03 1997 Gavin Koch <[email protected]>
1595
1596 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1597 and simBE when DEBUG is defined.
1598
1599Wed May 21 09:08:10 1997 Andrew Cagney <[email protected]>
1600
1601 * interp.c (interrupt_event): New function. Pass exception event
1602 onto exception handler.
1603
1604 * configure.in: Check for stdlib.h.
1605 * configure: Regenerate.
1606
1607 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1608 variable declaration.
1609 (build_instruction): Initialize memval1.
1610 (build_instruction): Add UNUSED attribute to byte, bigend,
1611 reverse.
1612 (build_operands): Ditto.
1613
1614 * interp.c: Fix GCC warnings.
1615 (sim_get_quit_code): Delete.
1616
1617 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1618 * Makefile.in: Ditto.
1619 * configure: Re-generate.
1620
1621 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1622
1623Tue May 20 15:08:56 1997 Andrew Cagney <[email protected]>
1624
1625 * interp.c (mips_option_handler): New function parse argumes using
1626 sim-options.
1627 (myname): Replace with STATE_MY_NAME.
1628 (sim_open): Delete check for host endianness - performed by
1629 sim_config.
1630 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1631 (sim_open): Move much of the initialization from here.
1632 (sim_load): To here. After the image has been loaded and
1633 endianness set.
1634 (sim_open): Move ColdReset from here.
1635 (sim_create_inferior): To here.
1636 (sim_open): Make FP check less dependant on host endianness.
1637
1638 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1639 run.
1640 * interp.c (sim_set_callbacks): Delete.
1641
1642 * interp.c (membank, membank_base, membank_size): Replace with
1643 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1644 (sim_open): Remove call to callback->init. gdb/run do this.
1645
1646 * interp.c: Update
1647
1648 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1649
1650 * interp.c (big_endian_p): Delete, replaced by
1651 current_target_byte_order.
1652
1653Tue May 20 13:55:00 1997 Andrew Cagney <[email protected]>
1654
1655 * interp.c (host_read_long, host_read_word, host_swap_word,
1656 host_swap_long): Delete. Using common sim-endian.
1657 (sim_fetch_register, sim_store_register): Use H2T.
1658 (pipeline_ticks): Delete. Handled by sim-events.
1659 (sim_info): Update.
1660 (sim_engine_run): Update.
1661
1662Tue May 20 13:42:03 1997 Andrew Cagney <[email protected]>
1663
1664 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1665 reason from here.
1666 (SignalException): To here. Signal using sim_engine_halt.
1667 (sim_stop_reason): Delete, moved to common.
1668
1669Tue May 20 10:19:48 1997 Andrew Cagney <[email protected]>
1670
1671 * interp.c (sim_open): Add callback argument.
1672 (sim_set_callbacks): Delete SIM_DESC argument.
1673 (sim_size): Ditto.
1674
1675Mon May 19 18:20:38 1997 Andrew Cagney <[email protected]>
1676
1677 * Makefile.in (SIM_OBJS): Add common modules.
1678
1679 * interp.c (sim_set_callbacks): Also set SD callback.
1680 (set_endianness, xfer_*, swap_*): Delete.
1681 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1682 Change to functions using sim-endian macros.
1683 (control_c, sim_stop): Delete, use common version.
1684 (simulate): Convert into.
1685 (sim_engine_run): This function.
1686 (sim_resume): Delete.
1687
1688 * interp.c (simulation): New variable - the simulator object.
1689 (sim_kind): Delete global - merged into simulation.
1690 (sim_load): Cleanup. Move PC assignment from here.
1691 (sim_create_inferior): To here.
1692
1693 * sim-main.h: New file.
1694 * interp.c (sim-main.h): Include.
1695
1696Thu Apr 24 00:39:51 1997 Doug Evans <[email protected]>
1697
1698 * configure: Regenerated to track ../common/aclocal.m4 changes.
1699
1700Wed Apr 23 17:32:19 1997 Doug Evans <[email protected]>
1701
1702 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1703
1704Mon Apr 21 17:16:13 1997 Gavin Koch <[email protected]>
1705
1706 * gencode.c (build_instruction): DIV instructions: check
1707 for division by zero and integer overflow before using
1708 host's division operation.
1709
1710Thu Apr 17 03:18:14 1997 Doug Evans <[email protected]>
1711
1712 * Makefile.in (SIM_OBJS): Add sim-load.o.
1713 * interp.c: #include bfd.h.
1714 (target_byte_order): Delete.
1715 (sim_kind, myname, big_endian_p): New static locals.
1716 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1717 after argument parsing. Recognize -E arg, set endianness accordingly.
1718 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1719 load file into simulator. Set PC from bfd.
1720 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1721 (set_endianness): Use big_endian_p instead of target_byte_order.
1722
1723Wed Apr 16 17:55:37 1997 Andrew Cagney <[email protected]>
1724
1725 * interp.c (sim_size): Delete prototype - conflicts with
1726 definition in remote-sim.h. Correct definition.
1727
1728Mon Apr 7 15:45:02 1997 Andrew Cagney <[email protected]>
1729
1730 * configure: Regenerated to track ../common/aclocal.m4 changes.
1731 * config.in: Ditto.
1732
1733Wed Apr 2 15:06:28 1997 Doug Evans <[email protected]>
1734
1735 * interp.c (sim_open): New arg `kind'.
1736
1737 * configure: Regenerated to track ../common/aclocal.m4 changes.
1738
1739Wed Apr 2 14:34:19 1997 Andrew Cagney <[email protected]>
1740
1741 * configure: Regenerated to track ../common/aclocal.m4 changes.
1742
1743Tue Mar 25 11:38:22 1997 Doug Evans <[email protected]>
1744
1745 * interp.c (sim_open): Set optind to 0 before calling getopt.
1746
1747Wed Mar 19 01:14:00 1997 Andrew Cagney <[email protected]>
1748
1749 * configure: Regenerated to track ../common/aclocal.m4 changes.
1750
1751Mon Mar 17 10:52:59 1997 Gavin Koch <[email protected]>
1752
1753 * interp.c : Replace uses of pr_addr with pr_uword64
1754 where the bit length is always 64 independent of SIM_ADDR.
1755 (pr_uword64) : added.
1756
1757Mon Mar 17 15:10:07 1997 Andrew Cagney <[email protected]>
1758
1759 * configure: Re-generate.
1760
1761Fri Mar 14 10:34:11 1997 Michael Meissner <[email protected]>
1762
1763 * configure: Regenerate to track ../common/aclocal.m4 changes.
1764
1765Thu Mar 13 12:51:36 1997 Doug Evans <[email protected]>
1766
1767 * interp.c (sim_open): New SIM_DESC result. Argument is now
1768 in argv form.
1769 (other sim_*): New SIM_DESC argument.
1770
1771Mon Feb 24 22:47:14 1997 Dawn Perchik <[email protected]>
1772
1773 * interp.c: Fix printing of addresses for non-64-bit targets.
1774 (pr_addr): Add function to print address based on size.
1775
1776Wed Feb 19 14:42:09 1997 Mark Alexander <[email protected]>
1777
1778 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1779
1780Thu Feb 13 14:08:30 1997 Ian Lance Taylor <[email protected]>
1781
1782 * gencode.c (build_mips16_operands): Correct computation of base
1783 address for extended PC relative instruction.
1784
1785Thu Feb 6 17:16:15 1997 Ian Lance Taylor <[email protected]>
1786
1787 * interp.c (mips16_entry): Add support for floating point cases.
1788 (SignalException): Pass floating point cases to mips16_entry.
1789 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1790 registers.
1791 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1792 or fmt_word.
1793 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1794 and then set the state to fmt_uninterpreted.
1795 (COP_SW): Temporarily set the state to fmt_word while calling
1796 ValueFPR.
1797
1798Tue Feb 4 16:48:25 1997 Ian Lance Taylor <[email protected]>
1799
1800 * gencode.c (build_instruction): The high order may be set in the
1801 comparison flags at any ISA level, not just ISA 4.
1802
1803Tue Feb 4 13:33:30 1997 Doug Evans <[email protected]>
1804
1805 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1806 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1807 * configure.in: sinclude ../common/aclocal.m4.
1808 * configure: Regenerated.
1809
1810Fri Jan 31 11:11:45 1997 Ian Lance Taylor <[email protected]>
1811
1812 * configure: Rebuild after change to aclocal.m4.
1813
1814Thu Jan 23 11:46:23 1997 Stu Grossman ([email protected])
1815
1816 * configure configure.in Makefile.in: Update to new configure
1817 scheme which is more compatible with WinGDB builds.
1818 * configure.in: Improve comment on how to run autoconf.
1819 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1820 * Makefile.in: Use autoconf substitution to install common
1821 makefile fragment.
1822
1823Wed Jan 8 12:39:03 1997 Jim Wilson <[email protected]>
1824
1825 * gencode.c (build_instruction): Use BigEndianCPU instead of
1826 ByteSwapMem.
1827
1828Thu Jan 02 22:23:04 1997 Mark Alexander <[email protected]>
1829
1830 * interp.c (sim_monitor): Make output to stdout visible in
1831 wingdb's I/O log window.
1832
1833Tue Dec 31 07:04:00 1996 Mark Alexander <[email protected]>
1834
1835 * support.h: Undo previous change to SIGTRAP
1836 and SIGQUIT values.
1837
1838Mon Dec 30 17:36:06 1996 Ian Lance Taylor <[email protected]>
1839
1840 * interp.c (store_word, load_word): New static functions.
1841 (mips16_entry): New static function.
1842 (SignalException): Look for mips16 entry and exit instructions.
1843 (simulate): Use the correct index when setting fpr_state after
1844 doing a pending move.
1845
1846Sun Dec 29 09:37:18 1996 Mark Alexander <[email protected]>
1847
1848 * interp.c: Fix byte-swapping code throughout to work on
1849 both little- and big-endian hosts.
1850
1851Sun Dec 29 09:18:32 1996 Mark Alexander <[email protected]>
1852
1853 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1854 with gdb/config/i386/xm-windows.h.
1855
1856Fri Dec 27 22:48:51 1996 Mark Alexander <[email protected]>
1857
1858 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1859 that messes up arithmetic shifts.
1860
1861Fri Dec 20 11:04:05 1996 Stu Grossman ([email protected])
1862
1863 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1864 SIGTRAP and SIGQUIT for _WIN32.
1865
1866Thu Dec 19 14:07:27 1996 Ian Lance Taylor <[email protected]>
1867
1868 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1869 force a 64 bit multiplication.
1870 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1871 destination register is 0, since that is the default mips16 nop
1872 instruction.
1873
1874Mon Dec 16 14:59:38 1996 Ian Lance Taylor <[email protected]>
1875
1876 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1877 (build_endian_shift): Don't check proc64.
1878 (build_instruction): Always set memval to uword64. Cast op2 to
1879 uword64 when shifting it left in memory instructions. Always use
1880 the same code for stores--don't special case proc64.
1881
1882 * gencode.c (build_mips16_operands): Fix base PC value for PC
1883 relative operands.
1884 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1885 jal instruction.
1886 * interp.c (simJALDELAYSLOT): Define.
1887 (JALDELAYSLOT): Define.
1888 (INDELAYSLOT, INJALDELAYSLOT): Define.
1889 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1890
1891Tue Dec 24 22:11:20 1996 Angela Marie Thomas ([email protected])
1892
1893 * interp.c (sim_open): add flush_cache as a PMON routine
1894 (sim_monitor): handle flush_cache by ignoring it
1895
1896Wed Dec 11 13:53:51 1996 Jim Wilson <[email protected]>
1897
1898 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1899 BigEndianMem.
1900 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1901 (BigEndianMem): Rename to ByteSwapMem and change sense.
1902 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1903 BigEndianMem references to !ByteSwapMem.
1904 (set_endianness): New function, with prototype.
1905 (sim_open): Call set_endianness.
1906 (sim_info): Use simBE instead of BigEndianMem.
1907 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1908 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1909 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1910 ifdefs, keeping the prototype declaration.
1911 (swap_word): Rewrite correctly.
1912 (ColdReset): Delete references to CONFIG. Delete endianness related
1913 code; moved to set_endianness.
1914
1915Tue Dec 10 11:32:04 1996 Jim Wilson <[email protected]>
1916
1917 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1918 * interp.c (CHECKHILO): Define away.
1919 (simSIGINT): New macro.
1920 (membank_size): Increase from 1MB to 2MB.
1921 (control_c): New function.
1922 (sim_resume): Rename parameter signal to signal_number. Add local
1923 variable prev. Call signal before and after simulate.
1924 (sim_stop_reason): Add simSIGINT support.
1925 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1926 functions always.
1927 (sim_warning): Delete call to SignalException. Do call printf_filtered
1928 if logfh is NULL.
1929 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1930 a call to sim_warning.
1931
1932Wed Nov 27 11:53:50 1996 Ian Lance Taylor <[email protected]>
1933
1934 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1935 16 bit instructions.
1936
1937Tue Nov 26 11:53:12 1996 Ian Lance Taylor <[email protected]>
1938
1939 Add support for mips16 (16 bit MIPS implementation):
1940 * gencode.c (inst_type): Add mips16 instruction encoding types.
1941 (GETDATASIZEINSN): Define.
1942 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1943 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1944 mtlo.
1945 (MIPS16_DECODE): New table, for mips16 instructions.
1946 (bitmap_val): New static function.
1947 (struct mips16_op): Define.
1948 (mips16_op_table): New table, for mips16 operands.
1949 (build_mips16_operands): New static function.
1950 (process_instructions): If PC is odd, decode a mips16
1951 instruction. Break out instruction handling into new
1952 build_instruction function.
1953 (build_instruction): New static function, broken out of
1954 process_instructions. Check modifiers rather than flags for SHIFT
1955 bit count and m[ft]{hi,lo} direction.
1956 (usage): Pass program name to fprintf.
1957 (main): Remove unused variable this_option_optind. Change
1958 ``*loptarg++'' to ``loptarg++''.
1959 (my_strtoul): Parenthesize && within ||.
1960 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1961 (simulate): If PC is odd, fetch a 16 bit instruction, and
1962 increment PC by 2 rather than 4.
1963 * configure.in: Add case for mips16*-*-*.
1964 * configure: Rebuild.
1965
1966Fri Nov 22 08:49:36 1996 Mark Alexander <[email protected]>
1967
1968 * interp.c: Allow -t to enable tracing in standalone simulator.
1969 Fix garbage output in trace file and error messages.
1970
1971Wed Nov 20 01:54:37 1996 Doug Evans <[email protected]>
1972
1973 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1974 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1975 * configure.in: Simplify using macros in ../common/aclocal.m4.
1976 * configure: Regenerated.
1977 * tconfig.in: New file.
1978
1979Tue Nov 12 13:34:00 1996 Dawn Perchik <[email protected]>
1980
1981 * interp.c: Fix bugs in 64-bit port.
1982 Use ansi function declarations for msvc compiler.
1983 Initialize and test file pointer in trace code.
1984 Prevent duplicate definition of LAST_EMED_REGNUM.
1985
1986Tue Oct 15 11:07:06 1996 Mark Alexander <[email protected]>
1987
1988 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1989
1990Thu Sep 26 17:35:00 1996 James G. Smith <[email protected]>
1991
1992 * interp.c (SignalException): Check for explicit terminating
1993 breakpoint value.
1994 * gencode.c: Pass instruction value through SignalException()
1995 calls for Trap, Breakpoint and Syscall.
1996
1997Thu Sep 26 11:35:17 1996 James G. Smith <[email protected]>
1998
1999 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2000 only used on those hosts that provide it.
2001 * configure.in: Add sqrt() to list of functions to be checked for.
2002 * config.in: Re-generated.
2003 * configure: Re-generated.
2004
2005Fri Sep 20 15:47:12 1996 Ian Lance Taylor <[email protected]>
2006
2007 * gencode.c (process_instructions): Call build_endian_shift when
2008 expanding STORE RIGHT, to fix swr.
2009 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2010 clear the high bits.
2011 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2012 Fix float to int conversions to produce signed values.
2013
2014Thu Sep 19 15:34:17 1996 Ian Lance Taylor <[email protected]>
2015
2016 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2017 (process_instructions): Correct handling of nor instruction.
2018 Correct shift count for 32 bit shift instructions. Correct sign
2019 extension for arithmetic shifts to not shift the number of bits in
2020 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2021 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2022 Fix madd.
2023 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2024 It's OK to have a mult follow a mult. What's not OK is to have a
2025 mult follow an mfhi.
2026 (Convert): Comment out incorrect rounding code.
2027
2028Mon Sep 16 11:38:16 1996 James G. Smith <[email protected]>
2029
2030 * interp.c (sim_monitor): Improved monitor printf
2031 simulation. Tidied up simulator warnings, and added "--log" option
2032 for directing warning message output.
2033 * gencode.c: Use sim_warning() rather than WARNING macro.
2034
2035Thu Aug 22 15:03:12 1996 Ian Lance Taylor <[email protected]>
2036
2037 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2038 getopt1.o, rather than on gencode.c. Link objects together.
2039 Don't link against -liberty.
2040 (gencode.o, getopt.o, getopt1.o): New targets.
2041 * gencode.c: Include <ctype.h> and "ansidecl.h".
2042 (AND): Undefine after including "ansidecl.h".
2043 (ULONG_MAX): Define if not defined.
2044 (OP_*): Don't define macros; now defined in opcode/mips.h.
2045 (main): Call my_strtoul rather than strtoul.
2046 (my_strtoul): New static function.
2047
2048Wed Jul 17 18:12:38 1996 Stu Grossman ([email protected])
2049
2050 * gencode.c (process_instructions): Generate word64 and uword64
2051 instead of `long long' and `unsigned long long' data types.
2052 * interp.c: #include sysdep.h to get signals, and define default
2053 for SIGBUS.
2054 * (Convert): Work around for Visual-C++ compiler bug with type
2055 conversion.
2056 * support.h: Make things compile under Visual-C++ by using
2057 __int64 instead of `long long'. Change many refs to long long
2058 into word64/uword64 typedefs.
2059
2060Wed Jun 26 12:24:55 1996 Jason Molenda ([email protected])
2061
2062 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2063 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2064 (docdir): Removed.
2065 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2066 (AC_PROG_INSTALL): Added.
2067 (AC_PROG_CC): Moved to before configure.host call.
2068 * configure: Rebuilt.
2069
2070Wed Jun 5 08:28:13 1996 James G. Smith <[email protected]>
2071
2072 * configure.in: Define @SIMCONF@ depending on mips target.
2073 * configure: Rebuild.
2074 * Makefile.in (run): Add @SIMCONF@ to control simulator
2075 construction.
2076 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2077 * interp.c: Remove some debugging, provide more detailed error
2078 messages, update memory accesses to use LOADDRMASK.
2079
2080Mon Jun 3 11:55:03 1996 Ian Lance Taylor <[email protected]>
2081
2082 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2083 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2084 stamp-h.
2085 * configure: Rebuild.
2086 * config.in: New file, generated by autoheader.
2087 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2088 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2089 HAVE_ANINT and HAVE_AINT, as appropriate.
2090 * Makefile.in (run): Use @LIBS@ rather than -lm.
2091 (interp.o): Depend upon config.h.
2092 (Makefile): Just rebuild Makefile.
2093 (clean): Remove stamp-h.
2094 (mostlyclean): Make the same as clean, not as distclean.
2095 (config.h, stamp-h): New targets.
2096
2097Fri May 10 00:41:17 1996 James G. Smith <[email protected]>
2098
2099 * interp.c (ColdReset): Fix boolean test. Make all simulator
2100 globals static.
2101
2102Wed May 8 15:12:58 1996 James G. Smith <[email protected]>
2103
2104 * interp.c (xfer_direct_word, xfer_direct_long,
2105 swap_direct_word, swap_direct_long, xfer_big_word,
2106 xfer_big_long, xfer_little_word, xfer_little_long,
2107 swap_word,swap_long): Added.
2108 * interp.c (ColdReset): Provide function indirection to
2109 host<->simulated_target transfer routines.
2110 * interp.c (sim_store_register, sim_fetch_register): Updated to
2111 make use of indirected transfer routines.
2112
2113Fri Apr 19 15:48:24 1996 James G. Smith <[email protected]>
2114
2115 * gencode.c (process_instructions): Ensure FP ABS instruction
2116 recognised.
2117 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2118 system call support.
2119
2120Wed Apr 10 09:51:38 1996 James G. Smith <[email protected]>
2121
2122 * interp.c (sim_do_command): Complain if callback structure not
2123 initialised.
2124
2125Thu Mar 28 13:50:51 1996 James G. Smith <[email protected]>
2126
2127 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2128 support for Sun hosts.
2129 * Makefile.in (gencode): Ensure the host compiler and libraries
2130 used for cross-hosted build.
2131
2132Wed Mar 27 14:42:12 1996 James G. Smith <[email protected]>
2133
2134 * interp.c, gencode.c: Some more (TODO) tidying.
2135
2136Thu Mar 7 11:19:33 1996 James G. Smith <[email protected]>
2137
2138 * gencode.c, interp.c: Replaced explicit long long references with
2139 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2140 * support.h (SET64LO, SET64HI): Macros added.
2141
2142Wed Feb 21 12:16:21 1996 Ian Lance Taylor <[email protected]>
2143
2144 * configure: Regenerate with autoconf 2.7.
2145
2146Tue Jan 30 08:48:18 1996 Fred Fish <[email protected]>
2147
2148 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2149 * support.h: Remove superfluous "1" from #if.
2150 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2151
2152Mon Dec 4 11:44:40 1995 Jamie Smith <[email protected]>
2153
2154 * interp.c (StoreFPR): Control UndefinedResult() call on
2155 WARN_RESULT manifest.
2156
2157Fri Dec 1 16:37:19 1995 James G. Smith <[email protected]>
2158
2159 * gencode.c: Tidied instruction decoding, and added FP instruction
2160 support.
2161
2162 * interp.c: Added dineroIII, and BSD profiling support. Also
2163 run-time FP handling.
2164
2165Sun Oct 22 00:57:18 1995 James G. Smith <[email protected]>
2166
2167 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2168 gencode.c, interp.c, support.h: created.
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