[binutils.git] / sim / m68hc11 / interp.c

/* interp.c -- Simulator for Motorola 68HC11/68HC12
   Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   Written by Stephane Carrez ([email protected])

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "sim-main.h"
#include "sim-assert.h"
#include "sim-hw.h"
#include "sim-options.h"
#include "hw-tree.h"
#include "hw-device.h"
#include "hw-ports.h"

#ifndef MONITOR_BASE
# define MONITOR_BASE (0x0C000)
# define MONITOR_SIZE (0x04000)
#endif

static void sim_get_info (SIM_DESC sd, char *cmd);


char *interrupt_names[] = {
  "reset",
  "nmi",
  "int",
  NULL
};

#ifndef INLINE
#if defined(__GNUC__) && defined(__OPTIMIZE__)
#define INLINE __inline__
#else
#define INLINE
#endif
#endif

struct sim_info_list
{
  const char *name;
  const char *device;
};

struct sim_info_list dev_list_68hc11[] = {
  {"cpu", "/m68hc11"},
  {"timer", "/m68hc11/m68hc11tim"},
  {"sio", "/m68hc11/m68hc11sio"},
  {"spi", "/m68hc11/m68hc11spi"},
  {"eeprom", "/m68hc11/m68hc11eepr"},
  {0, 0}
};

struct sim_info_list dev_list_68hc12[] = {
  {"cpu", "/m68hc12"},
  {"timer", "/m68hc12/m68hc12tim"},
  {"sio", "/m68hc12/m68hc12sio"},
  {"spi", "/m68hc12/m68hc12spi"},
  {"eeprom", "/m68hc12/m68hc12eepr"},
  {0, 0}
};

/* Cover function of sim_state_free to free the cpu buffers as well.  */

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);

  sim_state_free (sd);
}

/* Give some information about the simulator.  */
static void
sim_get_info (SIM_DESC sd, char *cmd)
{
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);
  if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
    {
      int i;
      struct hw *hw_dev;
      struct sim_info_list *dev_list;
      const struct bfd_arch_info *arch;

      arch = STATE_ARCHITECTURE (sd);
      cmd++;

      if (arch->arch == bfd_arch_m68hc11)
        dev_list = dev_list_68hc11;
      else
        dev_list = dev_list_68hc12;

      for (i = 0; dev_list[i].name; i++)
	if (strcmp (cmd, dev_list[i].name) == 0)
	  break;

      if (dev_list[i].name == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	  sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	  return;
	}
      hw_dev = sim_hw_parse (sd, dev_list[i].device);
      if (hw_dev == 0)
	{
	  sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	  return;
	}
      hw_ioctl (hw_dev, 23, 0);
      return;
    }

  cpu_info (sd, cpu);
  interrupts_info (sd, &cpu->cpu_interrupts);
}


void
sim_board_reset (SIM_DESC sd)
{
  struct hw *hw_cpu;
  sim_cpu *cpu;
  const struct bfd_arch_info *arch;
  const char *cpu_type;

  cpu = STATE_CPU (sd, 0);
  arch = STATE_ARCHITECTURE (sd);

  /*  hw_cpu = sim_hw_parse (sd, "/"); */
  if (arch->arch == bfd_arch_m68hc11)
    {
      cpu->cpu_type = CPU_M6811;
      cpu_type = "/m68hc11";
    }
  else
    {
      cpu->cpu_type = CPU_M6812;
      cpu_type = "/m68hc12";
    }
  
  hw_cpu = sim_hw_parse (sd, cpu_type);
  if (hw_cpu == 0)
    {
      sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
      return;
    }

  cpu_reset (cpu);
  hw_port_event (hw_cpu, 3, 0);
  cpu_restart (cpu);
}

int
sim_hw_configure (SIM_DESC sd)
{
  const struct bfd_arch_info *arch;
  struct hw *device_tree;
  sim_cpu *cpu;
  
  arch = STATE_ARCHITECTURE (sd);
  if (arch == 0)
    return 0;

  cpu = STATE_CPU (sd, 0);
  cpu->cpu_configured_arch = arch;
  device_tree = sim_hw_parse (sd, "/");
  if (arch->arch == bfd_arch_m68hc11)
    {
      cpu->cpu_interpretor = cpu_interp_m6811;
      if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	{
	  /* Allocate core managed memory */

	  /* the monitor  */
	  sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
			   /* MONITOR_BASE, MONITOR_SIZE */
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);
	  sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
	}

      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	  sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
          sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	  sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	  sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	  /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
	}
      if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	  sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	}
      sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
      sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
      cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
    }
  else
    {
      cpu->cpu_interpretor = cpu_interp_m6812;
      if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	{
	  /* Allocate core external memory.  */
	  sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
			   0x8000, M6811_RAM_LEVEL, 0x8000);
	  sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
			   M6811_RAM_LEVEL);

	  sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	}

      if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	  sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	{
	  /* M68hc11 Timer configuration. */
	  sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
          sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
	}

      /* Create the SPI device.  */
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	{
	  /* M68hc11 persistent ram configuration. */
	  sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	  sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	  sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	}
      if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	{
	  sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	  sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	}

      sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
      sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
      cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
    }
  return 0;
}

static int
sim_prepare_for_program (SIM_DESC sd, struct _bfd* abfd)
{
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);

  sim_hw_configure (sd);
  if (abfd != NULL)
    {
      cpu->cpu_elf_start = bfd_get_start_address (abfd);
    }

  /* reset all state information */
  sim_board_reset (sd);

  return SIM_RC_OK;
}

SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
          struct _bfd *abfd, char **argv)
{
  SIM_DESC sd;
  sim_cpu *cpu;

  sd = sim_state_alloc (kind, callback);
  cpu = STATE_CPU (sd, 0);

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* for compatibility */
  current_alignment = NONSTRICT_ALIGNMENT;
  current_target_byte_order = BIG_ENDIAN;

  cpu_initialize (sd, cpu);

  cpu->cpu_use_elf_start = 1;
  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* getopt will print the error message so we just have to exit if this fails.
     FIXME: Hmmm...  in the case of gdb we need getopt to call
     print_filtered.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }

  /* Check for/establish the a reference program image.  */
  if (sim_analyze_program (sd,
			   (STATE_PROG_ARGV (sd) != NULL
			    ? *STATE_PROG_ARGV (sd)
			    : NULL), abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Establish any remaining configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      /* Uninstall the modules to avoid memory leaks,
         file descriptor leaks, etc.  */
      free_state (sd);
      return 0;
    }

  sim_hw_configure (sd);

  /* Fudge our descriptor.  */
  return sd;
}


void
sim_close (SIM_DESC sd, int quitting)
{
  /* shut down modules */
  sim_module_uninstall (sd);

  /* Ensure that any resources allocated through the callback
     mechanism are released: */
  sim_io_shutdown (sd);

  /* FIXME - free SD */
  sim_state_free (sd);
  return;
}

void
sim_set_profile (int n)
{
}

void
sim_set_profile_size (int n)
{
}

/* Generic implementation of sim_engine_run that works within the
   sim_engine setjmp/longjmp framework. */

void
sim_engine_run (SIM_DESC sd,
                int next_cpu_nr,	/* ignore */
		int nr_cpus,	/* ignore */
		int siggnal)	/* ignore */
{
  sim_cpu *cpu;

  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  cpu = STATE_CPU (sd, 0);
  while (1)
    {
      cpu_single_step (cpu);

      /* process any events */
      if (sim_events_tickn (sd, cpu->cpu_current_cycle))
	{
	  sim_events_process (sd);
	}
    }
}

int
sim_trace (SIM_DESC sd)
{
  sim_resume (sd, 0, 0);
  return 1;
}

void
sim_info (SIM_DESC sd, int verbose)
{
  const char *cpu_type;
  const struct bfd_arch_info *arch;

  /* Nothing to do if there is no verbose flag set.  */
  if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
    return;

  arch = STATE_ARCHITECTURE (sd);
  if (arch->arch == bfd_arch_m68hc11)
    cpu_type = "68HC11";
  else
    cpu_type = "68HC12";

  sim_io_eprintf (sd, "Simulator info:\n");
  sim_io_eprintf (sd, "  CPU Motorola %s\n", cpu_type);
  sim_get_info (sd, 0);
  sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
}

SIM_RC
sim_create_inferior (SIM_DESC sd, struct _bfd *abfd,
                     char **argv, char **env)
{
  return sim_prepare_for_program (sd, abfd);
}


void
sim_set_callbacks (host_callback *p)
{
  /*  m6811_callback = p; */
}


int
sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
{
  sim_cpu *cpu;
  uint16 val;
  int size = 2;

  cpu = STATE_CPU (sd, 0);
  switch (rn)
    {
    case A_REGNUM:
      val = cpu_get_a (cpu);
      size = 1;
      break;

    case B_REGNUM:
      val = cpu_get_b (cpu);
      size = 1;
      break;

    case D_REGNUM:
      val = cpu_get_d (cpu);
      break;

    case X_REGNUM:
      val = cpu_get_x (cpu);
      break;

    case Y_REGNUM:
      val = cpu_get_y (cpu);
      break;

    case SP_REGNUM:
      val = cpu_get_sp (cpu);
      break;

    case PC_REGNUM:
      val = cpu_get_pc (cpu);
      break;

    case PSW_REGNUM:
      val = cpu_get_ccr (cpu);
      size = 1;
      break;

    case PAGE_REGNUM:
      val = cpu_get_page (cpu);
      size = 1;
      break;

    default:
      val = 0;
      break;
    }
  memory[0] = val >> 8;
  memory[1] = val & 0x0FF;
  return size;
}

int
sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
{
  uint16 val;
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);

  val = *memory++;
  if (length == 2)
    val = (val << 8) | *memory;

  switch (rn)
    {
    case D_REGNUM:
      cpu_set_d (cpu, val);
      break;

    case A_REGNUM:
      cpu_set_a (cpu, val);
      return 1;

    case B_REGNUM:
      cpu_set_b (cpu, val);
      return 1;

    case X_REGNUM:
      cpu_set_x (cpu, val);
      break;

    case Y_REGNUM:
      cpu_set_y (cpu, val);
      break;

    case SP_REGNUM:
      cpu_set_sp (cpu, val);
      break;

    case PC_REGNUM:
      cpu_set_pc (cpu, val);
      break;

    case PSW_REGNUM:
      cpu_set_ccr (cpu, val);
      return 1;

    case PAGE_REGNUM:
      cpu_set_page (cpu, val);
      return 1;

    default:
      break;
    }

  return 2;
}

void
sim_size (int s)
{
  ;
}

void
sim_do_command (SIM_DESC sd, char *cmd)
{
  char *mm_cmd = "memory-map";
  char *int_cmd = "interrupt";
  sim_cpu *cpu;

  cpu = STATE_CPU (sd, 0);
  /* Commands available from GDB:   */
  if (sim_args_command (sd, cmd) != SIM_RC_OK)
    {
      if (strncmp (cmd, "info", sizeof ("info") - 1) == 0)
	sim_get_info (sd, &cmd[4]);
      else if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
	sim_io_eprintf (sd,
			"`memory-map' command replaced by `sim memory'\n");
      else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
	sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
      else
	sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
    }

  /* If the architecture changed, re-configure.  */
  if (STATE_ARCHITECTURE (sd) != cpu->cpu_configured_arch)
    sim_hw_configure (sd);
}

/* Halt the simulator after just one instruction */

static void
has_stepped (SIM_DESC sd,
	     void *data)
{
  ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
  sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP);
}


/* Generic resume - assumes the existance of sim_engine_run */

void
sim_resume (SIM_DESC sd,
	    int step,
	    int siggnal)
{
  sim_engine *engine = STATE_ENGINE (sd);
  jmp_buf buf;
  int jmpval;

  ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

  /* we only want to be single stepping the simulator once */
  if (engine->stepper != NULL)
    {
      sim_events_deschedule (sd, engine->stepper);
      engine->stepper = NULL;
    }
  sim_module_resume (sd);

  /* run/resume the simulator */
  engine->jmpbuf = &buf;
  jmpval = setjmp (buf);
  if (jmpval == sim_engine_start_jmpval
      || jmpval == sim_engine_restart_jmpval)
    {
      int last_cpu_nr = sim_engine_last_cpu_nr (sd);
      int next_cpu_nr = sim_engine_next_cpu_nr (sd);
      int nr_cpus = sim_engine_nr_cpus (sd);

      sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus);
      if (next_cpu_nr >= nr_cpus)
	next_cpu_nr = 0;

      /* Only deliver the siggnal ]sic] the first time through - don't
         re-deliver any siggnal during a restart. */
      if (jmpval == sim_engine_restart_jmpval)
	siggnal = 0;

      /* Install the stepping event after having processed some
         pending events.  This is necessary for HC11/HC12 simulator
         because the tick counter is incremented by the number of cycles
         the instruction took.  Some pending ticks to process can still
         be recorded internally by the simulator and sim_events_preprocess
         will handle them.  If the stepping event is inserted before,
         these pending ticks will raise the event and the simulator will
         stop without having executed any instruction.  */
      if (step)
        engine->stepper = sim_events_schedule (sd, 0, has_stepped, sd);

#ifdef SIM_CPU_EXCEPTION_RESUME
      {
	sim_cpu* cpu = STATE_CPU (sd, next_cpu_nr);
	SIM_CPU_EXCEPTION_RESUME(sd, cpu, siggnal);
      }
#endif

      sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal);
    }
  engine->jmpbuf = NULL;

  sim_module_suspend (sd);
}
Commit	Line	Data
5abb9efa SC	1	/* interp.c -- Simulator for Motorola 68HC11/68HC12
5abb9efa SC	2	Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez ([email protected])
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#include "sim-main.h"
	22	#include "sim-assert.h"
	23	#include "sim-hw.h"
	24	#include "sim-options.h"
	25	#include "hw-tree.h"
	26	#include "hw-device.h"
	27	#include "hw-ports.h"
	28
	29	#ifndef MONITOR_BASE
	30	# define MONITOR_BASE (0x0C000)
	31	# define MONITOR_SIZE (0x04000)
	32	#endif
	33
	34	static void sim_get_info (SIM_DESC sd, char *cmd);
	35
	36
	37	char *interrupt_names[] = {
	38	"reset",
	39	"nmi",
	40	"int",
	41	NULL
	42	};
	43
	44	#ifndef INLINE
	45	#if defined(__GNUC__) && defined(__OPTIMIZE__)
	46	#define INLINE __inline__
	47	#else
	48	#define INLINE
	49	#endif
	50	#endif
	51
	52	struct sim_info_list
	53	{
	54	const char *name;
	55	const char *device;
	56	};
	57
81e09ed8	58	struct sim_info_list dev_list_68hc11[] = {
e0709f50 AC	59	{"cpu", "/m68hc11"},
	60	{"timer", "/m68hc11/m68hc11tim"},
	61	{"sio", "/m68hc11/m68hc11sio"},
	62	{"spi", "/m68hc11/m68hc11spi"},
	63	{"eeprom", "/m68hc11/m68hc11eepr"},
	64	{0, 0}
	65	};
	66
81e09ed8 SC	67	struct sim_info_list dev_list_68hc12[] = {
	68	{"cpu", "/m68hc12"},
	69	{"timer", "/m68hc12/m68hc12tim"},
	70	{"sio", "/m68hc12/m68hc12sio"},
	71	{"spi", "/m68hc12/m68hc12spi"},
	72	{"eeprom", "/m68hc12/m68hc12eepr"},
	73	{0, 0}
	74	};
	75
	76	/* Cover function of sim_state_free to free the cpu buffers as well. */
	77
	78	static void
	79	free_state (SIM_DESC sd)
	80	{
	81	if (STATE_MODULES (sd) != NULL)
	82	sim_module_uninstall (sd);
	83
	84	sim_state_free (sd);
	85	}
	86
e0709f50 AC	87	/* Give some information about the simulator. */
	88	static void
	89	sim_get_info (SIM_DESC sd, char *cmd)
	90	{
	91	sim_cpu *cpu;
	92
81e09ed8	93	cpu = STATE_CPU (sd, 0);
e0709f50 AC	94	if (cmd != 0 && (cmd[0] == ' ' \|\| cmd[0] == '-'))
	95	{
	96	int i;
	97	struct hw *hw_dev;
81e09ed8 SC	98	struct sim_info_list *dev_list;
	99	const struct bfd_arch_info *arch;
	100
	101	arch = STATE_ARCHITECTURE (sd);
e0709f50 AC	102	cmd++;
e0709f50 AC	103
81e09ed8 SC	104	if (arch->arch == bfd_arch_m68hc11)
	105	dev_list = dev_list_68hc11;
	106	else
	107	dev_list = dev_list_68hc12;
	108
e0709f50 AC	109	for (i = 0; dev_list[i].name; i++)
	110	if (strcmp (cmd, dev_list[i].name) == 0)
	111	break;
	112
	113	if (dev_list[i].name == 0)
	114	{
	115	sim_io_eprintf (sd, "Device '%s' not found.\n", cmd);
	116	sim_io_eprintf (sd, "Valid devices: cpu timer sio eeprom\n");
	117	return;
	118	}
	119	hw_dev = sim_hw_parse (sd, dev_list[i].device);
	120	if (hw_dev == 0)
	121	{
	122	sim_io_eprintf (sd, "Device '%s' not found\n", dev_list[i].device);
	123	return;
	124	}
	125	hw_ioctl (hw_dev, 23, 0);
	126	return;
	127	}
	128
e0709f50 AC	129	cpu_info (sd, cpu);
	130	interrupts_info (sd, &cpu->cpu_interrupts);
	131	}
	132
	133
	134	void
	135	sim_board_reset (SIM_DESC sd)
	136	{
	137	struct hw *hw_cpu;
	138	sim_cpu *cpu;
81e09ed8 SC	139	const struct bfd_arch_info *arch;
81e09ed8 SC	140	const char *cpu_type;
e0709f50 AC	141
e0709f50 AC	142	cpu = STATE_CPU (sd, 0);
81e09ed8 SC	143	arch = STATE_ARCHITECTURE (sd);
81e09ed8 SC	144
e0709f50	145	/* hw_cpu = sim_hw_parse (sd, "/"); */
81e09ed8 SC	146	if (arch->arch == bfd_arch_m68hc11)
	147	{
	148	cpu->cpu_type = CPU_M6811;
	149	cpu_type = "/m68hc11";
	150	}
	151	else
	152	{
	153	cpu->cpu_type = CPU_M6812;
	154	cpu_type = "/m68hc12";
	155	}
	156
	157	hw_cpu = sim_hw_parse (sd, cpu_type);
e0709f50 AC	158	if (hw_cpu == 0)
e0709f50 AC	159	{
81e09ed8	160	sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
e0709f50 AC	161	return;
	162	}
	163
	164	cpu_reset (cpu);
	165	hw_port_event (hw_cpu, 3, 0);
	166	cpu_restart (cpu);
	167	}
	168
81e09ed8 SC	169	int
	170	sim_hw_configure (SIM_DESC sd)
	171	{
	172	const struct bfd_arch_info *arch;
	173	struct hw *device_tree;
81e09ed8 SC	174	sim_cpu *cpu;
	175
	176	arch = STATE_ARCHITECTURE (sd);
	177	if (arch == 0)
	178	return 0;
	179
	180	cpu = STATE_CPU (sd, 0);
	181	cpu->cpu_configured_arch = arch;
	182	device_tree = sim_hw_parse (sd, "/");
	183	if (arch->arch == bfd_arch_m68hc11)
	184	{
	185	cpu->cpu_interpretor = cpu_interp_m6811;
	186	if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
	187	{
	188	/* Allocate core managed memory */
	189
	190	/* the monitor */
	191	sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
	192	/* MONITOR_BASE, MONITOR_SIZE */
	193	0x8000, M6811_RAM_LEVEL, 0x8000);
	194	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
	195	M6811_RAM_LEVEL);
	196	sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
	197	}
	198
	199	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
	200	{
	201	sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
	202	sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
	203	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
	204	}
	205	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
	206	{
	207	/* M68hc11 Timer configuration. */
	208	sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
	209	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
827ec39a	210	sim_hw_parse (sd, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
81e09ed8 SC	211	}
	212
	213	/* Create the SPI device. */
	214	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
	215	{
	216	sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
	217	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
	218	}
	219	if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
	220	{
	221	/* M68hc11 persistent ram configuration. */
	222	sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
	223	sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
	224	sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
	225	/sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); /
	226	}
	227	if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
	228	{
	229	sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
	230	sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
	231	}
dcceded2 SC	232	sim_hw_parse (sd, "/m68hc11 > port-a cpu-write-port /m68hc11");
	233	sim_hw_parse (sd, "/m68hc11 > port-b cpu-write-port /m68hc11");
	234	sim_hw_parse (sd, "/m68hc11 > port-c cpu-write-port /m68hc11");
	235	sim_hw_parse (sd, "/m68hc11 > port-d cpu-write-port /m68hc11");
827ec39a	236	cpu->hw_cpu = sim_hw_parse (sd, "/m68hc11");
81e09ed8 SC	237	}
	238	else
	239	{
	240	cpu->cpu_interpretor = cpu_interp_m6812;
	241	if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
	242	{
	243	/* Allocate core external memory. */
	244	sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
	245	0x8000, M6811_RAM_LEVEL, 0x8000);
	246	sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
	247	M6811_RAM_LEVEL);
	248
	249	sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
	250	}
	251
	252	if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
	253	{
	254	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
	255	sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
	256	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
	257	}
81e09ed8 SC	258	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
	259	{
	260	/* M68hc11 Timer configuration. */
	261	sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
	262	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
dcceded2	263	sim_hw_parse (sd, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
81e09ed8 SC	264	}
	265
	266	/* Create the SPI device. */
	267	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
	268	{
	269	sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
	270	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
	271	}
	272	if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
	273	{
	274	/* M68hc11 persistent ram configuration. */
	275	sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
	276	sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
	277	sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
	278	}
	279	if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
	280	{
	281	sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
	282	sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
	283	}
827ec39a	284
dcceded2 SC	285	sim_hw_parse (sd, "/m68hc12 > port-a cpu-write-port /m68hc12");
	286	sim_hw_parse (sd, "/m68hc12 > port-b cpu-write-port /m68hc12");
	287	sim_hw_parse (sd, "/m68hc12 > port-c cpu-write-port /m68hc12");
	288	sim_hw_parse (sd, "/m68hc12 > port-d cpu-write-port /m68hc12");
827ec39a	289	cpu->hw_cpu = sim_hw_parse (sd, "/m68hc12");
81e09ed8 SC	290	}
	291	return 0;
	292	}
	293
	294	static int
	295	sim_prepare_for_program (SIM_DESC sd, struct _bfd* abfd)
	296	{
	297	sim_cpu *cpu;
	298
	299	cpu = STATE_CPU (sd, 0);
	300
	301	sim_hw_configure (sd);
	302	if (abfd != NULL)
	303	{
	304	cpu->cpu_elf_start = bfd_get_start_address (abfd);
	305	}
	306
	307	/* reset all state information */
	308	sim_board_reset (sd);
	309
	310	return SIM_RC_OK;
	311	}
	312
e0709f50 AC	313	SIM_DESC
	314	sim_open (SIM_OPEN_KIND kind, host_callback *callback,
	315	struct _bfd abfd, char *argv)
	316	{
e0709f50 AC	317	SIM_DESC sd;
e0709f50 AC	318	sim_cpu *cpu;
e0709f50 AC	319
	320	sd = sim_state_alloc (kind, callback);
	321	cpu = STATE_CPU (sd, 0);
	322
	323	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	324
	325	/* for compatibility */
	326	current_alignment = NONSTRICT_ALIGNMENT;
	327	current_target_byte_order = BIG_ENDIAN;
	328
	329	cpu_initialize (sd, cpu);
	330
	331	cpu->cpu_use_elf_start = 1;
	332	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
81e09ed8 SC	333	{
	334	free_state (sd);
	335	return 0;
	336	}
e0709f50 AC	337
	338	/* getopt will print the error message so we just have to exit if this fails.
	339	FIXME: Hmmm... in the case of gdb we need getopt to call
	340	print_filtered. */
	341	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	342	{
	343	/* Uninstall the modules to avoid memory leaks,
	344	file descriptor leaks, etc. */
81e09ed8	345	free_state (sd);
e0709f50 AC	346	return 0;
	347	}
	348
e0709f50 AC	349	/* Check for/establish the a reference program image. */
	350	if (sim_analyze_program (sd,
	351	(STATE_PROG_ARGV (sd) != NULL
	352	? *STATE_PROG_ARGV (sd)
	353	: NULL), abfd) != SIM_RC_OK)
	354	{
81e09ed8	355	free_state (sd);
e0709f50 AC	356	return 0;
	357	}
	358
	359	/* Establish any remaining configuration options. */
	360	if (sim_config (sd) != SIM_RC_OK)
	361	{
81e09ed8	362	free_state (sd);
e0709f50 AC	363	return 0;
	364	}
	365
	366	if (sim_post_argv_init (sd) != SIM_RC_OK)
	367	{
	368	/* Uninstall the modules to avoid memory leaks,
	369	file descriptor leaks, etc. */
81e09ed8	370	free_state (sd);
e0709f50 AC	371	return 0;
	372	}
	373
81e09ed8	374	sim_hw_configure (sd);
e0709f50 AC	375
	376	/* Fudge our descriptor. */
	377	return sd;
	378	}
	379
	380
	381	void
	382	sim_close (SIM_DESC sd, int quitting)
	383	{
	384	/* shut down modules */
	385	sim_module_uninstall (sd);
	386
	387	/* Ensure that any resources allocated through the callback
	388	mechanism are released: */
	389	sim_io_shutdown (sd);
	390
	391	/* FIXME - free SD */
81e09ed8	392	sim_state_free (sd);
e0709f50 AC	393	return;
	394	}
	395
	396	void
	397	sim_set_profile (int n)
	398	{
	399	}
	400
	401	void
	402	sim_set_profile_size (int n)
	403	{
	404	}
	405
	406	/* Generic implementation of sim_engine_run that works within the
	407	sim_engine setjmp/longjmp framework. */
	408
	409	void
	410	sim_engine_run (SIM_DESC sd,
	411	int next_cpu_nr, /* ignore */
	412	int nr_cpus, /* ignore */
	413	int siggnal) /* ignore */
	414	{
	415	sim_cpu *cpu;
	416
	417	SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	418	cpu = STATE_CPU (sd, 0);
	419	while (1)
	420	{
	421	cpu_single_step (cpu);
	422
	423	/* process any events */
	424	if (sim_events_tickn (sd, cpu->cpu_current_cycle))
	425	{
	426	sim_events_process (sd);
	427	}
	428	}
	429	}
	430
	431	int
	432	sim_trace (SIM_DESC sd)
	433	{
	434	sim_resume (sd, 0, 0);
	435	return 1;
	436	}
	437
	438	void
	439	sim_info (SIM_DESC sd, int verbose)
	440	{
81e09ed8 SC	441	const char *cpu_type;
	442	const struct bfd_arch_info *arch;
	443
00d0c012 SC	444	/* Nothing to do if there is no verbose flag set. */
	445	if (verbose == 0 && STATE_VERBOSE_P (sd) == 0)
	446	return;
	447
81e09ed8 SC	448	arch = STATE_ARCHITECTURE (sd);
	449	if (arch->arch == bfd_arch_m68hc11)
	450	cpu_type = "68HC11";
	451	else
	452	cpu_type = "68HC12";
	453
e0709f50	454	sim_io_eprintf (sd, "Simulator info:\n");
81e09ed8	455	sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
e0709f50 AC	456	sim_get_info (sd, 0);
	457	sim_module_info (sd, verbose \|\| STATE_VERBOSE_P (sd));
	458	}
	459
	460	SIM_RC
	461	sim_create_inferior (SIM_DESC sd, struct _bfd *abfd,
	462	char argv, char env)
	463	{
81e09ed8	464	return sim_prepare_for_program (sd, abfd);
e0709f50 AC	465	}
	466
	467
	468	void
	469	sim_set_callbacks (host_callback *p)
	470	{
	471	/* m6811_callback = p; */
	472	}
	473
	474
	475	int
	476	sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
	477	{
	478	sim_cpu *cpu;
	479	uint16 val;
63f36def	480	int size = 2;
e0709f50 AC	481
	482	cpu = STATE_CPU (sd, 0);
	483	switch (rn)
	484	{
	485	case A_REGNUM:
	486	val = cpu_get_a (cpu);
63f36def	487	size = 1;
e0709f50 AC	488	break;
	489
	490	case B_REGNUM:
	491	val = cpu_get_b (cpu);
63f36def	492	size = 1;
e0709f50 AC	493	break;
	494
	495	case D_REGNUM:
	496	val = cpu_get_d (cpu);
	497	break;
	498
	499	case X_REGNUM:
	500	val = cpu_get_x (cpu);
	501	break;
	502
	503	case Y_REGNUM:
	504	val = cpu_get_y (cpu);
	505	break;
	506
	507	case SP_REGNUM:
	508	val = cpu_get_sp (cpu);
	509	break;
	510
	511	case PC_REGNUM:
	512	val = cpu_get_pc (cpu);
	513	break;
	514
	515	case PSW_REGNUM:
	516	val = cpu_get_ccr (cpu);
63f36def SC	517	size = 1;
	518	break;
	519
	520	case PAGE_REGNUM:
	521	val = cpu_get_page (cpu);
	522	size = 1;
e0709f50 AC	523	break;
e0709f50 AC	524
e0709f50	525	default:
9830501b	526	val = 0;
e0709f50 AC	527	break;
	528	}
	529	memory[0] = val >> 8;
	530	memory[1] = val & 0x0FF;
63f36def	531	return size;
e0709f50 AC	532	}
	533
	534	int
	535	sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
	536	{
	537	uint16 val;
	538	sim_cpu *cpu;
	539
	540	cpu = STATE_CPU (sd, 0);
	541
	542	val = *memory++;
	543	if (length == 2)
	544	val = (val << 8) \| *memory;
	545
	546	switch (rn)
	547	{
	548	case D_REGNUM:
	549	cpu_set_d (cpu, val);
	550	break;
	551
	552	case A_REGNUM:
	553	cpu_set_a (cpu, val);
63f36def	554	return 1;
e0709f50 AC	555
	556	case B_REGNUM:
	557	cpu_set_b (cpu, val);
63f36def	558	return 1;
e0709f50 AC	559
	560	case X_REGNUM:
	561	cpu_set_x (cpu, val);
	562	break;
	563
	564	case Y_REGNUM:
	565	cpu_set_y (cpu, val);
	566	break;
	567
	568	case SP_REGNUM:
	569	cpu_set_sp (cpu, val);
	570	break;
	571
	572	case PC_REGNUM:
	573	cpu_set_pc (cpu, val);
	574	break;
	575
	576	case PSW_REGNUM:
	577	cpu_set_ccr (cpu, val);
63f36def SC	578	return 1;
	579
	580	case PAGE_REGNUM:
	581	cpu_set_page (cpu, val);
	582	return 1;
e0709f50	583
e0709f50	584	default:
e0709f50 AC	585	break;
	586	}
	587
	588	return 2;
	589	}
	590
	591	void
	592	sim_size (int s)
	593	{
	594	;
	595	}
	596
	597	void
	598	sim_do_command (SIM_DESC sd, char *cmd)
	599	{
	600	char *mm_cmd = "memory-map";
	601	char *int_cmd = "interrupt";
81e09ed8	602	sim_cpu *cpu;
e0709f50	603
81e09ed8	604	cpu = STATE_CPU (sd, 0);
e0709f50 AC	605	/* Commands available from GDB: */
	606	if (sim_args_command (sd, cmd) != SIM_RC_OK)
	607	{
	608	if (strncmp (cmd, "info", sizeof ("info") - 1) == 0)
	609	sim_get_info (sd, &cmd[4]);
e0709f50 AC	610	else if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
	611	sim_io_eprintf (sd,
	612	"`memory-map' command replaced by `sim memory'\n");
	613	else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
	614	sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
	615	else
	616	sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
	617	}
81e09ed8 SC	618
	619	/* If the architecture changed, re-configure. */
	620	if (STATE_ARCHITECTURE (sd) != cpu->cpu_configured_arch)
	621	sim_hw_configure (sd);
e0709f50	622	}
00d0c012 SC	623
	624	/* Halt the simulator after just one instruction */
	625
	626	static void
	627	has_stepped (SIM_DESC sd,
	628	void *data)
	629	{
	630	ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	631	sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP);
	632	}
	633
	634
	635	/* Generic resume - assumes the existance of sim_engine_run */
	636
	637	void
	638	sim_resume (SIM_DESC sd,
	639	int step,
	640	int siggnal)
	641	{
	642	sim_engine *engine = STATE_ENGINE (sd);
	643	jmp_buf buf;
	644	int jmpval;
	645
	646	ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
	647
	648	/* we only want to be single stepping the simulator once */
	649	if (engine->stepper != NULL)
	650	{
	651	sim_events_deschedule (sd, engine->stepper);
	652	engine->stepper = NULL;
	653	}
	654	sim_module_resume (sd);
	655
	656	/* run/resume the simulator */
	657	engine->jmpbuf = &buf;
	658	jmpval = setjmp (buf);
	659	if (jmpval == sim_engine_start_jmpval
	660	\|\| jmpval == sim_engine_restart_jmpval)
	661	{
	662	int last_cpu_nr = sim_engine_last_cpu_nr (sd);
	663	int next_cpu_nr = sim_engine_next_cpu_nr (sd);
	664	int nr_cpus = sim_engine_nr_cpus (sd);
	665
	666	sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus);
	667	if (next_cpu_nr >= nr_cpus)
	668	next_cpu_nr = 0;
	669
	670	/* Only deliver the siggnal ]sic] the first time through - don't
	671	re-deliver any siggnal during a restart. */
	672	if (jmpval == sim_engine_restart_jmpval)
	673	siggnal = 0;
	674
	675	/* Install the stepping event after having processed some
	676	pending events. This is necessary for HC11/HC12 simulator
	677	because the tick counter is incremented by the number of cycles
	678	the instruction took. Some pending ticks to process can still
	679	be recorded internally by the simulator and sim_events_preprocess
	680	will handle them. If the stepping event is inserted before,
	681	these pending ticks will raise the event and the simulator will
	682	stop without having executed any instruction. */
	683	if (step)
	684	engine->stepper = sim_events_schedule (sd, 0, has_stepped, sd);
	685
	686	#ifdef SIM_CPU_EXCEPTION_RESUME
687	{
688	sim_cpu* cpu = STATE_CPU (sd, next_cpu_nr);
689	SIM_CPU_EXCEPTION_RESUME(sd, cpu, siggnal);
690	}
691	#endif
692
693	sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal);
694	}
695	engine->jmpbuf = NULL;
696
697	sim_module_suspend (sd);
698	}