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Update copyright notices to add year 2010.
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8b082fb1
TS		 1// -*- C -*-
2
3// Simulator definition for the MIPS DSP REV 2 ASE.
dc3cf14f 4// Copyright (C) 2007, 2010 Free Software Foundation, Inc.
8bf3ddc8
TS		 5// Contributed by MIPS Technologies, Inc.
6// Written by Chao-ying Fu ([email protected]).
8b082fb1
TS		 7//
8// This file is part of GDB, the GNU debugger.
9//
10// This program is free software; you can redistribute it and/or modify
11// it under the terms of the GNU General Public License as published by
4744ac1b
JB		 12// the Free Software Foundation; either version 3 of the License, or
13// (at your option) any later version.
8b082fb1
TS		 14//
15// This program is distributed in the hope that it will be useful,
16// but WITHOUT ANY WARRANTY; without even the implied warranty of
17// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18// GNU General Public License for more details.
19//
20// You should have received a copy of the GNU General Public License
4744ac1b 21// along with this program. If not, see <http://www.gnu.org/licenses/>.
8b082fb1
TS		 22
23
24// op: 0 = ADD, 1 = SUB
25// sat: 0 = no saturation, 1 = saturation
26:function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat
27{
28 int i;
29 unsigned32 h0;
30 unsigned16 h1, h2;
31 unsigned32 v1 = GPR[rs];
32 unsigned32 v2 = GPR[rt];
33 unsigned32 result = 0;
34 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
35 {
36 h1 = (unsigned16)(v1 & 0xffff);
37 h2 = (unsigned16)(v2 & 0xffff);
38 if (op == 0) // ADD
39 h0 = (unsigned32)h1 + (unsigned32)h2;
40 else // SUB
41 h0 = (unsigned32)h1 - (unsigned32)h2;
42 if (op == 0 && (h0 > (unsigned32)0x0000ffff)) // ADD SAT
43 {
44 DSPCR |= DSPCR_OUFLAG4;
45 if (sat == 1)
46 h0 = 0xffff;
47 }
48 else if (op == 1 && h1 < h2) // SUB SAT
49 {
50 DSPCR |= DSPCR_OUFLAG4;
51 if (sat == 1)
52 h0 = 0x0;
53 }
54 result |= ((unsigned32)((unsigned16)h0) << i);
55 }
56 GPR[rd] = EXTEND32 (result);
57}
58
59// op: 0 = ADD, 1 = SUB
60// round: 0 = no rounding, 1 = rounding
61:function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round
62{
63 int i;
64 unsigned32 h0;
65 unsigned8 h1, h2;
66 unsigned32 v1 = GPR[rs];
67 unsigned32 v2 = GPR[rt];
68 unsigned32 result = 0;
69 for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
70 {
71 h1 = (unsigned8)(v1 & 0xff);
72 h2 = (unsigned8)(v2 & 0xff);
73 if (op == 0) // ADD
74 h0 = (unsigned32)h1 + (unsigned32)h2;
75 else // SUB
76 h0 = (unsigned32)h1 - (unsigned32)h2;
77 if (round == 1)
78 h0 = (h0 + 1) >> 1;
79 else
80 h0 = h0 >> 1;
81 result |= ((unsigned32)((unsigned8)h0) << i);
82 }
83 GPR[rd] = EXTEND32 (result);
84}
85
86// op: 0 = EQ, 1 = LT, 2 = LE
87:function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op
88{
89 int i, j;
90 unsigned32 v1 = GPR[rs];
91 unsigned32 v2 = GPR[rt];
92 unsigned8 h1, h2;
93 unsigned32 result = 0;
94 unsigned32 mask;
95 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
96 {
97 h1 = (unsigned8)(v1 & 0xff);
98 h2 = (unsigned8)(v2 & 0xff);
99 mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
100 DSPCR &= mask;
101 if (op == 0) // EQ
102 {
103 result |= ((h1 == h2) << j);
104 DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
105 }
106 else if (op == 1) // LT
107 {
108 result |= ((h1 < h2) << j);
109 DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
110 }
111 else // LE
112 {
113 result |= ((h1 <= h2) << j);
114 DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
115 }
116 }
117 GPR[rd] = EXTEND32 (result);
118}
119
120// op: 0 = DPA 1 = DPS
121:function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op
122{
123 int i;
124 unsigned32 v1 = GPR[rs];
125 unsigned32 v2 = GPR[rt];
126 signed16 h1, h2;
127 signed32 result;
128 unsigned32 lo = DSPLO(ac);
129 unsigned32 hi = DSPHI(ac);
130 signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
131 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
132 {
133 h1 = (signed16)(v1 & 0xffff);
134 h2 = (signed16)(v2 & 0xffff);
135 result = (signed32)h1 * (signed32)h2;
136 if (op == 0) // DPA
137 prod += (signed64)result;
138 else // DPS
139 prod -= (signed64)result;
140 }
141 DSPLO(ac) = EXTEND32 (prod);
142 DSPHI(ac) = EXTEND32 (prod >> 32);
143}
144
145// round: 0 = no rounding, 1 = rounding
146:function:::void:do_w_mulq:int rd, int rs, int rt, int round
147{
148 unsigned32 v1 = GPR[rs];
149 unsigned32 v2 = GPR[rt];
150 signed32 w1, w2;
151 signed64 prod;
152 unsigned32 result;
153 w1 = (signed32) v1;
154 w2 = (signed32 )v2;
155 if (w1 == (signed32) 0x80000000 && w2 == (signed32) 0x80000000)
156 {
157 DSPCR |= DSPCR_OUFLAG5;
158 prod = 0x7fffffff;
159 }
160 else
161 {
162 prod = ((signed64) w1 * (signed64) w2) << 1;
163 if (round == 1)
164 prod += 0x0000000080000000LL;
165 prod = prod >> 32;
166 }
167 result = (unsigned32) prod;
168 GPR[rd] = EXTEND32 (result);
169}
170
171// round: 0 = no rounding, 1 = rounding
172:function:::void:do_precr_sra:int rt, int rs, int sa, int round
173{
174 unsigned32 v1 = GPR[rt];
175 unsigned32 v2 = GPR[rs];
176 signed32 w1 = (signed32) v1;
177 signed32 w2 = (signed32) v2;
178 signed32 result;
179 if (sa != 0)
180 {
181 if (round == 1 && (w1 & (1 << (sa - 1))))
182 w1 = (w1 >> sa) + 1;
183 else
184 w1 = w1 >> sa;
185
186 if (round == 1 && (w2 & (1 << (sa - 1))))
187 w2 = (w2 >> sa) + 1;
188 else
189 w2 = w2 >> sa;
190 }
191 result = (w1 << 16) | (w2 & 0xffff);
192 GPR[rt] = EXTEND32 (result);
193}
194
195// round: 0 = no rounding, 1 = rounding
196:function:::void:do_qb_shra:int rd, int rt, int shift, int round
197{
198 int i, j;
199 signed8 q0;
200 unsigned32 v1 = GPR[rt];
201 unsigned32 result = 0;
202 for (i = 0; i < 32; i += 8, v1 >>= 8)
203 {
204 q0 = (signed8)(v1 & 0xff);
205 if (shift != 0)
206 {
207 if (round == 1 && (q0 & (1 << (shift - 1))))
208 q0 = (q0 >> shift) + 1;
209 else
210 q0 = q0 >> shift;
211 }
212 result |= ((unsigned32)((unsigned8)q0) << i);
213 }
214 GPR[rd] = EXTEND32 (result);
215}
216
217:function:::void:do_ph_shrl:int rd, int rt, int shift
218{
219 int i, j;
220 unsigned16 h0;
221 unsigned32 v1 = GPR[rt];
222 unsigned32 result = 0;
223 for (i = 0; i < 32; i += 16, v1 >>= 16)
224 {
225 h0 = (unsigned16)(v1 & 0xffff);
226 h0 = h0 >> shift;
227 result |= ((unsigned32)h0 << i);
228 }
229 GPR[rd] = EXTEND32 (result);
230}
231
232// op: 0 = ADD, 1 = SUB
233// round: 0 = no rounding, 1 = rounding
234:function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round
235{
236 int i;
237 signed32 h0;
238 signed16 h1, h2;
239 unsigned32 v1 = GPR[rs];
240 unsigned32 v2 = GPR[rt];
241 unsigned32 result = 0;
242 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
243 {
244 h1 = (signed16)(v1 & 0xffff);
245 h2 = (signed16)(v2 & 0xffff);
246 if (op == 0) // ADD
247 h0 = (signed32)h1 + (signed32)h2;
248 else // SUB
249 h0 = (signed32)h1 - (signed32)h2;
250 if (round == 1)
251 h0 = (h0 + 1) >> 1;
252 else
253 h0 = h0 >> 1;
254 result |= ((unsigned32)((unsigned16)h0) << i);
255 }
256 GPR[rd] = EXTEND32 (result);
257}
258
259// op: 0 = ADD, 1 = SUB
260// round: 0 = no rounding, 1 = rounding
261:function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round
262{
263 int i;
264 signed64 v0;
265 signed32 v1 = (signed32)GPR[rs];
266 signed32 v2 = (signed32)GPR[rt];
267 if (op == 0) // ADD
268 v0 = (signed64)v1 + (signed64)v2;
269 else // SUB
270 v0 = (signed64)v1 - (signed64)v2;
271 if (round == 1)
272 v0 = (v0 + 1) >> 1;
273 else
274 v0 = v0 >> 1;
275 GPR[rd] = EXTEND32 (v0);
276}
277
278// op: 0 = DPAX, 1 = DPSX
279:function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op
280{
281 int i;
282 unsigned32 v1 = GPR[rs];
283 unsigned32 v2 = GPR[rt];
284 signed16 h1, h2;
285 signed32 result;
286 unsigned32 lo = DSPLO(ac);
287 unsigned32 hi = DSPHI(ac);
288 signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
289 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
290 {
291 h1 = (signed16)(v1 & 0xffff);
292 h2 = (signed16)((v2 & 0xffff0000) >> 16);
293 result = (signed32)h1 * (signed32)h2;
294 if (op == 0) // DPAX
295 prod += (signed64)result;
296 else // DPSX
297 prod -= (signed64)result;
298 }
299 DSPLO(ac) = EXTEND32 (prod);
300 DSPHI(ac) = EXTEND32 (prod >> 32);
301}
302
303// op: 0 = DPAQX, 1 = DPSQX
304// sat: 0 = no saturation, 1 = saturation of the accumulator
305:function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat
306{
307 int i;
308 unsigned32 v1 = GPR[rs];
309 unsigned32 v2 = GPR[rt];
310 signed16 h1, h2;
311 signed32 result;
312 unsigned32 lo = DSPLO(ac);
313 unsigned32 hi = DSPHI(ac);
314 signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
315 signed64 max, min;
316 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16)
317 {
318 h1 = (signed16)(v1 & 0xffff);
319 h2 = (signed16)((v2 & 0xffff0000) >> 16);
320 if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
321 {
322 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
323 result = 0x7fffffff;
324 }
325 else
326 result = ((signed32)h1 * (signed32)h2) << 1;
327 if (op == 0) // DPAQX
328 prod += (signed64)result;
329 else // DPSQX
330 prod -= (signed64)result;
331 }
332 // Saturation on the accumulator.
333 if (sat == 1)
334 {
335 max = (signed64) 0x7fffffffLL;
336 min = (signed64) 0xffffffff80000000LL;
337 if (prod > max)
338 {
339 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
340 prod = max;
341 }
342 else if (prod < min)
343 {
344 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
345 prod = min;
346 }
347 }
348 DSPLO(ac) = EXTEND32 (prod);
349 DSPHI(ac) = EXTEND32 (prod >> 32);
350}
351
352011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB
353"absq_s.qb r<RD>, r<RT>"
354*dsp2:
355{
356 int i;
357 signed8 q0;
358 unsigned32 v1 = GPR[RT];
359 unsigned32 result = 0;
360 for (i = 0; i < 32; i += 8, v1 >>= 8)
361 {
362 q0 = (signed8)(v1 & 0xff);
363 if (q0 == (signed8)0x80)
364 {
365 DSPCR |= DSPCR_OUFLAG4;
366 q0 = 0x7f;
367 }
368 else if (q0 & 0x80)
369 q0 = -q0;
370 result |= ((unsigned32)((unsigned8)q0) << i);
371 }
372 GPR[RD] = EXTEND32 (result);
373}
374
375011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH
376"addu.ph r<RD>, r<RS>, r<RT>"
377*dsp2:
378{
379 do_u_ph_op (SD_, RD, RS, RT, 0, 0);
380}
381
382011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH
383"addu_s.ph r<RD>, r<RS>, r<RT>"
384*dsp2:
385{
386 do_u_ph_op (SD_, RD, RS, RT, 0, 1);
387}
388
389011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB
390"adduh.qb r<RD>, r<RS>, r<RT>"
391*dsp2:
392{
393 do_uh_qb_op (SD_, RD, RS, RT, 0, 0);
394}
395
396011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB
397"adduh_r.qb r<RD>, r<RS>, r<RT>"
398*dsp2:
399{
400 do_uh_qb_op (SD_, RD, RS, RT, 0, 1);
401}
402
403011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND
404"append r<RT>, r<RS>, <SA>"
405*dsp2:
406{
407 unsigned32 v0 = GPR[RS];
408 unsigned32 v1 = GPR[RT];
409 unsigned32 result;
410 unsigned32 mask = (1 << SA) - 1;
411 result = (v1 << SA) | (v0 & mask);
412 GPR[RT] = EXTEND32 (result);
413}
414
415011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN
416"balign r<RT>, r<RS>, <BP>"
417*dsp2:
418{
419 unsigned32 v0 = GPR[RS];
420 unsigned32 v1 = GPR[RT];
421 unsigned32 result;
422 if (BP == 0)
423 result = v1;
424 else
425 result = (v1 << 8 * BP) | (v0 >> 8 * (4 - BP));
426 GPR[RT] = EXTEND32 (result);
427}
428
429011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB
430"cmpgdu.eq.qb r<RD>, r<RS>, r<RT>"
431*dsp2:
432{
433 do_qb_cmpgdu (SD_, RD, RS, RT, 0);
434}
435
436011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB
437"cmpgdu.lt.qb r<RD>, r<RS>, r<RT>"
438*dsp2:
439{
440 do_qb_cmpgdu (SD_, RD, RS, RT, 1);
441}
442
443011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB
444"cmpgdu.le.qb r<RD>, r<RS>, r<RT>"
445*dsp2:
446{
447 do_qb_cmpgdu (SD_, RD, RS, RT, 2);
448}
449
450011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH
451"dpa.w.ph ac<AC>, r<RS>, r<RT>"
452*dsp2:
453{
454 do_w_ph_dot_product (SD_, AC, RS, RT, 0);
455}
456
457011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH
458"dps.w.ph ac<AC>, r<RS>, r<RT>"
459*dsp2:
460{
461 do_w_ph_dot_product (SD_, AC, RS, RT, 1);
462}
463
464011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH
465"mul.ph r<RD>, r<RS>, r<RT>"
466*dsp2:
467{
468 do_ph_op (SD_, RD, RS, RT, 2, 0);
469}
470
471011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH
472"mul_s.ph r<RD>, r<RS>, r<RT>"
473*dsp2:
474{
475 do_ph_op (SD_, RD, RS, RT, 2, 1);
476}
477
478011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W
479"mulq_rs.w r<RD>, r<RS>, r<RT>"
480*dsp2:
481{
482 do_w_mulq (SD_, RD, RS, RT, 1);
483}
484
485011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH
486"mulq_s.ph r<RD>, r<RS>, r<RT>"
487*dsp2:
488{
489 do_ph_mulq (SD_, RD, RS, RT, 0);
490}
491
492011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W
493"mulq_s.w r<RD>, r<RS>, r<RT>"
494*dsp2:
495{
496 do_w_mulq (SD_, RD, RS, RT, 0);
497}
498
499011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH
500"mulsa.w.ph ac<AC>, r<RS>, r<RT>"
501*dsp2:
502{
503 int i;
504 unsigned32 v1 = GPR[RS];
505 unsigned32 v2 = GPR[RT];
506 signed16 h1, h2;
507 signed32 result;
508 unsigned32 lo = DSPLO(AC);
509 unsigned32 hi = DSPHI(AC);
510 signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
511 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
512 {
513 h1 = (signed16)(v1 & 0xffff);
514 h2 = (signed16)(v2 & 0xffff);
515 result = (signed32)h1 * (signed32)h2;
516
517 if (i == 0)
518 prod -= (signed64) result;
519 else
520 prod += (signed64) result;
521 }
522 DSPLO(AC) = EXTEND32 (prod);
523 DSPHI(AC) = EXTEND32 (prod >> 32);
524}
525
526011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH
527"precr.qb.ph r<RD>, r<RS>, r<RT>"
528*dsp2:
529{
530 unsigned32 v1 = GPR[RS];
531 unsigned32 v2 = GPR[RT];
532 unsigned32 tempu = (v1 & 0xff0000) >> 16;
533 unsigned32 tempv = (v1 & 0xff);
534 unsigned32 tempw = (v2 & 0xff0000) >> 16;
535 unsigned32 tempx = (v2 & 0xff);
536 GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
537}
538
539011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W
540"precr_sra.ph.w r<RT>, r<RS>, <SA>"
541*dsp2:
542{
543 do_precr_sra (SD_, RT, RS, SA, 0);
544}
545
546011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W
547"precr_sra_r.ph.w r<RT>, r<RS>, <SA>"
548*dsp2:
549{
550 do_precr_sra (SD_, RT, RS, SA, 1);
551}
552
553011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND
554"prepend r<RT>, r<RS>, <SA>"
555*dsp2:
556{
557 unsigned32 v0 = GPR[RS];
558 unsigned32 v1 = GPR[RT];
559 unsigned32 result;
560 if (SA == 0)
561 result = v1;
562 else
563 result = (v0 << (32 - SA)) | (v1 >> SA);
564 GPR[RT] = EXTEND32 (result);
565}
566
567011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB
568"shra.qb r<RD>, r<RT>, <SHIFT3>"
569*dsp2:
570{
571 do_qb_shra (SD_, RD, RT, SHIFT3, 0);
572}
573
574011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB
575"shra_r.qb r<RD>, r<RT>, <SHIFT3>"
576*dsp2:
577{
578 do_qb_shra (SD_, RD, RT, SHIFT3, 1);
579}
580
581011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB
582"shrav.qb r<RD>, r<RT>, r<RS>"
583*dsp2:
584{
585 unsigned32 shift = GPR[RS] & 0x7;
586 do_qb_shra (SD_, RD, RT, shift, 0);
587}
588
589011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB
590"shrav_r.qb r<RD>, r<RT>, r<RS>"
591*dsp2:
592{
593 unsigned32 shift = GPR[RS] & 0x7;
594 do_qb_shra (SD_, RD, RT, shift, 1);
595}
596
597011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH
598"shrl.ph r<RD>, r<RT>, <SHIFT4>"
599*dsp2:
600{
601 do_ph_shrl (SD_, RD, RT, SHIFT4);
602}
603
604011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH
605"shrlv.ph r<RD>, r<RT>, r<RS>"
606*dsp2:
607{
608 unsigned32 shift = GPR[RS] & 0xf;
609 do_ph_shrl (SD_, RD, RT, shift);
610}
611
612011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH
613"subu.ph r<RD>, r<RS>, r<RT>"
614*dsp2:
615{
616 do_u_ph_op (SD_, RD, RS, RT, 1, 0);
617}
618
619011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH
620"subu_s.ph r<RD>, r<RS>, r<RT>"
621*dsp2:
622{
623 do_u_ph_op (SD_, RD, RS, RT, 1, 1);
624}
625
626011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB
627"subuh.qb r<RD>, r<RS>, r<RT>"
628*dsp2:
629{
630 do_uh_qb_op (SD_, RD, RS, RT, 1, 0);
631}
632
633011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB
634"subuh_r.qb r<RD>, r<RS>, r<RT>"
635*dsp2:
636{
637 do_uh_qb_op (SD_, RD, RS, RT, 1, 1);
638}
639
640011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH
641"addqh.ph r<RD>, r<RS>, r<RT>"
642*dsp2:
643{
644 do_qh_ph_op (SD_, RD, RS, RT, 0, 0);
645}
646
647011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH
648"addqh_r.ph r<RD>, r<RS>, r<RT>"
649*dsp2:
650{
651 do_qh_ph_op (SD_, RD, RS, RT, 0, 1);
652}
653
654011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W
655"addqh.w r<RD>, r<RS>, r<RT>"
656*dsp2:
657{
658 do_qh_w_op (SD_, RD, RS, RT, 0, 0);
659}
660
661011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W
662"addqh_r.w r<RD>, r<RS>, r<RT>"
663*dsp2:
664{
665 do_qh_w_op (SD_, RD, RS, RT, 0, 1);
666}
667
668011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH
669"subqh.ph r<RD>, r<RS>, r<RT>"
670*dsp2:
671{
672 do_qh_ph_op (SD_, RD, RS, RT, 1, 0);
673}
674
675011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH
676"subqh_r.ph r<RD>, r<RS>, r<RT>"
677*dsp2:
678{
679 do_qh_ph_op (SD_, RD, RS, RT, 1, 1);
680}
681
682011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W
683"subqh.w r<RD>, r<RS>, r<RT>"
684*dsp2:
685{
686 do_qh_w_op (SD_, RD, RS, RT, 1, 0);
687}
688
689011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W
690"subqh_r.w r<RD>, r<RS>, r<RT>"
691*dsp2:
692{
693 do_qh_w_op (SD_, RD, RS, RT, 1, 1);
694}
695
696011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH
697"dpax.w.ph ac<AC>, r<RS>, r<RT>"
698*dsp2:
699{
700 do_x_w_ph_dot_product (SD_, AC, RS, RT, 0);
701}
702
703011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH
704"dpsx.w.ph ac<AC>, r<RS>, r<RT>"
705*dsp2:
706{
707 do_x_w_ph_dot_product (SD_, AC, RS, RT, 1);
708}
709
710011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH
711"dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>"
712*dsp2:
713{
714 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0);
715}
716
717011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH
718"dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
719*dsp2:
720{
721 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1);
722}
723
724011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH
725"dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>"
726*dsp2:
727{
728 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0);
729}
730
731011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH
732"dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>"
733*dsp2:
734{
735 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1);
736}
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