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db3ad2f0 TT |
1 | /* Ravenscar RISC-V target support. |
2 | ||
b811d2c2 | 3 | Copyright (C) 2019-2020 Free Software Foundation, Inc. |
db3ad2f0 TT |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "gdbarch.h" | |
22 | #include "gdbcore.h" | |
23 | #include "regcache.h" | |
24 | #include "riscv-tdep.h" | |
25 | #include "inferior.h" | |
26 | #include "ravenscar-thread.h" | |
27 | #include "riscv-ravenscar-thread.h" | |
28 | ||
29 | struct riscv_ravenscar_ops : public ravenscar_arch_ops | |
30 | { | |
31 | void fetch_registers (struct regcache *regcache, int regnum) override; | |
32 | void store_registers (struct regcache *regcache, int regnum) override; | |
33 | ||
34 | private: | |
35 | ||
36 | /* Return the offset of the register in the context buffer. */ | |
37 | int register_offset (struct gdbarch *arch, int regnum); | |
38 | }; | |
39 | ||
40 | int | |
41 | riscv_ravenscar_ops::register_offset (struct gdbarch *arch, int regnum) | |
42 | { | |
43 | int offset; | |
44 | if (regnum == RISCV_RA_REGNUM || regnum == RISCV_PC_REGNUM) | |
45 | offset = 0; | |
46 | else if (regnum == RISCV_SP_REGNUM) | |
47 | offset = 1; | |
48 | else if (regnum == RISCV_ZERO_REGNUM + 8) /* S0 */ | |
49 | offset = 2; | |
50 | else if (regnum == RISCV_ZERO_REGNUM + 9) /* S1 */ | |
51 | offset = 3; | |
52 | else if (regnum >= RISCV_ZERO_REGNUM + 19 | |
53 | && regnum <= RISCV_ZERO_REGNUM + 27) /* S2..S11 */ | |
54 | offset = regnum - (RISCV_ZERO_REGNUM + 19) + 4; | |
55 | else if (regnum >= RISCV_FIRST_FP_REGNUM | |
56 | && regnum <= RISCV_FIRST_FP_REGNUM + 11) | |
57 | offset = regnum - RISCV_FIRST_FP_REGNUM + 14; /* FS0..FS11 */ | |
58 | else | |
59 | { | |
60 | /* Not saved. */ | |
61 | return -1; | |
62 | } | |
63 | ||
64 | int size = register_size (arch, regnum); | |
65 | return offset * size; | |
66 | } | |
67 | ||
68 | /* Supply register REGNUM, which has been saved on REGISTER_ADDR, to the | |
69 | regcache. */ | |
70 | ||
71 | static void | |
72 | supply_register_at_address (struct regcache *regcache, int regnum, | |
dda83cd7 | 73 | CORE_ADDR register_addr) |
db3ad2f0 TT |
74 | { |
75 | struct gdbarch *gdbarch = regcache->arch (); | |
76 | int buf_size = register_size (gdbarch, regnum); | |
77 | gdb_byte *buf; | |
78 | ||
79 | buf = (gdb_byte *) alloca (buf_size); | |
80 | read_memory (register_addr, buf, buf_size); | |
81 | regcache->raw_supply (regnum, buf); | |
82 | } | |
83 | ||
84 | void | |
85 | riscv_ravenscar_ops::fetch_registers (struct regcache *regcache, int regnum) | |
86 | { | |
87 | struct gdbarch *gdbarch = regcache->arch (); | |
88 | const int num_regs = gdbarch_num_regs (gdbarch); | |
89 | int current_regnum; | |
90 | CORE_ADDR current_address; | |
91 | CORE_ADDR thread_descriptor_address; | |
92 | ||
93 | /* The tid is the thread_id field, which is a pointer to the thread. */ | |
94 | thread_descriptor_address = (CORE_ADDR) inferior_ptid.tid (); | |
95 | ||
96 | /* Read registers. */ | |
97 | for (current_regnum = 0; current_regnum < num_regs; current_regnum++) | |
98 | { | |
99 | int offset = register_offset (gdbarch, current_regnum); | |
100 | ||
101 | if (offset != -1) | |
dda83cd7 SM |
102 | { |
103 | current_address = thread_descriptor_address + offset; | |
104 | supply_register_at_address (regcache, current_regnum, | |
105 | current_address); | |
106 | } | |
db3ad2f0 TT |
107 | } |
108 | } | |
109 | ||
110 | void | |
111 | riscv_ravenscar_ops::store_registers (struct regcache *regcache, int regnum) | |
112 | { | |
113 | struct gdbarch *gdbarch = regcache->arch (); | |
114 | int buf_size = register_size (gdbarch, regnum); | |
115 | gdb_byte buf[buf_size]; | |
116 | CORE_ADDR register_address; | |
117 | ||
118 | int offset = register_offset (gdbarch, regnum); | |
119 | if (offset != -1) | |
120 | { | |
121 | register_address = inferior_ptid.tid () + offset; | |
122 | ||
123 | regcache->raw_collect (regnum, buf); | |
124 | write_memory (register_address, | |
125 | buf, | |
126 | buf_size); | |
127 | } | |
128 | } | |
129 | ||
130 | /* The ravenscar_arch_ops vector for most RISC-V targets. */ | |
131 | ||
132 | static struct riscv_ravenscar_ops riscv_ravenscar_ops; | |
133 | ||
134 | /* Register riscv_ravenscar_ops in GDBARCH. */ | |
135 | ||
136 | void | |
137 | register_riscv_ravenscar_ops (struct gdbarch *gdbarch) | |
138 | { | |
139 | set_gdbarch_ravenscar_ops (gdbarch, &riscv_ravenscar_ops); | |
140 | } |