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[binutils.git] / bfd / coff-sh.c
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252b5132 1/* BFD back-end for Hitachi Super-H COFF binaries.
5f771d47 2 Copyright 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <[email protected]>.
5 Relaxing code written by Ian Lance Taylor, <[email protected]>.
6
7This file is part of BFD, the Binary File Descriptor library.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2 of the License, or
12(at your option) any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program; if not, write to the Free Software
21Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23#include "bfd.h"
24#include "sysdep.h"
25#include "libbfd.h"
26#include "bfdlink.h"
27#include "coff/sh.h"
28#include "coff/internal.h"
29#include "libcoff.h"
30
31/* Internal functions. */
32static bfd_reloc_status_type sh_reloc
33 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
34static long get_symbol_value PARAMS ((asymbol *));
252b5132
RH		 35static boolean sh_relax_section
36 PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *));
37static boolean sh_relax_delete_bytes
38 PARAMS ((bfd *, asection *, bfd_vma, int));
39static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
40static boolean sh_align_loads
41 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, boolean *));
42static boolean sh_swap_insns
43 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
44static boolean sh_relocate_section
45 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
46 struct internal_reloc *, struct internal_syment *, asection **));
47static bfd_byte *sh_coff_get_relocated_section_contents
48 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
49 bfd_byte *, boolean, asymbol **));
50
51/* Default section alignment to 2**4. */
52#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (4)
53
54/* Generate long file names. */
55#define COFF_LONG_FILENAMES
56
57/* The supported relocations. There are a lot of relocations defined
58 in coff/internal.h which we do not expect to ever see. */
59static reloc_howto_type sh_coff_howtos[] =
60{
5f771d47
ILT		 61 EMPTY_HOWTO (0),
62 EMPTY_HOWTO (1),
63 EMPTY_HOWTO (2),
64 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
65 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
66 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
67 EMPTY_HOWTO (6), /* R_SH_IMM24 */
68 EMPTY_HOWTO (7), /* R_SH_LOW16 */
69 EMPTY_HOWTO (8),
70 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 71
72 HOWTO (R_SH_PCDISP8BY2, /* type */
73 1, /* rightshift */
74 1, /* size (0 = byte, 1 = short, 2 = long) */
75 8, /* bitsize */
76 true, /* pc_relative */
77 0, /* bitpos */
78 complain_overflow_signed, /* complain_on_overflow */
79 sh_reloc, /* special_function */
80 "r_pcdisp8by2", /* name */
81 true, /* partial_inplace */
82 0xff, /* src_mask */
83 0xff, /* dst_mask */
84 true), /* pcrel_offset */
85
5f771d47 86 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 87
88 HOWTO (R_SH_PCDISP, /* type */
89 1, /* rightshift */
90 1, /* size (0 = byte, 1 = short, 2 = long) */
91 12, /* bitsize */
92 true, /* pc_relative */
93 0, /* bitpos */
94 complain_overflow_signed, /* complain_on_overflow */
95 sh_reloc, /* special_function */
96 "r_pcdisp12by2", /* name */
97 true, /* partial_inplace */
98 0xfff, /* src_mask */
99 0xfff, /* dst_mask */
100 true), /* pcrel_offset */
101
5f771d47 102 EMPTY_HOWTO (13),
252b5132
RH		 103
104 HOWTO (R_SH_IMM32, /* type */
105 0, /* rightshift */
106 2, /* size (0 = byte, 1 = short, 2 = long) */
107 32, /* bitsize */
108 false, /* pc_relative */
109 0, /* bitpos */
110 complain_overflow_bitfield, /* complain_on_overflow */
111 sh_reloc, /* special_function */
112 "r_imm32", /* name */
113 true, /* partial_inplace */
114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
116 false), /* pcrel_offset */
117
5f771d47
ILT		 118 EMPTY_HOWTO (15),
119 EMPTY_HOWTO (16), /* R_SH_IMM8 */
120 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
121 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
122 EMPTY_HOWTO (19), /* R_SH_IMM4 */
123 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
124 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 125
126 HOWTO (R_SH_PCRELIMM8BY2, /* type */
127 1, /* rightshift */
128 1, /* size (0 = byte, 1 = short, 2 = long) */
129 8, /* bitsize */
130 true, /* pc_relative */
131 0, /* bitpos */
132 complain_overflow_unsigned, /* complain_on_overflow */
133 sh_reloc, /* special_function */
134 "r_pcrelimm8by2", /* name */
135 true, /* partial_inplace */
136 0xff, /* src_mask */
137 0xff, /* dst_mask */
138 true), /* pcrel_offset */
139
140 HOWTO (R_SH_PCRELIMM8BY4, /* type */
141 2, /* rightshift */
142 1, /* size (0 = byte, 1 = short, 2 = long) */
143 8, /* bitsize */
144 true, /* pc_relative */
145 0, /* bitpos */
146 complain_overflow_unsigned, /* complain_on_overflow */
147 sh_reloc, /* special_function */
148 "r_pcrelimm8by4", /* name */
149 true, /* partial_inplace */
150 0xff, /* src_mask */
151 0xff, /* dst_mask */
152 true), /* pcrel_offset */
153
154 HOWTO (R_SH_IMM16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 false, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield, /* complain_on_overflow */
161 sh_reloc, /* special_function */
162 "r_imm16", /* name */
163 true, /* partial_inplace */
164 0xffff, /* src_mask */
165 0xffff, /* dst_mask */
166 false), /* pcrel_offset */
167
168 HOWTO (R_SH_SWITCH16, /* type */
169 0, /* rightshift */
170 1, /* size (0 = byte, 1 = short, 2 = long) */
171 16, /* bitsize */
172 false, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield, /* complain_on_overflow */
175 sh_reloc, /* special_function */
176 "r_switch16", /* name */
177 true, /* partial_inplace */
178 0xffff, /* src_mask */
179 0xffff, /* dst_mask */
180 false), /* pcrel_offset */
181
182 HOWTO (R_SH_SWITCH32, /* type */
183 0, /* rightshift */
184 2, /* size (0 = byte, 1 = short, 2 = long) */
185 32, /* bitsize */
186 false, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield, /* complain_on_overflow */
189 sh_reloc, /* special_function */
190 "r_switch32", /* name */
191 true, /* partial_inplace */
192 0xffffffff, /* src_mask */
193 0xffffffff, /* dst_mask */
194 false), /* pcrel_offset */
195
196 HOWTO (R_SH_USES, /* type */
197 0, /* rightshift */
198 1, /* size (0 = byte, 1 = short, 2 = long) */
199 16, /* bitsize */
200 false, /* pc_relative */
201 0, /* bitpos */
202 complain_overflow_bitfield, /* complain_on_overflow */
203 sh_reloc, /* special_function */
204 "r_uses", /* name */
205 true, /* partial_inplace */
206 0xffff, /* src_mask */
207 0xffff, /* dst_mask */
208 false), /* pcrel_offset */
209
210 HOWTO (R_SH_COUNT, /* type */
211 0, /* rightshift */
212 2, /* size (0 = byte, 1 = short, 2 = long) */
213 32, /* bitsize */
214 false, /* pc_relative */
215 0, /* bitpos */
216 complain_overflow_bitfield, /* complain_on_overflow */
217 sh_reloc, /* special_function */
218 "r_count", /* name */
219 true, /* partial_inplace */
220 0xffffffff, /* src_mask */
221 0xffffffff, /* dst_mask */
222 false), /* pcrel_offset */
223
224 HOWTO (R_SH_ALIGN, /* type */
225 0, /* rightshift */
226 2, /* size (0 = byte, 1 = short, 2 = long) */
227 32, /* bitsize */
228 false, /* pc_relative */
229 0, /* bitpos */
230 complain_overflow_bitfield, /* complain_on_overflow */
231 sh_reloc, /* special_function */
232 "r_align", /* name */
233 true, /* partial_inplace */
234 0xffffffff, /* src_mask */
235 0xffffffff, /* dst_mask */
236 false), /* pcrel_offset */
237
238 HOWTO (R_SH_CODE, /* type */
239 0, /* rightshift */
240 2, /* size (0 = byte, 1 = short, 2 = long) */
241 32, /* bitsize */
242 false, /* pc_relative */
243 0, /* bitpos */
244 complain_overflow_bitfield, /* complain_on_overflow */
245 sh_reloc, /* special_function */
246 "r_code", /* name */
247 true, /* partial_inplace */
248 0xffffffff, /* src_mask */
249 0xffffffff, /* dst_mask */
250 false), /* pcrel_offset */
251
252 HOWTO (R_SH_DATA, /* type */
253 0, /* rightshift */
254 2, /* size (0 = byte, 1 = short, 2 = long) */
255 32, /* bitsize */
256 false, /* pc_relative */
257 0, /* bitpos */
258 complain_overflow_bitfield, /* complain_on_overflow */
259 sh_reloc, /* special_function */
260 "r_data", /* name */
261 true, /* partial_inplace */
262 0xffffffff, /* src_mask */
263 0xffffffff, /* dst_mask */
264 false), /* pcrel_offset */
265
266 HOWTO (R_SH_LABEL, /* type */
267 0, /* rightshift */
268 2, /* size (0 = byte, 1 = short, 2 = long) */
269 32, /* bitsize */
270 false, /* pc_relative */
271 0, /* bitpos */
272 complain_overflow_bitfield, /* complain_on_overflow */
273 sh_reloc, /* special_function */
274 "r_label", /* name */
275 true, /* partial_inplace */
276 0xffffffff, /* src_mask */
277 0xffffffff, /* dst_mask */
278 false), /* pcrel_offset */
279
280 HOWTO (R_SH_SWITCH8, /* type */
281 0, /* rightshift */
282 0, /* size (0 = byte, 1 = short, 2 = long) */
283 8, /* bitsize */
284 false, /* pc_relative */
285 0, /* bitpos */
286 complain_overflow_bitfield, /* complain_on_overflow */
287 sh_reloc, /* special_function */
288 "r_switch8", /* name */
289 true, /* partial_inplace */
290 0xff, /* src_mask */
291 0xff, /* dst_mask */
292 false) /* pcrel_offset */
293};
294
295#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
296
297/* Check for a bad magic number. */
298#define BADMAG(x) SHBADMAG(x)
299
300/* Customize coffcode.h (this is not currently used). */
301#define SH 1
302
303/* FIXME: This should not be set here. */
304#define __A_MAGIC_SET__
305
306/* Swap the r_offset field in and out. */
307#define SWAP_IN_RELOC_OFFSET bfd_h_get_32
308#define SWAP_OUT_RELOC_OFFSET bfd_h_put_32
309
310/* Swap out extra information in the reloc structure. */
311#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
312 do \
313 { \
314 dst->r_stuff[0] = 'S'; \
315 dst->r_stuff[1] = 'C'; \
316 } \
317 while (0)
318
319/* Get the value of a symbol, when performing a relocation. */
320
321static long
322get_symbol_value (symbol)
323 asymbol *symbol;
324{
325 bfd_vma relocation;
326
327 if (bfd_is_com_section (symbol->section))
328 relocation = 0;
329 else
330 relocation = (symbol->value +
331 symbol->section->output_section->vma +
332 symbol->section->output_offset);
333
334 return relocation;
335}
336
337/* This macro is used in coffcode.h to get the howto corresponding to
338 an internal reloc. */
339
340#define RTYPE2HOWTO(relent, internal) \
341 ((relent)->howto = \
342 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
343 ? &sh_coff_howtos[(internal)->r_type] \
344 : (reloc_howto_type *) NULL))
345
346/* This is the same as the macro in coffcode.h, except that it copies
347 r_offset into reloc_entry->addend for some relocs. */
348#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
349 { \
350 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
351 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
352 coffsym = (obj_symbols (abfd) \
353 + (cache_ptr->sym_ptr_ptr - symbols)); \
354 else if (ptr) \
355 coffsym = coff_symbol_from (abfd, ptr); \
356 if (coffsym != (coff_symbol_type *) NULL \
357 && coffsym->native->u.syment.n_scnum == 0) \
358 cache_ptr->addend = 0; \
359 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
360 && ptr->section != (asection *) NULL) \
361 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
362 else \
363 cache_ptr->addend = 0; \
364 if ((reloc).r_type == R_SH_SWITCH8 \
365 || (reloc).r_type == R_SH_SWITCH16 \
366 || (reloc).r_type == R_SH_SWITCH32 \
367 || (reloc).r_type == R_SH_USES \
368 || (reloc).r_type == R_SH_COUNT \
369 || (reloc).r_type == R_SH_ALIGN) \
370 cache_ptr->addend = (reloc).r_offset; \
371 }
372
373/* This is the howto function for the SH relocations. */
374
375static bfd_reloc_status_type
376sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
377 error_message)
378 bfd *abfd;
379 arelent *reloc_entry;
380 asymbol *symbol_in;
381 PTR data;
382 asection *input_section;
383 bfd *output_bfd;
5f771d47 384 char **error_message ATTRIBUTE_UNUSED;
252b5132
RH		 385{
386 unsigned long insn;
387 bfd_vma sym_value;
388 unsigned short r_type;
389 bfd_vma addr = reloc_entry->address;
390 bfd_byte *hit_data = addr + (bfd_byte *) data;
391
392 r_type = reloc_entry->howto->type;
393
394 if (output_bfd != NULL)
395 {
396 /* Partial linking--do nothing. */
397 reloc_entry->address += input_section->output_offset;
398 return bfd_reloc_ok;
399 }
400
401 /* Almost all relocs have to do with relaxing. If any work must be
402 done for them, it has been done in sh_relax_section. */
403 if (r_type != R_SH_IMM32
404 && (r_type != R_SH_PCDISP
405 || (symbol_in->flags & BSF_LOCAL) != 0))
406 return bfd_reloc_ok;
407
408 if (symbol_in != NULL
409 && bfd_is_und_section (symbol_in->section))
410 return bfd_reloc_undefined;
411
412 sym_value = get_symbol_value (symbol_in);
413
414 switch (r_type)
415 {
416 case R_SH_IMM32:
417 insn = bfd_get_32 (abfd, hit_data);
418 insn += sym_value + reloc_entry->addend;
419 bfd_put_32 (abfd, insn, hit_data);
420 break;
421 case R_SH_PCDISP:
422 insn = bfd_get_16 (abfd, hit_data);
423 sym_value += reloc_entry->addend;
424 sym_value -= (input_section->output_section->vma
425 + input_section->output_offset
426 + addr
427 + 4);
428 sym_value += (insn & 0xfff) << 1;
429 if (insn & 0x800)
430 sym_value -= 0x1000;
431 insn = (insn & 0xf000) | (sym_value & 0xfff);
432 bfd_put_16 (abfd, insn, hit_data);
433 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
434 return bfd_reloc_overflow;
435 break;
436 default:
437 abort ();
438 break;
439 }
440
441 return bfd_reloc_ok;
442}
443
875f7f69 444#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 445
446/* We can do relaxing. */
447#define coff_bfd_relax_section sh_relax_section
448
449/* We use the special COFF backend linker. */
450#define coff_relocate_section sh_relocate_section
451
452/* When relaxing, we need to use special code to get the relocated
453 section contents. */
454#define coff_bfd_get_relocated_section_contents \
455 sh_coff_get_relocated_section_contents
456
457#include "coffcode.h"
458\f
459/* This function handles relaxing on the SH.
460
461 Function calls on the SH look like this:
462
463 movl L1,r0
464 ...
465 jsr @r0
466 ...
467 L1:
468 .long function
469
470 The compiler and assembler will cooperate to create R_SH_USES
471 relocs on the jsr instructions. The r_offset field of the
472 R_SH_USES reloc is the PC relative offset to the instruction which
473 loads the register (the r_offset field is computed as though it
474 were a jump instruction, so the offset value is actually from four
475 bytes past the instruction). The linker can use this reloc to
476 determine just which function is being called, and thus decide
477 whether it is possible to replace the jsr with a bsr.
478
479 If multiple function calls are all based on a single register load
480 (i.e., the same function is called multiple times), the compiler
481 guarantees that each function call will have an R_SH_USES reloc.
482 Therefore, if the linker is able to convert each R_SH_USES reloc
483 which refers to that address, it can safely eliminate the register
484 load.
485
486 When the assembler creates an R_SH_USES reloc, it examines it to
487 determine which address is being loaded (L1 in the above example).
488 It then counts the number of references to that address, and
489 creates an R_SH_COUNT reloc at that address. The r_offset field of
490 the R_SH_COUNT reloc will be the number of references. If the
491 linker is able to eliminate a register load, it can use the
492 R_SH_COUNT reloc to see whether it can also eliminate the function
493 address.
494
495 SH relaxing also handles another, unrelated, matter. On the SH, if
496 a load or store instruction is not aligned on a four byte boundary,
497 the memory cycle interferes with the 32 bit instruction fetch,
498 causing a one cycle bubble in the pipeline. Therefore, we try to
499 align load and store instructions on four byte boundaries if we
500 can, by swapping them with one of the adjacent instructions. */
501
502static boolean
503sh_relax_section (abfd, sec, link_info, again)
504 bfd *abfd;
505 asection *sec;
506 struct bfd_link_info *link_info;
507 boolean *again;
508{
509 struct internal_reloc *internal_relocs;
510 struct internal_reloc *free_relocs = NULL;
511 boolean have_code;
512 struct internal_reloc *irel, *irelend;
513 bfd_byte *contents = NULL;
514 bfd_byte *free_contents = NULL;
515
516 *again = false;
517
518 if (link_info->relocateable
519 || (sec->flags & SEC_RELOC) == 0
520 || sec->reloc_count == 0)
521 return true;
522
523 /* If this is the first time we have been called for this section,
524 initialize the cooked size. */
525 if (sec->_cooked_size == 0)
526 sec->_cooked_size = sec->_raw_size;
527
528 internal_relocs = (_bfd_coff_read_internal_relocs
529 (abfd, sec, link_info->keep_memory,
530 (bfd_byte *) NULL, false,
531 (struct internal_reloc *) NULL));
532 if (internal_relocs == NULL)
533 goto error_return;
534 if (! link_info->keep_memory)
535 free_relocs = internal_relocs;
536
537 have_code = false;
538
539 irelend = internal_relocs + sec->reloc_count;
540 for (irel = internal_relocs; irel < irelend; irel++)
541 {
542 bfd_vma laddr, paddr, symval;
543 unsigned short insn;
544 struct internal_reloc *irelfn, *irelscan, *irelcount;
545 struct internal_syment sym;
546 bfd_signed_vma foff;
547
548 if (irel->r_type == R_SH_CODE)
549 have_code = true;
550
551 if (irel->r_type != R_SH_USES)
552 continue;
553
554 /* Get the section contents. */
555 if (contents == NULL)
556 {
557 if (coff_section_data (abfd, sec) != NULL
558 && coff_section_data (abfd, sec)->contents != NULL)
559 contents = coff_section_data (abfd, sec)->contents;
560 else
561 {
562 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
563 if (contents == NULL)
564 goto error_return;
565 free_contents = contents;
566
567 if (! bfd_get_section_contents (abfd, sec, contents,
568 (file_ptr) 0, sec->_raw_size))
569 goto error_return;
570 }
571 }
572
573 /* The r_offset field of the R_SH_USES reloc will point us to
574 the register load. The 4 is because the r_offset field is
575 computed as though it were a jump offset, which are based
576 from 4 bytes after the jump instruction. */
577 laddr = irel->r_vaddr - sec->vma + 4;
578 /* Careful to sign extend the 32-bit offset. */
579 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
580 if (laddr >= sec->_raw_size)
581 {
582 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
583 bfd_get_filename (abfd),
584 (unsigned long) irel->r_vaddr);
585 continue;
586 }
587 insn = bfd_get_16 (abfd, contents + laddr);
588
589 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
590 if ((insn & 0xf000) != 0xd000)
591 {
592 ((*_bfd_error_handler)
593 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
594 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr, insn));
595 continue;
596 }
597
598 /* Get the address from which the register is being loaded. The
599 displacement in the mov.l instruction is quadrupled. It is a
600 displacement from four bytes after the movl instruction, but,
601 before adding in the PC address, two least significant bits
602 of the PC are cleared. We assume that the section is aligned
603 on a four byte boundary. */
604 paddr = insn & 0xff;
605 paddr *= 4;
606 paddr += (laddr + 4) &~ 3;
607 if (paddr >= sec->_raw_size)
608 {
609 ((*_bfd_error_handler)
610 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
611 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
612 continue;
613 }
614
615 /* Get the reloc for the address from which the register is
616 being loaded. This reloc will tell us which function is
617 actually being called. */
618 paddr += sec->vma;
619 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
620 if (irelfn->r_vaddr == paddr
621 && irelfn->r_type == R_SH_IMM32)
622 break;
623 if (irelfn >= irelend)
624 {
625 ((*_bfd_error_handler)
626 ("%s: 0x%lx: warning: could not find expected reloc",
627 bfd_get_filename (abfd), (unsigned long) paddr));
628 continue;
629 }
630
631 /* Get the value of the symbol referred to by the reloc. */
632 if (! _bfd_coff_get_external_symbols (abfd))
633 goto error_return;
634 bfd_coff_swap_sym_in (abfd,
635 ((bfd_byte *) obj_coff_external_syms (abfd)
636 + (irelfn->r_symndx
637 * bfd_coff_symesz (abfd))),
638 &sym);
639 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
640 {
641 ((*_bfd_error_handler)
642 ("%s: 0x%lx: warning: symbol in unexpected section",
643 bfd_get_filename (abfd), (unsigned long) paddr));
644 continue;
645 }
646
647 if (sym.n_sclass != C_EXT)
648 {
649 symval = (sym.n_value
650 - sec->vma
651 + sec->output_section->vma
652 + sec->output_offset);
653 }
654 else
655 {
656 struct coff_link_hash_entry *h;
657
658 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
659 BFD_ASSERT (h != NULL);
660 if (h->root.type != bfd_link_hash_defined
661 && h->root.type != bfd_link_hash_defweak)
662 {
663 /* This appears to be a reference to an undefined
664 symbol. Just ignore it--it will be caught by the
665 regular reloc processing. */
666 continue;
667 }
668
669 symval = (h->root.u.def.value
670 + h->root.u.def.section->output_section->vma
671 + h->root.u.def.section->output_offset);
672 }
673
674 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
675
676 /* See if this function call can be shortened. */
677 foff = (symval
678 - (irel->r_vaddr
679 - sec->vma
680 + sec->output_section->vma
681 + sec->output_offset
682 + 4));
683 if (foff < -0x1000 || foff >= 0x1000)
684 {
685 /* After all that work, we can't shorten this function call. */
686 continue;
687 }
688
689 /* Shorten the function call. */
690
691 /* For simplicity of coding, we are going to modify the section
692 contents, the section relocs, and the BFD symbol table. We
693 must tell the rest of the code not to free up this
694 information. It would be possible to instead create a table
695 of changes which have to be made, as is done in coff-mips.c;
696 that would be more work, but would require less memory when
697 the linker is run. */
698
699 if (coff_section_data (abfd, sec) == NULL)
700 {
701 sec->used_by_bfd =
702 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
703 if (sec->used_by_bfd == NULL)
704 goto error_return;
705 }
706
707 coff_section_data (abfd, sec)->relocs = internal_relocs;
708 coff_section_data (abfd, sec)->keep_relocs = true;
709 free_relocs = NULL;
710
711 coff_section_data (abfd, sec)->contents = contents;
712 coff_section_data (abfd, sec)->keep_contents = true;
713 free_contents = NULL;
714
715 obj_coff_keep_syms (abfd) = true;
716
717 /* Replace the jsr with a bsr. */
718
719 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
720 replace the jsr with a bsr. */
721 irel->r_type = R_SH_PCDISP;
722 irel->r_symndx = irelfn->r_symndx;
723 if (sym.n_sclass != C_EXT)
724 {
725 /* If this needs to be changed because of future relaxing,
726 it will be handled here like other internal PCDISP
727 relocs. */
728 bfd_put_16 (abfd,
729 0xb000 | ((foff >> 1) & 0xfff),
730 contents + irel->r_vaddr - sec->vma);
731 }
732 else
733 {
734 /* We can't fully resolve this yet, because the external
735 symbol value may be changed by future relaxing. We let
736 the final link phase handle it. */
737 bfd_put_16 (abfd, 0xb000, contents + irel->r_vaddr - sec->vma);
738 }
739
740 /* See if there is another R_SH_USES reloc referring to the same
741 register load. */
742 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
743 if (irelscan->r_type == R_SH_USES
744 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
745 break;
746 if (irelscan < irelend)
747 {
748 /* Some other function call depends upon this register load,
749 and we have not yet converted that function call.
750 Indeed, we may never be able to convert it. There is
751 nothing else we can do at this point. */
752 continue;
753 }
754
755 /* Look for a R_SH_COUNT reloc on the location where the
756 function address is stored. Do this before deleting any
757 bytes, to avoid confusion about the address. */
758 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
759 if (irelcount->r_vaddr == paddr
760 && irelcount->r_type == R_SH_COUNT)
761 break;
762
763 /* Delete the register load. */
764 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
765 goto error_return;
766
767 /* That will change things, so, just in case it permits some
768 other function call to come within range, we should relax
769 again. Note that this is not required, and it may be slow. */
770 *again = true;
771
772 /* Now check whether we got a COUNT reloc. */
773 if (irelcount >= irelend)
774 {
775 ((*_bfd_error_handler)
776 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
777 bfd_get_filename (abfd), (unsigned long) paddr));
778 continue;
779 }
780
781 /* The number of uses is stored in the r_offset field. We've
782 just deleted one. */
783 if (irelcount->r_offset == 0)
784 {
785 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
786 bfd_get_filename (abfd),
787 (unsigned long) paddr));
788 continue;
789 }
790
791 --irelcount->r_offset;
792
793 /* If there are no more uses, we can delete the address. Reload
794 the address from irelfn, in case it was changed by the
795 previous call to sh_relax_delete_bytes. */
796 if (irelcount->r_offset == 0)
797 {
798 if (! sh_relax_delete_bytes (abfd, sec,
799 irelfn->r_vaddr - sec->vma, 4))
800 goto error_return;
801 }
802
803 /* We've done all we can with that function call. */
804 }
805
806 /* Look for load and store instructions that we can align on four
807 byte boundaries. */
808 if (have_code)
809 {
810 boolean swapped;
811
812 /* Get the section contents. */
813 if (contents == NULL)
814 {
815 if (coff_section_data (abfd, sec) != NULL
816 && coff_section_data (abfd, sec)->contents != NULL)
817 contents = coff_section_data (abfd, sec)->contents;
818 else
819 {
820 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
821 if (contents == NULL)
822 goto error_return;
823 free_contents = contents;
824
825 if (! bfd_get_section_contents (abfd, sec, contents,
826 (file_ptr) 0, sec->_raw_size))
827 goto error_return;
828 }
829 }
830
831 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
832 goto error_return;
833
834 if (swapped)
835 {
836 if (coff_section_data (abfd, sec) == NULL)
837 {
838 sec->used_by_bfd =
839 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
840 if (sec->used_by_bfd == NULL)
841 goto error_return;
842 }
843
844 coff_section_data (abfd, sec)->relocs = internal_relocs;
845 coff_section_data (abfd, sec)->keep_relocs = true;
846 free_relocs = NULL;
847
848 coff_section_data (abfd, sec)->contents = contents;
849 coff_section_data (abfd, sec)->keep_contents = true;
850 free_contents = NULL;
851
852 obj_coff_keep_syms (abfd) = true;
853 }
854 }
855
856 if (free_relocs != NULL)
857 {
858 free (free_relocs);
859 free_relocs = NULL;
860 }
861
862 if (free_contents != NULL)
863 {
864 if (! link_info->keep_memory)
865 free (free_contents);
866 else
867 {
868 /* Cache the section contents for coff_link_input_bfd. */
869 if (coff_section_data (abfd, sec) == NULL)
870 {
871 sec->used_by_bfd =
872 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
873 if (sec->used_by_bfd == NULL)
874 goto error_return;
875 coff_section_data (abfd, sec)->relocs = NULL;
876 }
877 coff_section_data (abfd, sec)->contents = contents;
878 }
879 }
880
881 return true;
882
883 error_return:
884 if (free_relocs != NULL)
885 free (free_relocs);
886 if (free_contents != NULL)
887 free (free_contents);
888 return false;
889}
890
891/* Delete some bytes from a section while relaxing. */
892
893static boolean
894sh_relax_delete_bytes (abfd, sec, addr, count)
895 bfd *abfd;
896 asection *sec;
897 bfd_vma addr;
898 int count;
899{
900 bfd_byte *contents;
901 struct internal_reloc *irel, *irelend;
902 struct internal_reloc *irelalign;
903 bfd_vma toaddr;
904 bfd_byte *esym, *esymend;
905 bfd_size_type symesz;
906 struct coff_link_hash_entry **sym_hash;
907 asection *o;
908
909 contents = coff_section_data (abfd, sec)->contents;
910
911 /* The deletion must stop at the next ALIGN reloc for an aligment
912 power larger than the number of bytes we are deleting. */
913
914 irelalign = NULL;
915 toaddr = sec->_cooked_size;
916
917 irel = coff_section_data (abfd, sec)->relocs;
918 irelend = irel + sec->reloc_count;
919 for (; irel < irelend; irel++)
920 {
921 if (irel->r_type == R_SH_ALIGN
922 && irel->r_vaddr - sec->vma > addr
923 && count < (1 << irel->r_offset))
924 {
925 irelalign = irel;
926 toaddr = irel->r_vaddr - sec->vma;
927 break;
928 }
929 }
930
931 /* Actually delete the bytes. */
932 memmove (contents + addr, contents + addr + count, toaddr - addr - count);
933 if (irelalign == NULL)
934 sec->_cooked_size -= count;
935 else
936 {
937 int i;
938
939#define NOP_OPCODE (0x0009)
940
941 BFD_ASSERT ((count & 1) == 0);
942 for (i = 0; i < count; i += 2)
943 bfd_put_16 (abfd, NOP_OPCODE, contents + toaddr - count + i);
944 }
945
946 /* Adjust all the relocs. */
947 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
948 {
949 bfd_vma nraddr, stop;
950 bfd_vma start = 0;
951 int insn = 0;
952 struct internal_syment sym;
953 int off, adjust, oinsn;
954 bfd_signed_vma voff = 0;
955 boolean overflow;
956
957 /* Get the new reloc address. */
958 nraddr = irel->r_vaddr - sec->vma;
959 if ((irel->r_vaddr - sec->vma > addr
960 && irel->r_vaddr - sec->vma < toaddr)
961 || (irel->r_type == R_SH_ALIGN
962 && irel->r_vaddr - sec->vma == toaddr))
963 nraddr -= count;
964
965 /* See if this reloc was for the bytes we have deleted, in which
966 case we no longer care about it. Don't delete relocs which
967 represent addresses, though. */
968 if (irel->r_vaddr - sec->vma >= addr
969 && irel->r_vaddr - sec->vma < addr + count
970 && irel->r_type != R_SH_ALIGN
971 && irel->r_type != R_SH_CODE
972 && irel->r_type != R_SH_DATA
973 && irel->r_type != R_SH_LABEL)
974 irel->r_type = R_SH_UNUSED;
975
976 /* If this is a PC relative reloc, see if the range it covers
977 includes the bytes we have deleted. */
978 switch (irel->r_type)
979 {
980 default:
981 break;
982
983 case R_SH_PCDISP8BY2:
984 case R_SH_PCDISP:
985 case R_SH_PCRELIMM8BY2:
986 case R_SH_PCRELIMM8BY4:
987 start = irel->r_vaddr - sec->vma;
988 insn = bfd_get_16 (abfd, contents + nraddr);
989 break;
990 }
991
992 switch (irel->r_type)
993 {
994 default:
995 start = stop = addr;
996 break;
997
998 case R_SH_IMM32:
999 /* If this reloc is against a symbol defined in this
1000 section, and the symbol will not be adjusted below, we
1001 must check the addend to see it will put the value in
1002 range to be adjusted, and hence must be changed. */
1003 bfd_coff_swap_sym_in (abfd,
1004 ((bfd_byte *) obj_coff_external_syms (abfd)
1005 + (irel->r_symndx
1006 * bfd_coff_symesz (abfd))),
1007 &sym);
1008 if (sym.n_sclass != C_EXT
1009 && sym.n_scnum == sec->target_index
1010 && ((bfd_vma) sym.n_value <= addr
1011 || (bfd_vma) sym.n_value >= toaddr))
1012 {
1013 bfd_vma val;
1014
1015 val = bfd_get_32 (abfd, contents + nraddr);
1016 val += sym.n_value;
1017 if (val > addr && val < toaddr)
1018 bfd_put_32 (abfd, val - count, contents + nraddr);
1019 }
1020 start = stop = addr;
1021 break;
1022
1023 case R_SH_PCDISP8BY2:
1024 off = insn & 0xff;
1025 if (off & 0x80)
1026 off -= 0x100;
1027 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1028 break;
1029
1030 case R_SH_PCDISP:
1031 bfd_coff_swap_sym_in (abfd,
1032 ((bfd_byte *) obj_coff_external_syms (abfd)
1033 + (irel->r_symndx
1034 * bfd_coff_symesz (abfd))),
1035 &sym);
1036 if (sym.n_sclass == C_EXT)
1037 start = stop = addr;
1038 else
1039 {
1040 off = insn & 0xfff;
1041 if (off & 0x800)
1042 off -= 0x1000;
1043 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1044 }
1045 break;
1046
1047 case R_SH_PCRELIMM8BY2:
1048 off = insn & 0xff;
1049 stop = start + 4 + off * 2;
1050 break;
1051
1052 case R_SH_PCRELIMM8BY4:
1053 off = insn & 0xff;
1054 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1055 break;
1056
1057 case R_SH_SWITCH8:
1058 case R_SH_SWITCH16:
1059 case R_SH_SWITCH32:
1060 /* These relocs types represent
1061 .word L2-L1
1062 The r_offset field holds the difference between the reloc
1063 address and L1. That is the start of the reloc, and
1064 adding in the contents gives us the top. We must adjust
1065 both the r_offset field and the section contents. */
1066
1067 start = irel->r_vaddr - sec->vma;
1068 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1069
1070 if (start > addr
1071 && start < toaddr
1072 && (stop <= addr || stop >= toaddr))
1073 irel->r_offset += count;
1074 else if (stop > addr
1075 && stop < toaddr
1076 && (start <= addr || start >= toaddr))
1077 irel->r_offset -= count;
1078
1079 start = stop;
1080
1081 if (irel->r_type == R_SH_SWITCH16)
1082 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1083 else if (irel->r_type == R_SH_SWITCH8)
1084 voff = bfd_get_8 (abfd, contents + nraddr);
1085 else
1086 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1087 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1088
1089 break;
1090
1091 case R_SH_USES:
1092 start = irel->r_vaddr - sec->vma;
1093 stop = (bfd_vma) ((bfd_signed_vma) start
1094 + (long) irel->r_offset
1095 + 4);
1096 break;
1097 }
1098
1099 if (start > addr
1100 && start < toaddr
1101 && (stop <= addr || stop >= toaddr))
1102 adjust = count;
1103 else if (stop > addr
1104 && stop < toaddr
1105 && (start <= addr || start >= toaddr))
1106 adjust = - count;
1107 else
1108 adjust = 0;
1109
1110 if (adjust != 0)
1111 {
1112 oinsn = insn;
1113 overflow = false;
1114 switch (irel->r_type)
1115 {
1116 default:
1117 abort ();
1118 break;
1119
1120 case R_SH_PCDISP8BY2:
1121 case R_SH_PCRELIMM8BY2:
1122 insn += adjust / 2;
1123 if ((oinsn & 0xff00) != (insn & 0xff00))
1124 overflow = true;
1125 bfd_put_16 (abfd, insn, contents + nraddr);
1126 break;
1127
1128 case R_SH_PCDISP:
1129 insn += adjust / 2;
1130 if ((oinsn & 0xf000) != (insn & 0xf000))
1131 overflow = true;
1132 bfd_put_16 (abfd, insn, contents + nraddr);
1133 break;
1134
1135 case R_SH_PCRELIMM8BY4:
1136 BFD_ASSERT (adjust == count || count >= 4);
1137 if (count >= 4)
1138 insn += adjust / 4;
1139 else
1140 {
1141 if ((irel->r_vaddr & 3) == 0)
1142 ++insn;
1143 }
1144 if ((oinsn & 0xff00) != (insn & 0xff00))
1145 overflow = true;
1146 bfd_put_16 (abfd, insn, contents + nraddr);
1147 break;
1148
1149 case R_SH_SWITCH8:
1150 voff += adjust;
1151 if (voff < 0 || voff >= 0xff)
1152 overflow = true;
1153 bfd_put_8 (abfd, voff, contents + nraddr);
1154 break;
1155
1156 case R_SH_SWITCH16:
1157 voff += adjust;
1158 if (voff < - 0x8000 || voff >= 0x8000)
1159 overflow = true;
1160 bfd_put_signed_16 (abfd, voff, contents + nraddr);
1161 break;
1162
1163 case R_SH_SWITCH32:
1164 voff += adjust;
1165 bfd_put_signed_32 (abfd, voff, contents + nraddr);
1166 break;
1167
1168 case R_SH_USES:
1169 irel->r_offset += adjust;
1170 break;
1171 }
1172
1173 if (overflow)
1174 {
1175 ((*_bfd_error_handler)
1176 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
1177 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
1178 bfd_set_error (bfd_error_bad_value);
1179 return false;
1180 }
1181 }
1182
1183 irel->r_vaddr = nraddr + sec->vma;
1184 }
1185
1186 /* Look through all the other sections. If there contain any IMM32
1187 relocs against internal symbols which we are not going to adjust
1188 below, we may need to adjust the addends. */
1189 for (o = abfd->sections; o != NULL; o = o->next)
1190 {
1191 struct internal_reloc *internal_relocs;
1192 struct internal_reloc *irelscan, *irelscanend;
1193 bfd_byte *ocontents;
1194
1195 if (o == sec
1196 || (o->flags & SEC_RELOC) == 0
1197 || o->reloc_count == 0)
1198 continue;
1199
1200 /* We always cache the relocs. Perhaps, if info->keep_memory is
1201 false, we should free them, if we are permitted to, when we
1202 leave sh_coff_relax_section. */
1203 internal_relocs = (_bfd_coff_read_internal_relocs
1204 (abfd, o, true, (bfd_byte *) NULL, false,
1205 (struct internal_reloc *) NULL));
1206 if (internal_relocs == NULL)
1207 return false;
1208
1209 ocontents = NULL;
1210 irelscanend = internal_relocs + o->reloc_count;
1211 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1212 {
1213 struct internal_syment sym;
1214
1215 if (irelscan->r_type != R_SH_IMM32)
1216 continue;
1217
1218 bfd_coff_swap_sym_in (abfd,
1219 ((bfd_byte *) obj_coff_external_syms (abfd)
1220 + (irelscan->r_symndx
1221 * bfd_coff_symesz (abfd))),
1222 &sym);
1223 if (sym.n_sclass != C_EXT
1224 && sym.n_scnum == sec->target_index
1225 && ((bfd_vma) sym.n_value <= addr
1226 || (bfd_vma) sym.n_value >= toaddr))
1227 {
1228 bfd_vma val;
1229
1230 if (ocontents == NULL)
1231 {
1232 if (coff_section_data (abfd, o)->contents != NULL)
1233 ocontents = coff_section_data (abfd, o)->contents;
1234 else
1235 {
1236 /* We always cache the section contents.
1237 Perhaps, if info->keep_memory is false, we
1238 should free them, if we are permitted to,
1239 when we leave sh_coff_relax_section. */
1240 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size);
1241 if (ocontents == NULL)
1242 return false;
1243 if (! bfd_get_section_contents (abfd, o, ocontents,
1244 (file_ptr) 0,
1245 o->_raw_size))
1246 return false;
1247 coff_section_data (abfd, o)->contents = ocontents;
1248 }
1249 }
1250
1251 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1252 val += sym.n_value;
1253 if (val > addr && val < toaddr)
1254 bfd_put_32 (abfd, val - count,
1255 ocontents + irelscan->r_vaddr - o->vma);
1256
1257 coff_section_data (abfd, o)->keep_contents = true;
1258 }
1259 }
1260 }
1261
1262 /* Adjusting the internal symbols will not work if something has
1263 already retrieved the generic symbols. It would be possible to
1264 make this work by adjusting the generic symbols at the same time.
1265 However, this case should not arise in normal usage. */
1266 if (obj_symbols (abfd) != NULL
1267 || obj_raw_syments (abfd) != NULL)
1268 {
1269 ((*_bfd_error_handler)
1270 ("%s: fatal: generic symbols retrieved before relaxing",
1271 bfd_get_filename (abfd)));
1272 bfd_set_error (bfd_error_invalid_operation);
1273 return false;
1274 }
1275
1276 /* Adjust all the symbols. */
1277 sym_hash = obj_coff_sym_hashes (abfd);
1278 symesz = bfd_coff_symesz (abfd);
1279 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1280 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1281 while (esym < esymend)
1282 {
1283 struct internal_syment isym;
1284
1285 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1286
1287 if (isym.n_scnum == sec->target_index
1288 && (bfd_vma) isym.n_value > addr
1289 && (bfd_vma) isym.n_value < toaddr)
1290 {
1291 isym.n_value -= count;
1292
1293 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1294
1295 if (*sym_hash != NULL)
1296 {
1297 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1298 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1299 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1300 && (*sym_hash)->root.u.def.value < toaddr);
1301 (*sym_hash)->root.u.def.value -= count;
1302 }
1303 }
1304
1305 esym += (isym.n_numaux + 1) * symesz;
1306 sym_hash += isym.n_numaux + 1;
1307 }
1308
1309 /* See if we can move the ALIGN reloc forward. We have adjusted
1310 r_vaddr for it already. */
1311 if (irelalign != NULL)
1312 {
1313 bfd_vma alignto, alignaddr;
1314
1315 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1316 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1317 1 << irelalign->r_offset);
1318 if (alignto != alignaddr)
1319 {
1320 /* Tail recursion. */
1321 return sh_relax_delete_bytes (abfd, sec, alignaddr,
1322 alignto - alignaddr);
1323 }
1324 }
1325
1326 return true;
1327}
1328\f
1329/* This is yet another version of the SH opcode table, used to rapidly
1330 get information about a particular instruction. */
1331
1332/* The opcode map is represented by an array of these structures. The
1333 array is indexed by the high order four bits in the instruction. */
1334
1335struct sh_major_opcode
1336{
1337 /* A pointer to the instruction list. This is an array which
1338 contains all the instructions with this major opcode. */
1339 const struct sh_minor_opcode *minor_opcodes;
1340 /* The number of elements in minor_opcodes. */
1341 unsigned short count;
1342};
1343
1344/* This structure holds information for a set of SH opcodes. The
1345 instruction code is anded with the mask value, and the resulting
1346 value is used to search the order opcode list. */
1347
1348struct sh_minor_opcode
1349{
1350 /* The sorted opcode list. */
1351 const struct sh_opcode *opcodes;
1352 /* The number of elements in opcodes. */
1353 unsigned short count;
1354 /* The mask value to use when searching the opcode list. */
1355 unsigned short mask;
1356};
1357
1358/* This structure holds information for an SH instruction. An array
1359 of these structures is sorted in order by opcode. */
1360
1361struct sh_opcode
1362{
1363 /* The code for this instruction, after it has been anded with the
1364 mask value in the sh_major_opcode structure. */
1365 unsigned short opcode;
1366 /* Flags for this instruction. */
1367 unsigned short flags;
1368};
1369
1370/* Flag which appear in the sh_opcode structure. */
1371
1372/* This instruction loads a value from memory. */
1373#define LOAD (0x1)
1374
1375/* This instruction stores a value to memory. */
1376#define STORE (0x2)
1377
1378/* This instruction is a branch. */
1379#define BRANCH (0x4)
1380
1381/* This instruction has a delay slot. */
1382#define DELAY (0x8)
1383
1384/* This instruction uses the value in the register in the field at
1385 mask 0x0f00 of the instruction. */
1386#define USES1 (0x10)
1387
1388/* This instruction uses the value in the register in the field at
1389 mask 0x00f0 of the instruction. */
1390#define USES2 (0x20)
1391
1392/* This instruction uses the value in register 0. */
1393#define USESR0 (0x40)
1394
1395/* This instruction sets the value in the register in the field at
1396 mask 0x0f00 of the instruction. */
1397#define SETS1 (0x80)
1398
1399/* This instruction sets the value in the register in the field at
1400 mask 0x00f0 of the instruction. */
1401#define SETS2 (0x100)
1402
1403/* This instruction sets register 0. */
1404#define SETSR0 (0x200)
1405
1406/* This instruction sets a special register. */
1407#define SETSSP (0x400)
1408
1409/* This instruction uses a special register. */
1410#define USESSP (0x800)
1411
1412/* This instruction uses the floating point register in the field at
1413 mask 0x0f00 of the instruction. */
1414#define USESF1 (0x1000)
1415
1416/* This instruction uses the floating point register in the field at
1417 mask 0x00f0 of the instruction. */
1418#define USESF2 (0x2000)
1419
1420/* This instruction uses floating point register 0. */
1421#define USESF0 (0x4000)
1422
1423/* This instruction sets the floating point register in the field at
1424 mask 0x0f00 of the instruction. */
1425#define SETSF1 (0x8000)
1426
1427static boolean sh_insn_uses_reg
1428 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1429static boolean sh_insn_uses_freg
1430 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1431static boolean sh_insns_conflict
1432 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1433 const struct sh_opcode *));
1434static boolean sh_load_use
1435 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1436 const struct sh_opcode *));
1437
1438/* The opcode maps. */
1439
1440#define MAP(a) a, sizeof a / sizeof a[0]
1441
1442static const struct sh_opcode sh_opcode00[] =
1443{
1444 { 0x0008, SETSSP }, /* clrt */
1445 { 0x0009, 0 }, /* nop */
1446 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1447 { 0x0018, SETSSP }, /* sett */
1448 { 0x0019, SETSSP }, /* div0u */
1449 { 0x001b, 0 }, /* sleep */
1450 { 0x0028, SETSSP }, /* clrmac */
1451 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1452 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1453 { 0x0048, SETSSP }, /* clrs */
1454 { 0x0058, SETSSP } /* sets */
1455};
1456
1457static const struct sh_opcode sh_opcode01[] =
1458{
1459 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1460 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1461 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
1462 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1463 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
1464 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
1465 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1466 { 0x0029, SETS1 | USESSP }, /* movt rn */
1467 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
1468 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1469 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
1470 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1471 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn */
1472 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
1473 { 0x0083, LOAD | USES1 }, /* pref @rn */
1474 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1475 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1476 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1477 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1478 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1479 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1480 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
1481};
1482
1483static const struct sh_opcode sh_opcode02[] =
1484{
1485 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1486 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1487 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1488 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1489 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1490 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1491 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1492 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1493};
1494
1495static const struct sh_minor_opcode sh_opcode0[] =
1496{
1497 { MAP (sh_opcode00), 0xffff },
1498 { MAP (sh_opcode01), 0xf0ff },
1499 { MAP (sh_opcode02), 0xf00f }
1500};
1501
1502static const struct sh_opcode sh_opcode10[] =
1503{
1504 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1505};
1506
1507static const struct sh_minor_opcode sh_opcode1[] =
1508{
1509 { MAP (sh_opcode10), 0xf000 }
1510};
1511
1512static const struct sh_opcode sh_opcode20[] =
1513{
1514 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1515 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1516 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1517 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1518 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1519 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1520 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1521 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1522 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1523 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1524 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1525 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1526 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1527 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1528 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1529};
1530
1531static const struct sh_minor_opcode sh_opcode2[] =
1532{
1533 { MAP (sh_opcode20), 0xf00f }
1534};
1535
1536static const struct sh_opcode sh_opcode30[] =
1537{
1538 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1539 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1540 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1541 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1542 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1543 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1544 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1545 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1546 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1547 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1548 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1549 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1550 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1551 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1552};
1553
1554static const struct sh_minor_opcode sh_opcode3[] =
1555{
1556 { MAP (sh_opcode30), 0xf00f }
1557};
1558
1559static const struct sh_opcode sh_opcode40[] =
1560{
1561 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1562 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1563 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1564 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1565 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1566 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1567 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
1568 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1569 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1570 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1571 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1572 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
1573 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1574 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1575 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1576 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1577 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1578 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1579 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
1580 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1581 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1582 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1583 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1584 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
1585 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1586 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1587 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1588 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1589 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
1590 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1591 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1592 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
1593 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1594 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1595 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1596 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1597 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
1598 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1599 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
1600 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
1601 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
1602 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
1603 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
1604 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
1605 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1606 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1607 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1608 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr,@-rn */
1609 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr */
1610 { 0x406a, SETSSP | USES1 } /* lds rm,fpscr */
1611};
1612
1613static const struct sh_opcode sh_opcode41[] =
1614{
1615 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l rx_bank,@-rn */
1616 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rx_bank */
1617 { 0x408e, SETSSP | USES1 } /* ldc rm,rx_bank */
1618};
1619
1620static const struct sh_opcode sh_opcode42[] =
1621{
1622 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1623 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1624 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1625};
1626
1627static const struct sh_minor_opcode sh_opcode4[] =
1628{
1629 { MAP (sh_opcode40), 0xf0ff },
1630 { MAP (sh_opcode41), 0xf08f },
1631 { MAP (sh_opcode42), 0xf00f }
1632};
1633
1634static const struct sh_opcode sh_opcode50[] =
1635{
1636 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1637};
1638
1639static const struct sh_minor_opcode sh_opcode5[] =
1640{
1641 { MAP (sh_opcode50), 0xf000 }
1642};
1643
1644static const struct sh_opcode sh_opcode60[] =
1645{
1646 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1647 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1648 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1649 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1650 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1651 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1652 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1653 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1654 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1655 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1656 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1657 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1658 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1659 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1660 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1661 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1662};
1663
1664static const struct sh_minor_opcode sh_opcode6[] =
1665{
1666 { MAP (sh_opcode60), 0xf00f }
1667};
1668
1669static const struct sh_opcode sh_opcode70[] =
1670{
1671 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1672};
1673
1674static const struct sh_minor_opcode sh_opcode7[] =
1675{
1676 { MAP (sh_opcode70), 0xf000 }
1677};
1678
1679static const struct sh_opcode sh_opcode80[] =
1680{
1681 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1682 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1683 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1684 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1685 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1686 { 0x8900, BRANCH | USESSP }, /* bt label */
1687 { 0x8b00, BRANCH | USESSP }, /* bf label */
1688 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
1689 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1690};
1691
1692static const struct sh_minor_opcode sh_opcode8[] =
1693{
1694 { MAP (sh_opcode80), 0xff00 }
1695};
1696
1697static const struct sh_opcode sh_opcode90[] =
1698{
1699 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1700};
1701
1702static const struct sh_minor_opcode sh_opcode9[] =
1703{
1704 { MAP (sh_opcode90), 0xf000 }
1705};
1706
1707static const struct sh_opcode sh_opcodea0[] =
1708{
1709 { 0xa000, BRANCH | DELAY } /* bra label */
1710};
1711
1712static const struct sh_minor_opcode sh_opcodea[] =
1713{
1714 { MAP (sh_opcodea0), 0xf000 }
1715};
1716
1717static const struct sh_opcode sh_opcodeb0[] =
1718{
1719 { 0xb000, BRANCH | DELAY } /* bsr label */
1720};
1721
1722static const struct sh_minor_opcode sh_opcodeb[] =
1723{
1724 { MAP (sh_opcodeb0), 0xf000 }
1725};
1726
1727static const struct sh_opcode sh_opcodec0[] =
1728{
1729 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1730 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1731 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1732 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1733 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1734 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1735 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1736 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1737 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1738 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1739 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1740 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1741 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1742 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1743 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1744 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1745};
1746
1747static const struct sh_minor_opcode sh_opcodec[] =
1748{
1749 { MAP (sh_opcodec0), 0xff00 }
1750};
1751
1752static const struct sh_opcode sh_opcoded0[] =
1753{
1754 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1755};
1756
1757static const struct sh_minor_opcode sh_opcoded[] =
1758{
1759 { MAP (sh_opcoded0), 0xf000 }
1760};
1761
1762static const struct sh_opcode sh_opcodee0[] =
1763{
1764 { 0xe000, SETS1 } /* mov #imm,rn */
1765};
1766
1767static const struct sh_minor_opcode sh_opcodee[] =
1768{
1769 { MAP (sh_opcodee0), 0xf000 }
1770};
1771
1772static const struct sh_opcode sh_opcodef0[] =
1773{
1774 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1775 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1776 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1777 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1778 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1779 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1780 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1781 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1782 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1783 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1784 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1785 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1786 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1787 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1788};
1789
1790static const struct sh_opcode sh_opcodef1[] =
1791{
1792 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1793 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1794 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1795 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1796 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1797 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1798 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1799 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1800 { 0xf08d, SETSF1 }, /* fldi0 fn */
1801 { 0xf09d, SETSF1 } /* fldi1 fn */
1802};
1803
1804static const struct sh_minor_opcode sh_opcodef[] =
1805{
1806 { MAP (sh_opcodef0), 0xf00f },
1807 { MAP (sh_opcodef1), 0xf0ff }
1808};
1809
1810static const struct sh_major_opcode sh_opcodes[] =
1811{
1812 { MAP (sh_opcode0) },
1813 { MAP (sh_opcode1) },
1814 { MAP (sh_opcode2) },
1815 { MAP (sh_opcode3) },
1816 { MAP (sh_opcode4) },
1817 { MAP (sh_opcode5) },
1818 { MAP (sh_opcode6) },
1819 { MAP (sh_opcode7) },
1820 { MAP (sh_opcode8) },
1821 { MAP (sh_opcode9) },
1822 { MAP (sh_opcodea) },
1823 { MAP (sh_opcodeb) },
1824 { MAP (sh_opcodec) },
1825 { MAP (sh_opcoded) },
1826 { MAP (sh_opcodee) },
1827 { MAP (sh_opcodef) }
1828};
1829
1830/* Given an instruction, return a pointer to the corresponding
1831 sh_opcode structure. Return NULL if the instruction is not
1832 recognized. */
1833
1834static const struct sh_opcode *
1835sh_insn_info (insn)
1836 unsigned int insn;
1837{
1838 const struct sh_major_opcode *maj;
1839 const struct sh_minor_opcode *min, *minend;
1840
1841 maj = &sh_opcodes[(insn & 0xf000) >> 12];
1842 min = maj->minor_opcodes;
1843 minend = min + maj->count;
1844 for (; min < minend; min++)
1845 {
1846 unsigned int l;
1847 const struct sh_opcode *op, *opend;
1848
1849 l = insn & min->mask;
1850 op = min->opcodes;
1851 opend = op + min->count;
1852
1853 /* Since the opcodes tables are sorted, we could use a binary
1854 search here if the count were above some cutoff value. */
1855 for (; op < opend; op++)
1856 if (op->opcode == l)
1857 return op;
1858 }
1859
1860 return NULL;
1861}
1862
1863/* See whether an instruction uses a general purpose register. */
1864
1865static boolean
1866sh_insn_uses_reg (insn, op, reg)
1867 unsigned int insn;
1868 const struct sh_opcode *op;
1869 unsigned int reg;
1870{
1871 unsigned int f;
1872
1873 f = op->flags;
1874
1875 if ((f & USES1) != 0
1876 && ((insn & 0x0f00) >> 8) == reg)
1877 return true;
1878 if ((f & USES2) != 0
1879 && ((insn & 0x00f0) >> 4) == reg)
1880 return true;
1881 if ((f & USESR0) != 0
1882 && reg == 0)
1883 return true;
1884
1885 return false;
1886}
1887
1888/* See whether an instruction uses a floating point register. */
1889
1890static boolean
1891sh_insn_uses_freg (insn, op, freg)
1892 unsigned int insn;
1893 const struct sh_opcode *op;
1894 unsigned int freg;
1895{
1896 unsigned int f;
1897
1898 f = op->flags;
1899
1900 /* We can't tell if this is a double-precision insn, so just play safe
1901 and assume that it might be. So not only have we test FREG against
1902 itself, but also even FREG against FREG+1 - if the using insn uses
1903 just the low part of a double precision value - but also an odd
1904 FREG against FREG-1 - if the setting insn sets just the low part
1905 of a double precision value.
1906 So what this all boils down to is that we have to ignore the lowest
1907 bit of the register number. */
1908
1909 if ((f & USESF1) != 0
1910 && ((insn & 0x0e00) >> 8) == (freg & 0xe))
1911 return true;
1912 if ((f & USESF2) != 0
1913 && ((insn & 0x00e0) >> 4) == (freg & 0xe))
1914 return true;
1915 if ((f & USESF0) != 0
1916 && freg == 0)
1917 return true;
1918
1919 return false;
1920}
1921
1922/* See whether instructions I1 and I2 conflict, assuming I1 comes
1923 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
1924 This should return true if there is a conflict, or false if the
1925 instructions can be swapped safely. */
1926
1927static boolean
1928sh_insns_conflict (i1, op1, i2, op2)
1929 unsigned int i1;
1930 const struct sh_opcode *op1;
1931 unsigned int i2;
1932 const struct sh_opcode *op2;
1933{
1934 unsigned int f1, f2;
1935
1936 f1 = op1->flags;
1937 f2 = op2->flags;
1938
1939 /* Load of fpscr conflicts with floating point operations.
1940 FIXME: shouldn't test raw opcodes here. */
1941 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
1942 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
1943 return true;
1944
1945 if ((f1 & (BRANCH | DELAY)) != 0
1946 || (f2 & (BRANCH | DELAY)) != 0)
1947 return true;
1948
1949 if ((f1 & SETSSP) != 0 && (f2 & USESSP) != 0)
1950 return true;
1951 if ((f2 & SETSSP) != 0 && (f1 & USESSP) != 0)
1952 return true;
1953
1954 if ((f1 & SETS1) != 0
1955 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
1956 return true;
1957 if ((f1 & SETS2) != 0
1958 && sh_insn_uses_reg (i2, op2, (i1 & 0x00f0) >> 4))
1959 return true;
1960 if ((f1 & SETSR0) != 0
1961 && sh_insn_uses_reg (i2, op2, 0))
1962 return true;
1963 if ((f1 & SETSF1) != 0
1964 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
1965 return true;
1966
1967 if ((f2 & SETS1) != 0
1968 && sh_insn_uses_reg (i1, op1, (i2 & 0x0f00) >> 8))
1969 return true;
1970 if ((f2 & SETS2) != 0
1971 && sh_insn_uses_reg (i1, op1, (i2 & 0x00f0) >> 4))
1972 return true;
1973 if ((f2 & SETSR0) != 0
1974 && sh_insn_uses_reg (i1, op1, 0))
1975 return true;
1976 if ((f2 & SETSF1) != 0
1977 && sh_insn_uses_freg (i1, op1, (i2 & 0x0f00) >> 8))
1978 return true;
1979
1980 /* The instructions do not conflict. */
1981 return false;
1982}
1983
1984/* I1 is a load instruction, and I2 is some other instruction. Return
1985 true if I1 loads a register which I2 uses. */
1986
1987static boolean
1988sh_load_use (i1, op1, i2, op2)
1989 unsigned int i1;
1990 const struct sh_opcode *op1;
1991 unsigned int i2;
1992 const struct sh_opcode *op2;
1993{
1994 unsigned int f1;
1995
1996 f1 = op1->flags;
1997
1998 if ((f1 & LOAD) == 0)
1999 return false;
2000
2001 /* If both SETS1 and SETSSP are set, that means a load to a special
2002 register using postincrement addressing mode, which we don't care
2003 about here. */
2004 if ((f1 & SETS1) != 0
2005 && (f1 & SETSSP) == 0
2006 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
2007 return true;
2008
2009 if ((f1 & SETSR0) != 0
2010 && sh_insn_uses_reg (i2, op2, 0))
2011 return true;
2012
2013 if ((f1 & SETSF1) != 0
2014 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
2015 return true;
2016
2017 return false;
2018}
2019
2020/* Try to align loads and stores within a span of memory. This is
2021 called by both the ELF and the COFF sh targets. ABFD and SEC are
2022 the BFD and section we are examining. CONTENTS is the contents of
2023 the section. SWAP is the routine to call to swap two instructions.
2024 RELOCS is a pointer to the internal relocation information, to be
2025 passed to SWAP. PLABEL is a pointer to the current label in a
2026 sorted list of labels; LABEL_END is the end of the list. START and
2027 STOP are the range of memory to examine. If a swap is made,
2028 *PSWAPPED is set to true. */
2029
2030boolean
2031_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2032 plabel, label_end, start, stop, pswapped)
2033 bfd *abfd;
2034 asection *sec;
2035 bfd_byte *contents;
2036 boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
2037 PTR relocs;
2038 bfd_vma **plabel;
2039 bfd_vma *label_end;
2040 bfd_vma start;
2041 bfd_vma stop;
2042 boolean *pswapped;
2043{
2044 bfd_vma i;
2045
2046 /* Instructions should be aligned on 2 byte boundaries. */
2047 if ((start & 1) == 1)
2048 ++start;
2049
2050 /* Now look through the unaligned addresses. */
2051 i = start;
2052 if ((i & 2) == 0)
2053 i += 2;
2054 for (; i < stop; i += 4)
2055 {
2056 unsigned int insn;
2057 const struct sh_opcode *op;
2058 unsigned int prev_insn = 0;
2059 const struct sh_opcode *prev_op = NULL;
2060
2061 insn = bfd_get_16 (abfd, contents + i);
2062 op = sh_insn_info (insn);
2063 if (op == NULL
2064 || (op->flags & (LOAD | STORE)) == 0)
2065 continue;
2066
2067 /* This is a load or store which is not on a four byte boundary. */
2068
2069 while (*plabel < label_end && **plabel < i)
2070 ++*plabel;
2071
2072 if (i > start)
2073 {
2074 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2075 prev_op = sh_insn_info (prev_insn);
2076
2077 /* If the load/store instruction is in a delay slot, we
2078 can't swap. */
2079 if (prev_op == NULL
2080 || (prev_op->flags & DELAY) != 0)
2081 continue;
2082 }
2083 if (i > start
2084 && (*plabel >= label_end || **plabel != i)
2085 && prev_op != NULL
2086 && (prev_op->flags & (LOAD | STORE)) == 0
2087 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2088 {
2089 boolean ok;
2090
2091 /* The load/store instruction does not have a label, and
2092 there is a previous instruction; PREV_INSN is not
2093 itself a load/store instruction, and PREV_INSN and
2094 INSN do not conflict. */
2095
2096 ok = true;
2097
2098 if (i >= start + 4)
2099 {
2100 unsigned int prev2_insn;
2101 const struct sh_opcode *prev2_op;
2102
2103 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2104 prev2_op = sh_insn_info (prev2_insn);
2105
2106 /* If the instruction before PREV_INSN has a delay
2107 slot--that is, PREV_INSN is in a delay slot--we
2108 can not swap. */
2109 if (prev2_op == NULL
2110 || (prev2_op->flags & DELAY) != 0)
2111 ok = false;
2112
2113 /* If the instruction before PREV_INSN is a load,
2114 and it sets a register which INSN uses, then
2115 putting INSN immediately after PREV_INSN will
2116 cause a pipeline bubble, so there is no point to
2117 making the swap. */
2118 if (ok
2119 && (prev2_op->flags & LOAD) != 0
2120 && sh_load_use (prev2_insn, prev2_op, insn, op))
2121 ok = false;
2122 }
2123
2124 if (ok)
2125 {
2126 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2127 return false;
2128 *pswapped = true;
2129 continue;
2130 }
2131 }
2132
2133 while (*plabel < label_end && **plabel < i + 2)
2134 ++*plabel;
2135
2136 if (i + 2 < stop
2137 && (*plabel >= label_end || **plabel != i + 2))
2138 {
2139 unsigned int next_insn;
2140 const struct sh_opcode *next_op;
2141
2142 /* There is an instruction after the load/store
2143 instruction, and it does not have a label. */
2144 next_insn = bfd_get_16 (abfd, contents + i + 2);
2145 next_op = sh_insn_info (next_insn);
2146 if (next_op != NULL
2147 && (next_op->flags & (LOAD | STORE)) == 0
2148 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2149 {
2150 boolean ok;
2151
2152 /* NEXT_INSN is not itself a load/store instruction,
2153 and it does not conflict with INSN. */
2154
2155 ok = true;
2156
2157 /* If PREV_INSN is a load, and it sets a register
2158 which NEXT_INSN uses, then putting NEXT_INSN
2159 immediately after PREV_INSN will cause a pipeline
2160 bubble, so there is no reason to make this swap. */
2161 if (prev_op != NULL
2162 && (prev_op->flags & LOAD) != 0
2163 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2164 ok = false;
2165
2166 /* If INSN is a load, and it sets a register which
2167 the insn after NEXT_INSN uses, then doing the
2168 swap will cause a pipeline bubble, so there is no
2169 reason to make the swap. However, if the insn
2170 after NEXT_INSN is itself a load or store
2171 instruction, then it is misaligned, so
2172 optimistically hope that it will be swapped
2173 itself, and just live with the pipeline bubble if
2174 it isn't. */
2175 if (ok
2176 && i + 4 < stop
2177 && (op->flags & LOAD) != 0)
2178 {
2179 unsigned int next2_insn;
2180 const struct sh_opcode *next2_op;
2181
2182 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2183 next2_op = sh_insn_info (next2_insn);
2184 if ((next2_op->flags & (LOAD | STORE)) == 0
2185 && sh_load_use (insn, op, next2_insn, next2_op))
2186 ok = false;
2187 }
2188
2189 if (ok)
2190 {
2191 if (! (*swap) (abfd, sec, relocs, contents, i))
2192 return false;
2193 *pswapped = true;
2194 continue;
2195 }
2196 }
2197 }
2198 }
2199
2200 return true;
2201}
2202
2203/* Look for loads and stores which we can align to four byte
2204 boundaries. See the longer comment above sh_relax_section for why
2205 this is desirable. This sets *PSWAPPED if some instruction was
2206 swapped. */
2207
2208static boolean
2209sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2210 bfd *abfd;
2211 asection *sec;
2212 struct internal_reloc *internal_relocs;
2213 bfd_byte *contents;
2214 boolean *pswapped;
2215{
2216 struct internal_reloc *irel, *irelend;
2217 bfd_vma *labels = NULL;
2218 bfd_vma *label, *label_end;
2219
2220 *pswapped = false;
2221
2222 irelend = internal_relocs + sec->reloc_count;
2223
2224 /* Get all the addresses with labels on them. */
2225 labels = (bfd_vma *) bfd_malloc (sec->reloc_count * sizeof (bfd_vma));
2226 if (labels == NULL)
2227 goto error_return;
2228 label_end = labels;
2229 for (irel = internal_relocs; irel < irelend; irel++)
2230 {
2231 if (irel->r_type == R_SH_LABEL)
2232 {
2233 *label_end = irel->r_vaddr - sec->vma;
2234 ++label_end;
2235 }
2236 }
2237
2238 /* Note that the assembler currently always outputs relocs in
2239 address order. If that ever changes, this code will need to sort
2240 the label values and the relocs. */
2241
2242 label = labels;
2243
2244 for (irel = internal_relocs; irel < irelend; irel++)
2245 {
2246 bfd_vma start, stop;
2247
2248 if (irel->r_type != R_SH_CODE)
2249 continue;
2250
2251 start = irel->r_vaddr - sec->vma;
2252
2253 for (irel++; irel < irelend; irel++)
2254 if (irel->r_type == R_SH_DATA)
2255 break;
2256 if (irel < irelend)
2257 stop = irel->r_vaddr - sec->vma;
2258 else
2259 stop = sec->_cooked_size;
2260
2261 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2262 (PTR) internal_relocs, &label,
2263 label_end, start, stop, pswapped))
2264 goto error_return;
2265 }
2266
2267 free (labels);
2268
2269 return true;
2270
2271 error_return:
2272 if (labels != NULL)
2273 free (labels);
2274 return false;
2275}
2276
2277/* Swap two SH instructions. */
2278
2279static boolean
2280sh_swap_insns (abfd, sec, relocs, contents, addr)
2281 bfd *abfd;
2282 asection *sec;
2283 PTR relocs;
2284 bfd_byte *contents;
2285 bfd_vma addr;
2286{
2287 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2288 unsigned short i1, i2;
2289 struct internal_reloc *irel, *irelend;
2290
2291 /* Swap the instructions themselves. */
2292 i1 = bfd_get_16 (abfd, contents + addr);
2293 i2 = bfd_get_16 (abfd, contents + addr + 2);
2294 bfd_put_16 (abfd, i2, contents + addr);
2295 bfd_put_16 (abfd, i1, contents + addr + 2);
2296
2297 /* Adjust all reloc addresses. */
2298 irelend = internal_relocs + sec->reloc_count;
2299 for (irel = internal_relocs; irel < irelend; irel++)
2300 {
2301 int type, add;
2302
2303 /* There are a few special types of relocs that we don't want to
2304 adjust. These relocs do not apply to the instruction itself,
2305 but are only associated with the address. */
2306 type = irel->r_type;
2307 if (type == R_SH_ALIGN
2308 || type == R_SH_CODE
2309 || type == R_SH_DATA
2310 || type == R_SH_LABEL)
2311 continue;
2312
2313 /* If an R_SH_USES reloc points to one of the addresses being
2314 swapped, we must adjust it. It would be incorrect to do this
2315 for a jump, though, since we want to execute both
2316 instructions after the jump. (We have avoided swapping
2317 around a label, so the jump will not wind up executing an
2318 instruction it shouldn't). */
2319 if (type == R_SH_USES)
2320 {
2321 bfd_vma off;
2322
2323 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2324 if (off == addr)
2325 irel->r_offset += 2;
2326 else if (off == addr + 2)
2327 irel->r_offset -= 2;
2328 }
2329
2330 if (irel->r_vaddr - sec->vma == addr)
2331 {
2332 irel->r_vaddr += 2;
2333 add = -2;
2334 }
2335 else if (irel->r_vaddr - sec->vma == addr + 2)
2336 {
2337 irel->r_vaddr -= 2;
2338 add = 2;
2339 }
2340 else
2341 add = 0;
2342
2343 if (add != 0)
2344 {
2345 bfd_byte *loc;
2346 unsigned short insn, oinsn;
2347 boolean overflow;
2348
2349 loc = contents + irel->r_vaddr - sec->vma;
2350 overflow = false;
2351 switch (type)
2352 {
2353 default:
2354 break;
2355
2356 case R_SH_PCDISP8BY2:
2357 case R_SH_PCRELIMM8BY2:
2358 insn = bfd_get_16 (abfd, loc);
2359 oinsn = insn;
2360 insn += add / 2;
2361 if ((oinsn & 0xff00) != (insn & 0xff00))
2362 overflow = true;
2363 bfd_put_16 (abfd, insn, loc);
2364 break;
2365
2366 case R_SH_PCDISP:
2367 insn = bfd_get_16 (abfd, loc);
2368 oinsn = insn;
2369 insn += add / 2;
2370 if ((oinsn & 0xf000) != (insn & 0xf000))
2371 overflow = true;
2372 bfd_put_16 (abfd, insn, loc);
2373 break;
2374
2375 case R_SH_PCRELIMM8BY4:
2376 /* This reloc ignores the least significant 3 bits of
2377 the program counter before adding in the offset.
2378 This means that if ADDR is at an even address, the
2379 swap will not affect the offset. If ADDR is an at an
2380 odd address, then the instruction will be crossing a
2381 four byte boundary, and must be adjusted. */
2382 if ((addr & 3) != 0)
2383 {
2384 insn = bfd_get_16 (abfd, loc);
2385 oinsn = insn;
2386 insn += add / 2;
2387 if ((oinsn & 0xff00) != (insn & 0xff00))
2388 overflow = true;
2389 bfd_put_16 (abfd, insn, loc);
2390 }
2391
2392 break;
2393 }
2394
2395 if (overflow)
2396 {
2397 ((*_bfd_error_handler)
2398 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
2399 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
2400 bfd_set_error (bfd_error_bad_value);
2401 return false;
2402 }
2403 }
2404 }
2405
2406 return true;
2407}
2408\f
2409/* This is a modification of _bfd_coff_generic_relocate_section, which
2410 will handle SH relaxing. */
2411
2412static boolean
2413sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2414 relocs, syms, sections)
5f771d47 2415 bfd *output_bfd ATTRIBUTE_UNUSED;
252b5132
RH		 2416 struct bfd_link_info *info;
2417 bfd *input_bfd;
2418 asection *input_section;
2419 bfd_byte *contents;
2420 struct internal_reloc *relocs;
2421 struct internal_syment *syms;
2422 asection **sections;
2423{
2424 struct internal_reloc *rel;
2425 struct internal_reloc *relend;
2426
2427 rel = relocs;
2428 relend = rel + input_section->reloc_count;
2429 for (; rel < relend; rel++)
2430 {
2431 long symndx;
2432 struct coff_link_hash_entry *h;
2433 struct internal_syment *sym;
2434 bfd_vma addend;
2435 bfd_vma val;
2436 reloc_howto_type *howto;
2437 bfd_reloc_status_type rstat;
2438
2439 /* Almost all relocs have to do with relaxing. If any work must
2440 be done for them, it has been done in sh_relax_section. */
2441 if (rel->r_type != R_SH_IMM32
2442 && rel->r_type != R_SH_PCDISP)
2443 continue;
2444
2445 symndx = rel->r_symndx;
2446
2447 if (symndx == -1)
2448 {
2449 h = NULL;
2450 sym = NULL;
2451 }
2452 else
2453 {
2454 if (symndx < 0
2455 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2456 {
2457 (*_bfd_error_handler)
2458 ("%s: illegal symbol index %ld in relocs",
2459 bfd_get_filename (input_bfd), symndx);
2460 bfd_set_error (bfd_error_bad_value);
2461 return false;
2462 }
2463 h = obj_coff_sym_hashes (input_bfd)[symndx];
2464 sym = syms + symndx;
2465 }
2466
2467 if (sym != NULL && sym->n_scnum != 0)
2468 addend = - sym->n_value;
2469 else
2470 addend = 0;
2471
2472 if (rel->r_type == R_SH_PCDISP)
2473 addend -= 4;
2474
2475 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2476 howto = NULL;
2477 else
2478 howto = &sh_coff_howtos[rel->r_type];
2479
2480 if (howto == NULL)
2481 {
2482 bfd_set_error (bfd_error_bad_value);
2483 return false;
2484 }
2485
2486 val = 0;
2487
2488 if (h == NULL)
2489 {
2490 asection *sec;
2491
2492 /* There is nothing to do for an internal PCDISP reloc. */
2493 if (rel->r_type == R_SH_PCDISP)
2494 continue;
2495
2496 if (symndx == -1)
2497 {
2498 sec = bfd_abs_section_ptr;
2499 val = 0;
2500 }
2501 else
2502 {
2503 sec = sections[symndx];
2504 val = (sec->output_section->vma
2505 + sec->output_offset
2506 + sym->n_value
2507 - sec->vma);
2508 }
2509 }
2510 else
2511 {
2512 if (h->root.type == bfd_link_hash_defined
2513 || h->root.type == bfd_link_hash_defweak)
2514 {
2515 asection *sec;
2516
2517 sec = h->root.u.def.section;
2518 val = (h->root.u.def.value
2519 + sec->output_section->vma
2520 + sec->output_offset);
2521 }
2522 else if (! info->relocateable)
2523 {
2524 if (! ((*info->callbacks->undefined_symbol)
2525 (info, h->root.root.string, input_bfd, input_section,
2526 rel->r_vaddr - input_section->vma)))
2527 return false;
2528 }
2529 }
2530
2531 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2532 contents,
2533 rel->r_vaddr - input_section->vma,
2534 val, addend);
2535
2536 switch (rstat)
2537 {
2538 default:
2539 abort ();
2540 case bfd_reloc_ok:
2541 break;
2542 case bfd_reloc_overflow:
2543 {
2544 const char *name;
2545 char buf[SYMNMLEN + 1];
2546
2547 if (symndx == -1)
2548 name = "*ABS*";
2549 else if (h != NULL)
2550 name = h->root.root.string;
2551 else if (sym->_n._n_n._n_zeroes == 0
2552 && sym->_n._n_n._n_offset != 0)
2553 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2554 else
2555 {
2556 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2557 buf[SYMNMLEN] = '\0';
2558 name = buf;
2559 }
2560
2561 if (! ((*info->callbacks->reloc_overflow)
2562 (info, name, howto->name, (bfd_vma) 0, input_bfd,
2563 input_section, rel->r_vaddr - input_section->vma)))
2564 return false;
2565 }
2566 }
2567 }
2568
2569 return true;
2570}
2571
2572/* This is a version of bfd_generic_get_relocated_section_contents
2573 which uses sh_relocate_section. */
2574
2575static bfd_byte *
2576sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
2577 data, relocateable, symbols)
2578 bfd *output_bfd;
2579 struct bfd_link_info *link_info;
2580 struct bfd_link_order *link_order;
2581 bfd_byte *data;
2582 boolean relocateable;
2583 asymbol **symbols;
2584{
2585 asection *input_section = link_order->u.indirect.section;
2586 bfd *input_bfd = input_section->owner;
2587 asection **sections = NULL;
2588 struct internal_reloc *internal_relocs = NULL;
2589 struct internal_syment *internal_syms = NULL;
2590
2591 /* We only need to handle the case of relaxing, or of having a
2592 particular set of section contents, specially. */
2593 if (relocateable
2594 || coff_section_data (input_bfd, input_section) == NULL
2595 || coff_section_data (input_bfd, input_section)->contents == NULL)
2596 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2597 link_order, data,
2598 relocateable,
2599 symbols);
2600
2601 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
2602 input_section->_raw_size);
2603
2604 if ((input_section->flags & SEC_RELOC) != 0
2605 && input_section->reloc_count > 0)
2606 {
2607 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2608 bfd_byte *esym, *esymend;
2609 struct internal_syment *isymp;
2610 asection **secpp;
2611
2612 if (! _bfd_coff_get_external_symbols (input_bfd))
2613 goto error_return;
2614
2615 internal_relocs = (_bfd_coff_read_internal_relocs
2616 (input_bfd, input_section, false, (bfd_byte *) NULL,
2617 false, (struct internal_reloc *) NULL));
2618 if (internal_relocs == NULL)
2619 goto error_return;
2620
2621 internal_syms = ((struct internal_syment *)
2622 bfd_malloc (obj_raw_syment_count (input_bfd)
2623 * sizeof (struct internal_syment)));
2624 if (internal_syms == NULL)
2625 goto error_return;
2626
2627 sections = (asection **) bfd_malloc (obj_raw_syment_count (input_bfd)
2628 * sizeof (asection *));
2629 if (sections == NULL)
2630 goto error_return;
2631
2632 isymp = internal_syms;
2633 secpp = sections;
2634 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2635 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2636 while (esym < esymend)
2637 {
2638 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
2639
2640 if (isymp->n_scnum != 0)
2641 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2642 else
2643 {
2644 if (isymp->n_value == 0)
2645 *secpp = bfd_und_section_ptr;
2646 else
2647 *secpp = bfd_com_section_ptr;
2648 }
2649
2650 esym += (isymp->n_numaux + 1) * symesz;
2651 secpp += isymp->n_numaux + 1;
2652 isymp += isymp->n_numaux + 1;
2653 }
2654
2655 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
2656 input_section, data, internal_relocs,
2657 internal_syms, sections))
2658 goto error_return;
2659
2660 free (sections);
2661 sections = NULL;
2662 free (internal_syms);
2663 internal_syms = NULL;
2664 free (internal_relocs);
2665 internal_relocs = NULL;
2666 }
2667
2668 return data;
2669
2670 error_return:
2671 if (internal_relocs != NULL)
2672 free (internal_relocs);
2673 if (internal_syms != NULL)
2674 free (internal_syms);
2675 if (sections != NULL)
2676 free (sections);
2677 return NULL;
2678}
2679
2680/* The target vectors. */
2681
c3c89269 2682CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL)
252b5132 2683
c3c89269
NC		 2684#ifdef TARGET_SHL_SYM
2685#define TARGET_SYM TARGET_SHL_SYM
2686#else
2687#define TARGET_SYM shlcoff_vec
2688#endif
2689
2690#ifndef TARGET_SHL_NAME
2691#define TARGET_SHL_NAME "coff-shl"
2692#endif
252b5132 2693
c3c89269
NC		 2694CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, 0, '_', NULL)
2695
252b5132
RH		 2696
2697/* Some people want versions of the SH COFF target which do not align
2698 to 16 byte boundaries. We implement that by adding a couple of new
2699 target vectors. These are just like the ones above, but they
2700 change the default section alignment. To generate them in the
2701 assembler, use -small. To use them in the linker, use -b
2702 coff-sh{l}-small and -oformat coff-sh{l}-small.
2703
2704 Yes, this is a horrible hack. A general solution for setting
2705 section alignment in COFF is rather complex. ELF handles this
2706 correctly. */
2707
2708/* Only recognize the small versions if the target was not defaulted.
2709 Otherwise we won't recognize the non default endianness. */
2710
2711static const bfd_target *
2712coff_small_object_p (abfd)
2713 bfd *abfd;
2714{
2715 if (abfd->target_defaulted)
2716 {
2717 bfd_set_error (bfd_error_wrong_format);
2718 return NULL;
2719 }
2720 return coff_object_p (abfd);
2721}
2722
2723/* Set the section alignment for the small versions. */
2724
2725static boolean
2726coff_small_new_section_hook (abfd, section)
2727 bfd *abfd;
2728 asection *section;
2729{
2730 if (! coff_new_section_hook (abfd, section))
2731 return false;
2732
2733 /* We must align to at least a four byte boundary, because longword
2734 accesses must be on a four byte boundary. */
2735 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
2736 section->alignment_power = 2;
2737
2738 return true;
2739}
2740
2741/* This is copied from bfd_coff_std_swap_table so that we can change
2742 the default section alignment power. */
2743
2744static const bfd_coff_backend_data bfd_coff_small_swap_table =
2745{
2746 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
2747 coff_swap_aux_out, coff_swap_sym_out,
2748 coff_swap_lineno_out, coff_swap_reloc_out,
2749 coff_swap_filehdr_out, coff_swap_aouthdr_out,
2750 coff_swap_scnhdr_out,
2751 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ,
2752#ifdef COFF_LONG_FILENAMES
2753 true,
2754#else
2755 false,
2756#endif
2757#ifdef COFF_LONG_SECTION_NAMES
2758 true,
2759#else
2760 false,
2761#endif
2762 2,
2763 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
2764 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
2765 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
2766 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
2767 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 2768 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 2769 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
2770 coff_adjust_symndx, coff_link_add_one_symbol,
2771 coff_link_output_has_begun, coff_final_link_postscript
2772};
2773
2774#define coff_small_close_and_cleanup \
2775 coff_close_and_cleanup
2776#define coff_small_bfd_free_cached_info \
2777 coff_bfd_free_cached_info
2778#define coff_small_get_section_contents \
2779 coff_get_section_contents
2780#define coff_small_get_section_contents_in_window \
2781 coff_get_section_contents_in_window
2782
c3c89269
NC		 2783extern const bfd_target shlcoff_small_vec;
2784
252b5132
RH		 2785const bfd_target shcoff_small_vec =
2786{
2787 "coff-sh-small", /* name */
2788 bfd_target_coff_flavour,
2789 BFD_ENDIAN_BIG, /* data byte order is big */
2790 BFD_ENDIAN_BIG, /* header byte order is big */
2791
2792 (HAS_RELOC | EXEC_P | /* object flags */
2793 HAS_LINENO | HAS_DEBUG |
2794 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2795
2796 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2797 '_', /* leading symbol underscore */
2798 '/', /* ar_pad_char */
2799 15, /* ar_max_namelen */
2800 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2801 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2802 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
2803 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2804 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2805 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
2806
2807 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
2808 bfd_generic_archive_p, _bfd_dummy_target},
2809 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2810 bfd_false},
2811 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2812 _bfd_write_archive_contents, bfd_false},
2813
2814 BFD_JUMP_TABLE_GENERIC (coff_small),
2815 BFD_JUMP_TABLE_COPY (coff),
2816 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2817 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2818 BFD_JUMP_TABLE_SYMBOLS (coff),
2819 BFD_JUMP_TABLE_RELOCS (coff),
2820 BFD_JUMP_TABLE_WRITE (coff),
2821 BFD_JUMP_TABLE_LINK (coff),
2822 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
2823
c3c89269
NC		 2824 & shlcoff_small_vec,
2825
252b5132
RH		 2826 (PTR) &bfd_coff_small_swap_table
2827};
2828
2829const bfd_target shlcoff_small_vec =
2830{
2831 "coff-shl-small", /* name */
2832 bfd_target_coff_flavour,
2833 BFD_ENDIAN_LITTLE, /* data byte order is little */
2834 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
2835
2836 (HAS_RELOC | EXEC_P | /* object flags */
2837 HAS_LINENO | HAS_DEBUG |
2838 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2839
2840 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2841 '_', /* leading symbol underscore */
2842 '/', /* ar_pad_char */
2843 15, /* ar_max_namelen */
2844 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2845 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2846 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
2847 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2848 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2849 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
2850
2851 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
2852 bfd_generic_archive_p, _bfd_dummy_target},
2853 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2854 bfd_false},
2855 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2856 _bfd_write_archive_contents, bfd_false},
2857
2858 BFD_JUMP_TABLE_GENERIC (coff_small),
2859 BFD_JUMP_TABLE_COPY (coff),
2860 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2861 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2862 BFD_JUMP_TABLE_SYMBOLS (coff),
2863 BFD_JUMP_TABLE_RELOCS (coff),
2864 BFD_JUMP_TABLE_WRITE (coff),
2865 BFD_JUMP_TABLE_LINK (coff),
2866 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
2867
c3c89269
NC		 2868 & shcoff_small_vec,
2869
252b5132
RH		 2870 (PTR) &bfd_coff_small_swap_table
2871};
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