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2002-02-28 Chris Demetriou <[email protected]>
[binutils.git] / sim / v850 / v850.igen
CommitLineData
c906108c
SS		 1:option:::insn-bit-size:16
2:option:::hi-bit-nr:15
3
4
5:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6:option:::format-names:XI,XII,XIII
7:option:::format-names:XIV,XV
8:option:::format-names:Z
9
10
11:model:::v850:v850:
12
13:option:::multi-sim:true
14:model:::v850e:v850e:
15
16:option:::multi-sim:true
17:model:::v850ea:v850ea:
18
19
20
21// Cache macros
22
23:cache:::unsigned:reg1:RRRRR:(RRRRR)
24:cache:::unsigned:reg2:rrrrr:(rrrrr)
25:cache:::unsigned:reg3:wwwww:(wwwww)
26
27:cache:::unsigned:disp4:dddd:(dddd)
28:cache:::unsigned:disp5:dddd:(dddd << 1)
29:cache:::unsigned:disp7:ddddddd:ddddddd
30:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
31:cache:::unsigned:disp8:dddddd:(dddddd << 2)
32:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
33:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
34:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
35:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
36
37:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
38:cache:::unsigned:imm6:iiiiii:iiiiii
39:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
40:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
41:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
42:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
43:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
44:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
45
46:cache:::unsigned:vector:iiiii:iiiii
47
48:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
49:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
50
51:cache:::unsigned:bit3:bbb:bbb
52
53
54// What do we do with an illegal instruction?
55:internal::::illegal:
56{
57 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
58 (unsigned long) cia);
59 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
60}
61
62
63
64// Add
65
66rrrrr,001110,RRRRR:I:::add
67"add r<reg1>, r<reg2>"
68{
69 COMPAT_1 (OP_1C0 ());
70}
71
72rrrrr,010010,iiiii:II:::add
73"add <imm5>,r<reg2>"
74{
75 COMPAT_1 (OP_240 ());
76}
77
78
79
80// ADDI
81rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
82"addi <simm16>, r<reg1>, r<reg2>"
83{
84 COMPAT_2 (OP_600 ());
85}
86
87
88
89// AND
90rrrrr,001010,RRRRR:I:::and
91"and r<reg1>, r<reg2>"
92{
93 COMPAT_1 (OP_140 ());
94}
95
96
97
98// ANDI
99rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
100"andi <uimm16>, r<reg1>, r<reg2>"
101{
102 COMPAT_2 (OP_6C0 ());
103}
104
105
106
107// Map condition code to a string
108:%s::::cccc:int cccc
109{
110 switch (cccc)
111 {
112 case 0xf: return "gt";
113 case 0xe: return "ge";
114 case 0x6: return "lt";
115
116 case 0x7: return "le";
117
118 case 0xb: return "h";
119 case 0x9: return "nl";
120 case 0x1: return "l";
121
122 case 0x3: return "nh";
123
124 case 0x2: return "e";
125
126 case 0xa: return "ne";
127
128 case 0x0: return "v";
129 case 0x8: return "nv";
130 case 0x4: return "n";
131 case 0xc: return "p";
132 /* case 0x1: return "c"; */
133 /* case 0x9: return "nc"; */
134 /* case 0x2: return "z"; */
135 /* case 0xa: return "nz"; */
136 case 0x5: return "r"; /* always */
137 case 0xd: return "sa";
138 }
139 return "(null)";
140}
141
142
143// Bcond
144ddddd,1011,ddd,cccc:III:::Bcond
145"b%s<cccc> <disp9>"
146{
b9791fcd
FCE		 147 int cond;
148 if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
149 // Special case - treat "br *" like illegal instruction
150 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
151 } else {
152 cond = condition_met (cccc);
153 if (cond)
154 nia = cia + disp9;
155 TRACE_BRANCH1 (cond);
156 }
c906108c
SS		 157}
158
159
160
161// BSH
162rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
163*v850e
164*v850ea
165"bsh r<reg2>, r<reg3>"
166{
167 unsigned32 value;
168 TRACE_ALU_INPUT1 (GR[reg2]);
169
170 value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
171 | MOVED32 (GR[reg2], 31, 24, 23, 16)
172 | MOVED32 (GR[reg2], 7, 0, 15, 8)
173 | MOVED32 (GR[reg2], 15, 8, 7, 0));
174
175 GR[reg3] = value;
176 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
177 if (value == 0) PSW |= PSW_Z;
178 if (value & 0x80000000) PSW |= PSW_S;
179 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
180
181 TRACE_ALU_RESULT (GR[reg3]);
182}
183
184// BSW
185rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
186*v850e
187*v850ea
188"bsw r<reg2>, r<reg3>"
189{
190#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
191 unsigned32 value;
192 TRACE_ALU_INPUT1 (GR[reg2]);
193
194 value = GR[reg2];
195 value >>= 24;
196 value |= (GR[reg2] << 24);
197 value |= ((GR[reg2] << 8) & 0x00ff0000);
198 value |= ((GR[reg2] >> 8) & 0x0000ff00);
199 GR[reg3] = value;
200
201 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
202
203 if (value == 0) PSW |= PSW_Z;
204 if (value & 0x80000000) PSW |= PSW_S;
205 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
206
207 TRACE_ALU_RESULT (GR[reg3]);
208}
209
210// CALLT
2110000001000,iiiiii:II:::callt
212*v850e
213*v850ea
214"callt <imm6>"
215{
216 unsigned32 adr;
217 unsigned32 off;
218 CTPC = cia + 2;
219 CTPSW = PSW;
220 adr = (CTBP & ~1) + (imm6 << 1);
221 off = load_mem (adr, 2) & ~1; /* Force alignment */
222 nia = (CTBP & ~1) + off;
223 TRACE_BRANCH3 (adr, CTBP, off);
224}
225
226
227// CLR1
22810,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
229"clr1 <bit3>, <disp16>[r<reg1>]"
230{
231 COMPAT_2 (OP_87C0 ());
232}
233
234rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
235*v850e
236*v850ea
237"clr1 r<reg2>, [r<reg1>]"
238{
239 COMPAT_2 (OP_E407E0 ());
240}
241
242
243// CTRET
2440000011111100000 + 0000000101000100:X:::ctret
245*v850e
246*v850ea
247"ctret"
248{
249 nia = (CTPC & ~1);
250 PSW = (CTPSW & (CPU)->psw_mask);
251 TRACE_BRANCH1 (PSW);
252}
253
254// CMOV
255rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
256*v850e
257*v850ea
258"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
259{
260 int cond = condition_met (cccc);
261 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
262 GR[reg3] = cond ? GR[reg1] : GR[reg2];
263 TRACE_ALU_RESULT (GR[reg3]);
264}
265
266rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
267*v850e
268*v850ea
269"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
270{
271 int cond = condition_met (cccc);
272 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
273 GR[reg3] = cond ? imm5 : GR[reg2];
274 TRACE_ALU_RESULT (GR[reg3]);
275}
276
277// CMP
278rrrrr,001111,RRRRR:I:::cmp
279"cmp r<reg1>, r<reg2>"
280{
281 COMPAT_1 (OP_1E0 ());
282}
283
284rrrrr,010011,iiiii:II:::cmp
285"cmp <imm5>, r<reg2>"
286{
287 COMPAT_1 (OP_260 ());
288}
289
290
291
292// DI
2930000011111100000 + 0000000101100000:X:::di
294"di"
295{
296 COMPAT_2 (OP_16007E0 ());
297}
298
299
300
301// DISPOSE
302// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
303// "dispose <imm5>, <list12>"
3040000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
305*v850e
306*v850ea
307"dispose <imm5>, <list12>":RRRRR == 0
308"dispose <imm5>, <list12>, [reg1]"
309{
310 int i;
311 SAVE_2;
312
313 trace_input ("dispose", OP_PUSHPOP1, 0);
314
315 SP += (OP[3] & 0x3e) << 1;
316
317 /* Load the registers with lower number registers being retrieved
318 from higher addresses. */
319 for (i = 12; i--;)
320 if ((OP[3] & (1 << type1_regs[ i ])))
321 {
322 State.regs[ 20 + i ] = load_mem (SP, 4);
323 SP += 4;
324 }
325
326 if ((OP[3] & 0x1f0000) != 0)
327 {
328 nia = State.regs[ (OP[3] >> 16) & 0x1f];
329 }
330
331 trace_output (OP_PUSHPOP1);
332}
333
334
335// DIV
336rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
337*v850e
338"div r<reg1>, r<reg2>, r<reg3>"
339{
340 COMPAT_2 (OP_2C007E0 ());
341}
342
343
344// DIVH
345rrrrr!0,000010,RRRRR!0:I:::divh
346"divh r<reg1>, r<reg2>"
347{
348 COMPAT_1 (OP_40 ());
349}
350
351rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
352*v850e
353"divh r<reg1>, r<reg2>, r<reg3>"
354{
355 COMPAT_2 (OP_28007E0 ());
356}
357
358
359// DIVHU
360rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
361*v850e
362"divhu r<reg1>, r<reg2>, r<reg3>"
363{
364 COMPAT_2 (OP_28207E0 ());
365}
366
367
368// DIVU
369rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
370*v850e
371"divu r<reg1>, r<reg2>, r<reg3>"
372{
373 COMPAT_2 (OP_2C207E0 ());
374}
375
376
377// EI
3781000011111100000 + 0000000101100000:X:::ei
379"ei"
380{
381 COMPAT_2 (OP_16087E0 ());
382}
383
384
385
386// HALT
3870000011111100000 + 0000000100100000:X:::halt
388"halt"
389{
390 COMPAT_2 (OP_12007E0 ());
391}
392
393
394
395// HSW
396rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
397*v850e
398*v850ea
399"hsw r<reg2>, r<reg3>"
400{
401 unsigned32 value;
402 TRACE_ALU_INPUT1 (GR[reg2]);
403
404 value = GR[reg2];
405 value >>= 16;
406 value |= (GR[reg2] << 16);
407
408 GR[reg3] = value;
409
410 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
411
412 if (value == 0) PSW |= PSW_Z;
413 if (value & 0x80000000) PSW |= PSW_S;
414 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
415
416 TRACE_ALU_RESULT (GR[reg3]);
417}
418
419
420
421// JARL
422rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
423"jarl <disp22>, r<reg2>"
424{
425 GR[reg2] = nia;
426 nia = cia + disp22;
427 TRACE_BRANCH1 (GR[reg2]);
428}
429
430
431
432// JMP
43300000000011,RRRRR:I:::jmp
434"jmp [r<reg1>]"
435{
436 nia = GR[reg1] & ~1;
437 TRACE_BRANCH0 ();
438}
439
440
441
442// JR
4430000011110,dddddd + ddddddddddddddd,0:V:::jr
444"jr <disp22>"
445{
446 nia = cia + disp22;
447 TRACE_BRANCH0 ();
448}
449
450
451
452// LD
453rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
454"ld.b <disp16>[r<reg1>], r<reg2>"
455{
456 COMPAT_2 (OP_700 ());
457}
458
459rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
460"ld.h <disp16>[r<reg1>], r<reg2>"
461{
462 COMPAT_2 (OP_720 ());
463}
464
465rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
466"ld.w <disp16>[r<reg1>], r<reg2>"
467{
468 COMPAT_2 (OP_10720 ());
469}
470
471rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
472*v850e
473*v850ea
474"ld.bu <disp16>[r<reg1>], r<reg2>"
475{
476 COMPAT_2 (OP_10780 ());
477}
478
479rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
480*v850e
481*v850ea
482"ld.hu <disp16>[r<reg1>], r<reg2>"
483{
484 COMPAT_2 (OP_107E0 ());
485}
486
487
488// LDSR
489regID,111111,RRRRR + 0000000000100000:IX:::ldsr
490"ldsr r<reg1>, s<regID>"
491{
492 TRACE_ALU_INPUT1 (GR[reg1]);
493
494 if (&PSW == &SR[regID])
495 PSW = (GR[reg1] & (CPU)->psw_mask);
496 else
497 SR[regID] = GR[reg1];
498
499 TRACE_ALU_RESULT (SR[regID]);
500}
501
502
503
504// MOV
505rrrrr!0,000000,RRRRR:I:::mov
506"mov r<reg1>, r<reg2>"
507{
508 TRACE_ALU_INPUT0 ();
509 GR[reg2] = GR[reg1];
510 TRACE_ALU_RESULT (GR[reg2]);
511}
512
513
514rrrrr!0,010000,iiiii:II:::mov
515"mov <imm5>, r<reg2>"
516{
517 COMPAT_1 (OP_200 ());
518}
519
52000000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
521*v850e
522*v850ea
523"mov <imm32>, r<reg1>"
524{
525 SAVE_2;
526 trace_input ("mov", OP_IMM_REG, 4);
527 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
528 trace_output (OP_IMM_REG);
529}
530
531
532
533// MOVEA
534rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
535"movea <simm16>, r<reg1>, r<reg2>"
536{
537 TRACE_ALU_INPUT2 (GR[reg1], simm16);
538 GR[reg2] = GR[reg1] + simm16;
539 TRACE_ALU_RESULT (GR[reg2]);
540}
541
542
543
544// MOVHI
545rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
546"movhi <uimm16>, r<reg1>, r<reg2>"
547{
548 COMPAT_2 (OP_640 ());
549}
550
551
552
553// MUL
554rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
555*v850e
556*v850ea
557"mul r<reg1>, r<reg2>, r<reg3>"
558{
559 COMPAT_2 (OP_22007E0 ());
560}
561
562rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
563*v850e
564*v850ea
565"mul <imm9>, r<reg2>, r<reg3>"
566{
567 COMPAT_2 (OP_24007E0 ());
568}
569
570
571// MULH
572rrrrr!0,000111,RRRRR:I:::mulh
573"mulh r<reg1>, r<reg2>"
574{
575 COMPAT_1 (OP_E0 ());
576}
577
578rrrrr!0,010111,iiiii:II:::mulh
579"mulh <imm5>, r<reg2>"
580{
581 COMPAT_1 (OP_2E0 ());
582}
583
584
585
586// MULHI
587rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
588"mulhi <uimm16>, r<reg1>, r<reg2>"
589{
590 COMPAT_2 (OP_6E0 ());
591}
592
593
594
595// MULU
596rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
597*v850e
598*v850ea
599"mulu r<reg1>, r<reg2>, r<reg3>"
600{
601 COMPAT_2 (OP_22207E0 ());
602}
603
604rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
605*v850e
606*v850ea
607"mulu <imm9>, r<reg2>, r<reg3>"
608{
609 COMPAT_2 (OP_24207E0 ());
610}
611
612
613
614// NOP
6150000000000000000:I:::nop
616"nop"
617{
618 /* do nothing, trace nothing */
619}
620
621
622
623// NOT
624rrrrr,000001,RRRRR:I:::not
625"not r<reg1>, r<reg2>"
626{
627 COMPAT_1 (OP_20 ());
628}
629
630
631
632// NOT1
63301,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
634"not1 <bit3>, <disp16>[r<reg1>]"
635{
636 COMPAT_2 (OP_47C0 ());
637}
638
639rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
640*v850e
641*v850ea
642"not1 r<reg2>, r<reg1>"
643{
644 COMPAT_2 (OP_E207E0 ());
645}
646
647
648
649// OR
650rrrrr,001000,RRRRR:I:::or
651"or r<reg1>, r<reg2>"
652{
653 COMPAT_1 (OP_100 ());
654}
655
656
657
658// ORI
659rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
660"ori <uimm16>, r<reg1>, r<reg2>"
661{
662 COMPAT_2 (OP_680 ());
663}
664
665
666
667// PREPARE
6680000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
669*v850e
670*v850ea
671"prepare <list12>, <imm5>"
672{
673 int i;
674 SAVE_2;
675
676 trace_input ("prepare", OP_PUSHPOP1, 0);
677
678 /* Store the registers with lower number registers being placed at
679 higher addresses. */
680 for (i = 0; i < 12; i++)
681 if ((OP[3] & (1 << type1_regs[ i ])))
682 {
683 SP -= 4;
684 store_mem (SP, 4, State.regs[ 20 + i ]);
685 }
686
687 SP -= (OP[3] & 0x3e) << 1;
688
689 trace_output (OP_PUSHPOP1);
690}
691
692
6930000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
694*v850e
695*v850ea
696"prepare <list12>, <imm5>, sp"
697{
698 COMPAT_2 (OP_30780 ());
699}
700
7010000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
702*v850e
703*v850ea
704"prepare <list12>, <imm5>, <uimm16>"
705{
706 COMPAT_2 (OP_B0780 ());
707}
708
7090000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
710*v850e
711*v850ea
712"prepare <list12>, <imm5>, <uimm16>"
713{
714 COMPAT_2 (OP_130780 ());
715}
716
7170000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
718*v850e
719*v850ea
720"prepare <list12>, <imm5>, <uimm32>"
721{
722 COMPAT_2 (OP_1B0780 ());
723}
724
725
726
727// RETI
7280000011111100000 + 0000000101000000:X:::reti
729"reti"
730{
731 if ((PSW & PSW_EP))
732 {
733 nia = (EIPC & ~1);
734 PSW = EIPSW;
735 }
736 else if ((PSW & PSW_NP))
737 {
738 nia = (FEPC & ~1);
739 PSW = FEPSW;
740 }
741 else
742 {
743 nia = (EIPC & ~1);
744 PSW = EIPSW;
745 }
746 TRACE_BRANCH1 (PSW);
747}
748
749
750
751// SAR
752rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
753"sar r<reg1>, r<reg2>"
754{
755 COMPAT_2 (OP_A007E0 ());
756}
757
758rrrrr,010101,iiiii:II:::sar
759"sar <imm5>, r<reg2>"
760{
761 COMPAT_1 (OP_2A0 ());
762}
763
764
765
766// SASF
767rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
768*v850e
769*v850ea
770"sasf %s<cccc>, r<reg2>"
771{
772 COMPAT_2 (OP_20007E0 ());
773}
774
775
776
777
778// SATADD
779rrrrr!0,000110,RRRRR:I:::satadd
780"satadd r<reg1>, r<reg2>"
781{
782 COMPAT_1 (OP_C0 ());
783}
784
785rrrrr!0,010001,iiiii:II:::satadd
786"satadd <imm5>, r<reg2>"
787{
788 COMPAT_1 (OP_220 ());
789}
790
791
792
793// SATSUB
794rrrrr!0,000101,RRRRR:I:::satsub
795"satsub r<reg1>, r<reg2>"
796{
797 COMPAT_1 (OP_A0 ());
798}
799
800
801
802// SATSUBI
803rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
804"satsubi <simm16>, r<reg1>, r<reg2>"
805{
806 COMPAT_2 (OP_660 ());
807}
808
809
810
811// SATSUBR
812rrrrr!0,000100,RRRRR:I:::satsubr
813"satsubr r<reg1>, r<reg2>"
814{
815 COMPAT_1 (OP_80 ());
816}
817
818
819
820// SETF
821rrrrr,1111110,cccc + 0000000000000000:IX:::setf
822"setf %s<cccc>, r<reg2>"
823{
824 COMPAT_2 (OP_7E0 ());
825}
826
827
828
829// SET1
83000,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
831"set1 <bit3>, <disp16>[r<reg1>]"
832{
833 COMPAT_2 (OP_7C0 ());
834}
835
836rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
837*v850e
838*v850ea
839"set1 r<reg2>, [r<reg1>]"
840{
841 COMPAT_2 (OP_E007E0 ());
842}
843
844
845
846// SHL
847rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
848"shl r<reg1>, r<reg2>"
849{
850 COMPAT_2 (OP_C007E0 ());
851}
852
853rrrrr,010110,iiiii:II:::shl
854"shl <imm5>, r<reg2>"
855{
856 COMPAT_1 (OP_2C0 ());
857}
858
859
860
861// SHR
862rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
863"shr r<reg1>, r<reg2>"
864{
865 COMPAT_2 (OP_8007E0 ());
866}
867
868rrrrr,010100,iiiii:II:::shr
869"shr <imm5>, r<reg2>"
870{
871 COMPAT_1 (OP_280 ());
872}
873
874
875
876// SLD
877rrrrr,0110,ddddddd:IV:::sld.b
878"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
879"sld.b <disp7>[ep], r<reg2>"
880{
881 unsigned32 addr = EP + disp7;
882 unsigned32 result = load_mem (addr, 1);
883 if (PSW & PSW_US)
884 {
885 GR[reg2] = result;
886 TRACE_LD_NAME ("sld.bu", addr, result);
887 }
888 else
889 {
890 result = EXTEND8 (result);
891 GR[reg2] = result;
892 TRACE_LD (addr, result);
893 }
894}
895
896rrrrr,1000,ddddddd:IV:::sld.h
897"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
898"sld.h <disp8>[ep], r<reg2>"
899{
900 unsigned32 addr = EP + disp8;
901 unsigned32 result = load_mem (addr, 2);
902 if (PSW & PSW_US)
903 {
904 GR[reg2] = result;
905 TRACE_LD_NAME ("sld.hu", addr, result);
906 }
907 else
908 {
909 result = EXTEND16 (result);
910 GR[reg2] = result;
911 TRACE_LD (addr, result);
912 }
913}
914
915rrrrr,1010,dddddd,0:IV:::sld.w
916"sld.w <disp8>[ep], r<reg2>"
917{
918 unsigned32 addr = EP + disp8;
919 unsigned32 result = load_mem (addr, 4);
920 GR[reg2] = result;
921 TRACE_LD (addr, result);
922}
923
924rrrrr!0,0000110,dddd:IV:::sld.bu
925*v850e
926*v850ea
927"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
928"sld.bu <disp4>[ep], r<reg2>"
929{
930 unsigned32 addr = EP + disp4;
931 unsigned32 result = load_mem (addr, 1);
932 if (PSW & PSW_US)
933 {
934 result = EXTEND8 (result);
935 GR[reg2] = result;
936 TRACE_LD_NAME ("sld.b", addr, result);
937 }
938 else
939 {
940 GR[reg2] = result;
941 TRACE_LD (addr, result);
942 }
943}
944
945rrrrr!0,0000111,dddd:IV:::sld.hu
946*v850e
947*v850ea
948"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
949"sld.hu <disp5>[ep], r<reg2>"
950{
951 unsigned32 addr = EP + disp5;
952 unsigned32 result = load_mem (addr, 2);
953 if (PSW & PSW_US)
954 {
955 result = EXTEND16 (result);
956 GR[reg2] = result;
957 TRACE_LD_NAME ("sld.h", addr, result);
958 }
959 else
960 {
961 GR[reg2] = result;
962 TRACE_LD (addr, result);
963 }
964}
965
966
967// SST
968rrrrr,0111,ddddddd:IV:::sst.b
969"sst.b r<reg2>, <disp7>[ep]"
970{
971 COMPAT_1 (OP_380 ());
972}
973
974rrrrr,1001,ddddddd:IV:::sst.h
975"sst.h r<reg2>, <disp8>[ep]"
976{
977 COMPAT_1 (OP_480 ());
978}
979
980rrrrr,1010,dddddd,1:IV:::sst.w
981"sst.w r<reg2>, <disp8>[ep]"
982{
983 COMPAT_1 (OP_501 ());
984}
985
986
987
988// ST
989rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
990"st.b r<reg2>, <disp16>[r<reg1>]"
991{
992 COMPAT_2 (OP_740 ());
993}
994
995rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
996"st.h r<reg2>, <disp16>[r<reg1>]"
997{
998 COMPAT_2 (OP_760 ());
999}
1000
1001rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1002"st.w r<reg2>, <disp16>[r<reg1>]"
1003{
1004 COMPAT_2 (OP_10760 ());
1005}
1006
1007
1008
1009// STSR
1010rrrrr,111111,regID + 0000000001000000:IX:::stsr
1011"stsr s<regID>, r<reg2>"
1012{
1013 TRACE_ALU_INPUT1 (SR[regID]);
1014 GR[reg2] = SR[regID];
1015 TRACE_ALU_RESULT (GR[reg2]);
1016}
1017
1018
1019
1020// SUB
1021rrrrr,001101,RRRRR:I:::sub
1022"sub r<reg1>, r<reg2>"
1023{
1024 COMPAT_1 (OP_1A0 ());
1025}
1026
1027
1028
1029// SUBR
1030rrrrr,001100,RRRRR:I:::subr
1031"subr r<reg1>, r<reg2>"
1032{
1033 COMPAT_1 (OP_180 ());
1034}
1035
1036
1037
1038// SWITCH
103900000000010,RRRRR:I:::switch
1040*v850e
1041*v850ea
1042"switch r<reg1>"
1043{
1044 unsigned long adr;
1045 SAVE_1;
1046 trace_input ("switch", OP_REG, 0);
1047 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1048 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1049 trace_output (OP_REG);
1050}
1051
1052
1053// SXB
105400000000101,RRRRR:I:::sxb
1055*v850e
1056*v850ea
1057"sxb r<reg1>"
1058{
1059 TRACE_ALU_INPUT1 (GR[reg1]);
1060 GR[reg1] = EXTEND8 (GR[reg1]);
1061 TRACE_ALU_RESULT (GR[reg1]);
1062}
1063
1064// SXH
106500000000111,RRRRR:I:::sxh
1066*v850e
1067*v850ea
1068"sxh r<reg1>"
1069{
1070 TRACE_ALU_INPUT1 (GR[reg1]);
1071 GR[reg1] = EXTEND16 (GR[reg1]);
1072 TRACE_ALU_RESULT (GR[reg1]);
1073}
1074
1075
1076
1077// TRAP
107800000111111,iiiii + 0000000100000000:X:::trap
1079"trap <vector>"
1080{
1081 COMPAT_2 (OP_10007E0 ());
1082}
1083
1084
1085
1086// TST
1087rrrrr,001011,RRRRR:I:::tst
1088"tst r<reg1>, r<reg2>"
1089{
1090 COMPAT_1 (OP_160 ());
1091}
1092
1093
1094
1095// TST1
109611,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1097"tst1 <bit3>, <disp16>[r<reg1>]"
1098{
1099 COMPAT_2 (OP_C7C0 ());
1100}
1101
1102rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1103*v850e
1104*v850ea
1105"tst1 r<reg2>, [r<reg1>]"
1106{
1107 COMPAT_2 (OP_E607E0 ());
1108}
1109
1110
1111
1112// XOR
1113rrrrr,001001,RRRRR:I:::xor
1114"xor r<reg1>, r<reg2>"
1115{
1116 COMPAT_1 (OP_120 ());
1117}
1118
1119
1120
1121// XORI
1122rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1123"xori <uimm16>, r<reg1>, r<reg2>"
1124{
1125 COMPAT_2 (OP_6A0 ());
1126}
1127
1128
1129
1130// ZXB
113100000000100,RRRRR:I:::zxb
1132*v850e
1133*v850ea
1134"zxb r<reg1>"
1135{
1136 TRACE_ALU_INPUT1 (GR[reg1]);
1137 GR[reg1] = GR[reg1] & 0xff;
1138 TRACE_ALU_RESULT (GR[reg1]);
1139}
1140
1141// ZXH
114200000000110,RRRRR:I:::zxh
1143*v850e
1144*v850ea
1145"zxh r<reg1>"
1146{
1147 TRACE_ALU_INPUT1 (GR[reg1]);
1148 GR[reg1] = GR[reg1] & 0xffff;
1149 TRACE_ALU_RESULT (GR[reg1]);
1150}
1151
1152
1153// Right field must be zero so that it doesn't clash with DIVH
1154// Left field must be non-zero so that it doesn't clash with SWITCH
115511111,000010,00000:I:::break
1156{
1157 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1158}
1159
1160
de616bc7
FCE		 1161// New breakpoint: 0x7E0 0x7E0
116200000,111111,00000 + 00000,11111,100000:X:::ilgop
1163{
1164 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1165}
1166
c906108c
SS		 1167// DIVHN
1168rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1169*v850ea
1170"divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1171{
1172 signed32 quotient;
1173 signed32 remainder;
1174 signed32 divide_by;
1175 signed32 divide_this;
1176 boolean overflow = false;
1177 SAVE_2;
1178
1179 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1180
1181 divide_by = EXTEND16 (State.regs[ reg1 ]);
1182 divide_this = State.regs[ reg2 ];
1183
1184 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1185
1186 State.regs[ reg2 ] = quotient;
1187 State.regs[ reg3 ] = remainder;
1188
1189 /* Set condition codes. */
1190 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1191
1192 if (overflow) PSW |= PSW_OV;
1193 if (quotient == 0) PSW |= PSW_Z;
1194 if (quotient < 0) PSW |= PSW_S;
1195
1196 trace_output (OP_IMM_REG_REG_REG);
1197}
1198
1199
1200
1201// DIVHUN
1202rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1203*v850ea
1204"divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1205{
1206 signed32 quotient;
1207 signed32 remainder;
1208 signed32 divide_by;
1209 signed32 divide_this;
1210 boolean overflow = false;
1211 SAVE_2;
1212
1213 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1214
1215 divide_by = State.regs[ reg1 ] & 0xffff;
1216 divide_this = State.regs[ reg2 ];
1217
1218 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1219
1220 State.regs[ reg2 ] = quotient;
1221 State.regs[ reg3 ] = remainder;
1222
1223 /* Set condition codes. */
1224 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1225
1226 if (overflow) PSW |= PSW_OV;
1227 if (quotient == 0) PSW |= PSW_Z;
1228 if (quotient & 0x80000000) PSW |= PSW_S;
1229
1230 trace_output (OP_IMM_REG_REG_REG);
1231}
1232
1233
1234
1235// DIVN
1236rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1237*v850ea
1238"divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1239{
1240 signed32 quotient;
1241 signed32 remainder;
1242 signed32 divide_by;
1243 signed32 divide_this;
1244 boolean overflow = false;
1245 SAVE_2;
1246
1247 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1248
1249 divide_by = State.regs[ reg1 ];
1250 divide_this = State.regs[ reg2 ];
1251
1252 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1253
1254 State.regs[ reg2 ] = quotient;
1255 State.regs[ reg3 ] = remainder;
1256
1257 /* Set condition codes. */
1258 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1259
1260 if (overflow) PSW |= PSW_OV;
1261 if (quotient == 0) PSW |= PSW_Z;
1262 if (quotient < 0) PSW |= PSW_S;
1263
1264 trace_output (OP_IMM_REG_REG_REG);
1265}
1266
1267
1268
1269// DIVUN
1270rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1271*v850ea
1272"divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1273{
1274 signed32 quotient;
1275 signed32 remainder;
1276 signed32 divide_by;
1277 signed32 divide_this;
1278 boolean overflow = false;
1279 SAVE_2;
1280
1281 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1282
1283 divide_by = State.regs[ reg1 ];
1284 divide_this = State.regs[ reg2 ];
1285
1286 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1287
1288 State.regs[ reg2 ] = quotient;
1289 State.regs[ reg3 ] = remainder;
1290
1291 /* Set condition codes. */
1292 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1293
1294 if (overflow) PSW |= PSW_OV;
1295 if (quotient == 0) PSW |= PSW_Z;
1296 if (quotient & 0x80000000) PSW |= PSW_S;
1297
1298 trace_output (OP_IMM_REG_REG_REG);
1299}
1300
1301
1302
1303// SDIVHN
1304rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1305*v850ea
1306"sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1307{
1308 COMPAT_2 (OP_18007E0 ());
1309}
1310
1311
1312
1313// SDIVHUN
1314rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1315*v850ea
1316"sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1317{
1318 COMPAT_2 (OP_18207E0 ());
1319}
1320
1321
1322
1323// SDIVN
1324rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1325*v850ea
1326"sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1327{
1328 COMPAT_2 (OP_1C007E0 ());
1329}
1330
1331
1332
1333// SDIVUN
1334rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1335*v850ea
1336"sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1337{
1338 COMPAT_2 (OP_1C207E0 ());
1339}
1340
1341
1342
1343// PUSHML
1344000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1345*v850ea
1346"pushml <list18>"
1347{
1348 int i;
1349 SAVE_2;
1350
1351 trace_input ("pushml", OP_PUSHPOP3, 0);
1352
1353 /* Store the registers with lower number registers being placed at
1354 higher addresses. */
1355
1356 for (i = 0; i < 15; i++)
1357 if ((OP[3] & (1 << type3_regs[ i ])))
1358 {
1359 SP -= 4;
1360 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1361 }
1362
1363 if (OP[3] & (1 << 3))
1364 {
1365 SP -= 4;
1366
1367 store_mem (SP & ~ 3, 4, PSW);
1368 }
1369
1370 if (OP[3] & (1 << 19))
1371 {
1372 SP -= 8;
1373
1374 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1375 {
1376 store_mem ((SP + 4) & ~ 3, 4, FEPC);
1377 store_mem ( SP & ~ 3, 4, FEPSW);
1378 }
1379 else
1380 {
1381 store_mem ((SP + 4) & ~ 3, 4, EIPC);
1382 store_mem ( SP & ~ 3, 4, EIPSW);
1383 }
1384 }
1385
1386 trace_output (OP_PUSHPOP2);
1387}
1388
1389
1390
1391// PUSHHML
1392000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1393*v850ea
1394"pushhml <list18>"
1395{
1396 COMPAT_2 (OP_307E0 ());
1397}
1398
1399
1400
1401// POPML
1402000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1403*v850ea
1404"popml <list18>"
1405{
1406 COMPAT_2 (OP_107F0 ());
1407}
1408
1409
1410
1411// POPMH
1412000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1413*v850ea
1414"popmh <list18>"
1415{
1416 COMPAT_2 (OP_307F0 ());
1417}
1418
Empty description
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