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b3adc24a | 1 | @c Copyright (C) 1991-2020 Free Software Foundation, Inc. |
1f041c6e SH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node OpenRISC-Dependent | |
7 | @chapter OPENRISC Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter OPENRISC Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex OPENRISC support | |
15 | @menu | |
16 | * OpenRISC-Syntax:: Syntax | |
17 | * OpenRISC-Float:: Floating Point | |
18 | * OpenRISC-Directives:: OpenRISC Machine Directives | |
19 | * OpenRISC-Opcodes:: Opcodes | |
20 | @end menu | |
21 | ||
22 | @cindex OPENRISC syntax | |
23 | @cindex syntax, OPENRISC | |
24 | @node OpenRISC-Syntax | |
25 | @section OpenRISC Syntax | |
26 | The assembler syntax follows the OpenRISC 1000 Architecture Manual. | |
27 | ||
28 | @menu | |
29 | * OpenRISC-Chars:: Special Characters | |
30 | * OpenRISC-Regs:: Register Names | |
31 | * OpenRISC-Relocs:: Relocations | |
32 | @end menu | |
33 | ||
34 | @node OpenRISC-Chars | |
35 | @subsection Special Characters | |
36 | ||
37 | @cindex line comment character, OpenRISC | |
38 | @cindex OpenRISC line comment character | |
39 | A @samp{#} character appearing anywhere on a line indicates the start | |
40 | of a comment that extends to the end of that line. | |
41 | ||
42 | @cindex line separator, OpenRISC | |
43 | @cindex statement separator, OpenRISC | |
44 | @cindex OpenRISC line separator | |
45 | @samp{;} can be used instead of a newline to separate statements. | |
46 | ||
47 | @node OpenRISC-Regs | |
48 | @subsection Register Names | |
49 | @cindex OpenRISC registers | |
50 | @cindex register names, OpenRISC | |
51 | ||
52 | The OpenRISC register file contains 32 general pupose registers. | |
53 | ||
54 | @itemize @bullet | |
55 | @item | |
56 | The 32 general purpose registers are referred to as @samp{r@var{n}}. | |
57 | ||
58 | @item | |
59 | The stack pointer register @samp{r1} can be referenced using the alias | |
60 | @samp{sp}. | |
61 | ||
62 | @item | |
63 | The frame pointer register @samp{r2} can be referenced using the alias | |
64 | @samp{fp}. | |
65 | ||
66 | @item | |
67 | The link register @samp{r9} can be referenced using the alias @samp{lr}. | |
68 | @end itemize | |
69 | ||
70 | Floating point operations use the same general purpose registers. The | |
71 | instructions @code{lf.itof.s} (single precision) and @code{lf.itof.d} (double | |
72 | precision) can be used to convert integer values to floating point. | |
73 | Likewise, instructions @code{lf.ftoi.s} (single precision) and | |
74 | @code{lf.ftoi.d} (double precision) can be used to convert floating point to | |
75 | integer. | |
76 | ||
77 | OpenRISC also contains privileged special purpose registers (SPRs). The | |
78 | SPRs are accessed using the @code{l.mfspr} and @code{l.mtspr} instructions. | |
79 | ||
80 | @node OpenRISC-Relocs | |
81 | @subsection Relocations | |
82 | @cindex OpenRISC relocations | |
83 | @cindex relocations, OpenRISC | |
84 | ||
85 | ELF relocations are available as defined in the OpenRISC architecture | |
86 | specification. | |
87 | ||
88 | @code{R_OR1K_HI_16_IN_INSN} is obtained using @samp{hi} and | |
89 | @code{R_OR1K_LO_16_IN_INSN} and @code{R_OR1K_SLO16} are obtained using | |
90 | @samp{lo}. For signed offsets @code{R_OR1K_AHI16} is obtained from | |
91 | @samp{ha}. For example: | |
92 | ||
93 | @example | |
94 | l.movhi r5, hi(symbol) | |
95 | l.ori r5, r5, lo(symbol) | |
96 | ||
97 | l.movhi r5, ha(symbol) | |
98 | l.addi r5, r5, lo(symbol) | |
99 | @end example | |
100 | ||
101 | These ``high'' mnemonics extract bits 31:16 of their operand, | |
102 | and the ``low'' mnemonics extract bits 15:0 of their operand. | |
103 | ||
104 | The PC relative relocation @code{R_OR1K_GOTPC_HI16} can be obtained by | |
105 | enclosing an operand inside of @samp{gotpchi}. Likewise, the | |
106 | @code{R_OR1K_GOTPC_LO16} relocation can be obtained using @samp{gotpclo}. | |
107 | These are mostly used when assembling PIC code. For example, the | |
108 | standard PIC sequence on OpenRISC to get the base of the global offset | |
109 | table, PC relative, into a register, can be performed as: | |
110 | ||
111 | @example | |
112 | l.jal 0x8 | |
113 | l.movhi r17, gotpchi(_GLOBAL_OFFSET_TABLE_-4) | |
114 | l.ori r17, r17, gotpclo(_GLOBAL_OFFSET_TABLE_+0) | |
115 | l.add r17, r17, r9 | |
116 | @end example | |
117 | ||
118 | Several relocations exist to allow the link editor to perform GOT data | |
119 | references. The @code{R_OR1K_GOT16} relocation can obtained by enclosing an | |
120 | operand inside of @samp{got}. For example, assuming the GOT base is in | |
121 | register @code{r17}. | |
122 | ||
123 | @example | |
124 | l.lwz r19, got(a)(r17) | |
125 | l.lwz r21, 0(r19) | |
126 | @end example | |
127 | ||
128 | Also, several relocations exist for local GOT references. The | |
129 | @code{R_OR1K_GOTOFF_AHI16} relocation can obtained by enclosing an operand | |
130 | inside of @samp{gotoffha}. Likewise, @code{R_OR1K_GOTOFF_LO16} and | |
131 | @code{R_OR1K_GOTOFF_SLO16} can be obtained by enclosing an operand inside of | |
132 | @samp{gotofflo}. For example, assuming the GOT base is in register | |
133 | @code{rl7}: | |
134 | ||
135 | @example | |
136 | l.movhi r19, gotoffha(symbol) | |
137 | l.add r19, r19, r17 | |
138 | l.lwz r19, gotofflo(symbol)(r19) | |
139 | @end example | |
140 | ||
141 | The above PC relative relocations use a @code{l.jal} (jump) instruction | |
142 | and reading of the link register to load the PC. OpenRISC also supports | |
143 | page offset PC relative locations without a jump instruction using the | |
144 | @code{l.adrp} instruction. By default the @code{l.adrp} instruction will | |
145 | create an @code{R_OR1K_PCREL_PG21} relocation. | |
146 | Likewise, @code{BFD_RELOC_OR1K_LO13} and @code{BFD_RELOC_OR1K_SLO13} can | |
147 | be obtained by enclosing an operand inside of @samp{po}. For example: | |
148 | ||
149 | @example | |
150 | l.adrp r3, symbol | |
151 | l.ori r4, r3, po(symbol) | |
152 | l.lbz r5, po(symbol)(r3) | |
153 | l.sb po(symbol)(r3), r6 | |
154 | @end example | |
155 | ||
156 | Likewise the page offset relocations can be used with GOT references. The | |
157 | relocation @code{R_OR1K_GOT_PG21} can be obtained by enclosing an | |
158 | @code{l.adrp} immediate operand inside of @samp{got}. Likewise, | |
159 | @code{R_OR1K_GOT_LO13} can be obtained by enclosing an operand inside of | |
160 | @samp{gotpo}. For example to load the value of a GOT symbol into register | |
161 | @samp{r5} we can do: | |
162 | ||
163 | @example | |
164 | l.adrp r17, got(_GLOBAL_OFFSET_TABLE_) | |
165 | l.lwz r5, gotpo(symbol)(r17) | |
166 | @end example | |
167 | ||
168 | There are many relocations that can be requested for access to | |
169 | thread local storage variables. All of the OpenRISC TLS mnemonics | |
170 | are supported: | |
171 | ||
172 | @itemize @bullet | |
173 | @item | |
174 | @code{R_OR1K_TLS_GD_HI16} is requested using @samp{tlsgdhi}. | |
175 | @item | |
176 | @code{R_OR1K_TLS_GD_LO16} is requested using @samp{tlsgdlo}. | |
177 | @item | |
178 | @code{R_OR1K_TLS_GD_PG21} is requested using @samp{tldgd}. | |
179 | @item | |
180 | @code{R_OR1K_TLS_GD_LO13} is requested using @samp{tlsgdpo}. | |
181 | ||
182 | @item | |
183 | @code{R_OR1K_TLS_LDM_HI16} is requested using @samp{tlsldmhi}. | |
184 | @item | |
185 | @code{R_OR1K_TLS_LDM_LO16} is requested using @samp{tlsldmlo}. | |
186 | @item | |
187 | @code{R_OR1K_TLS_LDM_PG21} is requested using @samp{tldldm}. | |
188 | @item | |
189 | @code{R_OR1K_TLS_LDM_LO13} is requested using @samp{tlsldmpo}. | |
190 | ||
191 | @item | |
192 | @code{R_OR1K_TLS_LDO_HI16} is requested using @samp{dtpoffhi}. | |
193 | @item | |
194 | @code{R_OR1K_TLS_LDO_LO16} is requested using @samp{dtpofflo}. | |
195 | ||
196 | @item | |
197 | @code{R_OR1K_TLS_IE_HI16} is requested using @samp{gottpoffhi}. | |
198 | @item | |
199 | @code{R_OR1K_TLS_IE_AHI16} is requested using @samp{gottpoffha}. | |
200 | @item | |
201 | @code{R_OR1K_TLS_IE_LO16} is requested using @samp{gottpofflo}. | |
202 | @item | |
203 | @code{R_OR1K_TLS_IE_PG21} is requested using @samp{gottp}. | |
204 | @item | |
205 | @code{R_OR1K_TLS_IE_LO13} is requested using @samp{gottppo}. | |
206 | ||
207 | @item | |
208 | @code{R_OR1K_TLS_LE_HI16} is requested using @samp{tpoffhi}. | |
209 | @item | |
210 | @code{R_OR1K_TLS_LE_AHI16} is requested using @samp{tpoffha}. | |
211 | @item | |
212 | @code{R_OR1K_TLS_LE_LO16} is requested using @samp{tpofflo}. | |
213 | @item | |
214 | @code{R_OR1K_TLS_LE_SLO16} also is requested using @samp{tpofflo} | |
215 | depending on the instruction format. | |
216 | @end itemize | |
217 | ||
218 | Here are some example TLS model sequences. | |
219 | ||
220 | First, General Dynamic: | |
221 | ||
222 | @example | |
223 | l.movhi r17, tlsgdhi(symbol) | |
224 | l.ori r17, r17, tlsgdlo(symbol) | |
225 | l.add r17, r17, r16 | |
226 | l.or r3, r17, r17 | |
227 | l.jal plt(__tls_get_addr) | |
228 | l.nop | |
229 | @end example | |
230 | ||
231 | Initial Exec: | |
232 | ||
233 | @example | |
234 | l.movhi r17, gottpoffhi(symbol) | |
235 | l.add r17, r17, r16 | |
236 | l.lwz r17, gottpofflo(symbol)(r17) | |
237 | l.add r17, r17, r10 | |
238 | l.lbs r17, 0(r17) | |
239 | @end example | |
240 | ||
241 | And finally, Local Exec: | |
242 | ||
243 | @example | |
244 | l.movhi r17, tpoffha(symbol) | |
245 | l.add r17, r17, r10 | |
246 | l.addi r17, r17, tpofflo(symbol) | |
247 | l.lbs r17, 0(r17) | |
248 | @end example | |
249 | ||
250 | @node OpenRISC-Float | |
251 | @section Floating Point | |
252 | ||
253 | @cindex floating point, OPENRISC (@sc{ieee}) | |
254 | @cindex OPENRISC floating point (@sc{ieee}) | |
255 | OpenRISC uses @sc{ieee} floating-point numbers. | |
256 | ||
257 | @node OpenRISC-Directives | |
258 | @section OpenRISC Machine Directives | |
259 | ||
260 | @cindex OPENRISC machine directives | |
261 | @cindex machine directives, OPENRISC | |
262 | The OpenRISC version of @code{@value{AS}} supports the following additional | |
263 | machine directives: | |
264 | ||
265 | @table @code | |
266 | @cindex @code{align} directive, OpenRISC | |
267 | @item .align | |
268 | This must be followed by the desired alignment in bytes. | |
269 | ||
270 | @cindex @code{word} directive, OpenRISC | |
271 | @item .word | |
272 | On the OpenRISC, the @code{.word} directive produces a 32 bit value. | |
273 | ||
274 | @cindex @code{nodelay} directive, OpenRISC | |
275 | @item .nodelay | |
276 | On the OpenRISC, the @code{.nodelay} directive sets a flag in elf binaries | |
277 | indicating that the binary is generated catering for no delay slots. | |
278 | ||
279 | @cindex @code{proc} directive, OpenRISC | |
280 | @item .proc | |
281 | This directive is ignored. Any text following it on the same | |
282 | line is also ignored. | |
283 | ||
284 | @cindex @code{endproc} directive, OpenRISC | |
285 | @item .endproc | |
286 | This directive is ignored. Any text following it on the same | |
287 | line is also ignored. | |
288 | @end table | |
289 | ||
290 | @node OpenRISC-Opcodes | |
291 | @section Opcodes | |
292 | ||
293 | @cindex OpenRISC opcode summary | |
294 | @cindex opcode summary, OpenRISC | |
295 | @cindex mnemonics, OpenRISC | |
296 | @cindex instruction summary, LM32 | |
297 | For detailed information on the OpenRISC machine instruction set, see | |
298 | @url{http://www.openrisc.io/architecture/}. | |
299 | ||
300 | @code{@value{AS}} implements all the standard OpenRISC opcodes. |