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b3adc24a | 1 | @c Copyright (C) 2005-2020 Free Software Foundation, Inc. |
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2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node M32C-Dependent | |
7 | @chapter M32C Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter M32C Dependent Features | |
12 | @end ifclear | |
34bca508 | 13 | |
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14 | @cindex M32C support |
15 | ||
16 | @code{@value{AS}} can assemble code for several different members of | |
17 | the Renesas M32C family. Normally the default is to assemble code for | |
18 | the M16C microprocessor. The @code{-m32c} option may be used to | |
19 | change the default to the M32C microprocessor. | |
20 | ||
21 | @menu | |
22 | * M32C-Opts:: M32C Options | |
7c31ae13 | 23 | * M32C-Syntax:: M32C Syntax |
49f58d10 | 24 | @end menu |
34bca508 | 25 | |
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26 | @node M32C-Opts |
27 | @section M32C Options | |
34bca508 | 28 | |
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29 | @cindex options, M32C |
30 | @cindex M32C options | |
34bca508 | 31 | |
6fd4f6cc | 32 | The Renesas M32C version of @code{@value{AS}} has these |
49f58d10 | 33 | machine-dependent options: |
34bca508 | 34 | |
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35 | @table @code |
36 | @item -m32c | |
37 | @cindex @samp{-m32c} option, M32C | |
38 | @cindex architecture options, M32C | |
39 | @cindex M32C architecture option | |
40 | Assemble M32C instructions. | |
34bca508 | 41 | |
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42 | @item -m16c |
43 | @cindex @samp{-m16c} option, M16C | |
44 | @cindex architecture options, M16C | |
45 | @cindex M16C architecture option | |
46 | Assemble M16C instructions (default). | |
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47 | |
48 | @item -relax | |
49 | Enable support for link-time relaxations. | |
50 | ||
51 | @item -h-tick-hex | |
52 | Support H'00 style hex constants in addition to 0x00 style. | |
53 | ||
34bca508 | 54 | |
49f58d10 | 55 | @end table |
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57 | @node M32C-Syntax |
58 | @section M32C Syntax | |
59 | @menu | |
60 | * M32C-Modifiers:: Symbolic Operand Modifiers | |
61 | * M32C-Chars:: Special Characters | |
62 | @end menu | |
63 | ||
fd54057a | 64 | @node M32C-Modifiers |
7c31ae13 | 65 | @subsection Symbolic Operand Modifiers |
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66 | |
67 | @cindex M32C modifiers | |
7c31ae13 | 68 | @cindex modifiers, M32C |
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69 | |
70 | The assembler supports several modifiers when using symbol addresses | |
71 | in M32C instruction operands. The general syntax is the following: | |
72 | ||
73 | @smallexample | |
74 | %modifier(symbol) | |
75 | @end smallexample | |
76 | ||
77 | @table @code | |
78 | @cindex symbol modifiers | |
79 | ||
80 | @item %dsp8 | |
81 | @itemx %dsp16 | |
82 | ||
83 | These modifiers override the assembler's assumptions about how big a | |
84 | symbol's address is. Normally, when it sees an operand like | |
85 | @samp{sym[a0]} it assumes @samp{sym} may require the widest | |
86 | displacement field (16 bits for @samp{-m16c}, 24 bits for | |
87 | @samp{-m32c}). These modifiers tell it to assume the address will fit | |
88 | in an 8 or 16 bit (respectively) unsigned displacement. Note that, of | |
89 | course, if it doesn't actually fit you will get linker errors. Example: | |
90 | ||
91 | @smallexample | |
92 | mov.w %dsp8(sym)[a0],r1 | |
93 | mov.b #0,%dsp8(sym)[a0] | |
94 | @end smallexample | |
95 | ||
96 | @item %hi8 | |
97 | ||
98 | This modifier allows you to load bits 16 through 23 of a 24 bit | |
99 | address into an 8 bit register. This is useful with, for example, the | |
100 | M16C @samp{smovf} instruction, which expects a 20 bit address in | |
101 | @samp{r1h} and @samp{a0}. Example: | |
102 | ||
103 | @smallexample | |
104 | mov.b #%hi8(sym),r1h | |
105 | mov.w #%lo16(sym),a0 | |
106 | smovf.b | |
107 | @end smallexample | |
108 | ||
109 | @item %lo16 | |
110 | ||
111 | Likewise, this modifier allows you to load bits 0 through 15 of a 24 | |
112 | bit address into a 16 bit register. | |
113 | ||
114 | @item %hi16 | |
115 | ||
116 | This modifier allows you to load bits 16 through 31 of a 32 bit | |
117 | address into a 16 bit register. While the M32C family only has 24 | |
118 | bits of address space, it does support addresses in pairs of 16 bit | |
119 | registers (like @samp{a1a0} for the @samp{lde} instruction). This | |
120 | modifier is for loading the upper half in such cases. Example: | |
121 | ||
122 | @smallexample | |
123 | mov.w #%hi16(sym),a1 | |
124 | mov.w #%lo16(sym),a0 | |
125 | @dots{} | |
126 | lde.w [a1a0],r1 | |
127 | @end smallexample | |
128 | ||
129 | @end table | |
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130 | |
131 | @node M32C-Chars | |
132 | @subsection Special Characters | |
133 | ||
134 | @cindex line comment character, M32C | |
135 | @cindex M32C line comment character | |
136 | The presence of a @samp{;} character on a line indicates the start of | |
137 | a comment that extends to the end of that line. | |
138 | ||
139 | If a @samp{#} appears as the first character of a line, the whole line | |
140 | is treated as a comment, but in this case the line can also be a | |
141 | logical line number directive (@pxref{Comments}) or a | |
142 | preprocessor control command (@pxref{Preprocessing}). | |
143 | ||
144 | @cindex line separator, M32C | |
145 | @cindex statement separator, M32C | |
146 | @cindex M32C line separator | |
147 | The @samp{|} character can be used to separate statements on the same | |
148 | line. |