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Commit | Line | Data |
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594266fc SC |
1 | /* Simulator for the Hitachi SH architecture. |
2 | ||
3 | Written by Steve Chamberlain of Cygnus Support. | |
4 | [email protected] | |
5 | ||
6 | This file is part of SH sim | |
7 | ||
8 | ||
9 | THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | ||
11 | Cygnus offers the following for use in the public domain. Cygnus | |
12 | makes no warranty with regard to the software or it's performance | |
13 | and the user accepts the software "AS IS" with all faults. | |
14 | ||
15 | CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO | |
16 | THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
17 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | ||
19 | */ | |
fe031f82 | 20 | |
631f6b24 | 21 | #include <signal.h> |
90fe361f | 22 | #include "sysdep.h" |
594266fc SC |
23 | #include <sys/times.h> |
24 | #include <sys/param.h> | |
631f6b24 | 25 | #include "bfd.h" |
fe031f82 DE |
26 | #include "remote-sim.h" |
27 | #include "../../newlib/libc/sys/sh/sys/syscall.h" | |
594266fc SC |
28 | #define O_RECOMPILE 85 |
29 | #define DEFINE_TABLE | |
30 | ||
31 | #define DISASSEMBLER_TABLE | |
32 | ||
33 | #define SBIT(x) ((x)&sbit) | |
90fe361f SC |
34 | #define R0 saved_state.asregs.regs[0] |
35 | #define Rn saved_state.asregs.regs[n] | |
36 | #define Rm saved_state.asregs.regs[m] | |
37 | #define UR0 (unsigned int)(saved_state.asregs.regs[0]) | |
38 | #define UR (unsigned int)R | |
39 | #define UR (unsigned int)R | |
40 | #define SR0 saved_state.asregs.regs[0] | |
41 | #define GBR saved_state.asregs.gbr | |
42 | #define VBR saved_state.asregs.vbr | |
43 | #define MACH saved_state.asregs.mach | |
44 | #define MACL saved_state.asregs.macl | |
45 | #define M saved_state.asregs.sr.bits.m | |
46 | #define Q saved_state.asregs.sr.bits.q | |
594266fc | 47 | |
594266fc SC |
48 | #define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word) |
49 | #define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;} | |
50 | ||
51 | #define PC pc | |
52 | #define C cycles | |
53 | ||
fe031f82 DE |
54 | char *fail() |
55 | { | |
56 | ||
57 | ||
58 | } | |
59 | ||
60 | ||
61 | ||
62 | /* Define this to enable register lifetime checking. | |
63 | The compiler generates "add #0,rn" insns to mark registers as invalid, | |
64 | the simulator uses this info to call fail if it finds a ref to an invalid | |
65 | register before a def | |
66 | ||
67 | #define PARANOID | |
68 | */ | |
69 | ||
70 | #ifdef PARANOID | |
71 | int valid[16]; | |
72 | #define CREF(x) if(!valid[x]) fail(); | |
73 | #define CDEF(x) valid[x] = 1; | |
74 | #define UNDEF(x) valid[x] = 0; | |
75 | #else | |
76 | #define CREF(x) | |
77 | #define CDEF(x) | |
78 | #define UNDEF(x) | |
79 | #endif | |
80 | ||
81 | ||
90fe361f | 82 | #ifdef TARGET_BIG_ENDIAN |
fe031f82 | 83 | #if 0 |
90fe361f SC |
84 | #define LMEM(x) *((long *)(memory+((x)&maskl))) |
85 | #define BMEM(x) *((char *)(memory+((x)&maskb))) | |
86 | #define UWMEM(x) *((unsigned short *)(memory+((x)&maskw))) | |
87 | #define SWMEM(x) *((short *)(memory+((x)&maskw))) | |
88 | #define WLAT(x,value) (LMEM(x) = value) | |
89 | #define RLAT(x) (LMEM(x)) | |
90 | #define WWAT(x,value) (UWMEM(x) = value) | |
91 | #define RSWAT(x) (SWMEM(x)) | |
92 | #define RUWAT(x) (UWMEM(x)) | |
93 | #define WBAT(x,value) (BMEM(x) = value) | |
94 | #define RBAT(x) (BMEM(x)) | |
95 | #else | |
fe031f82 DE |
96 | #define LMEM(x) ((x)&maskl ? fail() : *((long *)(memory+((x)&maskl)))) |
97 | #define BMEM(x) ((x) &maskb ? fail() : *((char *)(memory+((x)&maskb)))) | |
98 | #define UWMEM(x) ((x)&maskw ? fail() : *((unsigned short *)(memory+((x)&maskw)))) | |
99 | #define SWMEM(x) ((x)&maskw ? fail() : *((short *)(memory+((x)&maskw)))) | |
100 | #define WLAT(x,value) (LMEM(x) = value) | |
101 | #define RLAT(x) (LMEM(x)) | |
102 | #define WWAT(x,value) (UWMEM(x) = value) | |
103 | #define RSWAT(x) (SWMEM(x)) | |
104 | #define RUWAT(x) (UWMEM(x)) | |
105 | #define WBAT(x,value) (BMEM(x) = value) | |
106 | #define RBAT(x) (BMEM(x)) | |
107 | #endif | |
108 | #else | |
90fe361f SC |
109 | /* For little endian or unknown host machines */ |
110 | #define WLAT(x,value)\ | |
111 | { int v = value; unsigned char *p = memory + ((x) & maskl);\ | |
112 | p[0] =v>>24;p[1] = v>>16;p[2]=v>>8;p[3]=v; } | |
113 | ||
114 | #define WWAT(x,value)\ | |
115 | { int v = value; unsigned char *p = memory + (x & maskw);p[0] =v>>8;p[1] = v ;} | |
116 | ||
117 | #define WBAT(x,value)\ | |
118 | { unsigned char *p = memory + (x & maskb);p[0] =value;} | |
119 | ||
120 | #define RLAT(x)\ | |
121 | ((memory[x&maskl]<<24)|(memory[(x&maskl)+1]<<16)|(memory[(x&maskl)+2]<<8)| (memory[(x&maskl)+3])) | |
122 | ||
123 | #define RWAT(x)\ | |
124 | ((memory[x&maskw]<<8)|(memory[(x&maskw)+1])) | |
125 | ||
126 | #define RBAT(x)\ | |
127 | ((memory[x&maskb])) | |
128 | ||
129 | #define RUWAT(x) (RWAT(x) & 0xffff) | |
130 | #define RSWAT(x) ((short)(RWAT(x))) | |
131 | #define RSBAT(x) (SEXT(RBAT(x))) | |
132 | ||
133 | #endif | |
134 | ||
135 | ||
136 | ||
137 | #define SEXT(x) (((x&0xff) ^ (~0x7f))+0x80) | |
138 | #define SEXTW(y) ((int)((short)y)) | |
139 | ||
140 | #define SL(TEMPPC) iword= RUWAT(TEMPPC); goto top; | |
141 | ||
142 | ||
fe031f82 DE |
143 | int empty[16]; |
144 | ||
90fe361f SC |
145 | #define L(x) thislock = x; |
146 | #define TL(x) if ((x) == prevlock) stalls++; | |
147 | #define TB(x,y) if ((x) == prevlock || (y)==prevlock) stalls++; | |
fe031f82 DE |
148 | |
149 | #ifdef __GO32__ | |
90fe361f | 150 | int sim_memory_size = 19; |
fe031f82 DE |
151 | #else |
152 | int sim_memory_size = 24; | |
153 | #endif | |
154 | ||
90fe361f SC |
155 | static int sim_profile_size = 17; |
156 | static int nsamples; | |
631f6b24 DE |
157 | static int sim_timeout; |
158 | ||
594266fc SC |
159 | typedef union |
160 | { | |
161 | ||
162 | struct | |
163 | { | |
164 | ||
165 | int regs[16]; | |
166 | int pc; | |
167 | int pr; | |
168 | ||
169 | int gbr; | |
170 | int vbr; | |
171 | int mach; | |
172 | int macl; | |
173 | ||
174 | ||
175 | union | |
176 | { | |
177 | struct | |
178 | { | |
90fe361f SC |
179 | unsigned int d0:22; |
180 | unsigned int m:1; | |
181 | unsigned int q:1; | |
182 | unsigned int i:4; | |
183 | unsigned int d1:2; | |
184 | unsigned int s:1; | |
185 | unsigned int t:1; | |
594266fc SC |
186 | } |
187 | bits; | |
188 | int word; | |
189 | } | |
190 | sr; | |
191 | int ticks; | |
90fe361f | 192 | int stalls; |
594266fc SC |
193 | int cycles; |
194 | int insts; | |
594266fc | 195 | |
90fe361f SC |
196 | |
197 | int prevlock; | |
198 | int thislock; | |
199 | int exception; | |
200 | int msize; | |
201 | #define PROFILE_FREQ 1 | |
202 | #define PROFILE_SHIFT 2 | |
203 | int profile; | |
204 | unsigned short *profile_hist; | |
205 | unsigned char *memory; | |
fdc506e6 | 206 | |
594266fc SC |
207 | } |
208 | asregs; | |
90fe361f | 209 | int asints[28]; |
594266fc SC |
210 | |
211 | } | |
212 | ||
213 | saved_state_type; | |
594266fc SC |
214 | saved_state_type saved_state; |
215 | ||
594266fc SC |
216 | static int |
217 | get_now () | |
218 | { | |
fe031f82 | 219 | return time((long*)0); |
594266fc SC |
220 | } |
221 | ||
222 | static int | |
223 | now_persec () | |
224 | { | |
631f6b24 | 225 | return 1; |
90fe361f SC |
226 | } |
227 | ||
228 | ||
229 | ||
230 | static FILE *profile_file; | |
231 | ||
fdc506e6 SC |
232 | static void |
233 | swap (b, n) | |
90fe361f SC |
234 | unsigned char *b; |
235 | int n; | |
fdc506e6 SC |
236 | { |
237 | b[0] = n >> 24; | |
238 | b[1] = n >> 16; | |
239 | b[2] = n >> 8; | |
240 | b[3] = n >> 0; | |
90fe361f | 241 | } |
fdc506e6 SC |
242 | static void |
243 | swap16 (b, n) | |
90fe361f SC |
244 | unsigned char *b; |
245 | int n; | |
fdc506e6 SC |
246 | { |
247 | b[0] = n >> 8; | |
248 | b[1] = n >> 0; | |
594266fc SC |
249 | } |
250 | ||
90fe361f | 251 | static void |
fdc506e6 | 252 | swapout (n) |
90fe361f SC |
253 | int n; |
254 | { | |
fdc506e6 | 255 | if (profile_file) |
90fe361f SC |
256 | { |
257 | char b[4]; | |
fdc506e6 SC |
258 | swap (b, n); |
259 | fwrite (b, 4, 1, profile_file); | |
90fe361f | 260 | } |
fdc506e6 | 261 | } |
90fe361f SC |
262 | |
263 | static void | |
fdc506e6 | 264 | swapout16 (n) |
90fe361f SC |
265 | int n; |
266 | { | |
267 | char b[4]; | |
fdc506e6 SC |
268 | swap16 (b, n); |
269 | fwrite (b, 2, 1, profile_file); | |
270 | } | |
90fe361f SC |
271 | |
272 | ||
273 | /* Turn a pointer in a register into a pointer into real memory. */ | |
274 | ||
275 | static char * | |
276 | ptr (x) | |
277 | int x; | |
278 | { | |
fdc506e6 | 279 | return (char *) (x + saved_state.asregs.memory); |
90fe361f SC |
280 | } |
281 | ||
fe031f82 DE |
282 | static char *wwat(ptr, val) |
283 | char *ptr; | |
284 | int val; | |
285 | { | |
286 | ptr[0] = val >> 8; | |
287 | ptr[1] = val; | |
288 | return ptr+2; | |
289 | } | |
290 | ||
291 | static char *wlat(ptr,val) | |
292 | char *ptr; | |
293 | int val; | |
294 | { | |
295 | ptr[0] = val>> 24; | |
296 | ptr[1] = val >> 16; | |
297 | ptr[2] = val >>8; | |
298 | ptr[3] = val; | |
299 | return ptr+4; | |
300 | } | |
301 | ||
302 | /* Simulate a monitor trap, put the result into r0 and errno into r1 */ | |
90fe361f SC |
303 | |
304 | static void | |
594266fc | 305 | trap (i, regs) |
90fe361f | 306 | int i; |
594266fc SC |
307 | int *regs; |
308 | { | |
309 | switch (i) | |
310 | { | |
311 | case 1: | |
312 | printf ("%c", regs[0]); | |
313 | break; | |
314 | case 2: | |
315 | saved_state.asregs.exception = SIGQUIT; | |
316 | break; | |
90fe361f SC |
317 | case 3: |
318 | { | |
319 | extern int errno; | |
320 | int perrno = errno; | |
321 | errno = 0; | |
322 | ||
323 | switch (regs[4]) | |
324 | { | |
fe031f82 DE |
325 | #ifndef __GO32__ |
326 | case SYS_fork: | |
327 | regs[0] = fork(); | |
328 | break; | |
329 | ||
330 | case SYS_execve: | |
331 | regs[0] = execve(ptr(regs[5]), ptr(regs[6]), ptr(regs[7])); | |
332 | break; | |
333 | case SYS_execv: | |
334 | regs[0] = execv(ptr(regs[5]), ptr(regs[6])); | |
335 | break; | |
336 | case SYS_pipe: | |
337 | { | |
338 | char* buf; | |
339 | int host_fd[2]; | |
340 | ||
341 | buf = ptr(regs[5]); | |
342 | ||
343 | regs[0] = pipe(host_fd); | |
344 | ||
345 | buf = wlat(buf, host_fd[0]); | |
346 | buf = wlat(buf, host_fd[1]); | |
347 | } | |
348 | break; | |
349 | ||
350 | case SYS_wait: | |
351 | regs[0] = wait(ptr(regs[5])); | |
352 | break; | |
353 | #endif | |
354 | case SYS_read: | |
355 | regs[0] = read (regs[5], ptr (regs[6]), regs[7]); | |
90fe361f | 356 | break; |
fe031f82 DE |
357 | case SYS_write: |
358 | regs[0] = write (regs[5], ptr (regs[6]), regs[7]); | |
90fe361f | 359 | break; |
fe031f82 DE |
360 | case SYS_lseek: |
361 | regs[0] = lseek (regs[5], regs[6], regs[7]); | |
90fe361f | 362 | break; |
fe031f82 DE |
363 | case SYS_close: |
364 | regs[0] = close (regs[5]); | |
90fe361f | 365 | break; |
fe031f82 DE |
366 | case SYS_open: |
367 | regs[0] = open (ptr (regs[5]), regs[6]); | |
90fe361f | 368 | break; |
fe031f82 | 369 | case SYS_exit: |
631f6b24 DE |
370 | /* EXIT */ |
371 | saved_state.asregs.exception = SIGQUIT; | |
372 | errno = regs[5]; | |
373 | break; | |
374 | ||
fe031f82 DE |
375 | case SYS_stat: /* added at hmsi */ |
376 | /* stat system call */ | |
377 | { | |
378 | struct stat host_stat; | |
379 | char *buf; | |
380 | ||
381 | regs[0] = stat( ptr(regs[5]), &host_stat); | |
382 | ||
383 | buf = ptr(regs[6]); | |
384 | ||
385 | buf = wwat(buf, host_stat.st_dev); | |
386 | buf = wwat(buf, host_stat.st_ino); | |
387 | ||
388 | buf = wlat(buf, host_stat.st_mode); | |
389 | ||
390 | buf = wwat(buf, host_stat.st_nlink); | |
391 | buf = wwat(buf, host_stat.st_uid); | |
392 | buf = wwat(buf, host_stat.st_gid); | |
393 | buf = wwat(buf, host_stat.st_rdev); | |
394 | ||
395 | buf = wlat(buf, host_stat.st_size); | |
396 | buf = wlat(buf, host_stat.st_atime); | |
397 | buf = wlat(buf, 0); | |
398 | buf = wlat(buf, host_stat.st_mtime); | |
399 | buf = wlat(buf, 0); | |
400 | buf = wlat(buf, host_stat.st_ctime); | |
401 | buf = wlat(buf, 0); | |
402 | buf = wlat(buf, host_stat.st_blksize); | |
403 | buf = wlat(buf, host_stat.st_blocks); | |
404 | } | |
405 | break; | |
406 | ||
407 | case SYS_chown: | |
408 | regs[0] = chown( ptr(regs[5]), regs[6], regs[7] ); | |
409 | break; | |
410 | case SYS_chmod: | |
411 | regs[0] = chmod( ptr(regs[5]), regs[6]); | |
412 | break; | |
413 | case SYS_utime: | |
414 | regs[0] = utime (ptr(regs[5]), ptr(regs[6])); | |
415 | break; | |
416 | ||
90fe361f SC |
417 | default: |
418 | abort (); | |
419 | } | |
fe031f82 | 420 | regs[1] = errno; |
90fe361f SC |
421 | errno = perrno; |
422 | } | |
423 | ||
424 | break; | |
425 | ||
594266fc | 426 | case 255: |
631f6b24 | 427 | saved_state.asregs.exception = SIGTRAP; |
fe031f82 | 428 | saved_state.asregs.exception = 5; |
594266fc SC |
429 | break; |
430 | } | |
431 | ||
432 | } | |
433 | void | |
434 | control_c (sig, code, scp, addr) | |
435 | int sig; | |
436 | int code; | |
437 | char *scp; | |
438 | char *addr; | |
439 | { | |
440 | saved_state.asregs.exception = SIGINT; | |
441 | } | |
442 | ||
443 | ||
fdc506e6 | 444 | static int |
90fe361f | 445 | div1 (R, iRn2, iRn1, T) |
594266fc | 446 | int *R; |
90fe361f SC |
447 | int iRn1; |
448 | int iRn2; | |
594266fc SC |
449 | int T; |
450 | { | |
451 | unsigned long tmp0; | |
452 | unsigned char old_q, tmp1; | |
90fe361f | 453 | |
594266fc | 454 | old_q = Q; |
90fe361f SC |
455 | Q = (unsigned char) ((0x80000000 & R[iRn1]) != 0); |
456 | R[iRn1] <<= 1; | |
457 | R[iRn1] |= (unsigned long) T; | |
458 | ||
459 | switch (old_q) | |
594266fc | 460 | { |
fdc506e6 | 461 | case 0: |
90fe361f | 462 | switch (M) |
fdc506e6 SC |
463 | { |
464 | case 0: | |
465 | tmp0 = R[iRn1]; | |
466 | R[iRn1] -= R[iRn2]; | |
467 | tmp1 = (R[iRn1] > tmp0); | |
468 | switch (Q) | |
469 | { | |
470 | case 0: | |
471 | Q = tmp1; | |
472 | break; | |
473 | case 1: | |
474 | Q = (unsigned char) (tmp1 == 0); | |
475 | break; | |
476 | } | |
477 | break; | |
478 | case 1: | |
479 | tmp0 = R[iRn1]; | |
480 | R[iRn1] += R[iRn2]; | |
481 | tmp1 = (R[iRn1] < tmp0); | |
482 | switch (Q) | |
483 | { | |
484 | case 0: | |
485 | Q = (unsigned char) (tmp1 == 0); | |
486 | break; | |
487 | case 1: | |
488 | Q = tmp1; | |
489 | break; | |
490 | } | |
491 | break; | |
492 | } | |
594266fc SC |
493 | break; |
494 | case 1: | |
495 | switch (M) | |
496 | { | |
fdc506e6 | 497 | case 0: |
90fe361f SC |
498 | tmp0 = R[iRn1]; |
499 | R[iRn1] += R[iRn2]; | |
500 | tmp1 = (R[iRn1] < tmp0); | |
501 | switch (Q) | |
502 | { | |
503 | case 0: | |
504 | Q = tmp1; | |
505 | break; | |
506 | case 1: | |
507 | Q = (unsigned char) (tmp1 == 0); | |
fdc506e6 | 508 | break; |
90fe361f | 509 | } |
594266fc | 510 | break; |
fdc506e6 | 511 | case 1: |
90fe361f SC |
512 | tmp0 = R[iRn1]; |
513 | R[iRn1] -= R[iRn2]; | |
514 | tmp1 = (R[iRn1] > tmp0); | |
515 | switch (Q) | |
516 | { | |
517 | case 0: | |
518 | Q = (unsigned char) (tmp1 == 0); | |
519 | break; | |
520 | case 1: | |
521 | Q = tmp1; | |
522 | break; | |
523 | } | |
594266fc SC |
524 | break; |
525 | } | |
526 | break; | |
90fe361f SC |
527 | } |
528 | T = (Q == M); | |
529 | return T; | |
530 | } | |
531 | ||
90fe361f | 532 | |
fdc506e6 SC |
533 | static void |
534 | dmul (sign, rm, rn) | |
535 | int sign; | |
536 | unsigned int rm; | |
537 | unsigned int rn; | |
538 | { | |
539 | unsigned long RnL, RnH; | |
540 | unsigned long RmL, RmH; | |
541 | unsigned long temp0, temp1, temp2, temp3; | |
542 | unsigned long Res2, Res1, Res0; | |
90fe361f | 543 | |
594266fc | 544 | |
fdc506e6 | 545 | if (!sign) |
90fe361f | 546 | { |
594266fc | 547 | |
fdc506e6 SC |
548 | RnL = rn & 0xffff; |
549 | RnH = (rn >> 16) & 0xffff; | |
550 | RmL = rm & 0xffff; | |
551 | RmH = (rm >> 16) & 0xffff; | |
552 | temp0 = RmL * RnL; | |
553 | temp1 = RmH * RnL; | |
554 | temp2 = RmL * RnH; | |
555 | temp3 = RmH * RnH; | |
556 | Res2 = 0; | |
557 | Res1 = temp1 + temp2; | |
558 | if (Res1 < temp1) | |
559 | Res2 += 0x00010000; | |
560 | temp1 = (Res1 << 16) & 0xffff0000; | |
561 | Res0 = temp0 + temp1; | |
562 | if (Res0 < temp0) | |
563 | Res2 += 1; | |
564 | Res2 += ((Res1 >> 16) & 0xffff) + temp3; | |
565 | MACH = Res2; | |
566 | MACL = Res0; | |
594266fc | 567 | |
90fe361f | 568 | } |
fdc506e6 SC |
569 | |
570 | else | |
90fe361f | 571 | { |
fdc506e6 | 572 | abort (); |
90fe361f | 573 | } |
fdc506e6 | 574 | |
594266fc SC |
575 | } |
576 | ||
fdc506e6 | 577 | |
90fe361f SC |
578 | /* Set the memory size to the power of two provided. */ |
579 | ||
580 | void | |
581 | sim_size (power) | |
582 | int power; | |
583 | ||
584 | { | |
585 | saved_state.asregs.msize = 1 << power; | |
586 | ||
fdc506e6 | 587 | sim_memory_size = power; |
90fe361f SC |
588 | |
589 | ||
590 | if (saved_state.asregs.memory) | |
591 | { | |
592 | free (saved_state.asregs.memory); | |
593 | } | |
594 | ||
595 | saved_state.asregs.memory = | |
596 | (unsigned char *) calloc (64, saved_state.asregs.msize / 64); | |
597 | ||
598 | if (!saved_state.asregs.memory) | |
599 | { | |
600 | fprintf (stderr, | |
601 | "Not enough VM for simuation of %d bytes of RAM\n", | |
602 | saved_state.asregs.msize); | |
603 | ||
604 | saved_state.asregs.msize = 1; | |
fdc506e6 | 605 | saved_state.asregs.memory = (unsigned char *) calloc (1, 1); |
90fe361f SC |
606 | } |
607 | } | |
608 | ||
609 | ||
610 | ||
fdc506e6 | 611 | static |
90fe361f SC |
612 | void |
613 | init_pointers () | |
614 | { | |
615 | if (saved_state.asregs.msize != 1 << sim_memory_size) | |
616 | { | |
617 | sim_size (sim_memory_size); | |
618 | } | |
619 | ||
620 | if (saved_state.asregs.profile && !profile_file) | |
621 | { | |
fdc506e6 | 622 | profile_file = fopen ("gmon.out", "wb"); |
90fe361f | 623 | /* Seek to where to put the call arc data */ |
fdc506e6 | 624 | nsamples = (1 << sim_profile_size); |
90fe361f | 625 | |
fdc506e6 SC |
626 | fseek (profile_file, nsamples * 2 + 12, 0); |
627 | ||
628 | if (!profile_file) | |
90fe361f | 629 | { |
fdc506e6 | 630 | fprintf (stderr, "Can't open gmon.out\n"); |
90fe361f | 631 | } |
fdc506e6 | 632 | else |
90fe361f SC |
633 | { |
634 | saved_state.asregs.profile_hist = | |
fdc506e6 | 635 | (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64)); |
90fe361f SC |
636 | } |
637 | } | |
638 | } | |
639 | ||
640 | static void | |
fdc506e6 | 641 | dump_profile () |
90fe361f | 642 | { |
fdc506e6 | 643 | unsigned int minpc; |
90fe361f SC |
644 | unsigned int maxpc; |
645 | unsigned short *p; | |
646 | ||
647 | int thisshift; | |
fdc506e6 | 648 | |
90fe361f SC |
649 | unsigned short *first; |
650 | ||
651 | int i; | |
652 | p = saved_state.asregs.profile_hist; | |
fdc506e6 SC |
653 | minpc = 0; |
654 | maxpc = (1 << sim_profile_size); | |
655 | ||
656 | fseek (profile_file, 0L, 0); | |
657 | swapout (minpc << PROFILE_SHIFT); | |
658 | swapout (maxpc << PROFILE_SHIFT); | |
659 | swapout (nsamples * 2 + 12); | |
660 | for (i = 0; i < nsamples; i++) | |
661 | swapout16 (saved_state.asregs.profile_hist[i]); | |
662 | ||
90fe361f SC |
663 | } |
664 | ||
fdc506e6 SC |
665 | static int |
666 | gotcall (from, to) | |
90fe361f SC |
667 | int from; |
668 | int to; | |
669 | { | |
fdc506e6 SC |
670 | swapout (from); |
671 | swapout (to); | |
672 | swapout (1); | |
90fe361f SC |
673 | } |
674 | ||
675 | #define MMASKB ((saved_state.asregs.msize -1) & ~0) | |
fe031f82 | 676 | |
90fe361f | 677 | void |
fe031f82 DE |
678 | sim_resume (step, siggnal) |
679 | int step, siggnal; | |
594266fc | 680 | { |
fdc506e6 | 681 | register unsigned int pc; |
90fe361f SC |
682 | register int cycles = 0; |
683 | register int stalls = 0; | |
684 | register int insts = 0; | |
685 | register int prevlock; | |
fdc506e6 SC |
686 | register int thislock; |
687 | register unsigned int doprofile; | |
90fe361f | 688 | |
594266fc SC |
689 | int tick_start = get_now (); |
690 | void (*prev) (); | |
691 | extern unsigned char sh_jump_table0[]; | |
692 | ||
693 | register unsigned char *jump_table = sh_jump_table0; | |
694 | ||
695 | register int *R = &(saved_state.asregs.regs[0]); | |
696 | register int T; | |
697 | register int PR; | |
698 | ||
90fe361f SC |
699 | register int maskb = ((saved_state.asregs.msize - 1) & ~0); |
700 | register int maskw = ((saved_state.asregs.msize - 1) & ~1); | |
701 | register int maskl = ((saved_state.asregs.msize - 1) & ~3); | |
631f6b24 | 702 | register unsigned char *memory ; |
90fe361f SC |
703 | register unsigned int sbit = (1 << 31); |
704 | ||
594266fc SC |
705 | prev = signal (SIGINT, control_c); |
706 | ||
fdc506e6 SC |
707 | init_pointers (); |
708 | ||
631f6b24 DE |
709 | memory = saved_state.asregs.memory; |
710 | ||
594266fc SC |
711 | if (step) |
712 | { | |
713 | saved_state.asregs.exception = SIGTRAP; | |
714 | } | |
715 | else | |
716 | { | |
717 | saved_state.asregs.exception = 0; | |
718 | } | |
719 | ||
720 | pc = saved_state.asregs.pc; | |
721 | PR = saved_state.asregs.pr; | |
722 | T = saved_state.asregs.sr.bits.t; | |
90fe361f SC |
723 | prevlock = saved_state.asregs.prevlock; |
724 | thislock = saved_state.asregs.thislock; | |
725 | doprofile = saved_state.asregs.profile; | |
726 | ||
727 | /* If profiling not enabled, disable it by asking for | |
728 | profiles infrequently. */ | |
fdc506e6 | 729 | if (doprofile == 0) |
90fe361f | 730 | doprofile = ~0; |
fdc506e6 | 731 | |
594266fc SC |
732 | do |
733 | { | |
fdc506e6 SC |
734 | register unsigned int iword = RUWAT (pc); |
735 | register unsigned int ult; | |
594266fc SC |
736 | |
737 | insts++; | |
738 | top: | |
739 | ||
740 | #include "code.c" | |
741 | ||
90fe361f | 742 | |
594266fc | 743 | pc += 2; |
90fe361f SC |
744 | prevlock = thislock; |
745 | thislock = 30; | |
594266fc | 746 | cycles++; |
90fe361f SC |
747 | |
748 | if (cycles >= doprofile) | |
749 | { | |
631f6b24 DE |
750 | if (cycles > sim_timeout) |
751 | saved_state.asregs.exception = SIGQUIT; | |
752 | ||
90fe361f SC |
753 | saved_state.asregs.cycles += doprofile; |
754 | cycles -= doprofile; | |
fdc506e6 | 755 | if (saved_state.asregs.profile_hist) |
90fe361f SC |
756 | { |
757 | int n = pc >> PROFILE_SHIFT; | |
fdc506e6 | 758 | if (n < nsamples) |
90fe361f SC |
759 | { |
760 | int i = saved_state.asregs.profile_hist[n]; | |
761 | if (i < 65000) | |
fdc506e6 | 762 | saved_state.asregs.profile_hist[n] = i + 1; |
90fe361f | 763 | } |
fdc506e6 | 764 | |
90fe361f SC |
765 | } |
766 | } | |
594266fc SC |
767 | } |
768 | while (!saved_state.asregs.exception); | |
769 | ||
90fe361f | 770 | if (saved_state.asregs.exception == SIGILL) |
594266fc | 771 | { |
90fe361f | 772 | pc -= 2; |
594266fc | 773 | } |
90fe361f | 774 | |
594266fc SC |
775 | saved_state.asregs.ticks += get_now () - tick_start; |
776 | saved_state.asregs.cycles += cycles; | |
90fe361f | 777 | saved_state.asregs.stalls += stalls; |
594266fc SC |
778 | saved_state.asregs.insts += insts; |
779 | saved_state.asregs.pc = pc; | |
780 | saved_state.asregs.sr.bits.t = T; | |
781 | saved_state.asregs.pr = PR; | |
782 | ||
90fe361f SC |
783 | saved_state.asregs.prevlock = prevlock; |
784 | saved_state.asregs.thislock = thislock; | |
785 | ||
786 | ||
787 | if (profile_file) | |
788 | { | |
fdc506e6 | 789 | dump_profile (); |
90fe361f | 790 | } |
fdc506e6 | 791 | |
594266fc SC |
792 | signal (SIGINT, prev); |
793 | } | |
794 | ||
795 | ||
796 | ||
90fe361f | 797 | |
631f6b24 | 798 | int |
594266fc | 799 | sim_write (addr, buffer, size) |
fe031f82 | 800 | SIM_ADDR addr; |
594266fc SC |
801 | unsigned char *buffer; |
802 | int size; | |
803 | { | |
804 | int i; | |
805 | init_pointers (); | |
806 | ||
807 | for (i = 0; i < size; i++) | |
808 | { | |
809 | saved_state.asregs.memory[MMASKB & (addr + i)] = buffer[i]; | |
810 | } | |
fe031f82 | 811 | return size; |
594266fc SC |
812 | } |
813 | ||
631f6b24 | 814 | int |
594266fc | 815 | sim_read (addr, buffer, size) |
fe031f82 DE |
816 | SIM_ADDR addr; |
817 | unsigned char *buffer; | |
594266fc SC |
818 | int size; |
819 | { | |
820 | int i; | |
821 | ||
822 | init_pointers (); | |
823 | ||
824 | for (i = 0; i < size; i++) | |
825 | { | |
826 | buffer[i] = saved_state.asregs.memory[MMASKB & (addr + i)]; | |
827 | } | |
fe031f82 | 828 | return size; |
594266fc SC |
829 | } |
830 | ||
831 | ||
90fe361f | 832 | void |
594266fc SC |
833 | sim_store_register (rn, value) |
834 | int rn; | |
fe031f82 | 835 | unsigned char *value; |
594266fc | 836 | { |
631f6b24 | 837 | saved_state.asregs.regs[rn] = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | (value[3]); |
594266fc SC |
838 | } |
839 | ||
90fe361f | 840 | void |
594266fc SC |
841 | sim_fetch_register (rn, buf) |
842 | int rn; | |
fe031f82 | 843 | unsigned char *buf; |
594266fc | 844 | { |
594266fc SC |
845 | int value = ((int *) (&saved_state))[rn]; |
846 | ||
fdc506e6 | 847 | swap (buf, value); |
594266fc SC |
848 | } |
849 | ||
90fe361f | 850 | |
594266fc SC |
851 | int |
852 | sim_trace () | |
853 | { | |
594266fc | 854 | return 0; |
594266fc SC |
855 | } |
856 | ||
fe031f82 DE |
857 | void |
858 | sim_stop_reason (reason, sigrc) | |
859 | enum sim_stop *reason; | |
631f6b24 | 860 | int *sigrc; |
594266fc | 861 | { |
fe031f82 | 862 | *reason = sim_stopped; |
631f6b24 | 863 | *sigrc = saved_state.asregs.exception; |
594266fc SC |
864 | } |
865 | ||
866 | ||
90fe361f | 867 | void |
fe031f82 DE |
868 | sim_info (verbose) |
869 | int verbose; | |
594266fc SC |
870 | { |
871 | double timetaken = (double) saved_state.asregs.ticks / (double) now_persec (); | |
90fe361f SC |
872 | double virttime = saved_state.asregs.cycles / 36.0e6; |
873 | ||
fe031f82 DE |
874 | printf_filtered ("\n\n# instructions executed %10d\n", saved_state.asregs.insts); |
875 | printf_filtered ("# cycles %10d\n", saved_state.asregs.cycles); | |
876 | printf_filtered ("# pipeline stalls %10d\n", saved_state.asregs.stalls); | |
877 | printf_filtered ("# real time taken %10.4f\n", timetaken); | |
878 | printf_filtered ("# virtual time taken %10.4f\n", virttime); | |
879 | printf_filtered ("# profiling size %10d\n", sim_profile_size); | |
880 | printf_filtered ("# profiling frequency %10d\n", saved_state.asregs.profile); | |
881 | printf_filtered ("# profile maxpc %10x\n", (1 << sim_profile_size) << PROFILE_SHIFT); | |
fdc506e6 SC |
882 | |
883 | if (timetaken != 0) | |
90fe361f | 884 | { |
fe031f82 DE |
885 | printf_filtered ("# cycles/second %10d\n", (int) (saved_state.asregs.cycles / timetaken)); |
886 | printf_filtered ("# simulation ratio %10.4f\n", virttime / timetaken); | |
90fe361f | 887 | } |
594266fc SC |
888 | } |
889 | ||
90fe361f SC |
890 | |
891 | void | |
fdc506e6 | 892 | sim_set_profile (n) |
631f6b24 | 893 | int n; |
594266fc | 894 | { |
90fe361f SC |
895 | saved_state.asregs.profile = n; |
896 | } | |
897 | ||
898 | void | |
fdc506e6 | 899 | sim_set_profile_size (n) |
631f6b24 | 900 | int n; |
90fe361f SC |
901 | { |
902 | sim_profile_size = n; | |
594266fc | 903 | } |
631f6b24 DE |
904 | |
905 | ||
906 | void | |
fe031f82 DE |
907 | sim_open (name) |
908 | char *name; | |
631f6b24 | 909 | { |
fe031f82 DE |
910 | /* nothing to do */ |
911 | } | |
631f6b24 | 912 | |
fe031f82 DE |
913 | void |
914 | sim_close (quitting) | |
915 | int quitting; | |
916 | { | |
917 | /* nothing to do */ | |
631f6b24 DE |
918 | } |
919 | ||
920 | int | |
fe031f82 DE |
921 | sim_load (prog, from_tty) |
922 | char *prog; | |
923 | int from_tty; | |
631f6b24 | 924 | { |
fe031f82 DE |
925 | /* Return nonzero so GDB will handle it. */ |
926 | return 1; | |
631f6b24 | 927 | } |
fe031f82 DE |
928 | |
929 | void | |
930 | sim_create_inferior (start_address, argv, env) | |
931 | SIM_ADDR start_address; | |
932 | char **argv; | |
933 | char **env; | |
631f6b24 | 934 | { |
fe031f82 | 935 | saved_state.asregs.pc = start_address; |
631f6b24 DE |
936 | } |
937 | ||
fe031f82 DE |
938 | void |
939 | sim_kill () | |
940 | { | |
941 | /* nothing to do */ | |
942 | } |