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* Makefile.in (SFILES): Add target-memory.c.
[binutils.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
76a9d10f
MK		 3 Copyright (C) 2001, 2002, 2004, 2005, 2006
4 Free Software Foundation, Inc.
2aa830e4
DJ		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
2aa830e4
DJ		 22
23#include "defs.h"
24#include "gdbcore.h"
25#include "target.h"
26#include "solib-svr4.h"
19ed69dd 27#include "osabi.h"
96f026fc 28#include "mips-tdep.h"
19ed69dd 29#include "gdb_string.h"
96f026fc 30#include "gdb_assert.h"
6de918a6 31#include "frame.h"
2fdf551c 32#include "regcache.h"
5792a79b
DJ		 33#include "trad-frame.h"
34#include "tramp-frame.h"
d05f6826 35#include "floatformat.h"
d37eb719 36#include "mips-linux-tdep.h"
2aa830e4
DJ		 37
38/* Figure out where the longjmp will land.
295093a4
MS		 39 We expect the first arg to be a pointer to the jmp_buf structure
40 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
41 at. The pc is copied into PC. This routine returns 1 on
42 success. */
2aa830e4 43
19ed69dd
KB		 44#define MIPS_LINUX_JB_ELEMENT_SIZE 4
45#define MIPS_LINUX_JB_PC 0
46
47static int
2aa830e4
DJ		 48mips_linux_get_longjmp_target (CORE_ADDR *pc)
49{
50 CORE_ADDR jb_addr;
51 char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
52
613e114f 53 jb_addr = read_register (MIPS_A0_REGNUM);
2aa830e4 54
bf072999
DJ		 55 if (target_read_memory (jb_addr
56 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
57 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
2aa830e4
DJ		 58 return 0;
59
7c0b4a20 60 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
2aa830e4
DJ		 61
62 return 1;
63}
64
4246e332 65/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 66 for regcache_raw_supply(). This is needed when mips_isa_regsize()
67 is 8. */
96f026fc
KB		 68
69static void
70supply_32bit_reg (int regnum, const void *addr)
71{
d37eb719 72 gdb_byte buf[MAX_REGISTER_SIZE];
3acba339 73 store_signed_integer (buf, register_size (current_gdbarch, regnum),
96f026fc 74 extract_signed_integer (addr, 4));
23a6d369 75 regcache_raw_supply (current_regcache, regnum, buf);
96f026fc
KB		 76}
77
2aa830e4
DJ		 78/* Unpack an elf_gregset_t into GDB's register cache. */
79
d37eb719
DJ		 80void
81mips_supply_gregset (mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 82{
83 int regi;
d37eb719 84 mips_elf_greg_t *regp = *gregsetp;
d9d9c31f 85 char zerobuf[MAX_REGISTER_SIZE];
bf072999 86
d9d9c31f 87 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 88
89 for (regi = EF_REG0; regi <= EF_REG31; regi++)
96f026fc 90 supply_32bit_reg ((regi - EF_REG0), (char *)(regp + regi));
2aa830e4 91
56cea623
AC		 92 supply_32bit_reg (mips_regnum (current_gdbarch)->lo,
93 (char *)(regp + EF_LO));
94 supply_32bit_reg (mips_regnum (current_gdbarch)->hi,
95 (char *)(regp + EF_HI));
96
97 supply_32bit_reg (mips_regnum (current_gdbarch)->pc,
98 (char *)(regp + EF_CP0_EPC));
99 supply_32bit_reg (mips_regnum (current_gdbarch)->badvaddr,
100 (char *)(regp + EF_CP0_BADVADDR));
24e05951 101 supply_32bit_reg (MIPS_PS_REGNUM, (char *)(regp + EF_CP0_STATUS));
56cea623
AC		 102 supply_32bit_reg (mips_regnum (current_gdbarch)->cause,
103 (char *)(regp + EF_CP0_CAUSE));
2aa830e4
DJ		 104
105 /* Fill inaccessible registers with zero. */
613e114f 106 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 107 for (regi = MIPS_FIRST_EMBED_REGNUM;
108 regi < MIPS_LAST_EMBED_REGNUM;
109 regi++)
23a6d369 110 regcache_raw_supply (current_regcache, regi, zerobuf);
2aa830e4
DJ		 111}
112
113/* Pack our registers (or one register) into an elf_gregset_t. */
114
d37eb719
DJ		 115void
116mips_fill_gregset (mips_elf_gregset_t *gregsetp, int regno)
2aa830e4
DJ		 117{
118 int regaddr, regi;
d37eb719 119 mips_elf_greg_t *regp = *gregsetp;
96f026fc 120 void *dst;
2aa830e4
DJ		 121
122 if (regno == -1)
123 {
d37eb719 124 memset (regp, 0, sizeof (mips_elf_gregset_t));
2aa830e4 125 for (regi = 0; regi < 32; regi++)
9f62d0e2
DJ		 126 mips_fill_gregset (gregsetp, regi);
127 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
128 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
129 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
130 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->badvaddr);
131 mips_fill_gregset (gregsetp, MIPS_PS_REGNUM);
132 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->cause);
2aa830e4
DJ		 133
134 return;
135 }
136
137 if (regno < 32)
138 {
2aa830e4 139 dst = regp + regno + EF_REG0;
822c9732 140 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 141 return;
142 }
143
56cea623
AC		 144 if (regno == mips_regnum (current_gdbarch)->lo)
145 regaddr = EF_LO;
146 else if (regno == mips_regnum (current_gdbarch)->hi)
147 regaddr = EF_HI;
148 else if (regno == mips_regnum (current_gdbarch)->pc)
149 regaddr = EF_CP0_EPC;
150 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
151 regaddr = EF_CP0_BADVADDR;
24e05951 152 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 153 regaddr = EF_CP0_STATUS;
154 else if (regno == mips_regnum (current_gdbarch)->cause)
155 regaddr = EF_CP0_CAUSE;
156 else
157 regaddr = -1;
2aa830e4
DJ		 158
159 if (regaddr != -1)
160 {
2aa830e4 161 dst = regp + regaddr;
822c9732 162 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 163 }
164}
165
166/* Likewise, unpack an elf_fpregset_t. */
167
d37eb719
DJ		 168void
169mips_supply_fpregset (mips_elf_fpregset_t *fpregsetp)
2aa830e4 170{
52f0bd74 171 int regi;
d9d9c31f 172 char zerobuf[MAX_REGISTER_SIZE];
bf072999 173
d9d9c31f 174 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 175
176 for (regi = 0; regi < 32; regi++)
23a6d369
AC		 177 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
178 (char *)(*fpregsetp + regi));
2aa830e4 179
23a6d369
AC		 180 regcache_raw_supply (current_regcache,
181 mips_regnum (current_gdbarch)->fp_control_status,
182 (char *)(*fpregsetp + 32));
2aa830e4 183
295093a4 184 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
23a6d369
AC		 185 regcache_raw_supply (current_regcache,
186 mips_regnum (current_gdbarch)->fp_implementation_revision,
187 zerobuf);
2aa830e4
DJ		 188}
189
190/* Likewise, pack one or all floating point registers into an
191 elf_fpregset_t. */
192
d37eb719
DJ		 193void
194mips_fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4
DJ		 195{
196 char *from, *to;
197
198 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
199 {
2aa830e4 200 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
2fdf551c 201 regcache_raw_collect (current_regcache, regno, to);
2aa830e4 202 }
56cea623 203 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 204 {
2aa830e4 205 to = (char *) (*fpregsetp + 32);
2fdf551c 206 regcache_raw_collect (current_regcache, regno, to);
2aa830e4
DJ		 207 }
208 else if (regno == -1)
209 {
210 int regi;
211
212 for (regi = 0; regi < 32; regi++)
9f62d0e2
DJ		 213 mips_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
214 mips_fill_fpregset (fpregsetp,
215 mips_regnum (current_gdbarch)->fp_control_status);
2aa830e4
DJ		 216 }
217}
218
219/* Map gdb internal register number to ptrace ``address''.
220 These ``addresses'' are normally defined in <asm/ptrace.h>. */
221
96f026fc
KB		 222static CORE_ADDR
223mips_linux_register_addr (int regno, CORE_ADDR blockend)
2aa830e4
DJ		 224{
225 int regaddr;
226
227 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 228 error (_("Bogon register number %d."), regno);
2aa830e4
DJ		 229
230 if (regno < 32)
231 regaddr = regno;
56cea623
AC		 232 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
233 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
234 regaddr = FPR_BASE + (regno - mips_regnum (current_gdbarch)->fp0);
235 else if (regno == mips_regnum (current_gdbarch)->pc)
2aa830e4 236 regaddr = PC;
56cea623 237 else if (regno == mips_regnum (current_gdbarch)->cause)
2aa830e4 238 regaddr = CAUSE;
56cea623 239 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
2aa830e4 240 regaddr = BADVADDR;
56cea623 241 else if (regno == mips_regnum (current_gdbarch)->lo)
2aa830e4 242 regaddr = MMLO;
56cea623 243 else if (regno == mips_regnum (current_gdbarch)->hi)
2aa830e4 244 regaddr = MMHI;
56cea623 245 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 246 regaddr = FPC_CSR;
56cea623 247 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
2aa830e4
DJ		 248 regaddr = FPC_EIR;
249 else
8a3fe4f8 250 error (_("Unknowable register number %d."), regno);
2aa830e4
DJ		 251
252 return regaddr;
253}
254
96f026fc
KB		 255/* Support for 64-bit ABIs. */
256
96f026fc 257/* Figure out where the longjmp will land.
295093a4
MS		 258 We expect the first arg to be a pointer to the jmp_buf structure
259 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
260 at. The pc is copied into PC. This routine returns 1 on
261 success. */
96f026fc
KB		 262
263/* Details about jmp_buf. */
264
265#define MIPS64_LINUX_JB_PC 0
266
267static int
268mips64_linux_get_longjmp_target (CORE_ADDR *pc)
269{
270 CORE_ADDR jb_addr;
271 void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT);
272 int element_size = TARGET_PTR_BIT == 32 ? 4 : 8;
273
613e114f 274 jb_addr = read_register (MIPS_A0_REGNUM);
96f026fc
KB		 275
276 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
277 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
278 return 0;
279
7c0b4a20 280 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
96f026fc
KB		 281
282 return 1;
283}
284
d37eb719
DJ		 285/* Register set support functions. These operate on standard 64-bit
286 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
287 target will still use the 64-bit format for PTRACE_GETREGS. */
288
289/* Supply a 64-bit register. */
96f026fc 290
d37eb719
DJ		 291void
292supply_64bit_reg (int regnum, const gdb_byte *buf)
293{
294 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
295 && register_size (current_gdbarch, regnum) == 4)
296 regcache_raw_supply (current_regcache, regnum, buf + 4);
297 else
298 regcache_raw_supply (current_regcache, regnum, buf);
299}
300
301/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
302
303void
96f026fc
KB		 304mips64_supply_gregset (mips64_elf_gregset_t *gregsetp)
305{
306 int regi;
307 mips64_elf_greg_t *regp = *gregsetp;
d37eb719 308 gdb_byte zerobuf[MAX_REGISTER_SIZE];
96f026fc 309
d9d9c31f 310 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc
KB		 311
312 for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++)
d37eb719
DJ		 313 supply_64bit_reg (regi - MIPS64_EF_REG0, (gdb_byte *)(regp + regi));
314
315 supply_64bit_reg (mips_regnum (current_gdbarch)->lo,
316 (gdb_byte *) (regp + MIPS64_EF_LO));
317 supply_64bit_reg (mips_regnum (current_gdbarch)->hi,
318 (gdb_byte *) (regp + MIPS64_EF_HI));
319
320 supply_64bit_reg (mips_regnum (current_gdbarch)->pc,
321 (gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
322 supply_64bit_reg (mips_regnum (current_gdbarch)->badvaddr,
323 (gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
324 supply_64bit_reg (MIPS_PS_REGNUM,
325 (gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
326 supply_64bit_reg (mips_regnum (current_gdbarch)->cause,
327 (gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc
KB		 328
329 /* Fill inaccessible registers with zero. */
613e114f 330 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 331 for (regi = MIPS_FIRST_EMBED_REGNUM;
332 regi < MIPS_LAST_EMBED_REGNUM;
333 regi++)
23a6d369 334 regcache_raw_supply (current_regcache, regi, zerobuf);
96f026fc
KB		 335}
336
d37eb719 337/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 338
d37eb719 339void
96f026fc
KB		 340mips64_fill_gregset (mips64_elf_gregset_t *gregsetp, int regno)
341{
342 int regaddr, regi;
343 mips64_elf_greg_t *regp = *gregsetp;
344 void *src, *dst;
345
346 if (regno == -1)
347 {
348 memset (regp, 0, sizeof (mips64_elf_gregset_t));
349 for (regi = 0; regi < 32; regi++)
350 mips64_fill_gregset (gregsetp, regi);
56cea623
AC		 351 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
352 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
353 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
295093a4
MS		 354 mips64_fill_gregset (gregsetp,
355 mips_regnum (current_gdbarch)->badvaddr);
24e05951 356 mips64_fill_gregset (gregsetp, MIPS_PS_REGNUM);
295093a4
MS		 357 mips64_fill_gregset (gregsetp,
358 mips_regnum (current_gdbarch)->cause);
96f026fc
KB		 359
360 return;
361 }
362
363 if (regno < 32)
d37eb719
DJ		 364 regaddr = regno + MIPS64_EF_REG0;
365 else if (regno == mips_regnum (current_gdbarch)->lo)
56cea623
AC		 366 regaddr = MIPS64_EF_LO;
367 else if (regno == mips_regnum (current_gdbarch)->hi)
368 regaddr = MIPS64_EF_HI;
369 else if (regno == mips_regnum (current_gdbarch)->pc)
370 regaddr = MIPS64_EF_CP0_EPC;
371 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
372 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 373 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 374 regaddr = MIPS64_EF_CP0_STATUS;
375 else if (regno == mips_regnum (current_gdbarch)->cause)
376 regaddr = MIPS64_EF_CP0_CAUSE;
377 else
378 regaddr = -1;
96f026fc
KB		 379
380 if (regaddr != -1)
381 {
d37eb719
DJ		 382 gdb_byte buf[MAX_REGISTER_SIZE];
383 LONGEST val;
384
385 regcache_raw_collect (current_regcache, regno, buf);
386 val = extract_signed_integer (buf,
387 register_size (current_gdbarch, regno));
96f026fc 388 dst = regp + regaddr;
d37eb719 389 store_signed_integer (dst, 8, val);
96f026fc
KB		 390 }
391}
392
393/* Likewise, unpack an elf_fpregset_t. */
394
d37eb719 395void
96f026fc
KB		 396mips64_supply_fpregset (mips64_elf_fpregset_t *fpregsetp)
397{
52f0bd74 398 int regi;
96f026fc 399
d37eb719
DJ		 400 /* See mips_linux_o32_sigframe_init for a description of the
401 peculiar FP register layout. */
402 if (register_size (current_gdbarch, FP0_REGNUM) == 4)
403 for (regi = 0; regi < 32; regi++)
404 {
405 gdb_byte *reg_ptr = (gdb_byte *) (*fpregsetp + (regi & ~1));
406 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1))
407 reg_ptr += 4;
408 regcache_raw_supply (current_regcache, FP0_REGNUM + regi, reg_ptr);
409 }
410 else
411 for (regi = 0; regi < 32; regi++)
412 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
413 (char *)(*fpregsetp + regi));
414
415 supply_32bit_reg (mips_regnum (current_gdbarch)->fp_control_status,
416 (gdb_byte *)(*fpregsetp + 32));
417
418 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
419 include it - but the result of PTRACE_GETFPREGS does. The best we
420 can do is to assume that its value is present. */
421 supply_32bit_reg (mips_regnum (current_gdbarch)->fp_implementation_revision,
422 (gdb_byte *)(*fpregsetp + 32) + 4);
96f026fc
KB		 423}
424
425/* Likewise, pack one or all floating point registers into an
426 elf_fpregset_t. */
427
d37eb719 428void
96f026fc
KB		 429mips64_fill_fpregset (mips64_elf_fpregset_t *fpregsetp, int regno)
430{
d37eb719 431 gdb_byte *to;
96f026fc
KB		 432
433 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
434 {
d37eb719
DJ		 435 /* See mips_linux_o32_sigframe_init for a description of the
436 peculiar FP register layout. */
437 if (register_size (current_gdbarch, regno) == 4)
438 {
439 int regi = regno - FP0_REGNUM;
440
441 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
442 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1))
443 to += 4;
444 regcache_raw_collect (current_regcache, regno, to);
445 }
446 else
447 {
448 to = (gdb_byte *) (*fpregsetp + regno - FP0_REGNUM);
449 regcache_raw_collect (current_regcache, regno, to);
450 }
96f026fc 451 }
56cea623 452 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 453 {
d37eb719
DJ		 454 gdb_byte buf[MAX_REGISTER_SIZE];
455 LONGEST val;
456
457 regcache_raw_collect (current_regcache, regno, buf);
458 val = extract_signed_integer (buf,
459 register_size (current_gdbarch, regno));
460 to = (gdb_byte *) (*fpregsetp + 32);
461 store_signed_integer (to, 4, val);
462 }
463 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
464 {
465 gdb_byte buf[MAX_REGISTER_SIZE];
466 LONGEST val;
467
468 regcache_raw_collect (current_regcache, regno, buf);
469 val = extract_signed_integer (buf,
470 register_size (current_gdbarch, regno));
471 to = (gdb_byte *) (*fpregsetp + 32) + 4;
472 store_signed_integer (to, 4, val);
96f026fc
KB		 473 }
474 else if (regno == -1)
475 {
476 int regi;
477
478 for (regi = 0; regi < 32; regi++)
479 mips64_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
d37eb719
DJ		 480 mips64_fill_fpregset (fpregsetp,
481 mips_regnum (current_gdbarch)->fp_control_status);
482 mips64_fill_fpregset (fpregsetp, (mips_regnum (current_gdbarch)
483 ->fp_implementation_revision));
96f026fc
KB		 484 }
485}
486
487
488/* Map gdb internal register number to ptrace ``address''.
489 These ``addresses'' are normally defined in <asm/ptrace.h>. */
490
491static CORE_ADDR
492mips64_linux_register_addr (int regno, CORE_ADDR blockend)
493{
494 int regaddr;
495
496 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 497 error (_("Bogon register number %d."), regno);
96f026fc
KB		 498
499 if (regno < 32)
500 regaddr = regno;
56cea623
AC		 501 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
502 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
96f026fc 503 regaddr = MIPS64_FPR_BASE + (regno - FP0_REGNUM);
56cea623 504 else if (regno == mips_regnum (current_gdbarch)->pc)
96f026fc 505 regaddr = MIPS64_PC;
56cea623 506 else if (regno == mips_regnum (current_gdbarch)->cause)
96f026fc 507 regaddr = MIPS64_CAUSE;
56cea623 508 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
96f026fc 509 regaddr = MIPS64_BADVADDR;
56cea623 510 else if (regno == mips_regnum (current_gdbarch)->lo)
96f026fc 511 regaddr = MIPS64_MMLO;
56cea623 512 else if (regno == mips_regnum (current_gdbarch)->hi)
96f026fc 513 regaddr = MIPS64_MMHI;
56cea623 514 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 515 regaddr = MIPS64_FPC_CSR;
56cea623 516 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
96f026fc
KB		 517 regaddr = MIPS64_FPC_EIR;
518 else
8a3fe4f8 519 error (_("Unknowable register number %d."), regno);
96f026fc
KB		 520
521 return regaddr;
522}
523
2aa830e4
DJ		 524/* Use a local version of this function to get the correct types for
525 regsets, until multi-arch core support is ready. */
526
527static void
528fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
529 int which, CORE_ADDR reg_addr)
530{
d37eb719
DJ		 531 mips_elf_gregset_t gregset;
532 mips_elf_fpregset_t fpregset;
96f026fc
KB		 533 mips64_elf_gregset_t gregset64;
534 mips64_elf_fpregset_t fpregset64;
2aa830e4
DJ		 535
536 if (which == 0)
537 {
96f026fc 538 if (core_reg_size == sizeof (gregset))
2aa830e4 539 {
96f026fc 540 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
9f62d0e2 541 mips_supply_gregset (&gregset);
96f026fc
KB		 542 }
543 else if (core_reg_size == sizeof (gregset64))
544 {
545 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
546 mips64_supply_gregset (&gregset64);
2aa830e4
DJ		 547 }
548 else
549 {
8a3fe4f8 550 warning (_("wrong size gregset struct in core file"));
2aa830e4
DJ		 551 }
552 }
553 else if (which == 2)
554 {
96f026fc 555 if (core_reg_size == sizeof (fpregset))
2aa830e4 556 {
96f026fc 557 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
9f62d0e2 558 mips_supply_fpregset (&fpregset);
96f026fc
KB		 559 }
560 else if (core_reg_size == sizeof (fpregset64))
561 {
295093a4
MS		 562 memcpy ((char *) &fpregset64, core_reg_sect,
563 sizeof (fpregset64));
96f026fc 564 mips64_supply_fpregset (&fpregset64);
2aa830e4
DJ		 565 }
566 else
567 {
8a3fe4f8 568 warning (_("wrong size fpregset struct in core file"));
2aa830e4
DJ		 569 }
570 }
571}
572
573/* Register that we are able to handle ELF file formats using standard
574 procfs "regset" structures. */
575
576static struct core_fns regset_core_fns =
577{
578 bfd_target_elf_flavour, /* core_flavour */
579 default_check_format, /* check_format */
580 default_core_sniffer, /* core_sniffer */
581 fetch_core_registers, /* core_read_registers */
582 NULL /* next */
583};
584
295093a4
MS		 585/* Handle for obtaining pointer to the current register_addr()
586 function for a given architecture. */
96f026fc
KB		 587static struct gdbarch_data *register_addr_data;
588
589CORE_ADDR
590register_addr (int regno, CORE_ADDR blockend)
591{
592 CORE_ADDR (*register_addr_ptr) (int, CORE_ADDR) =
593 gdbarch_data (current_gdbarch, register_addr_data);
594
595 gdb_assert (register_addr_ptr != 0);
596
597 return register_addr_ptr (regno, blockend);
598}
599
600static void
601set_mips_linux_register_addr (struct gdbarch *gdbarch,
295093a4
MS		 602 CORE_ADDR (*register_addr_ptr) (int,
603 CORE_ADDR))
96f026fc 604{
295093a4
MS		 605 deprecated_set_gdbarch_data (gdbarch, register_addr_data,
606 register_addr_ptr);
96f026fc
KB		 607}
608
609static void *
610init_register_addr_data (struct gdbarch *gdbarch)
611{
612 return 0;
613}
614
295093a4
MS		 615/* Check the code at PC for a dynamic linker lazy resolution stub.
616 Because they aren't in the .plt section, we pattern-match on the
617 code generated by GNU ld. They look like this:
6de918a6
DJ		 618
619 lw t9,0x8010(gp)
620 addu t7,ra
621 jalr t9,ra
622 addiu t8,zero,INDEX
623
295093a4
MS		 624 (with the appropriate doubleword instructions for N64). Also
625 return the dynamic symbol index used in the last instruction. */
6de918a6
DJ		 626
627static int
628mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
629{
630 unsigned char buf[28], *p;
631 ULONGEST insn, insn1;
632 int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64);
633
634 read_memory (pc - 12, buf, 28);
635
636 if (n64)
637 {
638 /* ld t9,0x8010(gp) */
639 insn1 = 0xdf998010;
640 }
641 else
642 {
643 /* lw t9,0x8010(gp) */
644 insn1 = 0x8f998010;
645 }
646
647 p = buf + 12;
648 while (p >= buf)
649 {
650 insn = extract_unsigned_integer (p, 4);
651 if (insn == insn1)
652 break;
653 p -= 4;
654 }
655 if (p < buf)
656 return 0;
657
658 insn = extract_unsigned_integer (p + 4, 4);
659 if (n64)
660 {
661 /* daddu t7,ra */
662 if (insn != 0x03e0782d)
663 return 0;
664 }
665 else
666 {
667 /* addu t7,ra */
668 if (insn != 0x03e07821)
669 return 0;
670 }
295093a4 671
6de918a6
DJ		 672 insn = extract_unsigned_integer (p + 8, 4);
673 /* jalr t9,ra */
674 if (insn != 0x0320f809)
675 return 0;
676
677 insn = extract_unsigned_integer (p + 12, 4);
678 if (n64)
679 {
680 /* daddiu t8,zero,0 */
681 if ((insn & 0xffff0000) != 0x64180000)
682 return 0;
683 }
684 else
685 {
686 /* addiu t8,zero,0 */
687 if ((insn & 0xffff0000) != 0x24180000)
688 return 0;
689 }
690
691 return (insn & 0xffff);
692}
693
295093a4
MS		 694/* Return non-zero iff PC belongs to the dynamic linker resolution
695 code or to a stub. */
6de918a6
DJ		 696
697int
698mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
699{
295093a4
MS		 700 /* Check whether PC is in the dynamic linker. This also checks
701 whether it is in the .plt section, which MIPS does not use. */
6de918a6
DJ		 702 if (in_solib_dynsym_resolve_code (pc))
703 return 1;
704
295093a4
MS		 705 /* Pattern match for the stub. It would be nice if there were a
706 more efficient way to avoid this check. */
6de918a6
DJ		 707 if (mips_linux_in_dynsym_stub (pc, NULL))
708 return 1;
709
710 return 0;
711}
712
713/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
714 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
715 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba
AC		 716 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
717 "__dl_runtime_resolve" directly. An unresolved PLT entry will
718 point to _dl_runtime_resolve, which will first call
719 __dl_runtime_resolve, and then pass control to the resolved
720 function. */
6de918a6
DJ		 721
722static CORE_ADDR
723mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
724{
725 struct minimal_symbol *resolver;
726
727 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
728
729 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
295093a4 730 return frame_pc_unwind (get_current_frame ());
6de918a6
DJ		 731
732 return 0;
295093a4 733}
6de918a6 734
5792a79b
DJ		 735/* Signal trampoline support. There are four supported layouts for a
736 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
737 n64 rt_sigframe. We handle them all independently; not the most
738 efficient way, but simplest. First, declare all the unwinders. */
739
740static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
741 struct frame_info *next_frame,
742 struct trad_frame_cache *this_cache,
743 CORE_ADDR func);
744
745static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
746 struct frame_info *next_frame,
747 struct trad_frame_cache *this_cache,
748 CORE_ADDR func);
749
750#define MIPS_NR_LINUX 4000
751#define MIPS_NR_N64_LINUX 5000
752#define MIPS_NR_N32_LINUX 6000
753
754#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
755#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
756#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
757#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
758
759#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
760#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
761#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
762#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
763#define MIPS_INST_SYSCALL 0x0000000c
764
2cd8546d
AC		 765static const struct tramp_frame mips_linux_o32_sigframe = {
766 SIGTRAMP_FRAME,
5792a79b 767 4,
2cd8546d
AC		 768 {
769 { MIPS_INST_LI_V0_SIGRETURN, -1 },
770 { MIPS_INST_SYSCALL, -1 },
771 { TRAMP_SENTINEL_INSN, -1 }
772 },
5792a79b
DJ		 773 mips_linux_o32_sigframe_init
774};
775
2cd8546d
AC		 776static const struct tramp_frame mips_linux_o32_rt_sigframe = {
777 SIGTRAMP_FRAME,
5792a79b 778 4,
2cd8546d
AC		 779 {
780 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
781 { MIPS_INST_SYSCALL, -1 },
782 { TRAMP_SENTINEL_INSN, -1 } },
5792a79b
DJ		 783 mips_linux_o32_sigframe_init
784};
785
2cd8546d
AC		 786static const struct tramp_frame mips_linux_n32_rt_sigframe = {
787 SIGTRAMP_FRAME,
5792a79b 788 4,
2cd8546d
AC		 789 {
790 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
791 { MIPS_INST_SYSCALL, -1 },
792 { TRAMP_SENTINEL_INSN, -1 }
793 },
5792a79b
DJ		 794 mips_linux_n32n64_sigframe_init
795};
796
2cd8546d
AC		 797static const struct tramp_frame mips_linux_n64_rt_sigframe = {
798 SIGTRAMP_FRAME,
5792a79b 799 4,
295093a4
MS		 800 { MIPS_INST_LI_V0_N64_RT_SIGRETURN,
801 MIPS_INST_SYSCALL,
802 TRAMP_SENTINEL_INSN },
5792a79b
DJ		 803 mips_linux_n32n64_sigframe_init
804};
805
806/* *INDENT-OFF* */
807/* The unwinder for o32 signal frames. The legacy structures look
808 like this:
809
810 struct sigframe {
811 u32 sf_ass[4]; [argument save space for o32]
812 u32 sf_code[2]; [signal trampoline]
813 struct sigcontext sf_sc;
814 sigset_t sf_mask;
815 };
816
817 struct sigcontext {
818 unsigned int sc_regmask; [Unused]
819 unsigned int sc_status;
820 unsigned long long sc_pc;
821 unsigned long long sc_regs[32];
822 unsigned long long sc_fpregs[32];
823 unsigned int sc_ownedfp;
824 unsigned int sc_fpc_csr;
825 unsigned int sc_fpc_eir; [Unused]
826 unsigned int sc_used_math;
827 unsigned int sc_ssflags; [Unused]
828 [Alignment hole of four bytes]
829 unsigned long long sc_mdhi;
830 unsigned long long sc_mdlo;
831
832 unsigned int sc_cause; [Unused]
833 unsigned int sc_badvaddr; [Unused]
834
835 unsigned long sc_sigset[4]; [kernel's sigset_t]
836 };
837
838 The RT signal frames look like this:
839
840 struct rt_sigframe {
841 u32 rs_ass[4]; [argument save space for o32]
842 u32 rs_code[2] [signal trampoline]
843 struct siginfo rs_info;
844 struct ucontext rs_uc;
845 };
846
847 struct ucontext {
848 unsigned long uc_flags;
849 struct ucontext *uc_link;
850 stack_t uc_stack;
851 [Alignment hole of four bytes]
852 struct sigcontext uc_mcontext;
853 sigset_t uc_sigmask;
854 }; */
855/* *INDENT-ON* */
856
857#define SIGFRAME_CODE_OFFSET (4 * 4)
858#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
859
860#define RTSIGFRAME_SIGINFO_SIZE 128
861#define STACK_T_SIZE (3 * 4)
862#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
863#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
864 + RTSIGFRAME_SIGINFO_SIZE \
865 + UCONTEXT_SIGCONTEXT_OFFSET)
866
867#define SIGCONTEXT_PC (1 * 8)
868#define SIGCONTEXT_REGS (2 * 8)
869#define SIGCONTEXT_FPREGS (34 * 8)
870#define SIGCONTEXT_FPCSR (66 * 8 + 4)
871#define SIGCONTEXT_HI (69 * 8)
872#define SIGCONTEXT_LO (70 * 8)
873#define SIGCONTEXT_CAUSE (71 * 8 + 0)
874#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
875
876#define SIGCONTEXT_REG_SIZE 8
877
878static void
879mips_linux_o32_sigframe_init (const struct tramp_frame *self,
880 struct frame_info *next_frame,
881 struct trad_frame_cache *this_cache,
882 CORE_ADDR func)
883{
884 int ireg, reg_position;
885 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
886 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
37c4d197 887 CORE_ADDR regs_base;
5792a79b
DJ		 888
889 if (self == &mips_linux_o32_sigframe)
890 sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET;
891 else
892 sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 893
894 /* I'm not proud of this hack. Eventually we will have the
895 infrastructure to indicate the size of saved registers on a
896 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 897 bytes but we only want four. Use regs_base to access any
898 64-bit fields. */
5792a79b 899 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
37c4d197
DJ		 900 regs_base = sigcontext_base + 4;
901 else
902 regs_base = sigcontext_base;
5792a79b
DJ		 903
904#if 0
905 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
37c4d197 906 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 907#endif
908
909 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 910 trad_frame_set_reg_addr (this_cache,
911 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
37c4d197 912 regs_base + SIGCONTEXT_REGS
5792a79b
DJ		 913 + ireg * SIGCONTEXT_REG_SIZE);
914
37c4d197
DJ		 915 /* The way that floating point registers are saved, unfortunately,
916 depends on the architecture the kernel is built for. For the r3000 and
917 tx39, four bytes of each register are at the beginning of each of the
918 32 eight byte slots. For everything else, the registers are saved
919 using double precision; only the even-numbered slots are initialized,
920 and the high bits are the odd-numbered register. Assume the latter
921 layout, since we can't tell, and it's much more common. Which bits are
922 the "high" bits depends on endianness. */
5792a79b 923 for (ireg = 0; ireg < 32; ireg++)
37c4d197
DJ		 924 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1))
925 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
926 sigcontext_base + SIGCONTEXT_FPREGS + 4
927 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
928 else
929 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
930 sigcontext_base + SIGCONTEXT_FPREGS
931 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
5792a79b
DJ		 932
933 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
37c4d197 934 regs_base + SIGCONTEXT_PC);
5792a79b 935
295093a4
MS		 936 trad_frame_set_reg_addr (this_cache,
937 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 938 sigcontext_base + SIGCONTEXT_FPCSR);
939 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
37c4d197 940 regs_base + SIGCONTEXT_HI);
5792a79b 941 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
37c4d197 942 regs_base + SIGCONTEXT_LO);
5792a79b
DJ		 943 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
944 sigcontext_base + SIGCONTEXT_CAUSE);
945 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
946 sigcontext_base + SIGCONTEXT_BADVADDR);
947
948 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
949 trad_frame_set_id (this_cache,
295093a4
MS		 950 frame_id_build (func - SIGFRAME_CODE_OFFSET,
951 func));
5792a79b
DJ		 952}
953
954/* *INDENT-OFF* */
955/* For N32/N64 things look different. There is no non-rt signal frame.
956
957 struct rt_sigframe_n32 {
958 u32 rs_ass[4]; [ argument save space for o32 ]
959 u32 rs_code[2]; [ signal trampoline ]
960 struct siginfo rs_info;
961 struct ucontextn32 rs_uc;
962 };
963
964 struct ucontextn32 {
965 u32 uc_flags;
966 s32 uc_link;
967 stack32_t uc_stack;
968 struct sigcontext uc_mcontext;
969 sigset_t uc_sigmask; [ mask last for extensibility ]
970 };
295093a4 971
5792a79b
DJ		 972 struct rt_sigframe_n32 {
973 u32 rs_ass[4]; [ argument save space for o32 ]
974 u32 rs_code[2]; [ signal trampoline ]
975 struct siginfo rs_info;
976 struct ucontext rs_uc;
977 };
978
979 struct ucontext {
980 unsigned long uc_flags;
981 struct ucontext *uc_link;
982 stack_t uc_stack;
983 struct sigcontext uc_mcontext;
984 sigset_t uc_sigmask; [ mask last for extensibility ]
985 };
986
987 And the sigcontext is different (this is for both n32 and n64):
988
989 struct sigcontext {
990 unsigned long long sc_regs[32];
991 unsigned long long sc_fpregs[32];
992 unsigned long long sc_mdhi;
993 unsigned long long sc_mdlo;
994 unsigned long long sc_pc;
995 unsigned int sc_status;
996 unsigned int sc_fpc_csr;
997 unsigned int sc_fpc_eir;
998 unsigned int sc_used_math;
999 unsigned int sc_cause;
1000 unsigned int sc_badvaddr;
1001 }; */
1002/* *INDENT-ON* */
1003
1004#define N32_STACK_T_SIZE STACK_T_SIZE
1005#define N64_STACK_T_SIZE (2 * 8 + 4)
1006#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1007#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1008#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1009 + RTSIGFRAME_SIGINFO_SIZE \
1010 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1011#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1012 + RTSIGFRAME_SIGINFO_SIZE \
1013 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1014
1015#define N64_SIGCONTEXT_REGS (0 * 8)
1016#define N64_SIGCONTEXT_FPREGS (32 * 8)
1017#define N64_SIGCONTEXT_HI (64 * 8)
1018#define N64_SIGCONTEXT_LO (65 * 8)
1019#define N64_SIGCONTEXT_PC (66 * 8)
1020#define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1021#define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1022#define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1023#define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1024
1025#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1026
5792a79b
DJ		 1027static void
1028mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
1029 struct frame_info *next_frame,
1030 struct trad_frame_cache *this_cache,
1031 CORE_ADDR func)
1032{
1033 int ireg, reg_position;
1034 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
1035 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
1036
1037 if (self == &mips_linux_n32_rt_sigframe)
1038 sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET;
1039 else
1040 sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1041
5792a79b
DJ		 1042#if 0
1043 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
1044 sigcontext_base + N64_SIGCONTEXT_REGS);
1045#endif
1046
1047 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 1048 trad_frame_set_reg_addr (this_cache,
1049 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
5792a79b
DJ		 1050 sigcontext_base + N64_SIGCONTEXT_REGS
1051 + ireg * N64_SIGCONTEXT_REG_SIZE);
1052
1053 for (ireg = 0; ireg < 32; ireg++)
1054 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1055 sigcontext_base + N64_SIGCONTEXT_FPREGS
1056 + ireg * N64_SIGCONTEXT_REG_SIZE);
1057
1058 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
1059 sigcontext_base + N64_SIGCONTEXT_PC);
1060
295093a4
MS		 1061 trad_frame_set_reg_addr (this_cache,
1062 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 1063 sigcontext_base + N64_SIGCONTEXT_FPCSR);
1064 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
1065 sigcontext_base + N64_SIGCONTEXT_HI);
1066 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
1067 sigcontext_base + N64_SIGCONTEXT_LO);
1068 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
1069 sigcontext_base + N64_SIGCONTEXT_CAUSE);
1070 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
1071 sigcontext_base + N64_SIGCONTEXT_BADVADDR);
1072
1073 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1074 trad_frame_set_id (this_cache,
295093a4
MS		 1075 frame_id_build (func - SIGFRAME_CODE_OFFSET,
1076 func));
5792a79b
DJ		 1077}
1078
9f62d0e2
DJ		 1079/* Wrapper functions. These are only used by libthread_db. */
1080
1081void
d37eb719 1082supply_gregset (mips_elf_gregset_t *gregsetp)
9f62d0e2
DJ		 1083{
1084 if (mips_isa_regsize (current_gdbarch) == 4)
1085 mips_supply_gregset (gregsetp);
1086 else
1087 mips64_supply_gregset ((void *) gregsetp);
1088}
1089
1090void
d37eb719 1091fill_gregset (mips_elf_gregset_t *gregsetp, int regno)
9f62d0e2
DJ		 1092{
1093 if (mips_isa_regsize (current_gdbarch) == 4)
1094 mips_fill_gregset (gregsetp, regno);
1095 else
1096 mips64_fill_gregset ((void *) gregsetp, regno);
1097}
1098
1099/* Likewise, unpack an elf_fpregset_t. */
1100
1101void
d37eb719 1102supply_fpregset (mips_elf_fpregset_t *fpregsetp)
9f62d0e2
DJ		 1103{
1104 if (mips_isa_regsize (current_gdbarch) == 4)
1105 mips_supply_fpregset (fpregsetp);
1106 else
1107 mips64_supply_fpregset ((void *) fpregsetp);
1108}
1109
1110/* Likewise, pack one or all floating point registers into an
1111 elf_fpregset_t. */
1112
1113void
d37eb719 1114fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno)
9f62d0e2
DJ		 1115{
1116 if (mips_isa_regsize (current_gdbarch) == 4)
1117 mips_fill_fpregset (fpregsetp, regno);
1118 else
1119 mips64_fill_fpregset ((void *) fpregsetp, regno);
1120}
1121
5792a79b
DJ		 1122/* Initialize one of the GNU/Linux OS ABIs. */
1123
19ed69dd 1124static void
295093a4
MS		 1125mips_linux_init_abi (struct gdbarch_info info,
1126 struct gdbarch *gdbarch)
19ed69dd 1127{
96f026fc
KB		 1128 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1129 enum mips_abi abi = mips_abi (gdbarch);
1130
1131 switch (abi)
1132 {
1133 case MIPS_ABI_O32:
1134 set_gdbarch_get_longjmp_target (gdbarch,
1135 mips_linux_get_longjmp_target);
1136 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1137 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1138 set_mips_linux_register_addr (gdbarch, mips_linux_register_addr);
fb2be677
AC		 1139 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1140 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
96f026fc
KB		 1141 break;
1142 case MIPS_ABI_N32:
1143 set_gdbarch_get_longjmp_target (gdbarch,
1144 mips_linux_get_longjmp_target);
1145 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1146 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1147 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1148 set_gdbarch_long_double_bit (gdbarch, 128);
1149 /* These floatformats should probably be renamed. MIPS uses
1150 the same 128-bit IEEE floating point format that IA-64 uses,
1151 except that the quiet/signalling NaN bit is reversed (GDB
1152 does not distinguish between quiet and signalling NaNs). */
1153 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1154 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1155 else
1156 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1157 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
96f026fc
KB		 1158 break;
1159 case MIPS_ABI_N64:
1160 set_gdbarch_get_longjmp_target (gdbarch,
1161 mips64_linux_get_longjmp_target);
1162 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1163 (gdbarch, svr4_lp64_fetch_link_map_offsets);
96f026fc 1164 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1165 set_gdbarch_long_double_bit (gdbarch, 128);
1166 /* These floatformats should probably be renamed. MIPS uses
1167 the same 128-bit IEEE floating point format that IA-64 uses,
1168 except that the quiet/signalling NaN bit is reversed (GDB
1169 does not distinguish between quiet and signalling NaNs). */
1170 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1171 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1172 else
1173 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1174 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
96f026fc
KB		 1175 break;
1176 default:
e2e0b3e5 1177 internal_error (__FILE__, __LINE__, _("can't handle ABI"));
96f026fc
KB		 1178 break;
1179 }
6de918a6
DJ		 1180
1181 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1182
0d0266c6 1183 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1184
1185 /* Enable TLS support. */
1186 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1187 svr4_fetch_objfile_link_map);
19ed69dd
KB		 1188}
1189
2aa830e4 1190void
d1bacddc 1191_initialize_mips_linux_tdep (void)
2aa830e4 1192{
96f026fc
KB		 1193 const struct bfd_arch_info *arch_info;
1194
1195 register_addr_data =
030f20e1 1196 gdbarch_data_register_post_init (init_register_addr_data);
96f026fc
KB		 1197
1198 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1199 arch_info != NULL;
1200 arch_info = arch_info->next)
1201 {
295093a4
MS		 1202 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1203 GDB_OSABI_LINUX,
96f026fc
KB		 1204 mips_linux_init_abi);
1205 }
1206
00e32a35 1207 deprecated_add_core_fns (&regset_core_fns);
2aa830e4 1208}
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