[binutils.git] / opcodes / ip2k-desc.h

/* CPU data header for ip2k.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996-2015 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

   This file is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License along
   with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.

*/

#ifndef IP2K_CPU_H
#define IP2K_CPU_H

#define CGEN_ARCH ip2k

/* Given symbol S, return ip2k_cgen_<S>.  */
#define CGEN_SYM(s) ip2k##_cgen_##s


/* Selected cpu families.  */
#define HAVE_CPU_IP2KBF

#define CGEN_INSN_LSB0_P 1

/* Minimum size of any insn (in bytes).  */
#define CGEN_MIN_INSN_SIZE 2

/* Maximum size of any insn (in bytes).  */
#define CGEN_MAX_INSN_SIZE 2

#define CGEN_INT_INSN_P 1

/* Maximum number of syntax elements in an instruction.  */
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 12

/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
   we can't hash on everything up to the space.  */
#define CGEN_MNEMONIC_OPERANDS

/* Maximum number of fields in an instruction.  */
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 3

/* Enums.  */

/* Enum declaration for op6 enums.  */
typedef enum insn_op6 {
  OP6_OTHER1, OP6_OTHER2, OP6_SUB, OP6_DEC
 , OP6_OR, OP6_AND, OP6_XOR, OP6_ADD
 , OP6_TEST, OP6_NOT, OP6_INC, OP6_DECSZ
 , OP6_RR, OP6_RL, OP6_SWAP, OP6_INCSZ
 , OP6_CSE, OP6_POP, OP6_SUBC, OP6_DECSNZ
 , OP6_MULU, OP6_MULS, OP6_INCSNZ, OP6_ADDC
} INSN_OP6;

/* Enum declaration for dir enums.  */
typedef enum insn_dir {
  DIR_TO_W, DIR_NOTTO_W
} INSN_DIR;

/* Enum declaration for op4 enums.  */
typedef enum insn_op4 {
  OP4_LITERAL = 7, OP4_CLRB = 8, OP4_SETB = 9, OP4_SNB = 10
 , OP4_SB = 11
} INSN_OP4;

/* Enum declaration for op4mid enums.  */
typedef enum insn_op4mid {
  OP4MID_LOADH_L = 0, OP4MID_LOADL_L = 1, OP4MID_MULU_L = 2, OP4MID_MULS_L = 3
 , OP4MID_PUSH_L = 4, OP4MID_CSNE_L = 6, OP4MID_CSE_L = 7, OP4MID_RETW_L = 8
 , OP4MID_CMP_L = 9, OP4MID_SUB_L = 10, OP4MID_ADD_L = 11, OP4MID_MOV_L = 12
 , OP4MID_OR_L = 13, OP4MID_AND_L = 14, OP4MID_XOR_L = 15
} INSN_OP4MID;

/* Enum declaration for op3 enums.  */
typedef enum insn_op3 {
  OP3_CALL = 6, OP3_JMP = 7
} INSN_OP3;

/* Enum declaration for .  */
typedef enum register_names {
  H_REGISTERS_ADDRSEL = 2, H_REGISTERS_ADDRX = 3, H_REGISTERS_IPH = 4, H_REGISTERS_IPL = 5
 , H_REGISTERS_SPH = 6, H_REGISTERS_SPL = 7, H_REGISTERS_PCH = 8, H_REGISTERS_PCL = 9
 , H_REGISTERS_WREG = 10, H_REGISTERS_STATUS = 11, H_REGISTERS_DPH = 12, H_REGISTERS_DPL = 13
 , H_REGISTERS_SPDREG = 14, H_REGISTERS_MULH = 15, H_REGISTERS_ADDRH = 16, H_REGISTERS_ADDRL = 17
 , H_REGISTERS_DATAH = 18, H_REGISTERS_DATAL = 19, H_REGISTERS_INTVECH = 20, H_REGISTERS_INTVECL = 21
 , H_REGISTERS_INTSPD = 22, H_REGISTERS_INTF = 23, H_REGISTERS_INTE = 24, H_REGISTERS_INTED = 25
 , H_REGISTERS_FCFG = 26, H_REGISTERS_TCTRL = 27, H_REGISTERS_XCFG = 28, H_REGISTERS_EMCFG = 29
 , H_REGISTERS_IPCH = 30, H_REGISTERS_IPCL = 31, H_REGISTERS_RAIN = 32, H_REGISTERS_RAOUT = 33
 , H_REGISTERS_RADIR = 34, H_REGISTERS_LFSRH = 35, H_REGISTERS_RBIN = 36, H_REGISTERS_RBOUT = 37
 , H_REGISTERS_RBDIR = 38, H_REGISTERS_LFSRL = 39, H_REGISTERS_RCIN = 40, H_REGISTERS_RCOUT = 41
 , H_REGISTERS_RCDIR = 42, H_REGISTERS_LFSRA = 43, H_REGISTERS_RDIN = 44, H_REGISTERS_RDOUT = 45
 , H_REGISTERS_RDDIR = 46, H_REGISTERS_REIN = 48, H_REGISTERS_REOUT = 49, H_REGISTERS_REDIR = 50
 , H_REGISTERS_RFIN = 52, H_REGISTERS_RFOUT = 53, H_REGISTERS_RFDIR = 54, H_REGISTERS_RGOUT = 57
 , H_REGISTERS_RGDIR = 58, H_REGISTERS_RTTMR = 64, H_REGISTERS_RTCFG = 65, H_REGISTERS_T0TMR = 66
 , H_REGISTERS_T0CFG = 67, H_REGISTERS_T1CNTH = 68, H_REGISTERS_T1CNTL = 69, H_REGISTERS_T1CAP1H = 70
 , H_REGISTERS_T1CAP1L = 71, H_REGISTERS_T1CAP2H = 72, H_REGISTERS_T1CMP2H = 72, H_REGISTERS_T1CAP2L = 73
 , H_REGISTERS_T1CMP2L = 73, H_REGISTERS_T1CMP1H = 74, H_REGISTERS_T1CMP1L = 75, H_REGISTERS_T1CFG1H = 76
 , H_REGISTERS_T1CFG1L = 77, H_REGISTERS_T1CFG2H = 78, H_REGISTERS_T1CFG2L = 79, H_REGISTERS_ADCH = 80
 , H_REGISTERS_ADCL = 81, H_REGISTERS_ADCCFG = 82, H_REGISTERS_ADCTMR = 83, H_REGISTERS_T2CNTH = 84
 , H_REGISTERS_T2CNTL = 85, H_REGISTERS_T2CAP1H = 86, H_REGISTERS_T2CAP1L = 87, H_REGISTERS_T2CAP2H = 88
 , H_REGISTERS_T2CMP2H = 88, H_REGISTERS_T2CAP2L = 89, H_REGISTERS_T2CMP2L = 89, H_REGISTERS_T2CMP1H = 90
 , H_REGISTERS_T2CMP1L = 91, H_REGISTERS_T2CFG1H = 92, H_REGISTERS_T2CFG1L = 93, H_REGISTERS_T2CFG2H = 94
 , H_REGISTERS_T2CFG2L = 95, H_REGISTERS_S1TMRH = 96, H_REGISTERS_S1TMRL = 97, H_REGISTERS_S1TBUFH = 98
 , H_REGISTERS_S1TBUFL = 99, H_REGISTERS_S1TCFG = 100, H_REGISTERS_S1RCNT = 101, H_REGISTERS_S1RBUFH = 102
 , H_REGISTERS_S1RBUFL = 103, H_REGISTERS_S1RCFG = 104, H_REGISTERS_S1RSYNC = 105, H_REGISTERS_S1INTF = 106
 , H_REGISTERS_S1INTE = 107, H_REGISTERS_S1MODE = 108, H_REGISTERS_S1SMASK = 109, H_REGISTERS_PSPCFG = 110
 , H_REGISTERS_CMPCFG = 111, H_REGISTERS_S2TMRH = 112, H_REGISTERS_S2TMRL = 113, H_REGISTERS_S2TBUFH = 114
 , H_REGISTERS_S2TBUFL = 115, H_REGISTERS_S2TCFG = 116, H_REGISTERS_S2RCNT = 117, H_REGISTERS_S2RBUFH = 118
 , H_REGISTERS_S2RBUFL = 119, H_REGISTERS_S2RCFG = 120, H_REGISTERS_S2RSYNC = 121, H_REGISTERS_S2INTF = 122
 , H_REGISTERS_S2INTE = 123, H_REGISTERS_S2MODE = 124, H_REGISTERS_S2SMASK = 125, H_REGISTERS_CALLH = 126
 , H_REGISTERS_CALLL = 127
} REGISTER_NAMES;

/* Attributes.  */

/* Enum declaration for machine type selection.  */
typedef enum mach_attr {
  MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX
} MACH_ATTR;

/* Enum declaration for instruction set selection.  */
typedef enum isa_attr {
  ISA_IP2K, ISA_MAX
} ISA_ATTR;

/* Number of architecture variants.  */
#define MAX_ISAS  1
#define MAX_MACHS ((int) MACH_MAX)

/* Ifield support.  */

/* Ifield attribute indices.  */

/* Enum declaration for cgen_ifld attrs.  */
typedef enum cgen_ifld_attr {
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;

/* Number of non-boolean elements in cgen_ifld_attr.  */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)

/* cgen_ifld attribute accessor macros.  */
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)

/* Enum declaration for ip2k ifield types.  */
typedef enum ifield_type {
  IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG
 , IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO, IP2K_F_OP3
 , IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6, IP2K_F_OP8
 , IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3, IP2K_F_SKIPB
 , IP2K_F_PAGE3, IP2K_F_MAX
} IFIELD_TYPE;

#define MAX_IFLD ((int) IP2K_F_MAX)

/* Hardware attribute indices.  */

/* Enum declaration for cgen_hw attrs.  */
typedef enum cgen_hw_attr {
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;

/* Number of non-boolean elements in cgen_hw_attr.  */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)

/* cgen_hw attribute accessor macros.  */
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)

/* Enum declaration for ip2k hardware types.  */
typedef enum cgen_hw_type {
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 , HW_H_IADDR, HW_H_SPR, HW_H_REGISTERS, HW_H_STACK
 , HW_H_PABITS, HW_H_ZBIT, HW_H_CBIT, HW_H_DCBIT
 , HW_H_PC, HW_MAX
} CGEN_HW_TYPE;

#define MAX_HW ((int) HW_MAX)

/* Operand attribute indices.  */

/* Enum declaration for cgen_operand attrs.  */
typedef enum cgen_operand_attr {
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;

/* Number of non-boolean elements in cgen_operand_attr.  */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)

/* cgen_operand attribute accessor macros.  */
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)

/* Enum declaration for ip2k operand types.  */
typedef enum cgen_operand_type {
  IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8
 , IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H, IP2K_OPERAND_ADDR16L
 , IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT, IP2K_OPERAND_CBIT
 , IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX
} CGEN_OPERAND_TYPE;

/* Number of operands types.  */
#define MAX_OPERANDS 13

/* Maximum number of operands referenced by any insn.  */
#define MAX_OPERAND_INSTANCES 8

/* Insn attribute indices.  */

/* Enum declaration for cgen_insn attrs.  */
typedef enum cgen_insn_attr {
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA
 , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;

/* Number of non-boolean elements in cgen_insn_attr.  */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)

/* cgen_insn attribute accessor macros.  */
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
#define CGEN_ATTR_CGEN_INSN_EXT_SKIP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_EXT_SKIP_INSN)) != 0)
#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIPA)) != 0)

/* cgen.h uses things we just defined.  */
#include "opcode/cgen.h"

extern const struct cgen_ifld ip2k_cgen_ifld_table[];

/* Attributes.  */
extern const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[];

/* Hardware decls.  */


extern const CGEN_HW_ENTRY ip2k_cgen_hw_table[];


#endif /* IP2K_CPU_H */
Commit	Line	Data
a40cbfa3 NC	1	/* CPU data header for ip2k.
	2
	3	THIS FILE IS MACHINE GENERATED WITH CGEN.
	4
b90efa5b	5	Copyright (C) 1996-2015 Free Software Foundation, Inc.
a40cbfa3 NC	6
	7	This file is part of the GNU Binutils and/or GDB, the GNU debugger.
	8
9b201bb5 NC	9	This file is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 3, or (at your option)
	12	any later version.
a40cbfa3	13
9b201bb5 NC	14	It is distributed in the hope that it will be useful, but WITHOUT
	15	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	16	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	17	License for more details.
a40cbfa3	18
9b201bb5 NC	19	You should have received a copy of the GNU General Public License along
	20	with this program; if not, write to the Free Software Foundation, Inc.,
	21	51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
a40cbfa3 NC	22
	23	*/
	24
	25	#ifndef IP2K_CPU_H
	26	#define IP2K_CPU_H
	27
	28	#define CGEN_ARCH ip2k
	29
	30	/* Given symbol S, return ip2k_cgen_<S>. */
a40cbfa3	31	#define CGEN_SYM(s) ip2k##_cgen_##s
a40cbfa3 NC	32
	33
	34	/* Selected cpu families. */
	35	#define HAVE_CPU_IP2KBF
	36
	37	#define CGEN_INSN_LSB0_P 1
	38
	39	/* Minimum size of any insn (in bytes). */
	40	#define CGEN_MIN_INSN_SIZE 2
	41
	42	/* Maximum size of any insn (in bytes). */
	43	#define CGEN_MAX_INSN_SIZE 2
	44
	45	#define CGEN_INT_INSN_P 1
	46
	47	/* Maximum number of syntax elements in an instruction. */
	48	#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 12
	49
	50	/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
	51	e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
	52	we can't hash on everything up to the space. */
	53	#define CGEN_MNEMONIC_OPERANDS
	54
	55	/* Maximum number of fields in an instruction. */
	56	#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 3
	57
	58	/* Enums. */
	59
	60	/* Enum declaration for op6 enums. */
	61	typedef enum insn_op6 {
	62	OP6_OTHER1, OP6_OTHER2, OP6_SUB, OP6_DEC
	63	, OP6_OR, OP6_AND, OP6_XOR, OP6_ADD
	64	, OP6_TEST, OP6_NOT, OP6_INC, OP6_DECSZ
	65	, OP6_RR, OP6_RL, OP6_SWAP, OP6_INCSZ
	66	, OP6_CSE, OP6_POP, OP6_SUBC, OP6_DECSNZ
	67	, OP6_MULU, OP6_MULS, OP6_INCSNZ, OP6_ADDC
	68	} INSN_OP6;
	69
	70	/* Enum declaration for dir enums. */
	71	typedef enum insn_dir {
	72	DIR_TO_W, DIR_NOTTO_W
	73	} INSN_DIR;
	74
	75	/* Enum declaration for op4 enums. */
	76	typedef enum insn_op4 {
	77	OP4_LITERAL = 7, OP4_CLRB = 8, OP4_SETB = 9, OP4_SNB = 10
	78	, OP4_SB = 11
	79	} INSN_OP4;
	80
	81	/* Enum declaration for op4mid enums. */
	82	typedef enum insn_op4mid {
	83	OP4MID_LOADH_L = 0, OP4MID_LOADL_L = 1, OP4MID_MULU_L = 2, OP4MID_MULS_L = 3
	84	, OP4MID_PUSH_L = 4, OP4MID_CSNE_L = 6, OP4MID_CSE_L = 7, OP4MID_RETW_L = 8
	85	, OP4MID_CMP_L = 9, OP4MID_SUB_L = 10, OP4MID_ADD_L = 11, OP4MID_MOV_L = 12
	86	, OP4MID_OR_L = 13, OP4MID_AND_L = 14, OP4MID_XOR_L = 15
	87	} INSN_OP4MID;
	88
	89	/* Enum declaration for op3 enums. */
	90	typedef enum insn_op3 {
	91	OP3_CALL = 6, OP3_JMP = 7
	92	} INSN_OP3;
	93
	94	/* Enum declaration for . */
	95	typedef enum register_names {
96	H_REGISTERS_ADDRSEL = 2, H_REGISTERS_ADDRX = 3, H_REGISTERS_IPH = 4, H_REGISTERS_IPL = 5
97	, H_REGISTERS_SPH = 6, H_REGISTERS_SPL = 7, H_REGISTERS_PCH = 8, H_REGISTERS_PCL = 9
98	, H_REGISTERS_WREG = 10, H_REGISTERS_STATUS = 11, H_REGISTERS_DPH = 12, H_REGISTERS_DPL = 13
99	, H_REGISTERS_SPDREG = 14, H_REGISTERS_MULH = 15, H_REGISTERS_ADDRH = 16, H_REGISTERS_ADDRL = 17
100	, H_REGISTERS_DATAH = 18, H_REGISTERS_DATAL = 19, H_REGISTERS_INTVECH = 20, H_REGISTERS_INTVECL = 21
101	, H_REGISTERS_INTSPD = 22, H_REGISTERS_INTF = 23, H_REGISTERS_INTE = 24, H_REGISTERS_INTED = 25
102	, H_REGISTERS_FCFG = 26, H_REGISTERS_TCTRL = 27, H_REGISTERS_XCFG = 28, H_REGISTERS_EMCFG = 29
103	, H_REGISTERS_IPCH = 30, H_REGISTERS_IPCL = 31, H_REGISTERS_RAIN = 32, H_REGISTERS_RAOUT = 33
104	, H_REGISTERS_RADIR = 34, H_REGISTERS_LFSRH = 35, H_REGISTERS_RBIN = 36, H_REGISTERS_RBOUT = 37
105	, H_REGISTERS_RBDIR = 38, H_REGISTERS_LFSRL = 39, H_REGISTERS_RCIN = 40, H_REGISTERS_RCOUT = 41
106	, H_REGISTERS_RCDIR = 42, H_REGISTERS_LFSRA = 43, H_REGISTERS_RDIN = 44, H_REGISTERS_RDOUT = 45
107	, H_REGISTERS_RDDIR = 46, H_REGISTERS_REIN = 48, H_REGISTERS_REOUT = 49, H_REGISTERS_REDIR = 50
108	, H_REGISTERS_RFIN = 52, H_REGISTERS_RFOUT = 53, H_REGISTERS_RFDIR = 54, H_REGISTERS_RGOUT = 57
109	, H_REGISTERS_RGDIR = 58, H_REGISTERS_RTTMR = 64, H_REGISTERS_RTCFG = 65, H_REGISTERS_T0TMR = 66
110	, H_REGISTERS_T0CFG = 67, H_REGISTERS_T1CNTH = 68, H_REGISTERS_T1CNTL = 69, H_REGISTERS_T1CAP1H = 70
111	, H_REGISTERS_T1CAP1L = 71, H_REGISTERS_T1CAP2H = 72, H_REGISTERS_T1CMP2H = 72, H_REGISTERS_T1CAP2L = 73
112	, H_REGISTERS_T1CMP2L = 73, H_REGISTERS_T1CMP1H = 74, H_REGISTERS_T1CMP1L = 75, H_REGISTERS_T1CFG1H = 76
113	, H_REGISTERS_T1CFG1L = 77, H_REGISTERS_T1CFG2H = 78, H_REGISTERS_T1CFG2L = 79, H_REGISTERS_ADCH = 80
114	, H_REGISTERS_ADCL = 81, H_REGISTERS_ADCCFG = 82, H_REGISTERS_ADCTMR = 83, H_REGISTERS_T2CNTH = 84
115	, H_REGISTERS_T2CNTL = 85, H_REGISTERS_T2CAP1H = 86, H_REGISTERS_T2CAP1L = 87, H_REGISTERS_T2CAP2H = 88
116	, H_REGISTERS_T2CMP2H = 88, H_REGISTERS_T2CAP2L = 89, H_REGISTERS_T2CMP2L = 89, H_REGISTERS_T2CMP1H = 90
117	, H_REGISTERS_T2CMP1L = 91, H_REGISTERS_T2CFG1H = 92, H_REGISTERS_T2CFG1L = 93, H_REGISTERS_T2CFG2H = 94
118	, H_REGISTERS_T2CFG2L = 95, H_REGISTERS_S1TMRH = 96, H_REGISTERS_S1TMRL = 97, H_REGISTERS_S1TBUFH = 98
119	, H_REGISTERS_S1TBUFL = 99, H_REGISTERS_S1TCFG = 100, H_REGISTERS_S1RCNT = 101, H_REGISTERS_S1RBUFH = 102
120	, H_REGISTERS_S1RBUFL = 103, H_REGISTERS_S1RCFG = 104, H_REGISTERS_S1RSYNC = 105, H_REGISTERS_S1INTF = 106
121	, H_REGISTERS_S1INTE = 107, H_REGISTERS_S1MODE = 108, H_REGISTERS_S1SMASK = 109, H_REGISTERS_PSPCFG = 110
122	, H_REGISTERS_CMPCFG = 111, H_REGISTERS_S2TMRH = 112, H_REGISTERS_S2TMRL = 113, H_REGISTERS_S2TBUFH = 114
123	, H_REGISTERS_S2TBUFL = 115, H_REGISTERS_S2TCFG = 116, H_REGISTERS_S2RCNT = 117, H_REGISTERS_S2RBUFH = 118
124	, H_REGISTERS_S2RBUFL = 119, H_REGISTERS_S2RCFG = 120, H_REGISTERS_S2RSYNC = 121, H_REGISTERS_S2INTF = 122
125	, H_REGISTERS_S2INTE = 123, H_REGISTERS_S2MODE = 124, H_REGISTERS_S2SMASK = 125, H_REGISTERS_CALLH = 126
126	, H_REGISTERS_CALLL = 127
127	} REGISTER_NAMES;
128
129	/* Attributes. */
130
131	/* Enum declaration for machine type selection. */
132	typedef enum mach_attr {
133	MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX
134	} MACH_ATTR;
135
136	/* Enum declaration for instruction set selection. */
137	typedef enum isa_attr {
138	ISA_IP2K, ISA_MAX
139	} ISA_ATTR;
140
141	/* Number of architecture variants. */
142	#define MAX_ISAS 1
143	#define MAX_MACHS ((int) MACH_MAX)
144
145	/* Ifield support. */
146
a40cbfa3 NC	147	/* Ifield attribute indices. */
	148
	149	/* Enum declaration for cgen_ifld attrs. */
	150	typedef enum cgen_ifld_attr {
	151	CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
	152	, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
	153	, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
	154	} CGEN_IFLD_ATTR;
	155
	156	/* Number of non-boolean elements in cgen_ifld_attr. */
	157	#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
	158
fb53f5a8 DB	159	/* cgen_ifld attribute accessor macros. */
fb53f5a8 DB	160	#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
4469d2be AM	161	#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
	162	#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
	163	#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
	164	#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
	165	#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
	166	#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
fb53f5a8	167
a40cbfa3 NC	168	/* Enum declaration for ip2k ifield types. */
	169	typedef enum ifield_type {
	170	IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG
	171	, IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO, IP2K_F_OP3
	172	, IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6, IP2K_F_OP8
	173	, IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3, IP2K_F_SKIPB
	174	, IP2K_F_PAGE3, IP2K_F_MAX
	175	} IFIELD_TYPE;
	176
	177	#define MAX_IFLD ((int) IP2K_F_MAX)
	178
	179	/* Hardware attribute indices. */
	180
	181	/* Enum declaration for cgen_hw attrs. */
	182	typedef enum cgen_hw_attr {
	183	CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
	184	, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
	185	} CGEN_HW_ATTR;
	186
	187	/* Number of non-boolean elements in cgen_hw_attr. */
	188	#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
	189
fb53f5a8 DB	190	/* cgen_hw attribute accessor macros. */
fb53f5a8 DB	191	#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
4469d2be AM	192	#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
	193	#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
	194	#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
	195	#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
fb53f5a8	196
a40cbfa3 NC	197	/* Enum declaration for ip2k hardware types. */
	198	typedef enum cgen_hw_type {
	199	HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
	200	, HW_H_IADDR, HW_H_SPR, HW_H_REGISTERS, HW_H_STACK
	201	, HW_H_PABITS, HW_H_ZBIT, HW_H_CBIT, HW_H_DCBIT
	202	, HW_H_PC, HW_MAX
	203	} CGEN_HW_TYPE;
	204
	205	#define MAX_HW ((int) HW_MAX)
	206
	207	/* Operand attribute indices. */
	208
	209	/* Enum declaration for cgen_operand attrs. */
	210	typedef enum cgen_operand_attr {
	211	CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
	212	, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
	213	, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
	214	} CGEN_OPERAND_ATTR;
	215
	216	/* Number of non-boolean elements in cgen_operand_attr. */
	217	#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
	218
fb53f5a8 DB	219	/* cgen_operand attribute accessor macros. */
fb53f5a8 DB	220	#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
4469d2be AM	221	#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
	222	#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
	223	#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
	224	#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
	225	#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
	226	#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
	227	#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
	228	#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
fb53f5a8	229
a40cbfa3 NC	230	/* Enum declaration for ip2k operand types. */
	231	typedef enum cgen_operand_type {
	232	IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8
	233	, IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H, IP2K_OPERAND_ADDR16L
	234	, IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT, IP2K_OPERAND_CBIT
	235	, IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX
	236	} CGEN_OPERAND_TYPE;
	237
	238	/* Number of operands types. */
	239	#define MAX_OPERANDS 13
	240
	241	/* Maximum number of operands referenced by any insn. */
	242	#define MAX_OPERAND_INSTANCES 8
	243
	244	/* Insn attribute indices. */
	245
	246	/* Enum declaration for cgen_insn attrs. */
	247	typedef enum cgen_insn_attr {
	248	CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
b11dcf4e	249	, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
a40cbfa3 NC	250	, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA
	251	, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
	252	} CGEN_INSN_ATTR;
	253
	254	/* Number of non-boolean elements in cgen_insn_attr. */
	255	#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
	256
fb53f5a8 DB	257	/* cgen_insn attribute accessor macros. */
fb53f5a8 DB	258	#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
4469d2be AM	259	#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
	260	#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
	261	#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
	262	#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
	263	#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
	264	#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
	265	#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
	266	#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
	267	#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
	268	#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
	269	#define CGEN_ATTR_CGEN_INSN_EXT_SKIP_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_EXT_SKIP_INSN)) != 0)
	270	#define CGEN_ATTR_CGEN_INSN_SKIPA_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIPA)) != 0)
fb53f5a8	271
a40cbfa3 NC	272	/* cgen.h uses things we just defined. */
	273	#include "opcode/cgen.h"
	274
610ad19b AM	275	extern const struct cgen_ifld ip2k_cgen_ifld_table[];
610ad19b AM	276
a40cbfa3 NC	277	/* Attributes. */
	278	extern const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[];
	279	extern const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[];
	280	extern const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[];
	281	extern const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[];
	282
	283	/* Hardware decls. */
	284
	285
bf143b25	286	extern const CGEN_HW_ENTRY ip2k_cgen_hw_table[];
a40cbfa3 NC	287
	288
	289
	290	#endif /* IP2K_CPU_H */