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sim: bfin: handle odd shift values with shift insns
[binutils.git] / sim / bfin / machs.c
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ef016f83
MF		 1/* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "config.h"
22
23#include "sim-main.h"
24#include "gdb/sim-bfin.h"
25#include "bfd.h"
26
27#include "sim-hw.h"
28#include "devices.h"
29#include "dv-bfin_cec.h"
ef016f83 30#include "dv-bfin_dmac.h"
ef016f83
MF		 31
32static const MACH bfin_mach;
33
34struct bfin_memory_layout {
35 address_word addr, len;
36 unsigned mask; /* see mapmask in sim_core_attach() */
37};
38struct bfin_dev_layout {
39 address_word base, len;
40 unsigned int dmac;
41 const char *dev;
42};
43struct bfin_dmac_layout {
44 address_word base;
45 unsigned int dma_count;
46};
082e1c4a
MF		 47struct bfin_port_layout {
48 /* Which device this routes to (name/port). */
49 const char *dst, *dst_port;
50 /* Which device this routes from (name/port). */
51 const char *src, *src_port;
52};
ef016f83
MF		 53struct bfin_model_data {
54 bu32 chipid;
55 int model_num;
56 const struct bfin_memory_layout *mem;
57 size_t mem_count;
58 const struct bfin_dev_layout *dev;
59 size_t dev_count;
60 const struct bfin_dmac_layout *dmac;
61 size_t dmac_count;
082e1c4a
MF		 62 const struct bfin_port_layout *port;
63 size_t port_count;
ef016f83
MF		 64};
65
66#define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
67#define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
68#define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
082e1c4a
MF		 69#define PORT(_dst, _dst_port, _src, _src_port) \
70 { \
71 .dst = _dst, \
72 .dst_port = _dst_port, \
73 .src = _src, \
74 .src_port = _src_port, \
75 }
76#define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op)
ef016f83
MF		 77
78/* [1] Common sim code can't model exec-only memory.
79 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
80
81#define bf000_chipid 0
82static const struct bfin_memory_layout bf000_mem[] = {};
83static const struct bfin_dev_layout bf000_dev[] = {};
84static const struct bfin_dmac_layout bf000_dmac[] = {};
082e1c4a 85static const struct bfin_port_layout bf000_port[] = {};
ef016f83
MF		 86
87#define bf50x_chipid 0x2800
88#define bf504_chipid bf50x_chipid
89#define bf506_chipid bf50x_chipid
990d19fd
MF		 90static const struct bfin_memory_layout bf50x_mem[] =
91{
ef016f83
MF		 92 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
93 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 94 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
95 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
96 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
97 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
98 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
99 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
100 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
101};
102#define bf504_mem bf50x_mem
103#define bf506_mem bf50x_mem
990d19fd
MF		 104static const struct bfin_dev_layout bf50x_dev[] =
105{
ef016f83
MF		 106 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
107 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
108 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
109 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
110 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
111 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
112 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
113 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
114 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
115 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
116 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 117 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 118 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
119 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
120 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 121 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
122 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 123 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
124 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
125};
126#define bf504_dev bf50x_dev
127#define bf506_dev bf50x_dev
990d19fd
MF		 128static const struct bfin_dmac_layout bf50x_dmac[] =
129{
ef016f83
MF		 130 { BFIN_MMR_DMAC0_BASE, 12, },
131};
132#define bf504_dmac bf50x_dmac
133#define bf506_dmac bf50x_dmac
082e1c4a
MF		 134static const struct bfin_port_layout bf50x_port[] =
135{
136 SIC (0, 0, "bfin_pll", "pll"),
137/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
138 SIC (0, 2, "bfin_ppi@0", "stat"),
139 SIC (0, 3, "bfin_sport@0", "stat"),
140 SIC (0, 4, "bfin_sport@1", "stat"),
141 SIC (0, 5, "bfin_uart2@0", "stat"),
142 SIC (0, 6, "bfin_uart2@1", "stat"),
143 SIC (0, 7, "bfin_spi@0", "stat"),
144 SIC (0, 8, "bfin_spi@1", "stat"),
145 SIC (0, 9, "bfin_can@0", "stat"),
146 SIC (0, 10, "bfin_rsi@0", "int0"),
147/*SIC (0, 11, reserved),*/
148 SIC (0, 12, "bfin_counter@0", "stat"),
149 SIC (0, 13, "bfin_counter@1", "stat"),
150 SIC (0, 14, "bfin_dma@0", "di"),
151 SIC (0, 15, "bfin_dma@1", "di"),
152 SIC (0, 16, "bfin_dma@2", "di"),
153 SIC (0, 17, "bfin_dma@3", "di"),
154 SIC (0, 18, "bfin_dma@4", "di"),
155 SIC (0, 19, "bfin_dma@5", "di"),
156 SIC (0, 20, "bfin_dma@6", "di"),
157 SIC (0, 21, "bfin_dma@7", "di"),
158 SIC (0, 22, "bfin_dma@8", "di"),
159 SIC (0, 23, "bfin_dma@9", "di"),
160 SIC (0, 24, "bfin_dma@10", "di"),
161 SIC (0, 25, "bfin_dma@11", "di"),
162 SIC (0, 26, "bfin_can@0", "rx"),
163 SIC (0, 27, "bfin_can@0", "tx"),
164 SIC (0, 28, "bfin_twi@0", "stat"),
165 SIC (0, 29, "bfin_gpio@5", "mask_a"),
166 SIC (0, 30, "bfin_gpio@5", "mask_b"),
167/*SIC (0, 31, reserved),*/
168 SIC (1, 0, "bfin_gptimer@0", "stat"),
169 SIC (1, 1, "bfin_gptimer@1", "stat"),
170 SIC (1, 2, "bfin_gptimer@2", "stat"),
171 SIC (1, 3, "bfin_gptimer@3", "stat"),
172 SIC (1, 4, "bfin_gptimer@4", "stat"),
173 SIC (1, 5, "bfin_gptimer@5", "stat"),
174 SIC (1, 6, "bfin_gptimer@6", "stat"),
175 SIC (1, 7, "bfin_gptimer@7", "stat"),
176 SIC (1, 8, "bfin_gpio@6", "mask_a"),
177 SIC (1, 9, "bfin_gpio@6", "mask_b"),
178 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
179 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
180 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
181 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
182 SIC (1, 12, "bfin_wdog@0", "gpi"),
183 SIC (1, 13, "bfin_gpio@7", "mask_a"),
184 SIC (1, 14, "bfin_gpio@7", "mask_b"),
185 SIC (1, 15, "bfin_acm@0", "stat"),
186 SIC (1, 16, "bfin_acm@1", "int"),
187/*SIC (1, 17, reserved),*/
188/*SIC (1, 18, reserved),*/
189 SIC (1, 19, "bfin_pwm@0", "trip"),
190 SIC (1, 20, "bfin_pwm@0", "sync"),
191 SIC (1, 21, "bfin_pwm@1", "trip"),
192 SIC (1, 22, "bfin_pwm@1", "sync"),
193 SIC (1, 23, "bfin_rsi@0", "int1"),
194};
195#define bf504_port bf50x_port
196#define bf506_port bf50x_port
ef016f83
MF		 197
198#define bf51x_chipid 0x27e8
199#define bf512_chipid bf51x_chipid
200#define bf514_chipid bf51x_chipid
201#define bf516_chipid bf51x_chipid
202#define bf518_chipid bf51x_chipid
990d19fd
MF		 203static const struct bfin_memory_layout bf51x_mem[] =
204{
ef016f83 205 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 206 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
207 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 208 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
209 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
210 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
211 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
212 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
213 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
214 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
215 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
216 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
217};
218#define bf512_mem bf51x_mem
219#define bf514_mem bf51x_mem
220#define bf516_mem bf51x_mem
221#define bf518_mem bf51x_mem
990d19fd
MF		 222static const struct bfin_dev_layout bf512_dev[] =
223{
ef016f83
MF		 224 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
225 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
226 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
227 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
228 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
229 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
230 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
231 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
232 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
233 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
234 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
235 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 236 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 237 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
238 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
239 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
240 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 241 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
242 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 243 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
244 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
245 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
246};
247#define bf514_dev bf512_dev
990d19fd
MF		 248static const struct bfin_dev_layout bf516_dev[] =
249{
ef016f83
MF		 250 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
251 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
252 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
253 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
254 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
255 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
256 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
257 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
258 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
259 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
260 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
261 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 262 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 263 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
264 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
265 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
266 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 267 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
268 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 269 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
270 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
271 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
272 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
273 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
274};
275#define bf518_dev bf516_dev
276#define bf512_dmac bf50x_dmac
277#define bf514_dmac bf50x_dmac
278#define bf516_dmac bf50x_dmac
279#define bf518_dmac bf50x_dmac
082e1c4a
MF		 280static const struct bfin_port_layout bf51x_port[] =
281{
282 SIC (0, 0, "bfin_pll", "pll"),
283/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
284 SIC (0, 2, "bfin_dmar@0", "block"),
285 SIC (0, 3, "bfin_dmar@1", "block"),
286 SIC (0, 4, "bfin_dmar@0", "overflow"),
287 SIC (0, 5, "bfin_dmar@1", "overflow"),
288 SIC (0, 6, "bfin_ppi@0", "stat"),
289 SIC (0, 7, "bfin_emac", "stat"),
290 SIC (0, 8, "bfin_sport@0", "stat"),
291 SIC (0, 9, "bfin_sport@1", "stat"),
292 SIC (0, 10, "bfin_ptp", "stat"),
293/*SIC (0, 11, reserved),*/
294 SIC (0, 12, "bfin_uart@0", "stat"),
295 SIC (0, 13, "bfin_uart@1", "stat"),
296 SIC (0, 14, "bfin_rtc", "rtc"),
297 SIC (0, 15, "bfin_dma@0", "di"),
298 SIC (0, 16, "bfin_dma@3", "di"),
299 SIC (0, 17, "bfin_dma@4", "di"),
300 SIC (0, 18, "bfin_dma@5", "di"),
301 SIC (0, 19, "bfin_dma@6", "di"),
302 SIC (0, 20, "bfin_twi@0", "stat"),
303 SIC (0, 21, "bfin_dma@7", "di"),
304 SIC (0, 22, "bfin_dma@8", "di"),
305 SIC (0, 23, "bfin_dma@9", "di"),
306 SIC (0, 24, "bfin_dma@10", "di"),
307 SIC (0, 25, "bfin_dma@11", "di"),
308 SIC (0, 26, "bfin_otp", "stat"),
309 SIC (0, 27, "bfin_counter@0", "stat"),
310 SIC (0, 28, "bfin_dma@1", "di"),
311 SIC (0, 29, "bfin_gpio@7", "mask_a"),
312 SIC (0, 30, "bfin_dma@2", "di"),
313 SIC (0, 31, "bfin_gpio@7", "mask_b"),
314 SIC (1, 0, "bfin_gptimer@0", "stat"),
315 SIC (1, 1, "bfin_gptimer@1", "stat"),
316 SIC (1, 2, "bfin_gptimer@2", "stat"),
317 SIC (1, 3, "bfin_gptimer@3", "stat"),
318 SIC (1, 4, "bfin_gptimer@4", "stat"),
319 SIC (1, 5, "bfin_gptimer@5", "stat"),
320 SIC (1, 6, "bfin_gptimer@6", "stat"),
321 SIC (1, 7, "bfin_gptimer@7", "stat"),
322 SIC (1, 8, "bfin_gpio@6", "mask_a"),
323 SIC (1, 9, "bfin_gpio@6", "mask_b"),
324 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
325 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
326 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
327 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
328 SIC (1, 12, "bfin_wdog@0", "gpi"),
329 SIC (1, 13, "bfin_gpio@5", "mask_a"),
330 SIC (1, 14, "bfin_gpio@5", "mask_b"),
331 SIC (1, 15, "bfin_spi@0", "stat"),
332 SIC (1, 16, "bfin_spi@1", "stat"),
333/*SIC (1, 17, reserved),*/
334/*SIC (1, 18, reserved),*/
335 SIC (1, 19, "bfin_rsi@0", "int0"),
336 SIC (1, 20, "bfin_rsi@0", "int1"),
337 SIC (1, 21, "bfin_pwm@0", "trip"),
338 SIC (1, 22, "bfin_pwm@0", "sync"),
339 SIC (1, 23, "bfin_ptp", "stat"),
340};
341#define bf512_port bf51x_port
342#define bf514_port bf51x_port
343#define bf516_port bf51x_port
344#define bf518_port bf51x_port
ef016f83
MF		 345
346#define bf522_chipid 0x27e4
347#define bf523_chipid 0x27e0
348#define bf524_chipid bf522_chipid
349#define bf525_chipid bf523_chipid
350#define bf526_chipid bf522_chipid
351#define bf527_chipid bf523_chipid
990d19fd
MF		 352static const struct bfin_memory_layout bf52x_mem[] =
353{
ef016f83 354 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 355 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
356 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 357 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
358 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
359 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
360 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
361 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
362 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
363 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
364 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
365 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
366};
367#define bf522_mem bf52x_mem
368#define bf523_mem bf52x_mem
369#define bf524_mem bf52x_mem
370#define bf525_mem bf52x_mem
371#define bf526_mem bf52x_mem
372#define bf527_mem bf52x_mem
990d19fd
MF		 373static const struct bfin_dev_layout bf522_dev[] =
374{
ef016f83
MF		 375 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
376 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
377 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
378 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
379 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
380 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
381 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
382 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
383 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
384 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
385 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
386 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 387 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 388 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
389 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
390 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
391 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 392 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
393 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 394 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
395 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
396 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
397};
398#define bf523_dev bf522_dev
399#define bf524_dev bf522_dev
400#define bf525_dev bf522_dev
990d19fd
MF		 401static const struct bfin_dev_layout bf526_dev[] =
402{
ef016f83
MF		 403 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
404 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
405 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
406 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
407 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
408 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
409 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
410 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
411 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
412 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
413 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
414 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 415 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 416 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
417 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
418 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
419 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 420 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
421 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 422 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
423 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
424 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
425 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
426 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
427};
428#define bf527_dev bf526_dev
429#define bf522_dmac bf50x_dmac
430#define bf523_dmac bf50x_dmac
431#define bf524_dmac bf50x_dmac
432#define bf525_dmac bf50x_dmac
433#define bf526_dmac bf50x_dmac
434#define bf527_dmac bf50x_dmac
082e1c4a
MF		 435static const struct bfin_port_layout bf52x_port[] =
436{
437 SIC (0, 0, "bfin_pll", "pll"),
438/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
439 SIC (0, 2, "bfin_dmar@0", "block"),
440 SIC (0, 3, "bfin_dmar@1", "block"),
441 SIC (0, 4, "bfin_dmar@0", "overflow"),
442 SIC (0, 5, "bfin_dmar@1", "overflow"),
443 SIC (0, 6, "bfin_ppi@0", "stat"),
444 SIC (0, 7, "bfin_emac", "stat"),
445 SIC (0, 8, "bfin_sport@0", "stat"),
446 SIC (0, 9, "bfin_sport@1", "stat"),
447/*SIC (0, 10, reserved),*/
448/*SIC (0, 11, reserved),*/
449 SIC (0, 12, "bfin_uart@0", "stat"),
450 SIC (0, 13, "bfin_uart@1", "stat"),
451 SIC (0, 14, "bfin_rtc", "rtc"),
452 SIC (0, 15, "bfin_dma@0", "di"),
453 SIC (0, 16, "bfin_dma@3", "di"),
454 SIC (0, 17, "bfin_dma@4", "di"),
455 SIC (0, 18, "bfin_dma@5", "di"),
456 SIC (0, 19, "bfin_dma@6", "di"),
457 SIC (0, 20, "bfin_twi@0", "stat"),
458 SIC (0, 21, "bfin_dma@7", "di"),
459 SIC (0, 22, "bfin_dma@8", "di"),
460 SIC (0, 23, "bfin_dma@9", "di"),
461 SIC (0, 24, "bfin_dma@10", "di"),
462 SIC (0, 25, "bfin_dma@11", "di"),
463 SIC (0, 26, "bfin_otp", "stat"),
464 SIC (0, 27, "bfin_counter@0", "stat"),
465 SIC (0, 28, "bfin_dma@1", "di"),
466 SIC (0, 29, "bfin_gpio@7", "mask_a"),
467 SIC (0, 30, "bfin_dma@2", "di"),
468 SIC (0, 31, "bfin_gpio@7", "mask_b"),
469 SIC (1, 0, "bfin_gptimer@0", "stat"),
470 SIC (1, 1, "bfin_gptimer@1", "stat"),
471 SIC (1, 2, "bfin_gptimer@2", "stat"),
472 SIC (1, 3, "bfin_gptimer@3", "stat"),
473 SIC (1, 4, "bfin_gptimer@4", "stat"),
474 SIC (1, 5, "bfin_gptimer@5", "stat"),
475 SIC (1, 6, "bfin_gptimer@6", "stat"),
476 SIC (1, 7, "bfin_gptimer@7", "stat"),
477 SIC (1, 8, "bfin_gpio@6", "mask_a"),
478 SIC (1, 9, "bfin_gpio@6", "mask_b"),
479 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
480 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
481 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
482 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
483 SIC (1, 12, "bfin_wdog@0", "gpi"),
484 SIC (1, 13, "bfin_gpio@5", "mask_a"),
485 SIC (1, 14, "bfin_gpio@5", "mask_b"),
486 SIC (1, 15, "bfin_spi@0", "stat"),
487 SIC (1, 16, "bfin_nfc", "stat"),
488 SIC (1, 17, "bfin_hostdp", "stat"),
489 SIC (1, 18, "bfin_hostdp", "done"),
490 SIC (1, 20, "bfin_usb", "int0"),
491 SIC (1, 21, "bfin_usb", "int1"),
492 SIC (1, 22, "bfin_usb", "int2"),
493};
494#define bf522_port bf51x_port
495#define bf523_port bf51x_port
496#define bf524_port bf51x_port
497#define bf525_port bf51x_port
498#define bf526_port bf51x_port
499#define bf527_port bf51x_port
ef016f83
MF		 500
501#define bf531_chipid 0x27a5
502#define bf532_chipid bf531_chipid
503#define bf533_chipid bf531_chipid
990d19fd
MF		 504static const struct bfin_memory_layout bf531_mem[] =
505{
ef016f83 506 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 507 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
508 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
509 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
510 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
511 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
512};
990d19fd
MF		 513static const struct bfin_memory_layout bf532_mem[] =
514{
ef016f83 515 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 516 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
517 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
518 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
519 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
520 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
521 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
522 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
523};
990d19fd
MF		 524static const struct bfin_memory_layout bf533_mem[] =
525{
ef016f83 526 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 527 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
528 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
529 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
530 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
531 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
532 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
533 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
534 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
535 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
536 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
537};
990d19fd
MF		 538static const struct bfin_dev_layout bf533_dev[] =
539{
ef016f83
MF		 540 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
541 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
542 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
543 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
544 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
545 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
546 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
a9c3ef47 547 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 548 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
549 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
550 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
551};
552#define bf531_dev bf533_dev
553#define bf532_dev bf533_dev
990d19fd
MF		 554static const struct bfin_dmac_layout bf533_dmac[] =
555{
ef016f83
MF		 556 { BFIN_MMR_DMAC0_BASE, 8, },
557};
558#define bf531_dmac bf533_dmac
559#define bf532_dmac bf533_dmac
082e1c4a
MF		 560static const struct bfin_port_layout bf533_port[] =
561{
562 SIC (0, 0, "bfin_pll", "pll"),
563/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
564 SIC (0, 2, "bfin_ppi@0", "stat"),
565 SIC (0, 3, "bfin_sport@0", "stat"),
566 SIC (0, 4, "bfin_sport@1", "stat"),
567 SIC (0, 5, "bfin_spi@0", "stat"),
568 SIC (0, 6, "bfin_uart@0", "stat"),
569 SIC (0, 7, "bfin_rtc", "rtc"),
570 SIC (0, 8, "bfin_dma@0", "di"),
571 SIC (0, 9, "bfin_dma@1", "di"),
572 SIC (0, 10, "bfin_dma@2", "di"),
573 SIC (0, 11, "bfin_dma@3", "di"),
574 SIC (0, 12, "bfin_dma@4", "di"),
575 SIC (0, 13, "bfin_dma@5", "di"),
576 SIC (0, 14, "bfin_dma@6", "di"),
577 SIC (0, 15, "bfin_dma@7", "di"),
578 SIC (0, 16, "bfin_gptimer@0", "stat"),
579 SIC (0, 17, "bfin_gptimer@1", "stat"),
580 SIC (0, 18, "bfin_gptimer@2", "stat"),
581 SIC (0, 19, "bfin_gpio@5", "mask_a"),
582 SIC (0, 20, "bfin_gpio@5", "mask_b"),
583 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
584 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
585 SIC (0, 22, "bfin_dma@258", "di"), /* mdma */
586 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
587 SIC (0, 23, "bfin_wdog@0", "gpi"),
588};
589#define bf531_port bf533_port
590#define bf532_port bf533_port
ef016f83
MF		 591
592#define bf534_chipid 0x27c6
593#define bf536_chipid 0x27c8
594#define bf537_chipid bf536_chipid
990d19fd
MF		 595static const struct bfin_memory_layout bf534_mem[] =
596{
ef016f83 597 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 598 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
599 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 600 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
601 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
602 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
603 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
604 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
605 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
606 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
607 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
608};
990d19fd
MF		 609static const struct bfin_memory_layout bf536_mem[] =
610{
ef016f83 611 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 612 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
613 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 614 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
615 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
616 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
617 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
618 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
619 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
620};
990d19fd
MF		 621static const struct bfin_memory_layout bf537_mem[] =
622{
ef016f83 623 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
ef016f83
MF		 624 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
625 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 626 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
627 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
628 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
629 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
630 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
631 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
632 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
633 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
634};
990d19fd
MF		 635static const struct bfin_dev_layout bf534_dev[] =
636{
ef016f83
MF		 637 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
638 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
639 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
640 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
641 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
642 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
643 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
644 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
645 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
646 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
647 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
648 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 649 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 650 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
651 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
652 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
653 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 654 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
655 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83 656 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
eb324344
MF		 657 DEVICE (0, 0, "glue-or@1"),
658 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
659 DEVICE (0, 0, "glue-or@2"),
660 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
661 DEVICE (0, 0, "glue-or@17"),
662 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
663 DEVICE (0, 0, "glue-or@18"),
664 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
665 DEVICE (0, 0, "glue-or@27"),
666 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
667 DEVICE (0, 0, "glue-or@31"),
668 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
ef016f83 669};
990d19fd
MF		 670static const struct bfin_dev_layout bf537_dev[] =
671{
ef016f83
MF		 672 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
673 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
674 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
675 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
676 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
677 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
678 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
679 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
680 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
681 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
682 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
683 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 684 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 685 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
686 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
687 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
688 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47
MF		 689 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
690 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83
MF		 691 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
692 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
693 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
eb324344
MF		 694 DEVICE (0, 0, "glue-or@1"),
695 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
696 DEVICE (0, 0, "glue-or@2"),
697 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
698 DEVICE (0, 0, "glue-or@17"),
699 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
700 DEVICE (0, 0, "glue-or@18"),
701 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
702 DEVICE (0, 0, "glue-or@27"),
703 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
704 DEVICE (0, 0, "glue-or@31"),
705 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
ef016f83
MF		 706};
707#define bf536_dev bf537_dev
708#define bf534_dmac bf50x_dmac
709#define bf536_dmac bf50x_dmac
710#define bf537_dmac bf50x_dmac
082e1c4a
MF		 711static const struct bfin_port_layout bf537_port[] =
712{
713 SIC (0, 0, "bfin_pll", "pll"),
eb324344
MF		 714 SIC (0, 1, "glue-or@1", "int"),
715/*PORT ("glue-or@1", "int", "bfin_dmac@0", "stat"),*/
716 PORT ("glue-or@1", "int", "bfin_dmar@0", "block"),
717 PORT ("glue-or@1", "int", "bfin_dmar@1", "block"),
718 PORT ("glue-or@1", "int", "bfin_dmar@0", "overflow"),
719 PORT ("glue-or@1", "int", "bfin_dmar@1", "overflow"),
720 SIC (0, 2, "glue-or@2", "int"),
721 PORT ("glue-or@2", "int", "bfin_can@0", "stat"),
722 PORT ("glue-or@2", "int", "bfin_emac", "stat"),
723 PORT ("glue-or@2", "int", "bfin_sport@0", "stat"),
724 PORT ("glue-or@2", "int", "bfin_sport@1", "stat"),
725 PORT ("glue-or@2", "int", "bfin_ppi@0", "stat"),
726 PORT ("glue-or@2", "int", "bfin_spi@0", "stat"),
727 PORT ("glue-or@2", "int", "bfin_uart@0", "stat"),
728 PORT ("glue-or@2", "int", "bfin_uart@1", "stat"),
082e1c4a
MF		 729 SIC (0, 3, "bfin_rtc", "rtc"),
730 SIC (0, 4, "bfin_dma@0", "di"),
731 SIC (0, 5, "bfin_dma@3", "di"),
732 SIC (0, 6, "bfin_dma@4", "di"),
733 SIC (0, 7, "bfin_dma@5", "di"),
734 SIC (0, 8, "bfin_dma@6", "di"),
735 SIC (0, 9, "bfin_twi@0", "stat"),
736 SIC (0, 10, "bfin_dma@7", "di"),
737 SIC (0, 11, "bfin_dma@8", "di"),
738 SIC (0, 12, "bfin_dma@9", "di"),
739 SIC (0, 13, "bfin_dma@10", "di"),
740 SIC (0, 14, "bfin_dma@11", "di"),
741 SIC (0, 15, "bfin_can@0", "rx"),
742 SIC (0, 16, "bfin_can@0", "tx"),
eb324344
MF		 743 SIC (0, 17, "glue-or@17", "int"),
744 PORT ("glue-or@17", "int", "bfin_dma@1", "di"),
745 PORT ("glue-or@17", "int", "bfin_gpio@7", "mask_a"),
746 SIC (0, 18, "glue-or@18", "int"),
747 PORT ("glue-or@18", "int", "bfin_dma@2", "di"),
748 PORT ("glue-or@18", "int", "bfin_gpio@7", "mask_b"),
082e1c4a
MF		 749 SIC (0, 19, "bfin_gptimer@0", "stat"),
750 SIC (0, 20, "bfin_gptimer@1", "stat"),
751 SIC (0, 21, "bfin_gptimer@2", "stat"),
752 SIC (0, 22, "bfin_gptimer@3", "stat"),
753 SIC (0, 23, "bfin_gptimer@4", "stat"),
754 SIC (0, 24, "bfin_gptimer@5", "stat"),
755 SIC (0, 25, "bfin_gptimer@6", "stat"),
756 SIC (0, 26, "bfin_gptimer@7", "stat"),
eb324344
MF		 757 SIC (0, 27, "glue-or@27", "int"),
758 PORT ("glue-or@27", "int", "bfin_gpio@5", "mask_a"),
759 PORT ("glue-or@27", "int", "bfin_gpio@6", "mask_a"),
082e1c4a
MF		 760 SIC (0, 28, "bfin_gpio@6", "mask_b"),
761 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
762 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
763 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
764 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
eb324344
MF		 765 SIC (0, 31, "glue-or@31", "int"),
766 PORT ("glue-or@31", "int", "bfin_wdog@0", "gpi"),
767 PORT ("glue-or@31", "int", "bfin_gpio@5", "mask_b"),
082e1c4a
MF		 768};
769#define bf534_port bf537_port
770#define bf536_port bf537_port
ef016f83
MF		 771
772#define bf538_chipid 0x27c4
773#define bf539_chipid bf538_chipid
990d19fd
MF		 774static const struct bfin_memory_layout bf538_mem[] =
775{
ef016f83
MF		 776 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
777 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
778 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
779 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
780 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
781 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
782 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
783 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
784 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
785 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
786 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
787 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
788 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
789};
790#define bf539_mem bf538_mem
990d19fd
MF		 791static const struct bfin_dev_layout bf538_dev[] =
792{
ef016f83
MF		 793 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
794 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
795 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
796 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
797 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
798 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
799 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
800 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
801 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
802 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
803 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47 804 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 805 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
806 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
807 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
808 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
809 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
810};
811#define bf539_dev bf538_dev
990d19fd
MF		 812static const struct bfin_dmac_layout bf538_dmac[] =
813{
ef016f83
MF		 814 { BFIN_MMR_DMAC0_BASE, 8, },
815 { BFIN_MMR_DMAC1_BASE, 12, },
816};
817#define bf539_dmac bf538_dmac
082e1c4a
MF		 818static const struct bfin_port_layout bf538_port[] =
819{
820 SIC (0, 0, "bfin_pll", "pll"),
821 SIC (0, 1, "bfin_dmac@0", "stat"),
822 SIC (0, 2, "bfin_ppi@0", "stat"),
823 SIC (0, 3, "bfin_sport@0", "stat"),
824 SIC (0, 4, "bfin_sport@1", "stat"),
825 SIC (0, 5, "bfin_spi@0", "stat"),
826 SIC (0, 6, "bfin_uart@0", "stat"),
827 SIC (0, 7, "bfin_rtc", "rtc"),
828 SIC (0, 8, "bfin_dma@0", "di"),
829 SIC (0, 9, "bfin_dma@1", "di"),
830 SIC (0, 10, "bfin_dma@2", "di"),
831 SIC (0, 11, "bfin_dma@3", "di"),
832 SIC (0, 12, "bfin_dma@4", "di"),
833 SIC (0, 13, "bfin_dma@5", "di"),
834 SIC (0, 14, "bfin_dma@6", "di"),
835 SIC (0, 15, "bfin_dma@7", "di"),
836 SIC (0, 16, "bfin_gptimer@0", "stat"),
837 SIC (0, 17, "bfin_gptimer@1", "stat"),
838 SIC (0, 18, "bfin_gptimer@2", "stat"),
839 SIC (0, 19, "bfin_gpio@5", "mask_a"),
840 SIC (0, 20, "bfin_gpio@5", "mask_b"),
841 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
842 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
843 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
844 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
845 SIC (0, 23, "bfin_wdog@0", "gpi"),
846 SIC (0, 24, "bfin_dmac@1", "stat"),
847 SIC (0, 25, "bfin_sport@2", "stat"),
848 SIC (0, 26, "bfin_sport@3", "stat"),
849/*SIC (0, 27, reserved),*/
850 SIC (0, 28, "bfin_spi@1", "stat"),
851 SIC (0, 29, "bfin_spi@2", "stat"),
852 SIC (0, 30, "bfin_uart@1", "stat"),
853 SIC (0, 31, "bfin_uart@2", "stat"),
854 SIC (1, 0, "bfin_can@0", "stat"),
855 SIC (1, 1, "bfin_dma@8", "di"),
856 SIC (1, 2, "bfin_dma@9", "di"),
857 SIC (1, 3, "bfin_dma@10", "di"),
858 SIC (1, 4, "bfin_dma@11", "di"),
859 SIC (1, 5, "bfin_dma@12", "di"),
860 SIC (1, 6, "bfin_dma@13", "di"),
861 SIC (1, 7, "bfin_dma@14", "di"),
862 SIC (1, 8, "bfin_dma@15", "di"),
863 SIC (1, 9, "bfin_dma@16", "di"),
864 SIC (1, 10, "bfin_dma@17", "di"),
865 SIC (1, 11, "bfin_dma@18", "di"),
866 SIC (1, 12, "bfin_dma@19", "di"),
867 SIC (1, 13, "bfin_twi@0", "stat"),
868 SIC (1, 14, "bfin_twi@1", "stat"),
869 SIC (1, 15, "bfin_can@0", "rx"),
870 SIC (1, 16, "bfin_can@0", "tx"),
871 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
872 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
873 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
874 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
875};
876#define bf539_port bf538_port
ef016f83
MF		 877
878#define bf54x_chipid 0x27de
879#define bf542_chipid bf54x_chipid
880#define bf544_chipid bf54x_chipid
881#define bf547_chipid bf54x_chipid
882#define bf548_chipid bf54x_chipid
883#define bf549_chipid bf54x_chipid
990d19fd
MF		 884static const struct bfin_memory_layout bf54x_mem[] =
885{
ef016f83
MF		 886 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
887 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
888 LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */
889 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
890 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
891 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
892 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
893 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
894 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
895 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
896 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
897 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
898 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
899 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
900 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
901 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
902};
903#define bf542_mem bf54x_mem
904#define bf544_mem bf54x_mem
905#define bf547_mem bf54x_mem
906#define bf548_mem bf54x_mem
907#define bf549_mem bf54x_mem
990d19fd
MF		 908static const struct bfin_dev_layout bf542_dev[] =
909{
ef016f83
MF		 910 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
911 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
912 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
913 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
914 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
915 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
916 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
917 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
918 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
919 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
920 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
921 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
922 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
923 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
924 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
925 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
926 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
927 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
928 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
929 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
930 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
931 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
932 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
933};
990d19fd
MF		 934static const struct bfin_dev_layout bf544_dev[] =
935{
ef016f83
MF		 936 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
937 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
938 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
939 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
940 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
941 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
942 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
943 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
944 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
945 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
946 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
947 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
948 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
949 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
950 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
951 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
952 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
953 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
954 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
955 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
956 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
957 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
958 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
959 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
960 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
961 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
962 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
963 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
964};
990d19fd
MF		 965static const struct bfin_dev_layout bf547_dev[] =
966{
ef016f83
MF		 967 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
968 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
969 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
970 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
971 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
972 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
973 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
974 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
975 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
976 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
977 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
978 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
979 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
980 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
981 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
982 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
983 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
984 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
985 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
986 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
987 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
988 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
989 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
990 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
991 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
992 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
993 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
994 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
995};
996#define bf548_dev bf547_dev
997#define bf549_dev bf547_dev
990d19fd
MF		 998static const struct bfin_dmac_layout bf54x_dmac[] =
999{
ef016f83
MF		 1000 { BFIN_MMR_DMAC0_BASE, 12, },
1001 { BFIN_MMR_DMAC1_BASE, 12, },
1002};
1003#define bf542_dmac bf54x_dmac
1004#define bf544_dmac bf54x_dmac
1005#define bf547_dmac bf54x_dmac
1006#define bf548_dmac bf54x_dmac
1007#define bf549_dmac bf54x_dmac
082e1c4a
MF		 1008static const struct bfin_port_layout bf54x_port[] =
1009{
1010 SIC (0, 0, "bfin_pll", "pll"),
1011 SIC (0, 1, "bfin_dmac@0", "stat"),
1012 SIC (0, 2, "bfin_eppi@0", "stat"),
1013 SIC (0, 3, "bfin_sport@0", "stat"),
1014 SIC (0, 4, "bfin_sport@1", "stat"),
1015 SIC (0, 5, "bfin_spi@0", "stat"),
1016 SIC (0, 6, "bfin_uart2@0", "stat"),
1017 SIC (0, 7, "bfin_rtc", "rtc"),
1018 SIC (0, 8, "bfin_dma@12", "di"),
1019 SIC (0, 9, "bfin_dma@0", "di"),
1020 SIC (0, 10, "bfin_dma@1", "di"),
1021 SIC (0, 11, "bfin_dma@2", "di"),
1022 SIC (0, 12, "bfin_dma@3", "di"),
1023 SIC (0, 13, "bfin_dma@4", "di"),
1024 SIC (0, 14, "bfin_dma@6", "di"),
1025 SIC (0, 15, "bfin_dma@7", "di"),
1026 SIC (0, 16, "bfin_gptimer@8", "stat"),
1027 SIC (0, 17, "bfin_gptimer@9", "stat"),
1028 SIC (0, 18, "bfin_gptimer@10", "stat"),
1029 SIC (0, 19, "bfin_pint@0", "stat"),
1030 SIC (0, 20, "bfin_pint@1", "stat"),
1031 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
1032 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
1033 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
1034 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
1035 SIC (0, 23, "bfin_wdog@0", "gpi"),
1036 SIC (0, 24, "bfin_dmac@1", "stat"),
1037 SIC (0, 25, "bfin_sport@2", "stat"),
1038 SIC (0, 26, "bfin_sport@3", "stat"),
1039 SIC (0, 27, "bfin_mxvr", "data"),
1040 SIC (0, 28, "bfin_spi@1", "stat"),
1041 SIC (0, 29, "bfin_spi@2", "stat"),
1042 SIC (0, 30, "bfin_uart2@1", "stat"),
1043 SIC (0, 31, "bfin_uart2@2", "stat"),
1044 SIC (1, 0, "bfin_can@0", "stat"),
1045 SIC (1, 1, "bfin_dma@18", "di"),
1046 SIC (1, 2, "bfin_dma@19", "di"),
1047 SIC (1, 3, "bfin_dma@20", "di"),
1048 SIC (1, 4, "bfin_dma@21", "di"),
1049 SIC (1, 5, "bfin_dma@13", "di"),
1050 SIC (1, 6, "bfin_dma@14", "di"),
1051 SIC (1, 7, "bfin_dma@5", "di"),
1052 SIC (1, 8, "bfin_dma@23", "di"),
1053 SIC (1, 9, "bfin_dma@8", "di"),
1054 SIC (1, 10, "bfin_dma@9", "di"),
1055 SIC (1, 11, "bfin_dma@10", "di"),
1056 SIC (1, 12, "bfin_dma@11", "di"),
1057 SIC (1, 13, "bfin_twi@0", "stat"),
1058 SIC (1, 14, "bfin_twi@1", "stat"),
1059 SIC (1, 15, "bfin_can@0", "rx"),
1060 SIC (1, 16, "bfin_can@0", "tx"),
1061 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
1062 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
1063 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
1064 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
1065 SIC (1, 19, "bfin_mxvr", "stat"),
1066 SIC (1, 20, "bfin_mxvr", "message"),
1067 SIC (1, 21, "bfin_mxvr", "packet"),
1068 SIC (1, 22, "bfin_eppi@1", "stat"),
1069 SIC (1, 23, "bfin_eppi@2", "stat"),
1070 SIC (1, 24, "bfin_uart2@3", "stat"),
1071 SIC (1, 25, "bfin_hostdp", "stat"),
1072/*SIC (1, 26, reserved),*/
1073 SIC (1, 27, "bfin_pixc", "stat"),
1074 SIC (1, 28, "bfin_nfc", "stat"),
1075 SIC (1, 29, "bfin_atapi", "stat"),
1076 SIC (1, 30, "bfin_can@1", "stat"),
1077 SIC (1, 31, "bfin_dmar@0", "block"),
1078 SIC (1, 31, "bfin_dmar@1", "block"),
1079 SIC (1, 31, "bfin_dmar@0", "overflow"),
1080 SIC (1, 31, "bfin_dmar@1", "overflow"),
1081 SIC (2, 0, "bfin_dma@15", "di"),
1082 SIC (2, 1, "bfin_dma@16", "di"),
1083 SIC (2, 2, "bfin_dma@17", "di"),
1084 SIC (2, 3, "bfin_dma@22", "di"),
1085 SIC (2, 4, "bfin_counter@0", "stat"),
1086 SIC (2, 5, "bfin_kpad@0", "stat"),
1087 SIC (2, 6, "bfin_can@1", "rx"),
1088 SIC (2, 7, "bfin_can@1", "tx"),
1089 SIC (2, 8, "bfin_sdh", "mask0"),
1090 SIC (2, 9, "bfin_sdh", "mask1"),
1091/*SIC (2, 10, reserved),*/
1092 SIC (2, 11, "bfin_usb", "int0"),
1093 SIC (2, 12, "bfin_usb", "int1"),
1094 SIC (2, 13, "bfin_usb", "int2"),
1095 SIC (2, 14, "bfin_usb", "dma"),
1096 SIC (2, 15, "bfin_otp", "stat"),
1097/*SIC (2, 16, reserved),*/
1098/*SIC (2, 17, reserved),*/
1099/*SIC (2, 18, reserved),*/
1100/*SIC (2, 19, reserved),*/
1101/*SIC (2, 20, reserved),*/
1102/*SIC (2, 21, reserved),*/
1103 SIC (2, 22, "bfin_gptimer@0", "stat"),
1104 SIC (2, 23, "bfin_gptimer@1", "stat"),
1105 SIC (2, 24, "bfin_gptimer@2", "stat"),
1106 SIC (2, 25, "bfin_gptimer@3", "stat"),
1107 SIC (2, 26, "bfin_gptimer@4", "stat"),
1108 SIC (2, 27, "bfin_gptimer@5", "stat"),
1109 SIC (2, 28, "bfin_gptimer@6", "stat"),
1110 SIC (2, 29, "bfin_gptimer@7", "stat"),
1111 SIC (2, 30, "bfin_pint@2", "stat"),
1112 SIC (2, 31, "bfin_pint@3", "stat"),
1113};
1114#define bf542_port bf54x_port
1115#define bf544_port bf54x_port
1116#define bf547_port bf54x_port
1117#define bf548_port bf54x_port
1118#define bf549_port bf54x_port
ef016f83
MF		 1119
1120/* This is only Core A of course ... */
1121#define bf561_chipid 0x27bb
990d19fd
MF		 1122static const struct bfin_memory_layout bf561_mem[] =
1123{
ef016f83
MF		 1124 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1125 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 1126 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
1127 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
1128 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
1129 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
1130 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
1131 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1132 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
1133};
990d19fd
MF		 1134static const struct bfin_dev_layout bf561_dev[] =
1135{
ef016f83
MF		 1136 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1137 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1138 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1139 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1140 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1141 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1142 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1143 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1144 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1145 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1146 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
a9c3ef47 1147 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 1148 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
1149 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
1150 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
1151 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
1152 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
a9c3ef47 1153 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
ef016f83
MF		 1154 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
1155 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
1156 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
1157 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
a9c3ef47 1158 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
ef016f83 1159};
990d19fd
MF		 1160static const struct bfin_dmac_layout bf561_dmac[] =
1161{
ef016f83
MF		 1162 { BFIN_MMR_DMAC0_BASE, 12, },
1163 { BFIN_MMR_DMAC1_BASE, 12, },
1164 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
1165};
082e1c4a
MF		 1166static const struct bfin_port_layout bf561_port[] =
1167{
1168 /* SIC0 */
1169 SIC (0, 0, "bfin_pll", "pll"),
1170/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1171/*SIC (0, 2, "bfin_dmac@1", "stat"),*/
1172/*SIC (0, 3, "bfin_imdmac", "stat"),*/
1173 SIC (0, 4, "bfin_ppi@0", "stat"),
1174 SIC (0, 5, "bfin_ppi@1", "stat"),
1175 SIC (0, 6, "bfin_sport@0", "stat"),
1176 SIC (0, 7, "bfin_sport@1", "stat"),
1177 SIC (0, 8, "bfin_spi@0", "stat"),
1178 SIC (0, 9, "bfin_uart@0", "stat"),
1179/*SIC (0, 10, reserved),*/
1180 SIC (0, 11, "bfin_dma@12", "di"),
1181 SIC (0, 12, "bfin_dma@13", "di"),
1182 SIC (0, 13, "bfin_dma@14", "di"),
1183 SIC (0, 14, "bfin_dma@15", "di"),
1184 SIC (0, 15, "bfin_dma@16", "di"),
1185 SIC (0, 16, "bfin_dma@17", "di"),
1186 SIC (0, 17, "bfin_dma@18", "di"),
1187 SIC (0, 18, "bfin_dma@19", "di"),
1188 SIC (0, 19, "bfin_dma@20", "di"),
1189 SIC (0, 20, "bfin_dma@21", "di"),
1190 SIC (0, 21, "bfin_dma@22", "di"),
1191 SIC (0, 22, "bfin_dma@23", "di"),
1192 SIC (0, 23, "bfin_dma@0", "di"),
1193 SIC (0, 24, "bfin_dma@1", "di"),
1194 SIC (0, 25, "bfin_dma@2", "di"),
1195 SIC (0, 26, "bfin_dma@3", "di"),
1196 SIC (0, 27, "bfin_dma@4", "di"),
1197 SIC (0, 28, "bfin_dma@5", "di"),
1198 SIC (0, 29, "bfin_dma@6", "di"),
1199 SIC (0, 30, "bfin_dma@7", "di"),
1200 SIC (0, 31, "bfin_dma@8", "di"),
1201 SIC (1, 0, "bfin_dma@9", "di"),
1202 SIC (1, 1, "bfin_dma@10", "di"),
1203 SIC (1, 2, "bfin_dma@11", "di"),
1204 SIC (1, 3, "bfin_gptimer@0", "stat"),
1205 SIC (1, 4, "bfin_gptimer@1", "stat"),
1206 SIC (1, 5, "bfin_gptimer@2", "stat"),
1207 SIC (1, 6, "bfin_gptimer@3", "stat"),
1208 SIC (1, 7, "bfin_gptimer@4", "stat"),
1209 SIC (1, 8, "bfin_gptimer@5", "stat"),
1210 SIC (1, 9, "bfin_gptimer@6", "stat"),
1211 SIC (1, 10, "bfin_gptimer@7", "stat"),
1212 SIC (1, 11, "bfin_gptimer@8", "stat"),
1213 SIC (1, 12, "bfin_gptimer@9", "stat"),
1214 SIC (1, 13, "bfin_gptimer@10", "stat"),
1215 SIC (1, 14, "bfin_gptimer@11", "stat"),
1216 SIC (1, 15, "bfin_gpio@5", "mask_a"),
1217 SIC (1, 16, "bfin_gpio@5", "mask_b"),
1218 SIC (1, 17, "bfin_gpio@6", "mask_a"),
1219 SIC (1, 18, "bfin_gpio@6", "mask_b"),
1220 SIC (1, 19, "bfin_gpio@7", "mask_a"),
1221 SIC (1, 20, "bfin_gpio@7", "mask_b"),
1222 SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */
1223 SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */
1224 SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */
1225 SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */
1226 SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */
1227 SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */
1228 SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */
1229 SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */
1230 SIC (1, 25, "bfin_imdma@0", "di"),
1231 SIC (1, 26, "bfin_imdma@1", "di"),
1232 SIC (1, 27, "bfin_wdog@0", "gpi"),
1233 SIC (1, 27, "bfin_wdog@1", "gpi"),
1234/*SIC (1, 28, reserved),*/
1235/*SIC (1, 29, reserved),*/
1236 SIC (1, 30, "bfin_sic", "sup_irq@0"),
1237 SIC (1, 31, "bfin_sic", "sup_irq@1"),
1238};
ef016f83
MF		 1239
1240#define bf592_chipid 0x20cb
990d19fd
MF		 1241static const struct bfin_memory_layout bf592_mem[] =
1242{
ef016f83
MF		 1243 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1244 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
ef016f83
MF		 1245 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
1246 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1247 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
1248};
990d19fd
MF		 1249static const struct bfin_dev_layout bf592_dev[] =
1250{
ef016f83
MF		 1251 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1252 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1253 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1254 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1255 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1256 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
a9c3ef47 1257 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
ef016f83
MF		 1258 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
1259 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1260 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
a9c3ef47 1261 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
ef016f83 1262};
990d19fd
MF		 1263static const struct bfin_dmac_layout bf592_dmac[] =
1264{
ef016f83
MF		 1265 /* XXX: there are only 9 channels, but mdma code below assumes that they
1266 start right after the dma channels ... */
1267 { BFIN_MMR_DMAC0_BASE, 12, },
1268};
082e1c4a
MF		 1269static const struct bfin_port_layout bf592_port[] =
1270{
1271 SIC (0, 0, "bfin_pll", "pll"),
1272/*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1273 SIC (0, 2, "bfin_ppi@0", "stat"),
1274 SIC (0, 3, "bfin_sport@0", "stat"),
1275 SIC (0, 4, "bfin_sport@1", "stat"),
1276 SIC (0, 5, "bfin_spi@0", "stat"),
1277 SIC (0, 6, "bfin_spi@1", "stat"),
1278 SIC (0, 7, "bfin_uart@0", "stat"),
1279 SIC (0, 8, "bfin_dma@0", "di"),
1280 SIC (0, 9, "bfin_dma@1", "di"),
1281 SIC (0, 10, "bfin_dma@2", "di"),
1282 SIC (0, 11, "bfin_dma@3", "di"),
1283 SIC (0, 12, "bfin_dma@4", "di"),
1284 SIC (0, 13, "bfin_dma@5", "di"),
1285 SIC (0, 14, "bfin_dma@6", "di"),
1286 SIC (0, 15, "bfin_dma@7", "di"),
1287 SIC (0, 16, "bfin_dma@8", "di"),
1288 SIC (0, 17, "bfin_gpio@5", "mask_a"),
1289 SIC (0, 18, "bfin_gpio@5", "mask_b"),
1290 SIC (0, 19, "bfin_gptimer@0", "stat"),
1291 SIC (0, 20, "bfin_gptimer@1", "stat"),
1292 SIC (0, 21, "bfin_gptimer@2", "stat"),
1293 SIC (0, 22, "bfin_gpio@6", "mask_a"),
1294 SIC (0, 23, "bfin_gpio@6", "mask_b"),
1295 SIC (0, 24, "bfin_twi@0", "stat"),
1296/* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1297 SIC (0, 25, "bfin_dma@9", "di"),
1298 SIC (0, 26, "bfin_dma@10", "di"),
1299 SIC (0, 27, "bfin_dma@11", "di"),
1300 SIC (0, 28, "bfin_dma@12", "di"),
1301/*SIC (0, 25, reserved),*/
1302/*SIC (0, 26, reserved),*/
1303/*SIC (0, 27, reserved),*/
1304/*SIC (0, 28, reserved),*/
1305 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
1306 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
1307 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
1308 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
1309 SIC (0, 31, "bfin_wdog", "gpi"),
1310};
ef016f83
MF		 1311
1312static const struct bfin_model_data bfin_model_data[] =
1313{
1314#define P(n) \
1315 [MODEL_BF##n] = { \
1316 bf##n##_chipid, n, \
1317 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
1318 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
1319 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
082e1c4a 1320 bf##n##_port, ARRAY_SIZE (bf##n##_port), \
ef016f83
MF		 1321 },
1322#include "proc_list.def"
1323#undef P
1324};
1325
1326#define CORE_DEVICE(dev, DEV) \
1327 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
990d19fd
MF		 1328static const struct bfin_dev_layout bfin_core_dev[] =
1329{
ef016f83
MF		 1330 CORE_DEVICE (cec, CEC),
1331 CORE_DEVICE (ctimer, CTIMER),
1332 CORE_DEVICE (evt, EVT),
1333 CORE_DEVICE (jtag, JTAG),
1334 CORE_DEVICE (mmu, MMU),
c43aadca 1335 CORE_DEVICE (pfmon, PFMON),
ef016f83
MF		 1336 CORE_DEVICE (trace, TRACE),
1337 CORE_DEVICE (wp, WP),
1338};
1339
082e1c4a
MF		 1340static void
1341dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata,
1342 const char *dev)
1343{
1344 size_t i;
1345 const char *sdev;
1346
1347 sdev = strchr (dev, '/');
1348 if (sdev)
1349 ++sdev;
1350 else
1351 sdev = dev;
1352
1353 for (i = 0; i < mdata->port_count; ++i)
1354 {
1355 const struct bfin_port_layout *port = &mdata->port[i];
1356
1357 /* There might be more than one mapping. */
1358 if (!strcmp (sdev, port->src))
1359 sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev,
1360 port->src_port, port->dst_port, port->dst);
1361 }
1362}
1363
ef016f83
MF		 1364#define dv_bfin_hw_parse(sd, dv, DV) \
1365 do { \
1366 bu32 base = BFIN_MMR_##DV##_BASE; \
1367 bu32 size = BFIN_MMR_##DV##_SIZE; \
1368 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
1369 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
082e1c4a 1370 dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \
ef016f83
MF		 1371 } while (0)
1372
1373static void
1374bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
1375{
1376 const MODEL *model = CPU_MODEL (cpu);
1377 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1378 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1379 int mnum = MODEL_NUM (model);
1380 unsigned i, j, dma_chan;
1381
1382 /* Map the core devices. */
1383 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
1384 {
1385 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
1386 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1387 }
1388 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
1389
1390 if (mnum == MODEL_BF000)
1391 goto done;
1392
1393 /* Map the system devices. */
1394 dv_bfin_hw_parse (sd, sic, SIC);
ef016f83
MF		 1395 for (i = 7; i < 16; ++i)
1396 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
1397
1398 dv_bfin_hw_parse (sd, pll, PLL);
ef016f83
MF		 1399
1400 dma_chan = 0;
1401 for (i = 0; i < mdata->dmac_count; ++i)
1402 {
1403 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
1404
1405 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
1406
1407 /* Hook up the non-mdma channels. */
1408 for (j = 0; j < dmac->dma_count; ++j)
1409 {
082e1c4a 1410 char dev[64];
ef016f83 1411
082e1c4a
MF		 1412 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan);
1413 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1414 dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE);
1415 dv_bfin_hw_port_parse (sd, mdata, dev);
ef016f83
MF		 1416
1417 ++dma_chan;
1418 }
1419
1420 /* Hook up the mdma channels -- assume every DMAC has 4. */
1421 for (j = 0; j < 4; ++j)
1422 {
082e1c4a
MF		 1423 char dev[64];
1424
1425 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE);
1426 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
ef016f83
MF		 1427 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
1428 BFIN_MMR_DMA_SIZE);
082e1c4a 1429 dv_bfin_hw_port_parse (sd, mdata, dev);
ef016f83
MF		 1430 }
1431 }
1432
1433 for (i = 0; i < mdata->dev_count; ++i)
1434 {
1435 const struct bfin_dev_layout *dev = &mdata->dev[i];
082e1c4a 1436
eb324344
MF		 1437 if (dev->len)
1438 {
1439 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1440 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
1441 }
1442 else
1443 {
1444 sim_hw_parse (sd, "/core/%s", dev->dev);
1445 }
1446
1447 dv_bfin_hw_port_parse (sd, mdata, dev->dev);
ef016f83
MF		 1448 if (strchr (dev->dev, '/'))
1449 continue;
082e1c4a 1450
ef016f83
MF		 1451 if (!strncmp (dev->dev, "bfin_uart", 9)
1452 || !strncmp (dev->dev, "bfin_emac", 9)
1453 || !strncmp (dev->dev, "bfin_sport", 10))
1454 {
1455 const char *sint = dev->dev + 5;
1456 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1457 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
ef016f83
MF		 1458 }
1459 else if (!strncmp (dev->dev, "bfin_wdog", 9))
1460 {
1461 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
1462 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
b5215db0 1463 }
ef016f83
MF		 1464 }
1465
1466 done:
1467 /* Add any additional user board content. */
1468 if (board->hw_file)
1469 sim_do_commandf (sd, "hw-file %s", board->hw_file);
1470
1471 /* Trigger all the new devices' finish func. */
1472 hw_tree_finish (dv_get_device (cpu, "/"));
1473}
1474
1475#include "bfroms/all.h"
1476
1477struct bfrom {
1478 bu32 addr, len, alias_len;
1479 int sirev;
1480 const char *buf;
1481};
1482
1483#define BFROMA(addr, rom, sirev, alias_len) \
1484 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
1485 sirev, bfrom_bf##rom##_0_##sirev, }
1486#define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
1487#define BFROM_STUB { 0, 0, 0, 0, NULL, }
990d19fd
MF		 1488static const struct bfrom bf50x_roms[] =
1489{
ef016f83
MF		 1490 BFROM (50x, 0, 0x1000000),
1491 BFROM_STUB,
1492};
990d19fd
MF		 1493static const struct bfrom bf51x_roms[] =
1494{
ef016f83
MF		 1495 BFROM (51x, 2, 0x1000000),
1496 BFROM (51x, 1, 0x1000000),
1497 BFROM (51x, 0, 0x1000000),
1498 BFROM_STUB,
1499};
990d19fd
MF		 1500static const struct bfrom bf526_roms[] =
1501{
dfb61fb6 1502 BFROM (526, 2, 0x1000000),
ef016f83
MF		 1503 BFROM (526, 1, 0x1000000),
1504 BFROM (526, 0, 0x1000000),
1505 BFROM_STUB,
1506};
990d19fd
MF		 1507static const struct bfrom bf527_roms[] =
1508{
ef016f83
MF		 1509 BFROM (527, 2, 0x1000000),
1510 BFROM (527, 1, 0x1000000),
1511 BFROM (527, 0, 0x1000000),
1512 BFROM_STUB,
1513};
990d19fd
MF		 1514static const struct bfrom bf533_roms[] =
1515{
ef016f83
MF		 1516 BFROM (533, 6, 0x1000000),
1517 BFROM (533, 5, 0x1000000),
1518 BFROM (533, 4, 0x1000000),
1519 BFROM (533, 3, 0x1000000),
1520 BFROM (533, 2, 0x1000000),
1521 BFROM (533, 1, 0x1000000),
1522 BFROM_STUB,
1523};
990d19fd
MF		 1524static const struct bfrom bf537_roms[] =
1525{
ef016f83
MF		 1526 BFROM (537, 3, 0x100000),
1527 BFROM (537, 2, 0x100000),
1528 BFROM (537, 1, 0x100000),
1529 BFROM (537, 0, 0x100000),
1530 BFROM_STUB,
1531};
990d19fd
MF		 1532static const struct bfrom bf538_roms[] =
1533{
ef016f83
MF		 1534 BFROM (538, 5, 0x1000000),
1535 BFROM (538, 4, 0x1000000),
1536 BFROM (538, 3, 0x1000000),
1537 BFROM (538, 2, 0x1000000),
1538 BFROM (538, 1, 0x1000000),
1539 BFROM (538, 0, 0x1000000),
1540 BFROM_STUB,
1541};
990d19fd
MF		 1542static const struct bfrom bf54x_roms[] =
1543{
dfb61fb6 1544 BFROM (54x, 4, 0),
ef016f83
MF		 1545 BFROM (54x, 2, 0),
1546 BFROM (54x, 1, 0),
1547 BFROM (54x, 0, 0),
dfb61fb6 1548 BFROMA (0xffa14000, 54x_l1, 4, 0),
ef016f83
MF		 1549 BFROMA (0xffa14000, 54x_l1, 2, 0),
1550 BFROMA (0xffa14000, 54x_l1, 1, 0),
1551 BFROMA (0xffa14000, 54x_l1, 0, 0),
1552 BFROM_STUB,
1553};
990d19fd
MF		 1554static const struct bfrom bf561_roms[] =
1555{
ef016f83
MF		 1556 /* XXX: No idea what the actual wrap limit is here. */
1557 BFROM (561, 5, 0),
1558 BFROM_STUB,
1559};
990d19fd
MF		 1560static const struct bfrom bf59x_roms[] =
1561{
ef016f83
MF		 1562 BFROM (59x, 1, 0x1000000),
1563 BFROM (59x, 0, 0x1000000),
1564 BFROMA (0xffa10000, 59x_l1, 1, 0),
1565 BFROM_STUB,
1566};
1567
1568static void
1569bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
1570{
1571 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1572 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1573 int mnum = mdata->model_num;
1574 const struct bfrom *bfrom;
1575 unsigned int sirev;
1576
1577 if (mnum >= 500 && mnum <= 509)
1578 bfrom = bf50x_roms;
1579 else if (mnum >= 510 && mnum <= 519)
1580 bfrom = bf51x_roms;
1581 else if (mnum >= 520 && mnum <= 529)
1582 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
1583 else if (mnum >= 531 && mnum <= 533)
1584 bfrom = bf533_roms;
1585 else if (mnum == 535)
1586 /* Stub. */;
1587 else if (mnum >= 534 && mnum <= 537)
1588 bfrom = bf537_roms;
1589 else if (mnum >= 538 && mnum <= 539)
1590 bfrom = bf538_roms;
1591 else if (mnum >= 540 && mnum <= 549)
1592 bfrom = bf54x_roms;
1593 else if (mnum == 561)
1594 bfrom = bf561_roms;
1595 else if (mnum >= 590 && mnum <= 599)
1596 bfrom = bf59x_roms;
1597 else
1598 return;
1599
1600 if (board->sirev_valid)
1601 sirev = board->sirev;
1602 else
1603 sirev = bfrom->sirev;
1604 while (bfrom->buf)
1605 {
1606 /* Map all the ranges for this model/sirev. */
1607 if (bfrom->sirev == sirev)
1608 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
1609 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
1610 (char *)bfrom->buf);
1611 ++bfrom;
1612 }
1613}
1614
1615void
1616bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
1617{
1618 const MODEL *model = CPU_MODEL (cpu);
1619 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1620 int mnum = MODEL_NUM (model);
1621 size_t idx;
1622
1623 /* These memory maps are supposed to be cpu-specific, but the common sim
1624 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1625 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1626 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1627
1628 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1629 return;
1630
1631 if (mnum == MODEL_BF000)
1632 goto core_only;
1633
1634 /* Map in the on-chip memories (SRAMs). */
1635 mdata = &bfin_model_data[MODEL_NUM (model)];
1636 for (idx = 0; idx < mdata->mem_count; ++idx)
1637 {
1638 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1639 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1640 mem->len, 0, NULL, NULL);
1641 }
1642
1643 /* Map the on-chip ROMs. */
1644 bfin_model_map_bfrom (sd, cpu);
1645
1646 core_only:
1647 /* Finally, build up the tree for this cpu model. */
1648 bfin_model_hw_tree_init (sd, cpu);
1649}
1650
1651bu32
1652bfin_model_get_chipid (SIM_DESC sd)
1653{
1654 SIM_CPU *cpu = STATE_CPU (sd, 0);
1655 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1656 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1657 return
1658 (board->sirev << 28) |
1659 (mdata->chipid << 12) |
1660 (((0xE5 << 1) | 1) & 0xFF);
1661}
1662
1663bu32
1664bfin_model_get_dspid (SIM_DESC sd)
1665{
1666 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1667 return
1668 (0xE5 << 24) |
1669 (0x04 << 16) |
1670 (board->sirev);
1671}
1672
1673static void
1674bfin_model_init (SIM_CPU *cpu)
1675{
1676 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1677}
1678
1679static bu32
1680bfin_extract_unsigned_integer (unsigned char *addr, int len)
1681{
1682 bu32 retval;
1683 unsigned char * p;
1684 unsigned char * startaddr = (unsigned char *)addr;
1685 unsigned char * endaddr = startaddr + len;
1686
1687 retval = 0;
1688
1689 for (p = endaddr; p > startaddr;)
1690 retval = (retval << 8) | *--p;
1691
1692 return retval;
1693}
1694
1695static void
1696bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1697{
1698 unsigned char *p;
1699 unsigned char *startaddr = addr;
1700 unsigned char *endaddr = startaddr + len;
1701
1702 for (p = startaddr; p < endaddr;)
1703 {
1704 *p++ = val & 0xff;
1705 val >>= 8;
1706 }
1707}
1708
1709static bu32 *
1710bfin_get_reg (SIM_CPU *cpu, int rn)
1711{
1712 switch (rn)
1713 {
1714 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1715 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1716 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1717 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1718 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1719 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1720 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1721 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1722 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1723 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1724 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1725 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1726 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1727 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1728 case SIM_BFIN_SP_REGNUM: return &SPREG;
1729 case SIM_BFIN_FP_REGNUM: return &FPREG;
1730 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1731 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1732 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1733 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1734 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1735 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1736 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1737 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1738 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1739 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1740 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1741 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1742 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1743 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1744 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1745 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1746 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1747 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1748 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1749 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1750 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1751 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1752 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1753 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1754 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1755 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1756 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1757 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1758 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1759 case SIM_BFIN_USP_REGNUM: return &USPREG;
1760 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1761 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1762 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1763 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1764 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1765 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1766 case SIM_BFIN_PC_REGNUM: return &PCREG;
1767 default: return NULL;
1768 }
1769}
1770
1771static int
1772bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1773{
1774 bu32 value, *reg;
1775
1776 reg = bfin_get_reg (cpu, rn);
1777 if (reg)
1778 value = *reg;
1779 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1780 value = ASTAT;
1781 else if (rn == SIM_BFIN_CC_REGNUM)
1782 value = CCREG;
1783 else
1784 return 0; // will be an error in gdb
1785
1786 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1787 have the normal SP/USP behavior. User mode is tricky though. */
1788 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1789 && cec_is_user_mode (cpu))
1790 {
1791 if (rn == SIM_BFIN_SP_REGNUM)
1792 value = KSPREG;
1793 else if (rn == SIM_BFIN_USP_REGNUM)
1794 value = SPREG;
1795 }
1796
1797 bfin_store_unsigned_integer (buf, 4, value);
1798
1799 return -1; // disables size checking in gdb
1800}
1801
1802static int
1803bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1804{
1805 bu32 value, *reg;
1806
1807 value = bfin_extract_unsigned_integer (buf, 4);
1808 reg = bfin_get_reg (cpu, rn);
1809
1810 if (reg)
1811 /* XXX: Need register trace ? */
1812 *reg = value;
1813 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1814 SET_ASTAT (value);
1815 else if (rn == SIM_BFIN_CC_REGNUM)
1816 SET_CCREG (value);
1817 else
1818 return 0; // will be an error in gdb
1819
1820 return -1; // disables size checking in gdb
1821}
1822
1823static sim_cia
1824bfin_pc_get (SIM_CPU *cpu)
1825{
1826 return PCREG;
1827}
1828
1829static void
1830bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1831{
1832 SET_PCREG (newpc);
1833}
1834
1835static const char *
1836bfin_insn_name (SIM_CPU *cpu, int i)
1837{
1838 static const char * const insn_name[] = {
1839#define I(insn) #insn,
1840#include "insn_list.def"
1841#undef I
1842 };
1843 return insn_name[i];
1844}
1845
1846static void
1847bfin_init_cpu (SIM_CPU *cpu)
1848{
1849 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1850 CPU_REG_STORE (cpu) = bfin_reg_store;
1851 CPU_PC_FETCH (cpu) = bfin_pc_get;
1852 CPU_PC_STORE (cpu) = bfin_pc_set;
1853 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1854 CPU_INSN_NAME (cpu) = bfin_insn_name;
1855}
1856
1857static void
1858bfin_prepare_run (SIM_CPU *cpu)
1859{
1860}
1861
1862static const MODEL bfin_models[] =
1863{
1864#define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1865#include "proc_list.def"
1866#undef P
1867 { 0, NULL, 0, NULL, NULL, }
1868};
1869
1870static const MACH_IMP_PROPERTIES bfin_imp_properties =
1871{
1872 sizeof (SIM_CPU),
1873 0,
1874};
1875
1876static const MACH bfin_mach =
1877{
1878 "bfin", "bfin", MACH_BFIN,
1879 32, 32, & bfin_models[0], & bfin_imp_properties,
1880 bfin_init_cpu,
1881 bfin_prepare_run
1882};
1883
1884const MACH *sim_machs[] =
1885{
1886 & bfin_mach,
1887 NULL
1888};
1889\f
1890/* Device option parsing. */
1891
1892static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1893
1894enum {
1895 OPTION_MACH_SIREV = OPTION_START,
1896 OPTION_MACH_HW_BOARD_FILE,
1897};
1898
1899const OPTION bfin_mach_options[] =
1900{
1901 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1902 '\0', "NUMBER", "Set CPU silicon revision",
1903 bfin_mach_option_handler, NULL },
1904
1905 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1906 '\0', "FILE", "Add the supplemental devices listed in the file",
1907 bfin_mach_option_handler, NULL },
1908
1909 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1910};
1911
1912static SIM_RC
1913bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1914 char *arg, int is_command)
1915{
1916 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1917
1918 switch (opt)
1919 {
1920 case OPTION_MACH_SIREV:
1921 board->sirev_valid = 1;
1922 /* Accept (and throw away) a leading "0." in the version. */
1923 if (!strncmp (arg, "0.", 2))
1924 arg += 2;
1925 board->sirev = atoi (arg);
1926 if (board->sirev > 0xf)
1927 {
1928 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
1929 return SIM_RC_FAIL;
1930 }
1931 return SIM_RC_OK;
1932
1933 case OPTION_MACH_HW_BOARD_FILE:
1934 board->hw_file = xstrdup (arg);
1935 return SIM_RC_OK;
1936
1937 default:
1938 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
1939 return SIM_RC_FAIL;
1940 }
1941}
Empty description
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