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Revise targets able to run ELF 64k section test
[binutils.git] / gdb / nds32-tdep.c
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a28d8e50
YTL		 1/* Target-dependent code for the NDS32 architecture, for GDB.
2
3 Copyright (C) 2013-2016 Free Software Foundation, Inc.
4 Contributed by Andes Technology Corporation.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22#include "frame.h"
23#include "frame-unwind.h"
24#include "frame-base.h"
25#include "symtab.h"
26#include "gdbtypes.h"
27#include "gdbcore.h"
28#include "value.h"
29#include "reggroups.h"
30#include "inferior.h"
31#include "osabi.h"
32#include "arch-utils.h"
33#include "regcache.h"
34#include "dis-asm.h"
35#include "user-regs.h"
36#include "elf-bfd.h"
37#include "dwarf2-frame.h"
38#include "remote.h"
39#include "target-descriptions.h"
40
41#include "nds32-tdep.h"
42#include "elf/nds32.h"
43#include "opcode/nds32.h"
44#include "features/nds32.c"
45
46/* Simple macros for instruction analysis. */
47#define CHOP_BITS(insn, n) (insn & ~__MASK (n))
48#define N32_LSMW_ENABLE4(insn) (((insn) >> 6) & 0xf)
49#define N32_SMW_ADM \
50 N32_TYPE4 (LSMW, 0, 0, 0, 1, (N32_LSMW_ADM << 2) | N32_LSMW_LSMW)
51#define N32_LMW_BIM \
52 N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
53#define N32_FLDI_SP \
54 N32_TYPE2 (LDC, 0, REG_SP, 0)
55
56extern void _initialize_nds32_tdep (void);
57
58/* Use an invalid address value as 'not available' marker. */
59enum { REG_UNAVAIL = (CORE_ADDR) -1 };
60
61/* Use an impossible value as invalid offset. */
62enum { INVALID_OFFSET = (CORE_ADDR) -1 };
63
64/* Instruction groups for NDS32 epilogue analysis. */
65enum
66{
67 /* Instructions used everywhere, not only in epilogue. */
68 INSN_NORMAL,
69 /* Instructions used to reset sp for local vars, arguments, etc. */
70 INSN_RESET_SP,
71 /* Instructions used to recover saved regs and to recover padding. */
72 INSN_RECOVER,
73 /* Instructions used to return to the caller. */
74 INSN_RETURN,
75 /* Instructions used to recover saved regs and to return to the caller. */
76 INSN_RECOVER_RETURN,
77};
78
79static const char *const nds32_register_names[] =
80{
81 /* 32 GPRs. */
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
85 "r24", "r25", "r26", "r27", "fp", "gp", "lp", "sp",
86 /* PC. */
87 "pc",
88};
89
90static const char *const nds32_fdr_register_names[] =
91{
92 "fd0", "fd1", "fd2", "fd3", "fd4", "fd5", "fd6", "fd7",
93 "fd8", "fd9", "fd10", "fd11", "fd12", "fd13", "fd14", "fd15",
94 "fd16", "fd17", "fd18", "fd19", "fd20", "fd21", "fd22", "fd23",
95 "fd24", "fd25", "fd26", "fd27", "fd28", "fd29", "fd30", "fd31"
96};
97
98static const char *const nds32_fsr_register_names[] =
99{
100 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
101 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
102 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
103 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
104};
105
106/* The number of registers for four FPU configuration options. */
107const int num_fdr_map[] = { 4, 8, 16, 32 };
108const int num_fsr_map[] = { 8, 16, 32, 32 };
109
110/* Aliases for registers. */
111static const struct
112{
113 const char *name;
114 const char *alias;
115} nds32_register_aliases[] =
116{
117 {"r15", "ta"},
118 {"r26", "p0"},
119 {"r27", "p1"},
120 {"fp", "r28"},
121 {"gp", "r29"},
122 {"lp", "r30"},
123 {"sp", "r31"},
124
125 {"cr0", "cpu_ver"},
126 {"cr1", "icm_cfg"},
127 {"cr2", "dcm_cfg"},
128 {"cr3", "mmu_cfg"},
129 {"cr4", "msc_cfg"},
130 {"cr5", "core_id"},
131 {"cr6", "fucop_exist"},
132 {"cr7", "msc_cfg2"},
133
134 {"ir0", "psw"},
135 {"ir1", "ipsw"},
136 {"ir2", "p_psw"},
137 {"ir3", "ivb"},
138 {"ir4", "eva"},
139 {"ir5", "p_eva"},
140 {"ir6", "itype"},
141 {"ir7", "p_itype"},
142 {"ir8", "merr"},
143 {"ir9", "ipc"},
144 {"ir10", "p_ipc"},
145 {"ir11", "oipc"},
146 {"ir12", "p_p0"},
147 {"ir13", "p_p1"},
148 {"ir14", "int_mask"},
149 {"ir15", "int_pend"},
150 {"ir16", "sp_usr"},
151 {"ir17", "sp_priv"},
152 {"ir18", "int_pri"},
153 {"ir19", "int_ctrl"},
154 {"ir20", "sp_usr1"},
155 {"ir21", "sp_priv1"},
156 {"ir22", "sp_usr2"},
157 {"ir23", "sp_priv2"},
158 {"ir24", "sp_usr3"},
159 {"ir25", "sp_priv3"},
160 {"ir26", "int_mask2"},
161 {"ir27", "int_pend2"},
162 {"ir28", "int_pri2"},
163 {"ir29", "int_trigger"},
164
165 {"mr0", "mmu_ctl"},
166 {"mr1", "l1_pptb"},
167 {"mr2", "tlb_vpn"},
168 {"mr3", "tlb_data"},
169 {"mr4", "tlb_misc"},
170 {"mr5", "vlpt_idx"},
171 {"mr6", "ilmb"},
172 {"mr7", "dlmb"},
173 {"mr8", "cache_ctl"},
174 {"mr9", "hsmp_saddr"},
175 {"mr10", "hsmp_eaddr"},
176 {"mr11", "bg_region"},
177
178 {"dr0", "bpc0"},
179 {"dr1", "bpc1"},
180 {"dr2", "bpc2"},
181 {"dr3", "bpc3"},
182 {"dr4", "bpc4"},
183 {"dr5", "bpc5"},
184 {"dr6", "bpc6"},
185 {"dr7", "bpc7"},
186 {"dr8", "bpa0"},
187 {"dr9", "bpa1"},
188 {"dr10", "bpa2"},
189 {"dr11", "bpa3"},
190 {"dr12", "bpa4"},
191 {"dr13", "bpa5"},
192 {"dr14", "bpa6"},
193 {"dr15", "bpa7"},
194 {"dr16", "bpam0"},
195 {"dr17", "bpam1"},
196 {"dr18", "bpam2"},
197 {"dr19", "bpam3"},
198 {"dr20", "bpam4"},
199 {"dr21", "bpam5"},
200 {"dr22", "bpam6"},
201 {"dr23", "bpam7"},
202 {"dr24", "bpv0"},
203 {"dr25", "bpv1"},
204 {"dr26", "bpv2"},
205 {"dr27", "bpv3"},
206 {"dr28", "bpv4"},
207 {"dr29", "bpv5"},
208 {"dr30", "bpv6"},
209 {"dr31", "bpv7"},
210 {"dr32", "bpcid0"},
211 {"dr33", "bpcid1"},
212 {"dr34", "bpcid2"},
213 {"dr35", "bpcid3"},
214 {"dr36", "bpcid4"},
215 {"dr37", "bpcid5"},
216 {"dr38", "bpcid6"},
217 {"dr39", "bpcid7"},
218 {"dr40", "edm_cfg"},
219 {"dr41", "edmsw"},
220 {"dr42", "edm_ctl"},
221 {"dr43", "edm_dtr"},
222 {"dr44", "bpmtc"},
223 {"dr45", "dimbr"},
224 {"dr46", "tecr0"},
225 {"dr47", "tecr1"},
226
227 {"hspr0", "hsp_ctl"},
228 {"hspr1", "sp_bound"},
229 {"hspr2", "sp_bound_priv"},
230
231 {"pfr0", "pfmc0"},
232 {"pfr1", "pfmc1"},
233 {"pfr2", "pfmc2"},
234 {"pfr3", "pfm_ctl"},
235 {"pfr4", "pft_ctl"},
236
237 {"dmar0", "dma_cfg"},
238 {"dmar1", "dma_gcsw"},
239 {"dmar2", "dma_chnsel"},
240 {"dmar3", "dma_act"},
241 {"dmar4", "dma_setup"},
242 {"dmar5", "dma_isaddr"},
243 {"dmar6", "dma_esaddr"},
244 {"dmar7", "dma_tcnt"},
245 {"dmar8", "dma_status"},
246 {"dmar9", "dma_2dset"},
247 {"dmar10", "dma_2dsctl"},
248 {"dmar11", "dma_rcnt"},
249 {"dmar12", "dma_hstatus"},
250
251 {"racr0", "prusr_acc_ctl"},
252 {"fucpr", "fucop_ctl"},
253
254 {"idr0", "sdz_ctl"},
255 {"idr1", "misc_ctl"},
256 {"idr2", "ecc_misc"},
257
258 {"secur0", "sfcr"},
259 {"secur1", "sign"},
260 {"secur2", "isign"},
261 {"secur3", "p_isign"},
262};
263
264/* Value of a register alias. BATON is the regnum of the corresponding
265 register. */
266
267static struct value *
268value_of_nds32_reg (struct frame_info *frame, const void *baton)
269{
270 return value_of_register ((int) (intptr_t) baton, frame);
271}
272\f
273/* Implement the "frame_align" gdbarch method. */
274
275static CORE_ADDR
276nds32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
277{
278 /* 8-byte aligned. */
279 return align_down (sp, 8);
280}
281
282/* Implement the "breakpoint_from_pc" gdbarch method.
283
284 Use the program counter to determine the contents and size of a
285 breakpoint instruction. Return a pointer to a string of bytes that
286 encode a breakpoint instruction, store the length of the string in
287 *LENPTR and optionally adjust *PCPTR to point to the correct memory
288 location for inserting the breakpoint. */
289
290static const gdb_byte *
291nds32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
292 int *lenptr)
293{
294 /* The same insn machine code is used for little-endian and big-endian. */
295 static const gdb_byte break_insn[] = { 0xEA, 0x00 };
296
297 *lenptr = sizeof (break_insn);
298 return break_insn;
299}
300
301/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
302
303static int
304nds32_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
305{
306 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
307 const int FSR = 38;
308 const int FDR = FSR + 32;
309
310 if (num >= 0 && num < 32)
311 {
312 /* General-purpose registers (R0 - R31). */
313 return num;
314 }
315 else if (num >= FSR && num < FSR + 32)
316 {
317 /* Single precision floating-point registers (FS0 - FS31). */
318 return num - FSR + tdep->fs0_regnum;
319 }
320 else if (num >= FDR && num < FDR + 32)
321 {
322 /* Double precision floating-point registers (FD0 - FD31). */
323 return num - FDR + NDS32_FD0_REGNUM;
324 }
325
326 /* No match, return a inaccessible register number. */
327 return -1;
328}
329\f
330/* NDS32 register groups. */
331static struct reggroup *nds32_cr_reggroup;
332static struct reggroup *nds32_ir_reggroup;
333static struct reggroup *nds32_mr_reggroup;
334static struct reggroup *nds32_dr_reggroup;
335static struct reggroup *nds32_pfr_reggroup;
336static struct reggroup *nds32_hspr_reggroup;
337static struct reggroup *nds32_dmar_reggroup;
338static struct reggroup *nds32_racr_reggroup;
339static struct reggroup *nds32_idr_reggroup;
340static struct reggroup *nds32_secur_reggroup;
341
342static void
343nds32_init_reggroups (void)
344{
345 nds32_cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
346 nds32_ir_reggroup = reggroup_new ("ir", USER_REGGROUP);
347 nds32_mr_reggroup = reggroup_new ("mr", USER_REGGROUP);
348 nds32_dr_reggroup = reggroup_new ("dr", USER_REGGROUP);
349 nds32_pfr_reggroup = reggroup_new ("pfr", USER_REGGROUP);
350 nds32_hspr_reggroup = reggroup_new ("hspr", USER_REGGROUP);
351 nds32_dmar_reggroup = reggroup_new ("dmar", USER_REGGROUP);
352 nds32_racr_reggroup = reggroup_new ("racr", USER_REGGROUP);
353 nds32_idr_reggroup = reggroup_new ("idr", USER_REGGROUP);
354 nds32_secur_reggroup = reggroup_new ("secur", USER_REGGROUP);
355}
356
357static void
358nds32_add_reggroups (struct gdbarch *gdbarch)
359{
360 /* Add pre-defined register groups. */
361 reggroup_add (gdbarch, general_reggroup);
362 reggroup_add (gdbarch, float_reggroup);
363 reggroup_add (gdbarch, system_reggroup);
364 reggroup_add (gdbarch, all_reggroup);
365 reggroup_add (gdbarch, save_reggroup);
366 reggroup_add (gdbarch, restore_reggroup);
367
368 /* Add NDS32 register groups. */
369 reggroup_add (gdbarch, nds32_cr_reggroup);
370 reggroup_add (gdbarch, nds32_ir_reggroup);
371 reggroup_add (gdbarch, nds32_mr_reggroup);
372 reggroup_add (gdbarch, nds32_dr_reggroup);
373 reggroup_add (gdbarch, nds32_pfr_reggroup);
374 reggroup_add (gdbarch, nds32_hspr_reggroup);
375 reggroup_add (gdbarch, nds32_dmar_reggroup);
376 reggroup_add (gdbarch, nds32_racr_reggroup);
377 reggroup_add (gdbarch, nds32_idr_reggroup);
378 reggroup_add (gdbarch, nds32_secur_reggroup);
379}
380
381/* Implement the "register_reggroup_p" gdbarch method. */
382
383static int
384nds32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
385 struct reggroup *reggroup)
386{
387 const char *reg_name;
388 const char *group_name;
389 int ret;
390
391 if (reggroup == all_reggroup)
392 return 1;
393
394 /* General reggroup contains only GPRs and PC. */
395 if (reggroup == general_reggroup)
396 return regnum <= NDS32_PC_REGNUM;
397
398 if (reggroup == float_reggroup || reggroup == save_reggroup
399 || reggroup == restore_reggroup)
400 {
401 ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
402 if (ret != -1)
403 return ret;
404
405 return default_register_reggroup_p (gdbarch, regnum, reggroup);
406 }
407
408 if (reggroup == system_reggroup)
409 return (regnum > NDS32_PC_REGNUM)
410 && !nds32_register_reggroup_p (gdbarch, regnum, float_reggroup);
411
412 /* The NDS32 reggroup contains registers whose name is prefixed
413 by reggroup name. */
414 reg_name = gdbarch_register_name (gdbarch, regnum);
415 group_name = reggroup_name (reggroup);
416 return !strncmp (reg_name, group_name, strlen (group_name));
417}
418\f
419/* Implement the "pseudo_register_type" tdesc_arch_data method. */
420
421static struct type *
422nds32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
423{
424 regnum -= gdbarch_num_regs (gdbarch);
425
426 /* Currently, only FSRs could be defined as pseudo registers. */
427 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
428 return arch_float_type (gdbarch, -1, "builtin_type_ieee_single",
429 floatformats_ieee_single);
430
431 warning (_("Unknown nds32 pseudo register %d."), regnum);
432 return NULL;
433}
434
435/* Implement the "pseudo_register_name" tdesc_arch_data method. */
436
437static const char *
438nds32_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
439{
440 regnum -= gdbarch_num_regs (gdbarch);
441
442 /* Currently, only FSRs could be defined as pseudo registers. */
443 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
444 return nds32_fsr_register_names[regnum];
445
446 warning (_("Unknown nds32 pseudo register %d."), regnum);
447 return NULL;
448}
449
450/* Implement the "pseudo_register_read" gdbarch method. */
451
452static enum register_status
453nds32_pseudo_register_read (struct gdbarch *gdbarch,
454 struct regcache *regcache, int regnum,
455 gdb_byte *buf)
456{
457 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
458 gdb_byte reg_buf[8];
459 int offset, fdr_regnum;
460 enum register_status status = REG_UNKNOWN;
461
462 /* Sanity check. */
463 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
464 return status;
465
466 regnum -= gdbarch_num_regs (gdbarch);
467
468 /* Currently, only FSRs could be defined as pseudo registers. */
469 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
470 {
471 /* fs0 is always the most significant half of fd0. */
472 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
473 offset = (regnum & 1) ? 4 : 0;
474 else
475 offset = (regnum & 1) ? 0 : 4;
476
477 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
478 status = regcache_raw_read (regcache, fdr_regnum, reg_buf);
479 if (status == REG_VALID)
480 memcpy (buf, reg_buf + offset, 4);
481 }
482
483 return status;
484}
485
486/* Implement the "pseudo_register_write" gdbarch method. */
487
488static void
489nds32_pseudo_register_write (struct gdbarch *gdbarch,
490 struct regcache *regcache, int regnum,
491 const gdb_byte *buf)
492{
493 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
494 gdb_byte reg_buf[8];
495 int offset, fdr_regnum;
496
497 /* Sanity check. */
498 if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0)
499 return;
500
501 regnum -= gdbarch_num_regs (gdbarch);
502
503 /* Currently, only FSRs could be defined as pseudo registers. */
504 if (regnum < gdbarch_num_pseudo_regs (gdbarch))
505 {
506 /* fs0 is always the most significant half of fd0. */
507 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
508 offset = (regnum & 1) ? 4 : 0;
509 else
510 offset = (regnum & 1) ? 0 : 4;
511
512 fdr_regnum = NDS32_FD0_REGNUM + (regnum >> 1);
513 regcache_raw_read (regcache, fdr_regnum, reg_buf);
514 memcpy (reg_buf + offset, buf, 4);
515 regcache_raw_write (regcache, fdr_regnum, reg_buf);
516 }
517}
518\f
519/* Helper function for NDS32 ABI. Return true if FPRs can be used
520 to pass function arguments and return value. */
521
522static int
523nds32_abi_use_fpr (int elf_abi)
524{
525 return elf_abi == E_NDS_ABI_V2FP_PLUS;
526}
527
528/* Helper function for NDS32 ABI. Return true if GPRs and stack
529 can be used together to pass an argument. */
530
531static int
532nds32_abi_split (int elf_abi)
533{
534 return elf_abi == E_NDS_ABI_AABI;
535}
536
537#define NDS32_NUM_SAVED_REGS (NDS32_LP_REGNUM + 1)
538
539struct nds32_frame_cache
540{
541 /* The previous frame's inner most stack address. Used as this
542 frame ID's stack_addr. */
543 CORE_ADDR prev_sp;
544
545 /* The frame's base, optionally used by the high-level debug info. */
546 CORE_ADDR base;
547
548 /* During prologue analysis, keep how far the SP and FP have been offset
549 from the start of the stack frame (as defined by the previous frame's
550 stack pointer).
551 During epilogue analysis, keep how far the SP has been offset from the
552 current stack pointer. */
553 CORE_ADDR sp_offset;
554 CORE_ADDR fp_offset;
555
556 /* The address of the first instruction in this function. */
557 CORE_ADDR pc;
558
559 /* Saved registers. */
560 CORE_ADDR saved_regs[NDS32_NUM_SAVED_REGS];
561};
562
563/* Allocate and initialize a frame cache. */
564
565static struct nds32_frame_cache *
566nds32_alloc_frame_cache (void)
567{
568 struct nds32_frame_cache *cache;
569 int i;
570
571 cache = FRAME_OBSTACK_ZALLOC (struct nds32_frame_cache);
572
573 /* Initialize fp_offset to check if FP is set in prologue. */
574 cache->fp_offset = INVALID_OFFSET;
575
576 /* Saved registers. We initialize these to -1 since zero is a valid
577 offset. */
578 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
579 cache->saved_regs[i] = REG_UNAVAIL;
580
581 return cache;
582}
583
584/* Helper function for instructions used to push multiple words. */
585
586static void
587nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
588 int enable4)
589{
590 CORE_ADDR sp_offset = cache->sp_offset;
591 int i;
592
593 /* Check LP, GP, FP in enable4. */
594 for (i = 1; i <= 3; i++)
595 {
596 if ((enable4 >> i) & 0x1)
597 {
598 sp_offset += 4;
599 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
600 }
601 }
602
603 /* Skip case where re == rb == sp. */
604 if ((rb < REG_FP) && (re < REG_FP))
605 {
606 for (i = re; i >= rb; i--)
607 {
608 sp_offset += 4;
609 cache->saved_regs[i] = sp_offset;
610 }
611 }
612
613 /* For sp, update the offset. */
614 cache->sp_offset = sp_offset;
615}
616
617/* Analyze the instructions within the given address range. If CACHE
618 is non-NULL, fill it in. Return the first address beyond the given
619 address range. If CACHE is NULL, return the first address not
620 recognized as a prologue instruction. */
621
622static CORE_ADDR
623nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
624 CORE_ADDR limit_pc, struct nds32_frame_cache *cache)
625{
626 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
627 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
628 /* Current scanning status. */
629 int in_prologue_bb = 0;
630 int val_ta = 0;
631 uint32_t insn, insn_len;
632
633 for (; pc < limit_pc; pc += insn_len)
634 {
635 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
636
637 if ((insn & 0x80000000) == 0)
638 {
639 /* 32-bit instruction */
640 insn_len = 4;
641
642 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
643 {
644 /* addi $sp, $sp, imm15s */
645 int imm15s = N32_IMM15S (insn);
646
647 if (imm15s < 0)
648 {
649 if (cache != NULL)
650 cache->sp_offset += -imm15s;
651
652 in_prologue_bb = 1;
653 continue;
654 }
655 }
656 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
657 {
658 /* addi $fp, $sp, imm15s */
659 int imm15s = N32_IMM15S (insn);
660
661 if (imm15s > 0)
662 {
663 if (cache != NULL)
664 cache->fp_offset = cache->sp_offset - imm15s;
665
666 in_prologue_bb = 1;
667 continue;
668 }
669 }
670 else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
671 && N32_RA5 (insn) == REG_SP)
672 {
673 /* smw.adm Rb, [$sp], Re, enable4 */
674 if (cache != NULL)
675 nds32_push_multiple_words (cache, N32_RT5 (insn),
676 N32_RB5 (insn),
677 N32_LSMW_ENABLE4 (insn));
678 in_prologue_bb = 1;
679 continue;
680 }
681 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
682 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
683 {
684 /* add $sp, $sp, $ta */
685 /* add $sp, $ta, $sp */
686 if (val_ta < 0)
687 {
688 if (cache != NULL)
689 cache->sp_offset += -val_ta;
690
691 in_prologue_bb = 1;
692 continue;
693 }
694 }
695 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
696 {
697 /* movi $ta, imm20s */
698 if (cache != NULL)
699 val_ta = N32_IMM20S (insn);
700
701 continue;
702 }
703 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
704 {
705 /* sethi $ta, imm20u */
706 if (cache != NULL)
707 val_ta = N32_IMM20U (insn) << 12;
708
709 continue;
710 }
711 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
712 {
713 /* ori $ta, $ta, imm15u */
714 if (cache != NULL)
715 val_ta |= N32_IMM15U (insn);
716
717 continue;
718 }
719 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
720 {
721 /* addi $ta, $ta, imm15s */
722 if (cache != NULL)
723 val_ta += N32_IMM15S (insn);
724
725 continue;
726 }
727 if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
728 || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
729 {
730 /* add $gp, $ta, $gp */
731 /* add $gp, $gp, $ta */
732 in_prologue_bb = 1;
733 continue;
734 }
735 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
736 {
737 /* movi $gp, imm20s */
738 in_prologue_bb = 1;
739 continue;
740 }
741 else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
742 {
743 /* sethi $gp, imm20u */
744 in_prologue_bb = 1;
745 continue;
746 }
747 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
748 {
749 /* ori $gp, $gp, imm15u */
750 in_prologue_bb = 1;
751 continue;
752 }
753 else
754 {
755 /* Jump/Branch insns never appear in prologue basic block.
756 The loop can be escaped early when these insns are met. */
757 if (in_prologue_bb == 1)
758 {
759 int op = N32_OP6 (insn);
760
761 if (op == N32_OP6_JI
762 || op == N32_OP6_JREG
763 || op == N32_OP6_BR1
764 || op == N32_OP6_BR2
765 || op == N32_OP6_BR3)
766 break;
767 }
768 }
769
770 if (abi_use_fpr && N32_OP6 (insn) == N32_OP6_SDC
771 && __GF (insn, 12, 3) == 0)
772 {
773 /* For FPU insns, CP (bit [13:14]) should be CP0, and only
774 normal form (bit [12] == 0) is used. */
775
776 /* fsdi FDt, [$sp + (imm12s << 2)] */
777 if (N32_RA5 (insn) == REG_SP)
778 continue;
779 }
780
781 /* The optimizer might shove anything into the prologue, if
782 we build up cache (cache != NULL) from analyzing prologue,
783 we just skip what we don't recognize and analyze further to
784 make cache as complete as possible. However, if we skip
785 prologue, we'll stop immediately on unrecognized
786 instruction. */
787 if (cache == NULL)
788 break;
789 }
790 else
791 {
792 /* 16-bit instruction */
793 insn_len = 2;
794
795 insn >>= 16;
796
797 if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
798 {
799 /* addi10s.sp */
800 int imm10s = N16_IMM10S (insn);
801
802 if (imm10s < 0)
803 {
804 if (cache != NULL)
805 cache->sp_offset += -imm10s;
806
807 in_prologue_bb = 1;
808 continue;
809 }
810 }
811 else if (__GF (insn, 7, 8) == N16_T25_PUSH25)
812 {
813 /* push25 */
814 if (cache != NULL)
815 {
816 int imm8u = (insn & 0x1f) << 3;
817 int re = (insn >> 5) & 0x3;
818 const int reg_map[] = { 6, 8, 10, 14 };
819
820 /* Operation 1 -- smw.adm R6, [$sp], Re, #0xe */
821 nds32_push_multiple_words (cache, 6, reg_map[re], 0xe);
822
823 /* Operation 2 -- sp = sp - (imm5u << 3) */
824 cache->sp_offset += imm8u;
825 }
826
827 in_prologue_bb = 1;
828 continue;
829 }
830 else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
831 {
832 /* add5.pc $gp */
833 in_prologue_bb = 1;
834 continue;
835 }
836 else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
837 {
838 /* movi55 $gp, imm5s */
839 in_prologue_bb = 1;
840 continue;
841 }
842 else
843 {
844 /* Jump/Branch insns never appear in prologue basic block.
845 The loop can be escaped early when these insns are met. */
846 if (in_prologue_bb == 1)
847 {
848 uint32_t insn5 = CHOP_BITS (insn, 5);
849 uint32_t insn8 = CHOP_BITS (insn, 8);
850 uint32_t insn38 = CHOP_BITS (insn, 11);
851
852 if (insn5 == N16_TYPE5 (JR5, 0)
853 || insn5 == N16_TYPE5 (JRAL5, 0)
854 || insn5 == N16_TYPE5 (RET5, 0)
855 || insn8 == N16_TYPE8 (J8, 0)
856 || insn8 == N16_TYPE8 (BEQZS8, 0)
857 || insn8 == N16_TYPE8 (BNEZS8, 0)
858 || insn38 == N16_TYPE38 (BEQZ38, 0, 0)
859 || insn38 == N16_TYPE38 (BNEZ38, 0, 0)
860 || insn38 == N16_TYPE38 (BEQS38, 0, 0)
861 || insn38 == N16_TYPE38 (BNES38, 0, 0))
862 break;
863 }
864 }
865
866 /* The optimizer might shove anything into the prologue, if
867 we build up cache (cache != NULL) from analyzing prologue,
868 we just skip what we don't recognize and analyze further to
869 make cache as complete as possible. However, if we skip
870 prologue, we'll stop immediately on unrecognized
871 instruction. */
872 if (cache == NULL)
873 break;
874 }
875 }
876
877 return pc;
878}
879
880/* Implement the "skip_prologue" gdbarch method.
881
882 Find the end of function prologue. */
883
884static CORE_ADDR
885nds32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
886{
887 CORE_ADDR func_addr, limit_pc;
888
889 /* See if we can determine the end of the prologue via the symbol table.
890 If so, then return either PC, or the PC after the prologue, whichever
891 is greater. */
892 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
893 {
894 CORE_ADDR post_prologue_pc
895 = skip_prologue_using_sal (gdbarch, func_addr);
896 if (post_prologue_pc != 0)
897 return max (pc, post_prologue_pc);
898 }
899
900 /* Can't determine prologue from the symbol table, need to examine
901 instructions. */
902
903 /* Find an upper limit on the function prologue using the debug
904 information. If the debug information could not be used to provide
905 that bound, then use an arbitrary large number as the upper bound. */
906 limit_pc = skip_prologue_using_sal (gdbarch, pc);
907 if (limit_pc == 0)
908 limit_pc = pc + 128; /* Magic. */
909
910 /* Find the end of prologue. */
911 return nds32_analyze_prologue (gdbarch, pc, limit_pc, NULL);
912}
913
914/* Allocate and fill in *THIS_CACHE with information about the prologue of
915 *THIS_FRAME. Do not do this if *THIS_CACHE was already allocated. Return
916 a pointer to the current nds32_frame_cache in *THIS_CACHE. */
917
918static struct nds32_frame_cache *
919nds32_frame_cache (struct frame_info *this_frame, void **this_cache)
920{
921 struct gdbarch *gdbarch = get_frame_arch (this_frame);
922 struct nds32_frame_cache *cache;
923 CORE_ADDR current_pc;
924 ULONGEST prev_sp;
925 ULONGEST this_base;
926 int i;
927
928 if (*this_cache)
929 return (struct nds32_frame_cache *) *this_cache;
930
931 cache = nds32_alloc_frame_cache ();
932 *this_cache = cache;
933
934 cache->pc = get_frame_func (this_frame);
935 current_pc = get_frame_pc (this_frame);
936 nds32_analyze_prologue (gdbarch, cache->pc, current_pc, cache);
937
938 /* Compute the previous frame's stack pointer (which is also the
939 frame's ID's stack address), and this frame's base pointer. */
940 if (cache->fp_offset != INVALID_OFFSET)
941 {
942 /* FP is set in prologue, so it can be used to calculate other info. */
943 this_base = get_frame_register_unsigned (this_frame, NDS32_FP_REGNUM);
944 prev_sp = this_base + cache->fp_offset;
945 }
946 else
947 {
948 this_base = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
949 prev_sp = this_base + cache->sp_offset;
950 }
951
952 cache->prev_sp = prev_sp;
953 cache->base = this_base;
954
955 /* Adjust all the saved registers such that they contain addresses
956 instead of offsets. */
957 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
958 if (cache->saved_regs[i] != REG_UNAVAIL)
959 cache->saved_regs[i] = cache->prev_sp - cache->saved_regs[i];
960
961 return cache;
962}
963
964/* Implement the "this_id" frame_unwind method.
965
966 Our frame ID for a normal frame is the current function's starting
967 PC and the caller's SP when we were called. */
968
969static void
970nds32_frame_this_id (struct frame_info *this_frame,
971 void **this_cache, struct frame_id *this_id)
972{
973 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
974
975 /* This marks the outermost frame. */
976 if (cache->prev_sp == 0)
977 return;
978
979 *this_id = frame_id_build (cache->prev_sp, cache->pc);
980}
981
982/* Implement the "prev_register" frame_unwind method. */
983
984static struct value *
985nds32_frame_prev_register (struct frame_info *this_frame, void **this_cache,
986 int regnum)
987{
988 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
989
990 if (regnum == NDS32_SP_REGNUM)
991 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
992
993 /* The PC of the previous frame is stored in the LP register of
994 the current frame. */
995 if (regnum == NDS32_PC_REGNUM)
996 regnum = NDS32_LP_REGNUM;
997
998 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
999 return frame_unwind_got_memory (this_frame, regnum,
1000 cache->saved_regs[regnum]);
1001
1002 return frame_unwind_got_register (this_frame, regnum, regnum);
1003}
1004
1005static const struct frame_unwind nds32_frame_unwind =
1006{
1007 NORMAL_FRAME,
1008 default_frame_unwind_stop_reason,
1009 nds32_frame_this_id,
1010 nds32_frame_prev_register,
1011 NULL,
1012 default_frame_sniffer,
1013};
1014
1015/* Return the frame base address of *THIS_FRAME. */
1016
1017static CORE_ADDR
1018nds32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1019{
1020 struct nds32_frame_cache *cache = nds32_frame_cache (this_frame, this_cache);
1021
1022 return cache->base;
1023}
1024
1025static const struct frame_base nds32_frame_base =
1026{
1027 &nds32_frame_unwind,
1028 nds32_frame_base_address,
1029 nds32_frame_base_address,
1030 nds32_frame_base_address
1031};
1032\f
1033/* Helper function for instructions used to pop multiple words. */
1034
1035static void
1036nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
1037 int enable4)
1038{
1039 CORE_ADDR sp_offset = cache->sp_offset;
1040 int i;
1041
1042 /* Skip case where re == rb == sp. */
1043 if ((rb < REG_FP) && (re < REG_FP))
1044 {
1045 for (i = rb; i <= re; i++)
1046 {
1047 cache->saved_regs[i] = sp_offset;
1048 sp_offset += 4;
1049 }
1050 }
1051
1052 /* Check FP, GP, LP in enable4. */
1053 for (i = 3; i >= 1; i--)
1054 {
1055 if ((enable4 >> i) & 0x1)
1056 {
1057 cache->saved_regs[NDS32_SP_REGNUM - i] = sp_offset;
1058 sp_offset += 4;
1059 }
1060 }
1061
1062 /* For sp, update the offset. */
1063 cache->sp_offset = sp_offset;
1064}
1065
1066/* The instruction sequences in NDS32 epilogue are
1067
1068 INSN_RESET_SP (optional)
1069 (If exists, this must be the first instruction in epilogue
1070 and the stack has not been destroyed.).
1071 INSN_RECOVER (optional).
1072 INSN_RETURN/INSN_RECOVER_RETURN (required). */
1073
1074/* Helper function for analyzing the given 32-bit INSN. If CACHE is non-NULL,
1075 the necessary information will be recorded. */
1076
1077static inline int
1078nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
1079 struct nds32_frame_cache *cache)
1080{
1081 if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
1082 && N32_IMM15S (insn) > 0)
1083 /* addi $sp, $sp, imm15s */
1084 return INSN_RESET_SP;
1085 else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
1086 && N32_IMM15S (insn) < 0)
1087 /* addi $sp, $fp, imm15s */
1088 return INSN_RESET_SP;
1089 else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
1090 && N32_RA5 (insn) == REG_SP)
1091 {
1092 /* lmw.bim Rb, [$sp], Re, enable4 */
1093 if (cache != NULL)
1094 nds32_pop_multiple_words (cache, N32_RT5 (insn),
1095 N32_RB5 (insn), N32_LSMW_ENABLE4 (insn));
1096
1097 return INSN_RECOVER;
1098 }
1099 else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
1100 /* ret $lp */
1101 return INSN_RETURN;
1102 else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
1103 || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
1104 /* add $sp, $sp, $ta */
1105 /* add $sp, $ta, $sp */
1106 return INSN_RESET_SP;
1107 else if (abi_use_fpr
1108 && (insn & ~(__MASK (5) << 20 | __MASK (13))) == N32_FLDI_SP)
1109 {
1110 if (__GF (insn, 12, 1) == 0)
1111 /* fldi FDt, [$sp + (imm12s << 2)] */
1112 return INSN_RECOVER;
1113 else
1114 {
1115 /* fldi.bi FDt, [$sp], (imm12s << 2) */
1116 int offset = N32_IMM12S (insn) << 2;
1117
1118 if (offset == 8 || offset == 12)
1119 {
1120 if (cache != NULL)
1121 cache->sp_offset += offset;
1122
1123 return INSN_RECOVER;
1124 }
1125 }
1126 }
1127
1128 return INSN_NORMAL;
1129}
1130
1131/* Helper function for analyzing the given 16-bit INSN. If CACHE is non-NULL,
1132 the necessary information will be recorded. */
1133
1134static inline int
1135nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
1136{
1137 if (insn == N16_TYPE5 (RET5, REG_LP))
1138 /* ret5 $lp */
1139 return INSN_RETURN;
1140 else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
1141 {
1142 /* addi10s.sp */
1143 int imm10s = N16_IMM10S (insn);
1144
1145 if (imm10s > 0)
1146 {
1147 if (cache != NULL)
1148 cache->sp_offset += imm10s;
1149
1150 return INSN_RECOVER;
1151 }
1152 }
1153 else if (__GF (insn, 7, 8) == N16_T25_POP25)
1154 {
1155 /* pop25 */
1156 if (cache != NULL)
1157 {
1158 int imm8u = (insn & 0x1f) << 3;
1159 int re = (insn >> 5) & 0x3;
1160 const int reg_map[] = { 6, 8, 10, 14 };
1161
1162 /* Operation 1 -- sp = sp + (imm5u << 3) */
1163 cache->sp_offset += imm8u;
1164
1165 /* Operation 2 -- lmw.bim R6, [$sp], Re, #0xe */
1166 nds32_pop_multiple_words (cache, 6, reg_map[re], 0xe);
1167 }
1168
1169 /* Operation 3 -- ret $lp */
1170 return INSN_RECOVER_RETURN;
1171 }
1172
1173 return INSN_NORMAL;
1174}
1175
1176/* Analyze a reasonable amount of instructions from the given PC to find
1177 the instruction used to return to the caller. Return 1 if the 'return'
1178 instruction could be found, 0 otherwise.
1179
1180 If CACHE is non-NULL, fill it in. */
1181
1182static int
1183nds32_analyze_epilogue (struct gdbarch *gdbarch, CORE_ADDR pc,
1184 struct nds32_frame_cache *cache)
1185{
1186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1187 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1188 CORE_ADDR limit_pc;
1189 uint32_t insn, insn_len;
1190 int insn_type = INSN_NORMAL;
1191
1192 if (abi_use_fpr)
1193 limit_pc = pc + 48;
1194 else
1195 limit_pc = pc + 16;
1196
1197 for (; pc < limit_pc; pc += insn_len)
1198 {
1199 insn = read_memory_unsigned_integer (pc, 4, BFD_ENDIAN_BIG);
1200
1201 if ((insn & 0x80000000) == 0)
1202 {
1203 /* 32-bit instruction */
1204 insn_len = 4;
1205
1206 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, cache);
1207 if (insn_type == INSN_RETURN)
1208 return 1;
1209 else if (insn_type == INSN_RECOVER)
1210 continue;
1211 }
1212 else
1213 {
1214 /* 16-bit instruction */
1215 insn_len = 2;
1216
1217 insn >>= 16;
1218 insn_type = nds32_analyze_epilogue_insn16 (insn, cache);
1219 if (insn_type == INSN_RETURN || insn_type == INSN_RECOVER_RETURN)
1220 return 1;
1221 else if (insn_type == INSN_RECOVER)
1222 continue;
1223 }
1224
1225 /* Stop the scan if this is an unexpected instruction. */
1226 break;
1227 }
1228
1229 return 0;
1230}
1231
1232/* Implement the "stack_frame_destroyed_p" gdbarch method. */
1233
1234static int
1235nds32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR addr)
1236{
1237 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1238 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1239 int insn_type = INSN_NORMAL;
1240 int ret_found = 0;
1241 uint32_t insn;
1242
1243 insn = read_memory_unsigned_integer (addr, 4, BFD_ENDIAN_BIG);
1244
1245 if ((insn & 0x80000000) == 0)
1246 {
1247 /* 32-bit instruction */
1248
1249 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1250 }
1251 else
1252 {
1253 /* 16-bit instruction */
1254
1255 insn >>= 16;
1256 insn_type = nds32_analyze_epilogue_insn16 (insn, NULL);
1257 }
1258
1259 if (insn_type == INSN_NORMAL || insn_type == INSN_RESET_SP)
1260 return 0;
1261
1262 /* Search the required 'return' instruction within the following reasonable
1263 instructions. */
1264 ret_found = nds32_analyze_epilogue (gdbarch, addr, NULL);
1265 if (ret_found == 0)
1266 return 0;
1267
1268 /* Scan backwards to make sure that the last instruction has adjusted
1269 stack. Both a 16-bit and a 32-bit instruction will be tried. This is
1270 just a heuristic, so the false positives will be acceptable. */
1271 insn = read_memory_unsigned_integer (addr - 2, 4, BFD_ENDIAN_BIG);
1272
1273 /* Only 16-bit instructions are possible at addr - 2. */
1274 if ((insn & 0x80000000) != 0)
1275 {
1276 /* This may be a 16-bit instruction or part of a 32-bit instruction. */
1277
1278 insn_type = nds32_analyze_epilogue_insn16 (insn >> 16, NULL);
1279 if (insn_type == INSN_RECOVER)
1280 return 1;
1281 }
1282
1283 insn = read_memory_unsigned_integer (addr - 4, 4, BFD_ENDIAN_BIG);
1284
1285 /* If this is a 16-bit instruction at addr - 4, then there must be another
1286 16-bit instruction at addr - 2, so only 32-bit instructions need to
1287 be analyzed here. */
1288 if ((insn & 0x80000000) == 0)
1289 {
1290 /* This may be a 32-bit instruction or part of a 32-bit instruction. */
1291
1292 insn_type = nds32_analyze_epilogue_insn32 (abi_use_fpr, insn, NULL);
1293 if (insn_type == INSN_RECOVER || insn_type == INSN_RESET_SP)
1294 return 1;
1295 }
1296
1297 return 0;
1298}
1299
1300/* Implement the "sniffer" frame_unwind method. */
1301
1302static int
1303nds32_epilogue_frame_sniffer (const struct frame_unwind *self,
1304 struct frame_info *this_frame, void **this_cache)
1305{
1306 if (frame_relative_level (this_frame) == 0)
1307 return nds32_stack_frame_destroyed_p (get_frame_arch (this_frame),
1308 get_frame_pc (this_frame));
1309 else
1310 return 0;
1311}
1312
1313/* Allocate and fill in *THIS_CACHE with information needed to unwind
1314 *THIS_FRAME within epilogue. Do not do this if *THIS_CACHE was already
1315 allocated. Return a pointer to the current nds32_frame_cache in
1316 *THIS_CACHE. */
1317
1318static struct nds32_frame_cache *
1319nds32_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
1320{
1321 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1322 struct nds32_frame_cache *cache;
1323 CORE_ADDR current_pc, current_sp;
1324 int i;
1325
1326 if (*this_cache)
1327 return (struct nds32_frame_cache *) *this_cache;
1328
1329 cache = nds32_alloc_frame_cache ();
1330 *this_cache = cache;
1331
1332 cache->pc = get_frame_func (this_frame);
1333 current_pc = get_frame_pc (this_frame);
1334 nds32_analyze_epilogue (gdbarch, current_pc, cache);
1335
1336 current_sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1337 cache->prev_sp = current_sp + cache->sp_offset;
1338
1339 /* Adjust all the saved registers such that they contain addresses
1340 instead of offsets. */
1341 for (i = 0; i < NDS32_NUM_SAVED_REGS; i++)
1342 if (cache->saved_regs[i] != REG_UNAVAIL)
1343 cache->saved_regs[i] = current_sp + cache->saved_regs[i];
1344
1345 return cache;
1346}
1347
1348/* Implement the "this_id" frame_unwind method. */
1349
1350static void
1351nds32_epilogue_frame_this_id (struct frame_info *this_frame,
1352 void **this_cache, struct frame_id *this_id)
1353{
1354 struct nds32_frame_cache *cache
1355 = nds32_epilogue_frame_cache (this_frame, this_cache);
1356
1357 /* This marks the outermost frame. */
1358 if (cache->prev_sp == 0)
1359 return;
1360
1361 *this_id = frame_id_build (cache->prev_sp, cache->pc);
1362}
1363
1364/* Implement the "prev_register" frame_unwind method. */
1365
1366static struct value *
1367nds32_epilogue_frame_prev_register (struct frame_info *this_frame,
1368 void **this_cache, int regnum)
1369{
1370 struct nds32_frame_cache *cache
1371 = nds32_epilogue_frame_cache (this_frame, this_cache);
1372
1373 if (regnum == NDS32_SP_REGNUM)
1374 return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp);
1375
1376 /* The PC of the previous frame is stored in the LP register of
1377 the current frame. */
1378 if (regnum == NDS32_PC_REGNUM)
1379 regnum = NDS32_LP_REGNUM;
1380
1381 if (regnum < NDS32_NUM_SAVED_REGS && cache->saved_regs[regnum] != REG_UNAVAIL)
1382 return frame_unwind_got_memory (this_frame, regnum,
1383 cache->saved_regs[regnum]);
1384
1385 return frame_unwind_got_register (this_frame, regnum, regnum);
1386}
1387
1388static const struct frame_unwind nds32_epilogue_frame_unwind =
1389{
1390 NORMAL_FRAME,
1391 default_frame_unwind_stop_reason,
1392 nds32_epilogue_frame_this_id,
1393 nds32_epilogue_frame_prev_register,
1394 NULL,
1395 nds32_epilogue_frame_sniffer
1396};
1397\f
1398/* Implement the "dummy_id" gdbarch method. */
1399
1400static struct frame_id
1401nds32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1402{
1403 CORE_ADDR sp = get_frame_register_unsigned (this_frame, NDS32_SP_REGNUM);
1404
1405 return frame_id_build (sp, get_frame_pc (this_frame));
1406}
1407
1408/* Implement the "unwind_pc" gdbarch method. */
1409
1410static CORE_ADDR
1411nds32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1412{
1413 return frame_unwind_register_unsigned (next_frame, NDS32_PC_REGNUM);
1414}
1415
1416/* Implement the "unwind_sp" gdbarch method. */
1417
1418static CORE_ADDR
1419nds32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1420{
1421 return frame_unwind_register_unsigned (next_frame, NDS32_SP_REGNUM);
1422}
1423\f
1424/* Floating type and struct type that has only one floating type member
1425 can pass value using FPU registers (when FPU ABI is used). */
1426
1427static int
1428nds32_check_calling_use_fpr (struct type *type)
1429{
1430 struct type *t;
1431 enum type_code typecode;
1432
1433 t = type;
1434 while (1)
1435 {
1436 t = check_typedef (t);
1437 typecode = TYPE_CODE (t);
1438 if (typecode != TYPE_CODE_STRUCT)
1439 break;
1440 else if (TYPE_NFIELDS (t) != 1)
1441 return 0;
1442 else
1443 t = TYPE_FIELD_TYPE (t, 0);
1444 }
1445
1446 return typecode == TYPE_CODE_FLT;
1447}
1448
1449/* Return the alignment (in bytes) of the given type. */
1450
1451static int
1452nds32_type_align (struct type *type)
1453{
1454 int n;
1455 int align;
1456 int falign;
1457
1458 type = check_typedef (type);
1459 switch (TYPE_CODE (type))
1460 {
1461 default:
1462 /* Should never happen. */
1463 internal_error (__FILE__, __LINE__, _("unknown type alignment"));
1464 return 4;
1465
1466 case TYPE_CODE_PTR:
1467 case TYPE_CODE_ENUM:
1468 case TYPE_CODE_INT:
1469 case TYPE_CODE_FLT:
1470 case TYPE_CODE_SET:
1471 case TYPE_CODE_RANGE:
1472 case TYPE_CODE_REF:
1473 case TYPE_CODE_CHAR:
1474 case TYPE_CODE_BOOL:
1475 return TYPE_LENGTH (type);
1476
1477 case TYPE_CODE_ARRAY:
1478 case TYPE_CODE_COMPLEX:
1479 return nds32_type_align (TYPE_TARGET_TYPE (type));
1480
1481 case TYPE_CODE_STRUCT:
1482 case TYPE_CODE_UNION:
1483 align = 1;
1484 for (n = 0; n < TYPE_NFIELDS (type); n++)
1485 {
1486 falign = nds32_type_align (TYPE_FIELD_TYPE (type, n));
1487 if (falign > align)
1488 align = falign;
1489 }
1490 return align;
1491 }
1492}
1493
1494/* Implement the "push_dummy_call" gdbarch method. */
1495
1496static CORE_ADDR
1497nds32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1498 struct regcache *regcache, CORE_ADDR bp_addr,
1499 int nargs, struct value **args, CORE_ADDR sp,
1500 int struct_return, CORE_ADDR struct_addr)
1501{
1502 const int REND = 6; /* End for register offset. */
1503 int goff = 0; /* Current gpr offset for argument. */
1504 int foff = 0; /* Current fpr offset for argument. */
1505 int soff = 0; /* Current stack offset for argument. */
1506 int i;
1507 ULONGEST regval;
1508 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1509 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1510 struct type *func_type = value_type (function);
1511 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1512 int abi_split = nds32_abi_split (tdep->elf_abi);
1513
1514 /* Set the return address. For the NDS32, the return breakpoint is
1515 always at BP_ADDR. */
1516 regcache_cooked_write_unsigned (regcache, NDS32_LP_REGNUM, bp_addr);
1517
1518 /* If STRUCT_RETURN is true, then the struct return address (in
1519 STRUCT_ADDR) will consume the first argument-passing register.
1520 Both adjust the register count and store that value. */
1521 if (struct_return)
1522 {
1523 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, struct_addr);
1524 goff++;
1525 }
1526
1527 /* Now make sure there's space on the stack */
1528 for (i = 0; i < nargs; i++)
1529 {
1530 struct type *type = value_type (args[i]);
1531 int align = nds32_type_align (type);
1532
1533 /* If align is zero, it may be an empty struct.
1534 Just ignore the argument of empty struct. */
1535 if (align == 0)
1536 continue;
1537
1538 sp -= TYPE_LENGTH (type);
1539 sp = align_down (sp, align);
1540 }
1541
1542 /* Stack must be 8-byte aligned. */
1543 sp = align_down (sp, 8);
1544
1545 soff = 0;
1546 for (i = 0; i < nargs; i++)
1547 {
1548 const gdb_byte *val;
1549 int align, len;
1550 struct type *type;
1551 int calling_use_fpr;
1552 int use_fpr = 0;
1553
1554 type = value_type (args[i]);
1555 calling_use_fpr = nds32_check_calling_use_fpr (type);
1556 len = TYPE_LENGTH (type);
1557 align = nds32_type_align (type);
1558 val = value_contents (args[i]);
1559
1560 /* The size of a composite type larger than 4 bytes will be rounded
1561 up to the nearest multiple of 4. */
1562 if (len > 4)
1563 len = align_up (len, 4);
1564
1565 /* Variadic functions are handled differently between AABI and ABI2FP+.
1566
1567 For AABI, the caller pushes arguments in registers, callee stores
1568 unnamed arguments in stack, and then va_arg fetch arguments in stack.
1569 Therefore, we don't have to handle variadic functions specially.
1570
1571 For ABI2FP+, the caller pushes only named arguments in registers
1572 and pushes all unnamed arguments in stack. */
1573
1574 if (abi_use_fpr && TYPE_VARARGS (func_type)
1575 && i >= TYPE_NFIELDS (func_type))
1576 goto use_stack;
1577
1578 /* Try to use FPRs to pass arguments only when
1579 1. The program is built using toolchain with FPU support.
1580 2. The type of this argument can use FPR to pass value. */
1581 use_fpr = abi_use_fpr && calling_use_fpr;
1582
1583 if (use_fpr)
1584 {
1585 if (tdep->fpu_freg == -1)
1586 goto error_no_fpr;
1587
1588 /* Adjust alignment. */
1589 if ((align >> 2) > 0)
1590 foff = align_up (foff, align >> 2);
1591
1592 if (foff < REND)
1593 {
1594 switch (len)
1595 {
1596 case 4:
1597 regcache_cooked_write (regcache,
1598 tdep->fs0_regnum + foff, val);
1599 foff++;
1600 break;
1601 case 8:
1602 regcache_cooked_write (regcache,
1603 NDS32_FD0_REGNUM + (foff >> 1), val);
1604 foff += 2;
1605 break;
1606 default:
1607 /* Long double? */
1608 internal_error (__FILE__, __LINE__,
1609 "Do not know how to handle %d-byte double.\n",
1610 len);
1611 break;
1612 }
1613 continue;
1614 }
1615 }
1616 else
1617 {
1618 /*
1619 When passing arguments using GPRs,
1620
1621 * A composite type not larger than 4 bytes is passed in $rN.
1622 The format is as if the value is loaded with load instruction
1623 of corresponding size (e.g., LB, LH, LW).
1624
1625 For example,
1626
1627 r0
1628 31 0
1629 LITTLE: [x x b a]
1630 BIG: [x x a b]
1631
1632 * Otherwise, a composite type is passed in consecutive registers.
1633 The size is rounded up to the nearest multiple of 4.
1634 The successive registers hold the parts of the argument as if
1635 were loaded using lmw instructions.
1636
1637 For example,
1638
1639 r0 r1
1640 31 0 31 0
1641 LITTLE: [d c b a] [x x x e]
1642 BIG: [a b c d] [e x x x]
1643 */
1644
1645 /* Adjust alignment. */
1646 if ((align >> 2) > 0)
1647 goff = align_up (goff, align >> 2);
1648
1649 if (len <= (REND - goff) * 4)
1650 {
1651 /* This argument can be passed wholly via GPRs. */
1652 while (len > 0)
1653 {
1654 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1655 byte_order);
1656 regcache_cooked_write_unsigned (regcache,
1657 NDS32_R0_REGNUM + goff,
1658 regval);
1659 len -= 4;
1660 val += 4;
1661 goff++;
1662 }
1663 continue;
1664 }
1665 else if (abi_split)
1666 {
1667 /* Some parts of this argument can be passed via GPRs. */
1668 while (goff < REND)
1669 {
1670 regval = extract_unsigned_integer (val, (len > 4) ? 4 : len,
1671 byte_order);
1672 regcache_cooked_write_unsigned (regcache,
1673 NDS32_R0_REGNUM + goff,
1674 regval);
1675 len -= 4;
1676 val += 4;
1677 goff++;
1678 }
1679 }
1680 }
1681
1682use_stack:
1683 /*
1684 When pushing (split parts of) an argument into stack,
1685
1686 * A composite type not larger than 4 bytes is copied to different
1687 base address.
1688 In little-endian, the first byte of this argument is aligned
1689 at the low address of the next free word.
1690 In big-endian, the last byte of this argument is aligned
1691 at the high address of the next free word.
1692
1693 For example,
1694
1695 sp [ - ] [ c ] hi
1696 [ c ] [ b ]
1697 [ b ] [ a ]
1698 [ a ] [ - ] lo
1699 LITTLE BIG
1700 */
1701
1702 /* Adjust alignment. */
1703 soff = align_up (soff, align);
1704
1705 while (len > 0)
1706 {
1707 int rlen = (len > 4) ? 4 : len;
1708
1709 if (byte_order == BFD_ENDIAN_BIG)
1710 write_memory (sp + soff + 4 - rlen, val, rlen);
1711 else
1712 write_memory (sp + soff, val, rlen);
1713
1714 len -= 4;
1715 val += 4;
1716 soff += 4;
1717 }
1718 }
1719
1720 /* Finally, update the SP register. */
1721 regcache_cooked_write_unsigned (regcache, NDS32_SP_REGNUM, sp);
1722
1723 return sp;
1724
1725error_no_fpr:
1726 /* If use_fpr, but no floating-point register exists,
1727 then it is an error. */
1728 error (_("Fail to call. FPU registers are required."));
1729}
1730\f
1731/* Read, for architecture GDBARCH, a function return value of TYPE
1732 from REGCACHE, and copy that into VALBUF. */
1733
1734static void
1735nds32_extract_return_value (struct gdbarch *gdbarch, struct type *type,
1736 struct regcache *regcache, gdb_byte *valbuf)
1737{
1738 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1739 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1740 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1741 int calling_use_fpr;
1742 int len;
1743
1744 calling_use_fpr = nds32_check_calling_use_fpr (type);
1745 len = TYPE_LENGTH (type);
1746
1747 if (abi_use_fpr && calling_use_fpr)
1748 {
1749 if (len == 4)
1750 regcache_cooked_read (regcache, tdep->fs0_regnum, valbuf);
1751 else if (len == 8)
1752 regcache_cooked_read (regcache, NDS32_FD0_REGNUM, valbuf);
1753 else
1754 internal_error (__FILE__, __LINE__,
1755 _("Cannot extract return value of %d bytes "
1756 "long floating-point."), len);
1757 }
1758 else
1759 {
1760 /*
1761 When returning result,
1762
1763 * A composite type not larger than 4 bytes is returned in $r0.
1764 The format is as if the result is loaded with load instruction
1765 of corresponding size (e.g., LB, LH, LW).
1766
1767 For example,
1768
1769 r0
1770 31 0
1771 LITTLE: [x x b a]
1772 BIG: [x x a b]
1773
1774 * Otherwise, a composite type not larger than 8 bytes is returned
1775 in $r0 and $r1.
1776 In little-endian, the first word is loaded in $r0.
1777 In big-endian, the last word is loaded in $r1.
1778
1779 For example,
1780
1781 r0 r1
1782 31 0 31 0
1783 LITTLE: [d c b a] [x x x e]
1784 BIG: [x x x a] [b c d e]
1785 */
1786
1787 ULONGEST tmp;
1788
1789 if (len < 4)
1790 {
1791 /* By using store_unsigned_integer we avoid having to do
1792 anything special for small big-endian values. */
1793 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1794 store_unsigned_integer (valbuf, len, byte_order, tmp);
1795 }
1796 else if (len == 4)
1797 {
1798 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1799 }
1800 else if (len < 8)
1801 {
1802 int len1, len2;
1803
1804 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1805 len2 = len - len1;
1806
1807 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM, &tmp);
1808 store_unsigned_integer (valbuf, len1, byte_order, tmp);
1809
1810 regcache_cooked_read_unsigned (regcache, NDS32_R0_REGNUM + 1, &tmp);
1811 store_unsigned_integer (valbuf + len1, len2, byte_order, tmp);
1812 }
1813 else
1814 {
1815 regcache_cooked_read (regcache, NDS32_R0_REGNUM, valbuf);
1816 regcache_cooked_read (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1817 }
1818 }
1819}
1820
1821/* Write, for architecture GDBARCH, a function return value of TYPE
1822 from VALBUF into REGCACHE. */
1823
1824static void
1825nds32_store_return_value (struct gdbarch *gdbarch, struct type *type,
1826 struct regcache *regcache, const gdb_byte *valbuf)
1827{
1828 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1829 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1830 int abi_use_fpr = nds32_abi_use_fpr (tdep->elf_abi);
1831 int calling_use_fpr;
1832 int len;
1833
1834 calling_use_fpr = nds32_check_calling_use_fpr (type);
1835 len = TYPE_LENGTH (type);
1836
1837 if (abi_use_fpr && calling_use_fpr)
1838 {
1839 if (len == 4)
1840 regcache_cooked_write (regcache, tdep->fs0_regnum, valbuf);
1841 else if (len == 8)
1842 regcache_cooked_write (regcache, NDS32_FD0_REGNUM, valbuf);
1843 else
1844 internal_error (__FILE__, __LINE__,
1845 _("Cannot store return value of %d bytes "
1846 "long floating-point."), len);
1847 }
1848 else
1849 {
1850 ULONGEST regval;
1851
1852 if (len < 4)
1853 {
1854 regval = extract_unsigned_integer (valbuf, len, byte_order);
1855 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1856 }
1857 else if (len == 4)
1858 {
1859 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1860 }
1861 else if (len < 8)
1862 {
1863 int len1, len2;
1864
1865 len1 = byte_order == BFD_ENDIAN_BIG ? len - 4 : 4;
1866 len2 = len - len1;
1867
1868 regval = extract_unsigned_integer (valbuf, len1, byte_order);
1869 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM, regval);
1870
1871 regval = extract_unsigned_integer (valbuf + len1, len2, byte_order);
1872 regcache_cooked_write_unsigned (regcache, NDS32_R0_REGNUM + 1,
1873 regval);
1874 }
1875 else
1876 {
1877 regcache_cooked_write (regcache, NDS32_R0_REGNUM, valbuf);
1878 regcache_cooked_write (regcache, NDS32_R0_REGNUM + 1, valbuf + 4);
1879 }
1880 }
1881}
1882
1883/* Implement the "return_value" gdbarch method.
1884
1885 Determine, for architecture GDBARCH, how a return value of TYPE
1886 should be returned. If it is supposed to be returned in registers,
1887 and READBUF is non-zero, read the appropriate value from REGCACHE,
1888 and copy it into READBUF. If WRITEBUF is non-zero, write the value
1889 from WRITEBUF into REGCACHE. */
1890
1891static enum return_value_convention
1892nds32_return_value (struct gdbarch *gdbarch, struct value *func_type,
1893 struct type *type, struct regcache *regcache,
1894 gdb_byte *readbuf, const gdb_byte *writebuf)
1895{
1896 if (TYPE_LENGTH (type) > 8)
1897 {
1898 return RETURN_VALUE_STRUCT_CONVENTION;
1899 }
1900 else
1901 {
1902 if (readbuf != NULL)
1903 nds32_extract_return_value (gdbarch, type, regcache, readbuf);
1904 if (writebuf != NULL)
1905 nds32_store_return_value (gdbarch, type, regcache, writebuf);
1906
1907 return RETURN_VALUE_REGISTER_CONVENTION;
1908 }
1909}
1910\f
1911/* Implement the "get_longjmp_target" gdbarch method. */
1912
1913static int
1914nds32_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1915{
1916 gdb_byte buf[4];
1917 CORE_ADDR jb_addr;
1918 struct gdbarch *gdbarch = get_frame_arch (frame);
1919 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1920
1921 jb_addr = get_frame_register_unsigned (frame, NDS32_R0_REGNUM);
1922
1923 if (target_read_memory (jb_addr + 11 * 4, buf, 4))
1924 return 0;
1925
1926 *pc = extract_unsigned_integer (buf, 4, byte_order);
1927 return 1;
1928}
1929\f
1930/* Validate the given TDESC, and fixed-number some registers in it.
1931 Return 0 if the given TDESC does not contain the required feature
1932 or not contain required registers. */
1933
1934static int
1935nds32_validate_tdesc_p (const struct target_desc *tdesc,
1936 struct tdesc_arch_data *tdesc_data,
1937 int *fpu_freg, int *use_pseudo_fsrs)
1938{
1939 const struct tdesc_feature *feature;
1940 int i, valid_p;
1941
1942 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.core");
1943 if (feature == NULL)
1944 return 0;
1945
1946 valid_p = 1;
1947 /* Validate and fixed-number R0-R10. */
1948 for (i = NDS32_R0_REGNUM; i <= NDS32_R0_REGNUM + 10; i++)
1949 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1950 nds32_register_names[i]);
1951
1952 /* Validate R15. */
1953 valid_p &= tdesc_unnumbered_register (feature,
1954 nds32_register_names[NDS32_TA_REGNUM]);
1955
1956 /* Validate and fixed-number FP, GP, LP, SP, PC. */
1957 for (i = NDS32_FP_REGNUM; i <= NDS32_PC_REGNUM; i++)
1958 valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
1959 nds32_register_names[i]);
1960
1961 if (!valid_p)
1962 return 0;
1963
1964 /* Fixed-number R11-R27. */
1965 for (i = NDS32_R0_REGNUM + 11; i <= NDS32_R0_REGNUM + 27; i++)
1966 tdesc_numbered_register (feature, tdesc_data, i, nds32_register_names[i]);
1967
1968 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nds32.fpu");
1969 if (feature != NULL)
1970 {
1971 int num_fdr_regs, num_fsr_regs, fs0_regnum, num_listed_fsr;
1972 int freg = -1;
1973
1974 /* Guess FPU configuration via listed registers. */
1975 if (tdesc_unnumbered_register (feature, "fd31"))
1976 freg = 3;
1977 else if (tdesc_unnumbered_register (feature, "fd15"))
1978 freg = 2;
1979 else if (tdesc_unnumbered_register (feature, "fd7"))
1980 freg = 1;
1981 else if (tdesc_unnumbered_register (feature, "fd3"))
1982 freg = 0;
1983
1984 if (freg == -1)
1985 /* Required FDR is not found. */
1986 return 0;
1987 else
1988 *fpu_freg = freg;
1989
1990 /* Validate and fixed-number required FDRs. */
1991 num_fdr_regs = num_fdr_map[freg];
1992 for (i = 0; i < num_fdr_regs; i++)
1993 valid_p &= tdesc_numbered_register (feature, tdesc_data,
1994 NDS32_FD0_REGNUM + i,
1995 nds32_fdr_register_names[i]);
1996 if (!valid_p)
1997 return 0;
1998
1999 /* Count the number of listed FSRs, and fixed-number them if present. */
2000 num_fsr_regs = num_fsr_map[freg];
2001 fs0_regnum = NDS32_FD0_REGNUM + num_fdr_regs;
2002 num_listed_fsr = 0;
2003 for (i = 0; i < num_fsr_regs; i++)
2004 num_listed_fsr += tdesc_numbered_register (feature, tdesc_data,
2005 fs0_regnum + i,
2006 nds32_fsr_register_names[i]);
2007
2008 if (num_listed_fsr == 0)
2009 /* No required FSRs are listed explicitly, make them pseudo registers
2010 of FDRs. */
2011 *use_pseudo_fsrs = 1;
2012 else if (num_listed_fsr == num_fsr_regs)
2013 /* All required FSRs are listed explicitly. */
2014 *use_pseudo_fsrs = 0;
2015 else
2016 /* Some required FSRs are missing. */
2017 return 0;
2018 }
2019
2020 return 1;
2021}
2022
2023/* Initialize the current architecture based on INFO. If possible,
2024 re-use an architecture from ARCHES, which is a list of
2025 architectures already created during this debugging session.
2026
2027 Called e.g. at program startup, when reading a core file, and when
2028 reading a binary file. */
2029
2030static struct gdbarch *
2031nds32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2032{
2033 struct gdbarch *gdbarch;
2034 struct gdbarch_tdep *tdep;
2035 struct gdbarch_list *best_arch;
2036 struct tdesc_arch_data *tdesc_data = NULL;
2037 const struct target_desc *tdesc = info.target_desc;
2038 int elf_abi = E_NDS_ABI_AABI;
2039 int fpu_freg = -1;
2040 int use_pseudo_fsrs = 0;
2041 int i, num_regs, maxregs;
2042
2043 /* Extract the elf_flags if available. */
2044 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2045 elf_abi = elf_elfheader (info.abfd)->e_flags & EF_NDS_ABI;
2046
2047 /* If there is already a candidate, use it. */
2048 for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
2049 best_arch != NULL;
2050 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
2051 {
2052 struct gdbarch_tdep *idep = gdbarch_tdep (best_arch->gdbarch);
2053
2054 if (idep->elf_abi != elf_abi)
2055 continue;
2056
2057 /* Found a match. */
2058 break;
2059 }
2060
2061 if (best_arch != NULL)
2062 return best_arch->gdbarch;
2063
2064 if (!tdesc_has_registers (tdesc))
2065 tdesc = tdesc_nds32;
2066
2067 tdesc_data = tdesc_data_alloc ();
2068
2069 if (!nds32_validate_tdesc_p (tdesc, tdesc_data, &fpu_freg, &use_pseudo_fsrs))
2070 {
2071 tdesc_data_cleanup (tdesc_data);
2072 return NULL;
2073 }
2074
2075 /* Allocate space for the new architecture. */
2076 tdep = XCNEW (struct gdbarch_tdep);
2077 tdep->fpu_freg = fpu_freg;
2078 tdep->use_pseudo_fsrs = use_pseudo_fsrs;
2079 tdep->fs0_regnum = -1;
2080 tdep->elf_abi = elf_abi;
2081
2082 gdbarch = gdbarch_alloc (&info, tdep);
2083
2084 if (fpu_freg == -1)
2085 num_regs = NDS32_NUM_REGS;
2086 else if (use_pseudo_fsrs == 1)
2087 {
2088 set_gdbarch_pseudo_register_read (gdbarch, nds32_pseudo_register_read);
2089 set_gdbarch_pseudo_register_write (gdbarch, nds32_pseudo_register_write);
2090 set_tdesc_pseudo_register_name (gdbarch, nds32_pseudo_register_name);
2091 set_tdesc_pseudo_register_type (gdbarch, nds32_pseudo_register_type);
2092 set_gdbarch_num_pseudo_regs (gdbarch, num_fsr_map[fpu_freg]);
2093
2094 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg];
2095 }
2096 else
2097 num_regs = NDS32_NUM_REGS + num_fdr_map[fpu_freg] + num_fsr_map[fpu_freg];
2098
2099 set_gdbarch_num_regs (gdbarch, num_regs);
2100 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
2101
2102 /* Cache the register number of fs0. */
2103 if (fpu_freg != -1)
2104 tdep->fs0_regnum = user_reg_map_name_to_regnum (gdbarch, "fs0", -1);
2105
2106 /* Add NDS32 register aliases. To avoid search in user register name space,
2107 user_reg_map_name_to_regnum is not used. */
2108 maxregs = (gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch));
2109 for (i = 0; i < ARRAY_SIZE (nds32_register_aliases); i++)
2110 {
2111 int regnum, j;
2112
2113 regnum = -1;
2114 /* Search register name space. */
2115 for (j = 0; j < maxregs; j++)
2116 {
2117 const char *regname = gdbarch_register_name (gdbarch, j);
2118
2119 if (regname != NULL
2120 && strcmp (regname, nds32_register_aliases[i].name) == 0)
2121 {
2122 regnum = j;
2123 break;
2124 }
2125 }
2126
2127 /* Try next alias entry if the given name can not be found in register
2128 name space. */
2129 if (regnum == -1)
2130 continue;
2131
2132 user_reg_add (gdbarch, nds32_register_aliases[i].alias,
2133 value_of_nds32_reg, (const void *) (intptr_t) regnum);
2134 }
2135
2136 nds32_add_reggroups (gdbarch);
2137
2138 /* Hook in ABI-specific overrides, if they have been registered. */
2139 info.tdep_info = (void *) tdesc_data;
2140 gdbarch_init_osabi (info, gdbarch);
2141
2142 /* Override tdesc_register callbacks for system registers. */
2143 set_gdbarch_register_reggroup_p (gdbarch, nds32_register_reggroup_p);
2144
2145 set_gdbarch_sp_regnum (gdbarch, NDS32_SP_REGNUM);
2146 set_gdbarch_pc_regnum (gdbarch, NDS32_PC_REGNUM);
2147 set_gdbarch_unwind_sp (gdbarch, nds32_unwind_sp);
2148 set_gdbarch_unwind_pc (gdbarch, nds32_unwind_pc);
2149 set_gdbarch_stack_frame_destroyed_p (gdbarch, nds32_stack_frame_destroyed_p);
2150 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nds32_dwarf2_reg_to_regnum);
2151
2152 set_gdbarch_push_dummy_call (gdbarch, nds32_push_dummy_call);
2153 set_gdbarch_return_value (gdbarch, nds32_return_value);
2154 set_gdbarch_dummy_id (gdbarch, nds32_dummy_id);
2155
2156 set_gdbarch_skip_prologue (gdbarch, nds32_skip_prologue);
2157 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2158 set_gdbarch_breakpoint_from_pc (gdbarch, nds32_breakpoint_from_pc);
2159
2160 set_gdbarch_frame_align (gdbarch, nds32_frame_align);
2161 frame_base_set_default (gdbarch, &nds32_frame_base);
2162
2163 set_gdbarch_print_insn (gdbarch, print_insn_nds32);
2164
2165 /* Handle longjmp. */
2166 set_gdbarch_get_longjmp_target (gdbarch, nds32_get_longjmp_target);
2167
2168 /* The order of appending is the order it check frame. */
2169 dwarf2_append_unwinders (gdbarch);
2170 frame_unwind_append_unwinder (gdbarch, &nds32_epilogue_frame_unwind);
2171 frame_unwind_append_unwinder (gdbarch, &nds32_frame_unwind);
2172
2173 return gdbarch;
2174}
2175
2176void
2177_initialize_nds32_tdep (void)
2178{
2179 /* Initialize gdbarch. */
2180 register_gdbarch_init (bfd_arch_nds32, nds32_gdbarch_init);
2181
2182 initialize_tdesc_nds32 ();
2183 nds32_init_reggroups ();
2184}
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