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67278683
FF		 1/* Machine-dependent code which would otherwise be in inflow.c and core.c,
2 for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987 Free Software Foundation, Inc.
4 This code is for the i860 cpu.
be9a2362
FF		 5
6 GDB is distributed in the hope that it will be useful, but WITHOUT ANY
7 WARRANTY. No author or distributor accepts responsibility to anyone
8 for the consequences of using it or for whether it serves any
9 particular purpose or works at all, unless he says so in writing.
10 Refer to the GDB General Public License for full details.
11
12 Everyone is granted permission to copy, modify and redistribute GDB,
13 but only under the conditions described in the GDB General Public
14 License. A copy of this license is supposed to have been given to you
15 along with GDB so you can know your rights and responsibilities. It
16 should be in a file named COPYING. Among other things, the copyright
17 notice and this notice must be preserved on all copies.
18
19 In other words, go ahead and share GDB, but don't try to stop
20 anyone else from sharing it farther. Help stamp out software hoarding!
21 */
67278683 22#include <stdio.h>
2213b721
FF		 23#include <stdlib.h>
24#include <stdarg.h>
25
be9a2362 26
67278683 27#include "defs.h"
be9a2362
FF		 28#include "tm-i860.h"
29#include "frame.h"
30#include "inferior.h"
31#include "obstack.h"
32#include "symtab.h"
33#include "value.h"
34
be9a2362
FF		 35#include "i860-opcode.h"
36
67278683
FF		 37#include "breakpoint.h"
38#include "i860-break.h"
2213b721 39#include "command.h"
67278683 40#include "target.h"
be9a2362
FF		 41
42#ifdef notdef
be9a2362
FF		 43#include <sys/types.h>
44#include <sys/param.h>
45#include <sys/dir.h>
be9a2362
FF		 46#endif
47
48#include <signal.h>
49#include <sys/ioctl.h>
50#include <fcntl.h>
51
52/* #include <sys/reg.h> */
53#include "i860_reg.h"
54
55#include <a.out.h>
56#include <sys/file.h>
be9a2362
FF		 57#include <core.h>
58
59#include <sys/user.h>
be9a2362
FF		 60#include <elf.h>
61#include <sys/elftypes.h>
62#include <sys/elf_860.h>
63#include <libelf.h>
64
65
2213b721
FF		 66extern int read_memory();
67extern int write_memory();
68extern int read_memory_integer();
69extern int print_insn();
70extern void bzero();
71extern void bcopy();
2213b721 72
be9a2362 73int btdebug = 0; /* change value to 1 to enable debugging code */
67278683 74int ansi_conformant;
be9a2362
FF		 75
76#define BTDEBUG if (btdebug) btdebug_message
77
2213b721 78extern int errno;
67278683 79extern char registers[];
ca8820f9 80CORE_ADDR get_saved_basereg();
be9a2362 81
2213b721
FF		 82#define INSTRUCTION_LENGTH 4
83#define REGISTER_LENGTH 4
67278683
FF		 84#define ALIGN_ARG(size,len) ((size + (len-1))&(-len))
85#define NUM_FLOAT_ARG_REGS 8
86#define NUM_INT_ARG_REGS 12
be9a2362 87
2213b721
FF		 88/* routine to print debugging messages */
89void btdebug_message(char *format, ...)
be9a2362
FF		 90{
91 va_list arglist;
92 va_start( arglist, format );
93
94 if( btdebug )
95 vfprintf (stderr, format, arglist );
96 va_end ( arglist );
97}
98
67278683
FF		 99\f
100/* Peggy Fieland. Routine that attempts to find the start of the entry sequence
101 for a routine. */
102/* maximum number of instrutions to search back */
103#define MAX_ROUTINE_SIZE 4096
104CORE_ADDR find_entry_start(pc)
105CORE_ADDR pc;
106{
107 CORE_ADDR instr, top_pc;
108 int i;
109
110 top_pc = pc;
111 for (i = 0; i < MAX_ROUTINE_SIZE; ++i)
112
113 {
114 instr = (unsigned)( adj_read_memory_integer (top_pc));
115 /* Recognize "addu|adds -X,sp,sp" insn. */
116
117 if ((instr & 0xEFFF0000) == 0x84420000)
118 {
119 return (top_pc);
120 }
121 top_pc -= INSTRUCTION_LENGTH;
122 }
123 return (0);
124}
125
126
127\f
128/* Written by Peggy Fieland ([email protected]) */
129/* get the contents of a base register. Used for dwarf OP_BASEREG */
130/* At present, only OP_BASEREG generated is for R28. NOTE that for stuff based on R28,
131 the value we want is the VALUE AT PROCEDURE INVOKATION, and thus is the frame we
132 use to get the value is the caller's frame. */
133CORE_ADDR get_saved_basereg (frame, basereg)
134FRAME frame;
135int basereg;
136{
137 CORE_ADDR addr;
138 if (basereg == R28) /* Unconditionally ??? */
139 {
140 frame = get_prev_frame (frame);
141 get_saved_register((char *) &addr, (int *) NULL, (CORE_ADDR *) NULL, frame,
142 basereg, (enum lval_type *)NULL);
143
144 }
145 else
146 get_saved_register((char *) &addr, (int *) NULL, (CORE_ADDR *) NULL, frame,
147 basereg, (enum lval_type *)NULL);
148
149 return (addr);
150}
151
be9a2362
FF		 152\f
153
154/* return nonzero if the routine containing pc has been
155 * compiled with -g. We assume -g if the first instruction is
156 * an addu|adds -X,sp and the second is st.l fp,XX(sp)
157 *
158 * based on skip_prologue();
159 */
160
2213b721 161static int g_routine(pc)
67278683 162
be9a2362
FF		 163 CORE_ADDR pc;
164{
2213b721 165 CORE_ADDR instr;
be9a2362
FF		 166 CORE_ADDR top_pc;
167
168 top_pc = get_pc_function_start(pc);
67278683
FF		 169 if (top_pc == NULL)
170 top_pc = find_entry_start (pc);
171
2213b721 172 if (top_pc != NULL)
be9a2362 173 {
2213b721 174 instr = (unsigned)( adj_read_memory_integer (top_pc));
be9a2362
FF		 175 /* Recognize "addu|adds -X,sp,sp" insn. */
176
177 if ((instr & 0xEFFF0000) == 0x84420000)
178 {
2213b721
FF		 179 top_pc += INSTRUCTION_LENGTH;
180 instr = (unsigned)(adj_read_memory_integer (top_pc));
be9a2362
FF		 181
182 if( (instr & 0xFFE0F801) == 0x1C401801 ) /* st.l fp,X(sp) */
183 return(1);
184 }
185 }
186 return(0);
187}
188
189
2213b721
FF		 190/* return the stack offset where the fp register is stored */
191static int find_fp_offset(pc)
be9a2362
FF		 192CORE_ADDR pc;
193{
2213b721
FF		 194 int fp_off,i;
195 CORE_ADDR instr;
be9a2362 196
2213b721 197 /* look for the instruction and examine the offset */
be9a2362 198
2213b721
FF		 199 for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH){
200 instr = (unsigned)(adj_read_memory_integer(pc+i));
201 if( (instr & 0xFFE0F801) == 0x1C401801) { /* st.l fp,X(sp) */
202
203 fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) |
204 (instr&0x000007FE));
205 return(fp_off);
be9a2362 206 }
2213b721
FF		 207 }
208 return(0);
209}
210
67278683 211
2213b721 212/* return the stack offset where r1 (return linkage ) register is stored */
67278683
FF		 213static CORE_ADDR find_r1(pc,sp,fp)
214CORE_ADDR pc,sp, fp;
2213b721
FF		 215{
216 int r1_off,i;
67278683 217 CORE_ADDR instr, ret_pc;
be9a2362 218
2213b721 219 /* look for the instruction and examine the offset */
be9a2362 220
67278683
FF		 221 for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH)
222 {
223 instr = (unsigned)( adj_read_memory_integer(pc+i));
224 if ((instr & 0xFFE0F801) == 0x1C400801)
225 {
226 /* st.l r1,X(sp) */
2213b721 227
67278683
FF		 228 r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) |
229 (instr&0x000007FE));
230 ret_pc = read_memory_integer(sp+r1_off,sizeof(long));
231 return(ret_pc);
232 }
233 else if ((instr & 0xFFE0F801) == 0x1C600801)
234 {
235 /* st.l r1,X(fp) */
236 r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) |
237 (instr&0x000007FE));
238 ret_pc = read_memory_integer(fp+r1_off,sizeof(long));
239 return(ret_pc);
240 }
be9a2362 241 }
67278683 242 return(0);
be9a2362
FF		 243}
244
2213b721 245CORE_ADDR skip_prologue(CORE_ADDR);
be9a2362 246
2213b721
FF		 247/* does routine starting at pc build a stack frame of any kind?? */
248static int has_a_frame(pc)
249CORE_ADDR pc;
250{
251 if( skip_prologue(pc) != pc )return(1);
252 else return(0);
253}
be9a2362
FF		 254
255
2213b721
FF		 256/* written by Peggy Fieland [email protected]
257 Routine to validate the return register and the frame pointer
258 This routine is called when the routine we are in doesn't have a frame
259 In that case, we assume that the return address and frame pointer have
260 not been touched. In the following routine, we try to range check them
261 to see if they are valid. */
262
263static int valid_regs (rp, fp)
264CORE_ADDR rp, fp;
be9a2362 265{
2213b721
FF		 266 if ( ( (rp % 4) != 0) | ( (fp % 16) != 0) )
267 return (0);
268 else
269 return (1);
be9a2362 270}
2213b721
FF		 271/* get the pc and frame pointer (or sp )
272 * for the routine that called us
273 * when we (this_pc) is not within a -g routine
274 * if caller is non g we return sp for fp
275 */
be9a2362 276
2213b721
FF		 277/* note this is written for Metaware version R2.1d compiler */
278/* Modified by Peggy Fieland [email protected] */
67278683
FF		 279static int caller_pc(this_pc,this_sp,this_fp,to_pc,to_fp, called_from_frame_chain)
280 CORE_ADDR this_pc,this_sp, this_fp;
2213b721 281 CORE_ADDR *to_pc, *to_fp;
67278683 282 int called_from_frame_chain;
be9a2362 283{
2213b721
FF		 284 CORE_ADDR func_start;
285 int sp_offset,offset;
286 CORE_ADDR sp,pc,fp,instr;
be9a2362 287
2213b721 288 BTDEBUG("caller_pc %x sp = %x\n",this_pc,this_sp);
be9a2362 289
2213b721
FF		 290 func_start = get_pc_function_start(this_pc);
291
67278683
FF		 292 if (func_start == NULL)
293 func_start = find_entry_start (this_pc);
294
2213b721
FF		 295 BTDEBUG("caller_pc func_start %x\n", func_start);
296
67278683
FF		 297 if ((func_start == NULL))
298 {
299 /* error in traceback */
300 fprintf(stderr, "error, unable to find start of function\n");
301 return(0);
302
303 }
304
2213b721 305 if (func_start!= NULL)
be9a2362
FF		 306 {
307 if( has_a_frame(func_start) ){
308
309 BTDEBUG("has_a_frame\n");
310
311 /* if our caller has a preamble and
312 * declares space for a stack frame
313 * then we must work to find our return address
314 */
2213b721 315 instr = (unsigned)( adj_read_memory_integer (func_start));
be9a2362
FF		 316 /* Recognize "addu|adds -X,sp,sp" insn. */
317
318 if ((instr & 0xEFFF0000) == 0x84420000)
319 sp_offset=SIGN_EXT16(instr&0x0000FFFF);
320 }
2213b721
FF		 321 else
322 {
67278683 323 /* if we get here, procedure doesn't have a frame. If we
2213b721
FF		 324 do anything weird, the frame pointer and return register have
325 the values we want. Check them to see if they are valid. */
326
327 CORE_ADDR temp_rp, temp_fp;
328
67278683
FF		 329 /* temporary warning, since at the moment we don't have support for
330 the shared library */
331
2213b721
FF		 332 temp_rp = read_register(RP_REGNUM);
333 temp_fp = read_register(FP_REGNUM);
334
335 if (!valid_regs(temp_rp, temp_fp))
336 {
67278683
FF		 337 fprintf(stderr,
338 "error - unable to find return address, traceback terminating\n");
2213b721
FF		 339 return(0);
340 }
341 BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n",
342 temp_rp, temp_fp);
343 *to_pc = temp_rp;
344 *to_fp = temp_fp;
345 return (1);
346 }
be9a2362
FF		 347
348 BTDEBUG("sp_offset = %d %x\n",sp_offset,sp_offset);
349
67278683 350 pc = find_r1(func_start, this_sp, this_fp);
be9a2362 351
67278683
FF		 352 if(pc == NULL)
353 {
354
355 /* r1 wasn't stored between pc and function start */
356 pc = read_register (RP_REGNUM);
357 }
358
be9a2362
FF		 359 sp= this_sp - sp_offset;
360
361 BTDEBUG("callers pc = %x sp = %x\n",pc,sp);
362
363 /* our caller a -g routine ?
364 * if he is we have to find his real fp
365 * else provide the sp as his fp
366 */
367
368 if( g_routine(pc) ){
369
370 BTDEBUG("caller_a_g\n");
371
372 if( ! (offset = find_fp_offset(func_start)) ) {
67278683
FF		 373 fprintf(stderr, "error - unable to find caller frame for routine at 0x%x, "
374 "traceback terminating\n", func_start);
be9a2362
FF		 375 return(0);
376 }
377 BTDEBUG("offset = %x %d\n",offset,offset);
378
2213b721 379 fp = read_memory_integer(this_sp+offset,sizeof(long));
be9a2362
FF		 380 *to_pc = CLEAN_PC(pc);
381 *to_fp = fp;
382 return(1);
383 }else
384 *to_pc = CLEAN_PC(pc);
385 *to_fp = sp;
386 return(1);
387 } else {
388/* pc = read_register(RP_REGNUM); */
2213b721
FF		 389/* pc = 0; */
390 /* if we get here, procedure doesn't have a frame. If we didn't
391 do anything weird, the frame pointer and return register have
392 the values we want. Check them to see if they are valid. */
393
394 CORE_ADDR temp_rp, temp_fp;
395
396 temp_rp = read_register(RP_REGNUM);
397 temp_fp = read_register(FP_REGNUM);
398
399 if (!valid_regs(temp_rp, temp_fp))
400 {
67278683
FF		 401 fprintf(stderr,
402 "error - unable to find return address, traceback terminating\n");
403
2213b721
FF		 404 return(0);
405 }
406 BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n",
407 temp_rp, temp_fp);
408 *to_pc = temp_rp;
409 *to_fp = temp_fp;
410 return (1);
be9a2362
FF		 411 }
412}
413
2213b721
FF		 414/*
415 ** Figure out address to place next breakpoint. Avoid tricky spots,
416 ** ie. delayed instruction slots etc.
417 ** Need to upgrade this later to allow delayed instruction breakpoints
418 ** with fix-up work done AFTER breakpoint.
419 ** Note that this routine DOES deal with dual instruction mode
420 */
421#define BIM 0x8008
be9a2362 422
2213b721
FF		 423static branch_type
424 place_brk (addr, mode, brk)
425CORE_ADDR addr;
426int mode;
427struct breakpoint *brk;
be9a2362 428{
2213b721
FF		 429 CORE_ADDR instr;
430 CORE_ADDR nextadr, prevadr;
be9a2362
FF		 431 int val = not_branch;
432 long offset; /* Must be signed for sign-extend */
be9a2362
FF		 433 prevadr = nextadr = 0;
434
435 brk->address1 = 0;
436
437 if (mode == SINGLE_STEP_MODE)
438 {
439 if (INDIM || ENDIM)
440 {
2213b721
FF		 441 nextadr = brk->address = (addr + INSTRUCTION_LENGTH*2);
442 instr = (unsigned)(adj_read_memory_integer ((addr + INSTRUCTION_LENGTH)));
be9a2362
FF		 443 brk->mode = DIM;
444 }
445 else
446 {
2213b721
FF		 447 nextadr = brk->address = (addr + INSTRUCTION_LENGTH);
448 instr = (unsigned)(adj_read_memory_integer (addr));
be9a2362
FF		 449 if (STDIM)
450 brk->mode = DIM;
451 else
452 brk->mode = SIM;
453 }
454
455
456 /*
457 ** For br/call one more sequential instruction gets executed and then we
458 ** continue at the current addr + offset. We are definitely going to
459 ** the dest. We are NOT allowed to place a breakpoint in the "delay"
460 ** slot - (the next sequential instruction) so we only place 1 breakpoint
461 ** at the destination.
462 ** For the bc/bnc the next instruction executed is EITHER the next sequential
463 ** or the destination of the branch, we therefore place 2 breakpoints one
464 ** at each location.
465 ** For the bc.t/bnc.t either 1 more sequential instruction is performed
466 ** followed by a branch (like br/call) OR we skip the sequential
467 ** instruction and keep going. We therefore place a breakpoint at the
468 ** destination of the branch AND the second sequential instruction after
469 ** the branch. Again a breakpoint is NOT allowed in the "delay slot"
470 */
471 if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */
472 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
473 {
474 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
475 val = uncond_d;
476 else if ((instr & 0xF4000000) == 0x74000000) /* bc.t/bnc.t */
477 val = cond_d;
478 else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */
479 val = cond;
480 offset = (instr & 0x03ffffff);
481 if (offset & 0x02000000) /*?sign extend*/
482 offset |= 0xFC000000;
483 if (val == uncond_d) /* br/call*/
484 prevadr = 0;
485 else if (val == cond_d) /* bc.t/bnc.t */
486 {
487 if ((INDIM) && !(ENDIM))
2213b721 488 prevadr = nextadr + (2*INSTRUCTION_LENGTH);
be9a2362 489 else
2213b721 490 prevadr = nextadr + INSTRUCTION_LENGTH;
be9a2362
FF		 491 } else { /* bc /bnc */
492 if ((INDIM) && !(ENDIM))
493 prevadr = nextadr;
494 else
495 prevadr = nextadr;
496 }
497 nextadr += (offset << 2);
498 }
499 /*
500 ** We treat the bri/calli the same way as the br/call case.
501 */
502 else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */
503 (instr & 0xFC000000) == 0x40000000) /* bri */
504 {
505 val = uncond_d;
506 offset = ((instr & 0x0000F800) >> 11);
507 nextadr = (read_register(offset + R0) & 0xFFFFFFFC);
508 prevadr = 0;
509 }
510 /*
511 ** We treat the bte/btne the same way as the bc/bnc case.
512 */
513 else if ((instr & 0xF0000000) == 0x50000000) /* bte/btne */
514 {
515 val = cond;
516 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) |
517 (instr & 0x000007FF));
518 if ((INDIM) && !(ENDIM))
519 prevadr = nextadr;
520 else
521 prevadr = nextadr;
522
523 nextadr += (offset << 2);
524 }
525 /*
526 ** We treat the bte/btne the same way as the bc/bnc case.
527 ** With the caveat that the 2 breakpoints may turn out to be at the same
528 ** address in which case we ignore one of them.
529 */
530 else if ((instr & 0xFC000000) == 0xB4000000) /* bla */
531 {
532 val = cond_d;
533 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) |
534 (instr & 0x000007FF));
535 if ((INDIM) && !(ENDIM))
536 {
2213b721 537 prevadr = nextadr + 2*INSTRUCTION_LENGTH;
be9a2362 538 } else {
2213b721 539 prevadr = nextadr + INSTRUCTION_LENGTH;
be9a2362
FF		 540 }
541 nextadr += (offset << 2);
542 if (prevadr == nextadr) prevadr = 0;
543 }
544 } else {
545 int adjust = 0;
546
547 nextadr = addr;
548
549 if (ISDIM(FOPADR(addr)))
550 {
2213b721 551 if (ISDIM(FOPADR(nextadr- INSTRUCTION_LENGTH*2)))
be9a2362 552 {
2213b721
FF		 553 instr = (unsigned)(adj_read_memory_integer(CORADR(addr
554 -(INSTRUCTION_LENGTH*2))));
be9a2362
FF		 555 brk->mode = DIM;
556 } else {
2213b721 557 instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH));
be9a2362
FF		 558 brk->mode = RIM;
559 }
560 } else {
2213b721 561 if (ISDIM(addr-INSTRUCTION_LENGTH))
be9a2362 562 {
2213b721 563 instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH));
be9a2362
FF		 564 brk->mode = BIM;
565 } else {
2213b721 566 instr = (unsigned)(adj_read_memory_integer (addr-INSTRUCTION_LENGTH));
be9a2362
FF		 567 brk->mode = SIM;
568 }
569 }
570
571 /* examine the PREVIOUS instruction to determine if we are in a branch delay
572 slot. If we are, dont set a break here -- set it on the previous instruction.
573 This code also accounts for dual instruction mode */
574 if ((instr & 0xE0000000) == 0x60000000 &&
575 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
576 {
2213b721
FF		 577 adjust++;
578 /* br /call */
579 /* bc /bnc */
580 /* bc.t /bnc.t*/
581 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
67278683 582 BTDEBUG(" Breakpoint adjusted to avoid br/call delay slot and multiple breakpoints\n");
2213b721
FF		 583
584 if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */
67278683
FF		 585 BTDEBUG(" Breakpoint adjusted to avoid bc.t/bnc.t delay slot and"
586 "multiple breakpoints\n");
587
2213b721
FF		 588 /* it IS really OK to set a break on the instruction AFTER the conditional branch
589 -- it DOESN't have a delay slot */
590 if ((instr & 0xF4000000) == 0x70000000) /* bc / bnc */
2213b721
FF		 591 adjust = 0;
592 } else if
593 ((instr & 0xFC00003F) == 0x4C000002 || /* bri/ calli */
594 (instr & 0xFC000000) == 0x40000000)
595 {
596 adjust++;
67278683
FF		 597 BTDEBUG(" Breakpoint adjusted to avoid calli/bri delay slot and"
598 " multiple breakpoints\n");
2213b721
FF		 599 } else if
600 ((instr & 0xF0000000) == 0x50000000) /* bte - btne */
601 {
602 /* it's OK to set a break here -- we are NOT in aa branch delay slot */
603 /*
604 adjust++;
605 printf(" Breakpoint adjusted to avoid bte/btne multiple breakpoints\n");
606 */
607 adjust = 0;
608 } else if
609 ((instr & 0xFC000000) == 0xB4000000)
610 {
611 adjust++;
67278683
FF		 612 BTDEBUG(" Breakpoint adjusted to avoid bla delay slot and"
613 " multiple breakpoints\n");
2213b721
FF		 614 }
615 if (adjust != 0)
616 {
617 if (brk->mode == DIM)
618 {
619 nextadr -= INSTRUCTION_LENGTH*2;
620 nextadr = CORADR(nextadr);
621 }
622 else
623 nextadr -= INSTRUCTION_LENGTH;
624 }
625
626 }
627
628 if (brk->mode == RIM)
629 brk->mode = DIM;
630 if (brk->mode == BIM)
631 brk->mode = SIM;
632
633 if (nextadr != NULL)
634 {
635 if (brk->mode == DIM)
636 {
637 brk->act_addr[0] = CORADR(nextadr);
638 brk->act_addr[1] = FOPADR(nextadr);
639 } else {
640 brk->act_addr[0] = nextadr;
641 brk->act_addr[1] = 0;
642 }
643 }
644
645 if (prevadr != NULL)
646 {
647 brk->address1 = prevadr;
648 if (brk->mode == DIM)
649 {
650 brk->act_addr[2] = CORADR(prevadr);
651 brk->act_addr[3] = FOPADR(prevadr);
652 } else {
653 brk->act_addr[2] = prevadr;
654 brk->act_addr[3] = 0;
655 }
656 } else {
657 brk->act_addr[2] = brk->act_addr[3] = 0;
658 }
659 return val;
660}
661
662/* This routine checks to see if r1 has been stored into the frame between
663 the addresses prologue_start and prologue_end. Recognize stores of r1
664 relative to both the sp and fp registers. */
665static int has_stored_r1(CORE_ADDR prologue_start, CORE_ADDR prologue_end)
666{
667 CORE_ADDR instr;
668 CORE_ADDR addr;
669
670 BTDEBUG("has_stored_r1, prologue_start %x, prologue_end %x\n",
671 prologue_start, prologue_end);
672
673 for (addr = prologue_start; addr <= prologue_end; addr += INSTRUCTION_LENGTH)
674 {
675
676 instr = (unsigned)(adj_read_memory_integer (addr));
677 if ((instr & 0xFFE0F801) == 0x1C400801 /* st.l r1,X(sp) */
678 || (instr & 0xFFE0F801) == 0x1C600801) /* st.l r1,X(fp) */
679 return (1);
680 }
681 return 0;
682}
683/* This is used when GDB is exiting. It gives less chance of error.*/
684
685
686/* Simulate single-step ptrace call for sun4. Code written by Gary
687 Beihl ([email protected]). */
688/* Modified for i860 by Jim Hanko ([email protected]) */
689
690
691static struct breakpoint brk;
692typedef char binsn_quantum[sizeof break_insn];
693
694/* Non-zero if we just simulated a single-step ptrace call. This is
695 needed because we cannot remove the breakpoints in the inferior
696 process until after the `wait' in `wait_for_inferior'. Used for
697 i860. */
698
699int one_stepped;
700
701/* single_step() is called just before we want to resume the inferior,
702 if we want to single-step it but there is no hardware or kernel single-step
703 support. We find all the possible targets of the coming instruction and
704 breakpoint them.
705
706 single_step is also called just after the inferior stops. If we had
707 set up a simulated single-step, we undo our damage. */
708/* Note that we don't need the parameter, but it's dictated as part of the interface. */
709void
710 single_step (signal)
711int signal;
712{
713 CORE_ADDR pc;
714 branch_type place_brk();
67278683
FF		 715 int *shadow0, *shadow1, *shadow2, *shadow3;
716
717 shadow0 = (int *) &brk.shadow_contents[0];
718 shadow1 = (int *) &brk.shadow_contents[4];
719 shadow2 = (int *) &brk.shadow_contents[8];
720 shadow3 = (int *) &brk.shadow_contents[12];
2213b721
FF		 721 pc = read_register (PC_REGNUM);
722
723 if (!one_stepped)
724 {
725 brk.address = pc;
726 place_brk (pc, SINGLE_STEP_MODE, &brk);
67278683 727 *shadow0 = *shadow1 = *shadow2 = *shadow3 = 0;
2213b721
FF		 728
729 if (brk.mode == DIM)
730 {
731 if (btdebug != 0)
732 {
733 btdebug_message(" DIM1 -> %x : ", brk.act_addr[3]);
734 print_insn( brk.act_addr[3], stderr);
735 btdebug_message("\t -|- %x : ", brk.act_addr[2]);
736 print_insn( brk.act_addr[2], stderr);
737 btdebug_message("\n");
738 }
739 if (( brk.address1 != NULL))
740 {
67278683 741 adj_read_memory (brk.act_addr[2], shadow2,
2213b721
FF		 742 INSTRUCTION_LENGTH);
743 adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH);
67278683 744 adj_read_memory (brk.act_addr[3], shadow3,
2213b721
FF		 745 INSTRUCTION_LENGTH);
746 /* adj_write_memory (brk.act_addr[3], float_insn,
747 INSTRUCTION_LENGTH); */
748
749 }
750 if (btdebug != 0)
751 {
752 if ( brk.address1 != 0)
753 btdebug_message(" DIM2 ->");
754 else
755 btdebug_message(" DIM1 ->");
756
757 btdebug_message(" %x : ", brk.act_addr[1]);
758 print_insn( brk.act_addr[1], stderr);
759 btdebug_message("\t -|- %x : ", brk.act_addr[0]);
760 print_insn( brk.act_addr[0], stderr);
761 btdebug_message("\n");
762 }
763
67278683 764 adj_read_memory (brk.act_addr[0], shadow0,
2213b721
FF		 765 INSTRUCTION_LENGTH);
766 adj_write_memory (brk.act_addr[0], break_insn,
767 INSTRUCTION_LENGTH);
67278683 768 adj_read_memory (brk.act_addr[1], shadow1,
2213b721
FF		 769 INSTRUCTION_LENGTH);
770 /* adj_write_memory (brk.act_addr[1], float_insn,
771 INSTRUCTION_LENGTH); */
772
773 }
774 else {
775 if (brk.address1 != NULL)
776 {
777 if (btdebug)
778 {
779 btdebug_message(" SIM1 ->");
780 btdebug_message(" %x : ", brk.act_addr[2]);
781 print_insn( brk.act_addr[2], stderr);
782 btdebug_message("\n");
783 }
67278683 784 adj_read_memory (brk.act_addr[2], shadow2,
2213b721
FF		 785 INSTRUCTION_LENGTH);
786 adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH);
787 }
788 if (btdebug)
789 {
790 if ( brk.address1 != NULL)
791 btdebug_message(" SIM2 ->");
792 else
793 btdebug_message(" SIM1 ->");
794
795 btdebug_message(" %x : ", brk.act_addr[0]);
796 print_insn( brk.act_addr[0], stderr);
797 btdebug_message("\n");
798 }
67278683 799 adj_read_memory (brk.act_addr[0], shadow0,
2213b721
FF		 800 INSTRUCTION_LENGTH);
801 adj_write_memory (brk.act_addr[0], break_insn,INSTRUCTION_LENGTH);
802 }
803
804 /* Let it go */
805 one_stepped = 1;
806 return;
807 }
808 else
809 {
810 /* Remove breakpoints */
811 if (brk.mode == DIM)
812 {
67278683 813 adj_write_memory (brk.act_addr[0], shadow0,
2213b721 814 INSTRUCTION_LENGTH);
67278683 815 adj_write_memory (brk.act_addr[1], shadow1,
2213b721
FF		 816 INSTRUCTION_LENGTH);
817 } else {
67278683 818 adj_write_memory (brk.act_addr[0], shadow0,
2213b721
FF		 819 INSTRUCTION_LENGTH);
820 }
821
822 if (brk.address1 != NULL)
823 {
824 if (brk.mode == DIM)
825 {
67278683 826 adj_write_memory (brk.act_addr[2], shadow2,
2213b721 827 INSTRUCTION_LENGTH);
67278683 828 adj_write_memory (brk.act_addr[3], shadow3,
2213b721
FF		 829 INSTRUCTION_LENGTH);
830 } else {
67278683 831 adj_write_memory (brk.act_addr[2], shadow2,
2213b721
FF		 832 INSTRUCTION_LENGTH);
833 }
834 }
835 one_stepped = 0;
836 }
837}
838
839
840
841/* Written for i860 by Jim Hanko ([email protected]) */
842/* This code was based on SPARC code written by Gary Beihl ([email protected]),
843 by Michael Tiemann ([email protected]). */
844/* This routine returns the first memory address following the prologue code,
845 if there is a prologue. */
846
847struct command_line *get_breakpoint_commands ();
848
849CORE_ADDR
850 skip_prologue (pc)
851CORE_ADDR pc;
852{
853 CORE_ADDR instr;
854 int regno;
855
856 instr = (unsigned)(adj_read_memory_integer (pc));
857
858 /* Recognize "addu|adds -X,sp,sp" insn. */
859 if ((instr & 0xEFFF0000) == 0x84420000)
860 {
861 pc += INSTRUCTION_LENGTH;
862 instr = (unsigned)(adj_read_memory_integer (pc));
863 }
864 else
865 return(pc); /* No frame! */
866
867 /* Recognize store of return addr and frame pointer into frame */
868 for (; ;)
869 {
870 if ((instr & 0xFFE0F801) == 0x1C400801 || /* st.l r1,X(sp) */
871 (instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */
872 {
873 pc += INSTRUCTION_LENGTH;
874 instr = (unsigned)(adj_read_memory_integer (pc));
875 }
876 else
877 break;
878 }
879
880 /* Recognize "addu|adds X,sp,fp" insn. */
881 if ((instr & 0xEFFF0000) == 0x84430000)
882 {
883 pc += INSTRUCTION_LENGTH;
884 instr = (unsigned)(adj_read_memory_integer (pc));
885 }
886
887 /* Now recognize stores into the frame from the registers. */
888
889 for (; ;)
890 {
891 if ((instr & 0xFFA00003) == 0x1C200001 || /* st.l rn,X(fp|sp) */
892 (instr & 0xFFA00001) == 0x4C200000) /* fst.y fn,X(fp|sp) */
893 {
894 regno = (instr >> 11) & 0x1f;
895 if (regno == 0) /* source reg == 0? quit */
896 break;
897 pc += INSTRUCTION_LENGTH;
898 instr = (unsigned)(adj_read_memory_integer (pc));
899 }
900 else
901 break;
902 }
903
904 return(pc);
905}
906
907#if 0
908/* This routine is uncalled. Remove it sometime. */
909/* Set *nextpc to branch target if we find a branch. If it is not a branch,
910 set it to the next instruction (addr + 4) */
911
912
913branch_type
914 isabranch (addr, nextpc)
915CORE_ADDR addr, *nextpc;
916{
917 CORE_ADDR instr;
918 branch_type val = not_branch;
919 long offset; /* Must be signed for sign-extend */
920
921 BTDEBUG(" isabranch\n");
922 *nextpc = addr;
923 instr = (unsigned)(adj_read_memory_integer (addr));
924
925 if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */
926 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
927 {
928 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
929 val = uncond_d;
930 else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */
931 val = cond_d;
932 else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */
933 val = cond;
934
935 offset = (instr & 0x03ffffff);
936 if (offset & 0x02000000) /* sign extend? */
937 offset |= 0xFC000000;
938 *nextpc = addr + 4 + (offset << 2);
939 }
940 else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */
941 (instr & 0xFC000000) == 0x40000000) /* bri */
942 {
943 val = uncond_d;
944 offset = ((instr & 0x0000F800) >> 11);
945 *nextpc = (read_register(offset) & 0xFFFFFFFC);
946 }
947 else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */
948 {
949 val = cond;
950
951 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
952 *nextpc = addr + 4 + (offset << 2);
953 }
954 else if ((instr & 0xFC000000) == 0xB4000000) /* bla */
955 {
956 val = cond_d;
957
958 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
959 *nextpc = addr + 4 + (offset << 2);
960 }
961
962 BTDEBUG(" Final addr - %x\n", *nextpc);
963 /*BTDEBUG("isabranch ret: %d\n",val); */
964 return val;
965}
966#endif
967
968/* set in call_function() [valops.c] to the address of the "call dummy" code
969 so dummy frames can be easily recognized; also used in wait_for_inferior()
970 [infrun.c]. When not used, it points into the ABI's 'reserved area' */
971
972CORE_ADDR call_dummy_set = 0; /* true if dummy call being done */
973CORE_ADDR call_dummy_start; /* address of call dummy code */
974
975/* this routine routine gets the values of the registers stored in the frame
976 and stores their values into the frame_saved_regs structure. */
977
978void
979frame_find_saved_regs(frame_info, frame_saved_regs)
980 struct frame_info *frame_info;
981 struct frame_saved_regs *frame_saved_regs;
982{
983 register CORE_ADDR pc;
984 CORE_ADDR instr;
985 long offset, spdelta = 0;
986 int i, size, reg;
987 int r1_off = -1, fp_off = -1;
988 int framesize;
989
990 bzero (frame_saved_regs, sizeof(*frame_saved_regs));
991
992 if (call_dummy_set && frame_info->pc >= call_dummy_start &&
993 frame_info->pc <= call_dummy_start + CALL_DUMMY_LENGTH)
994 {
995 /* DUMMY frame - all registers stored in order at fp; old sp is
996 at fp + NUM_REGS*4 */
997
998 for (i = 1; i < NUM_REGS; i++) /* skip reg 0 */
67278683
FF		 999 /* the register numbers used in the instruction and the ones used to index
1000 the regs array are not the same -- compensate */
1001 frame_saved_regs->regs[i+R0] = frame_info->frame + i*REGISTER_LENGTH;
2213b721
FF		 1002
1003 call_dummy_set = 0;
1004 return;
1005 }
1006
1007 pc = get_pc_function_start (frame_info->pc);
67278683
FF		 1008 if (pc == NULL)
1009 pc = find_entry_start (frame_info->pc);
1010
2213b721
FF		 1011 if (pc != NULL)
1012 {
1013 instr = (unsigned)(adj_read_memory_integer (pc));
1014 /* Recognize "addu|adds -X,sp,sp" insn. */
1015 if ((instr & 0xEFFF0000) == 0x84420000)
1016 {
1017 framesize = -SIGN_EXT16(instr & 0x0000FFFF);
1018 pc += INSTRUCTION_LENGTH;
1019 instr = (unsigned)(adj_read_memory_integer (pc));
1020 }
1021 }
1022 else
1023 goto punt; /* No frame! */
1024
1025 /* Recognize store of return addr and frame pointer into frame */
1026 for (; ;)
1027 {
1028 if ((instr & 0xFFE0F801) == 0x1C400801) /* st.l r1,X(sp) */
1029 {
1030 r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE));
1031 pc += INSTRUCTION_LENGTH;
1032 instr = (unsigned)(adj_read_memory_integer (pc));
1033 }
1034 else if ((instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */
1035 {
1036 fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE));
1037 pc += INSTRUCTION_LENGTH;
1038 instr = (unsigned)(adj_read_memory_integer (pc));
1039 }
1040 else
1041 break;
1042 }
1043
1044 /* Recognize "addu|adds X,sp,fp" insn. */
1045 if ((instr & 0xEFFF0000) == 0x84430000)
1046 {
1047 spdelta = SIGN_EXT16(instr & 0x0000FFFF);
1048 pc += INSTRUCTION_LENGTH;
1049 instr = (unsigned)(adj_read_memory_integer (pc));
1050 }
1051
1052 /* Now recognize stores into the frame from the registers. */
1053
1054 for (; ;)
1055 {
1056 if ((instr & 0xFFC00003) == 0x1C400001) /* st.l rn,X(fp|sp) */
1057 {
1058 offset = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE));
1059 reg = (instr >> 11) & 0x1F;
1060 if (reg == 0)
1061 break;
1062 if ((instr & 0x00200000) == 0) /* was this using sp? */
1063 if (spdelta != 0) /* and we know sp-fp delta */
1064 offset -= spdelta; /* if so, adjust the offset */
1065 else
1066 break; /* if not, give up */
1067
1068
1069 /* Handle the case where the return address is stored after the fp
1070 is adjusted */
1071
1072 if (reg == 1)
1073 frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + offset;
1074 else
1075 frame_saved_regs->regs[reg+R0] = frame_info->frame + offset;
1076
1077 pc += INSTRUCTION_LENGTH;
1078 instr = (unsigned)(adj_read_memory_integer (pc));
1079 }
1080 else if ((instr & 0xFFC00001) == 0x2C400000) /* fst.y fn,X(fp|sp) */
1081 {
1082 /*
1083 * The number of words in a floating store based on 3 LSB of instr
1084 */
1085 static int fst_sizes[] = {2, 0, 1, 0, 4, 0, 1, 0};
1086
1087 size = fst_sizes[instr & 7];
1088 reg = ((instr >> 16) & 0x1F) + FP0_REGNUM;
1089 if (reg == 0)
1090 break;
1091
1092 if (size > 1) /* align the offset */
1093 offset = SIGN_EXT16(instr & 0x0000FFF8); /* drop 3 bits */
1094 else
1095 offset = SIGN_EXT16(instr & 0x0000FFFC); /* drop 2 bits */
1096
1097 if ((instr & 0x00200000) == 0) /* was this using sp? */
1098 if (spdelta != 0) /* and we know sp-fp delta */
1099 offset -= spdelta; /* if so, adjust the offset */
1100 else
1101 break; /* if not, give up */
1102
1103 for (i = 0; i < size; i++)
1104 {
1105 frame_saved_regs->regs[reg] = frame_info->frame + offset;
1106
1107 offset += REGISTER_LENGTH;
1108 reg++;
1109 }
1110
1111 pc += INSTRUCTION_LENGTH;
1112 instr = (unsigned)(adj_read_memory_integer (pc));
1113 }
1114 else
1115 break;
1116 }
1117
1118 punt: ;
1119 if (framesize != 0 && spdelta != 0)
1120 frame_saved_regs->regs[SP_REGNUM] = frame_info->frame+(framesize-spdelta);
1121 else
1122 frame_saved_regs->regs[SP_REGNUM] = frame_info->frame + 8;
1123
1124 if ((spdelta != 0) && fp_off != -1)
1125 frame_saved_regs->regs[FP_REGNUM] = frame_info->frame - spdelta + fp_off;
1126 else
1127 frame_saved_regs->regs[FP_REGNUM] = frame_info->frame;
1128
1129 if ((spdelta != 0) && r1_off != -1)
1130 frame_saved_regs->regs[PC_REGNUM] = frame_info->frame - spdelta + r1_off;
1131 else
1132 frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + 4;
1133}
1134
1135
1136/* get the frame pointer of the caller.
1137 * note that only routines that have been compiled with
1138 * -g have full (XX)fp style stack frames
1139 * if we are not returning to a non -g caller then we
1140 * return the sp at entry to us as it is the caller's
1141 * frame reference.
1142 */
1143
1144frame_chain(thisframe)
1145 FRAME thisframe;
1146{
1147 CORE_ADDR fp, pc;
1148 CORE_ADDR func_start;
1149 CORE_ADDR instr;
1150 int offset;
1151 CORE_ADDR thisfp = thisframe->frame;
67278683
FF		 1152 struct frame_saved_regs fsr;
1153 CORE_ADDR thissp;
1154
1155 /* get the frame pointer actually sp for a non -g
2213b721
FF		 1156 * for the routine that called us routine
1157 */
1158
1159 BTDEBUG("FRAME_CHAIN(%x)\n",thisframe);
1160
1161 if ( !read_memory_integer (thisframe->frame,sizeof(long)) )
1162 {
1163 return (0);
1164 }
1165
1166 if( ! g_routine(thisframe->pc) ){
67278683
FF		 1167 thissp = get_saved_basereg (thisframe, SP_REGNUM);
1168
2213b721 1169 BTDEBUG( "non g at %x\n",thisframe->pc);
67278683 1170 caller_pc(thisframe->pc, thissp, thisfp,&pc,&fp, 1);
2213b721
FF		 1171 BTDEBUG("caller_pc returned %x %x \n",pc,fp);
1172 return(fp);
1173
1174 }/* else a -g routine */
1175
1176
1177 fp = read_memory_integer (thisfp, sizeof(long));
1178
1179 if (fp < thisfp || fp > (unsigned) STACK_END_ADDR)
1180 {
1181 /* handle the Metaware-type pseudo-frame */
1182
1183 func_start = get_pc_function_start(thisframe->pc);
67278683
FF		 1184 if (func_start == NULL)
1185 func_start = find_entry_start (thisframe->pc);
1186
2213b721
FF		 1187 if (func_start != NULL)
1188 {
1189
1190 instr = (unsigned)(adj_read_memory_integer (func_start));
1191 /* Recognize "addu|adds -X,sp,sp" insn. */
1192 if ((instr & 0xEFFF0000) == 0x84420000)
1193 offset = SIGN_EXT16(instr & 0x0000FFFF);
be9a2362 1194
be9a2362
FF		 1195 }
1196
2213b721
FF		 1197 fp = 0;
1198 if (offset < 0)
1199 fp = thisfp - offset;
be9a2362 1200 }
2213b721
FF		 1201 BTDEBUG("frame_chain returned %d\n",fp);
1202 return(fp);
1203}
1204
1205/* This function returns 1 if there is no stored r1, 0 otherwise.
1206 The function returns 1 if the pc is in a function prologue,
1207 or the function prologue didn't save the return pointer in
1208 the stack frame, 0 otherwise */
1209
1210int no_stored_rp(CORE_ADDR pc)
1211{
1212 CORE_ADDR func_start, prologue_end;
be9a2362 1213
2213b721 1214 func_start = get_pc_function_start(pc);
67278683
FF		 1215 if (func_start == NULL)
1216 func_start = find_entry_start (pc);
1217
2213b721 1218 if (func_start != NULL)
be9a2362 1219 {
2213b721
FF		 1220 prologue_end = func_start;
1221 SKIP_PROLOGUE(prologue_end);
1222 if ( (pc >= func_start) && (pc <= prologue_end))
be9a2362 1223 {
2213b721
FF		 1224 BTDEBUG("no_stored_rp: pc %x is in prologue \n",pc);
1225 return 1;
1226 }
1227 /* otherwise, see if the entry sequence stored the return pointer.
1228 If it didn't, return 1 */
1229 /* Some procedures , at least, store the return pointer AFTER
1230 the prologue sequence, so check for stores from function start to
1231 present pc value. */
1232 if (!has_stored_r1(func_start, pc))
1233 {
1234 BTDEBUG("no_stored_rp, for pc %x, prologue didn't store r1\n",pc);
1235 return 1;
be9a2362
FF		 1236 }
1237 }
2213b721
FF		 1238 BTDEBUG("no_stored_rp for pc %x return pointer was stored \n", pc);
1239
1240 return 0;
1241}
1242
1243/* get the PC of the caller */
1244CORE_ADDR frame_saved_pc(frame_struct)
1245FRAME frame_struct;
1246{
1247 CORE_ADDR frame;
1248 CORE_ADDR pc;
1249 CORE_ADDR pc1;
1250 CORE_ADDR sp ;
1251 CORE_ADDR fp;
67278683 1252 struct frame_saved_regs fsr;
2213b721
FF		 1253
1254 frame = frame_struct->frame;
1255 pc = frame_struct->pc;
67278683
FF		 1256
1257
2213b721
FF		 1258 BTDEBUG("frame_saved_pc input: frame %x, pc %x",
1259 frame, pc);
1260
1261 /* First see if this is the current frame. If it is, return the value in r1,
1262 as it may not have been stored */
1263
1264 fp = read_register(FP_REGNUM);
1265
1266 /* check to see if we are in an entry sequence, where the return pointer has not yet been stored */
1267 if (fp == frame && no_stored_rp(pc))
1268 {
1269 pc = read_register(RP_REGNUM);
1270 frame_struct->rp = pc;
1271 }
1272 else if( ! g_routine(pc) )
1273 {
67278683
FF		 1274 sp = get_saved_basereg (frame_struct, SP_REGNUM);
1275
1276 caller_pc(pc,sp,frame_struct->frame, &pc,&frame, 0);
2213b721
FF		 1277 }
1278 else
1279 {
1280
1281 pc = read_memory_integer (frame + 4, sizeof(long));
1282
67278683 1283 if (inside_entry_file(pc))
2213b721
FF		 1284 {
1285
67278683 1286 BTDEBUG("pc %x outside entry file \n",pc);
2213b721
FF		 1287
1288 pc1 = read_memory_integer (frame, sizeof(long));
1289
67278683 1290 if (!inside_entry_file(pc1))
2213b721
FF		 1291 pc = pc1;
1292 else
1293 pc = 0;
1294 }
1295 }
1296 BTDEBUG(" returning pc %x\n", CLEAN_PC(pc));
1297 return(CLEAN_PC(pc));
1298
1299 }
1300
1301/* Pass arguments to a function in the inferior process - ABI compliant
67278683
FF		 1302 Modified by Peggy Fieland ([email protected]) to account
1303 for newer ABI conventions. Note that now, unfortunately, we MUST KNOW
1304 if we expect a float or a double. For now, we will assume that the
1305 caller of this routine has the types of these arguments correct....
1306 NOTE THAT THIS ROUTINE DOES NO ARGUMENT COERCION -- it's all in the
1307 caller.
1308 Modified by Peggy Fieland to handle memory argument lists.
1309 */
2213b721 1310
67278683
FF		 1311#define IS_EVEN_REG(fl) (((fl - FP0_REGNUM)%2) == 0)
1312CORE_ADDR
1313pass_function_arguments(args, nargs, struct_return, struct_addr, sp)
2213b721
FF		 1314 value *args;
1315 int nargs;
1316 int struct_return;
67278683
FF		 1317 CORE_ADDR struct_addr;
1318 CORE_ADDR sp;
2213b721 1319{
67278683
FF		 1320 int ireg = (struct_return) ? R17 : R16;
1321 int freg = F8;
2213b721
FF		 1322 int i;
1323 struct type *type;
1324 value arg;
67278683
FF		 1325 signed long tmp;
1326 unsigned long ul_tmp;
1327 signed short s_tmp;
1328 unsigned short us_tmp;
1329 signed char c_tmp;
1330 unsigned char uc_tmp;
1331 CORE_ADDR arg_ptr;
1332 int len;
1333
1334 if (struct_return)
1335 {
1336 write_register(R16, struct_addr);
1337 }
1338
1339 arg_ptr = sp; /* Space was allocated for memory argument list in i860_arg_coerce */
1340
1341 /* Loop through the arguments, putting the values in a register or memory as appropriate. */
2213b721
FF		 1342
1343 for (i = 0; i < nargs; i++)
be9a2362 1344 {
67278683 1345 arg = args[i];
2213b721 1346 type = VALUE_TYPE(arg);
67278683 1347 len = TYPE_LENGTH(type);
2213b721 1348 if (type == builtin_type_double)
be9a2362 1349 {
67278683
FF		 1350 /* see ABI . Note freg MUST BE INCREMENTED even if arg goes into the
1351 memory argument list for this code to work correctly for subsequent
1352 arguments. */
1353 if (!IS_EVEN_REG(freg))
1354 freg += 1;
1355 /* see if argument can be put in a register, or whether it must go
1356 into the memory argument list */
1357 if (freg < F8 + NUM_FLOAT_ARG_REGS)
1358 {
1359 /* It can go in a register */
1360 bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(double));
1361 write_register_bytes(REGISTER_BYTE(freg), (char *) &tmp, TYPE_LENGTH(type));
1362 freg += 2;
1363 }
1364 else
1365 {
1366 /* It goes into memory argument list */
1367 arg_ptr = ALIGN_ARG( arg_ptr, sizeof(double));
1368 write_memory (arg_ptr, VALUE_CONTENTS (arg), len);
1369 arg_ptr += len;
1370 }
1371
1372 }
1373 else if (type == builtin_type_float)
1374 {
1375 if (freg < F8 + NUM_FLOAT_ARG_REGS)
1376 {
1377 /* It can go in a register */
1378 bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(long));
1379 write_register_bytes (REGISTER_BYTE(freg), (char *) &tmp, TYPE_LENGTH(type));
1380 freg++;
1381 }
1382 else
1383 {
1384 /* It goes into the memory argument list */
1385 arg_ptr = ALIGN_ARG(arg_ptr, sizeof(float));
1386 write_memory (arg_ptr, VALUE_CONTENTS (arg), len);
1387 arg_ptr += len;
1388 }
2213b721
FF		 1389 }
1390 else
1391 {
67278683
FF		 1392 /* All structs are passed by value, and hence they all go into the memory
1393 argument list (see ABI); otherwise, as above, see if we have run
1394 out of registers */
1395
1396 /* Cast value correctly so we can load it into a register or into the
1397 memory argument list -- see ABI */
1398 if (TYPE_LENGTH(type) < sizeof(long))
1399 {
1400 if (TYPE_FLAGS(type) & TYPE_FLAG_UNSIGNED)
1401 arg = value_cast(builtin_type_unsigned_int, arg);
1402 else
1403 arg = value_cast (builtin_type_int, arg);
1404 type = VALUE_TYPE(arg);
1405 len = TYPE_LENGTH(type);
1406 }
1407
1408 if ((TYPE_CODE(type) == TYPE_CODE_STRUCT) || (ireg >= R16 + NUM_INT_ARG_REGS))
1409 {
1410 /* It goes into the memory argument list. Minimum alignment requirements
1411 are on a 4-byte boundary */
1412
1413 if ((TYPE_CODE(type) == TYPE_CODE_INT) ||
1414 (TYPE_CODE(type) == TYPE_CODE_ENUM) ||
1415 (TYPE_CODE(type) == TYPE_CODE_CHAR) ||
1416 (TYPE_CODE(type) == TYPE_CODE_BOOL))
1417 arg_ptr = ALIGN_ARG(arg_ptr, len);
1418 else
1419 arg_ptr = ALIGN_ARG (arg_ptr, sizeof(long)); /* align on 4-byte boundary */
1420 write_memory (arg_ptr, VALUE_CONTENTS (arg), len);
1421 arg_ptr += len;
1422 }
1423 else
1424 {
1425
1426 bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(long));
1427 write_register(ireg, tmp);
1428 ireg++;
1429 }
1430
be9a2362 1431 }
be9a2362 1432 }
67278683
FF		 1433
1434
1435 return (sp);
1436
2213b721
FF		 1437}
1438
1439
1440#define SPACES " "
1441#define P_SPACES " "
1442#define BYTE 0xff
1443
1444int screen_lines=24;
1445
1446char *spec_reg[] = {
1447 "fsr", "db", "dirbase", "fir", "psr", "epsr",
1448};
1449
1450char *doro_reg[] = {
1451 "scp", "cbsp", "pt_cs", "intmsk", "intack",
1452};
1453#define NREGS 32
1454
67278683 1455
2213b721
FF		 1456get_reg(regno)
1457{
1458 char raw_buffer[32];
1459 int addr;
1460 int virtual_buffer;
67278683
FF		 1461
1462 /* NOTE that only integer and floating point registers can be relative to a frame */
1463
1464 if ((regno >= R0) && (regno <= F31)) /* user register */
1465 read_relative_register_raw_bytes (regno, raw_buffer);
1466 else
1467 bcopy (&registers[regno << 2], raw_buffer, sizeof (long));
1468
2213b721
FF		 1469 REGISTER_CONVERT_TO_VIRTUAL (addr, raw_buffer, &virtual_buffer);
1470 return(virtual_buffer);
be9a2362 1471}
2213b721
FF		 1472
1473
1474#if 0
1475/* This routine is uncalled. Remove it sometime. */
be9a2362
FF		 1476
1477/*
1478 ** Figure out whether we are in a delayed slot and if so then take necessary
1479 ** action to resume properly - remember trap pre-empts instruction
1480 */
1481int
1482 wasabranch (addr, nextpc, ss)
1483CORE_ADDR addr, *nextpc;
1484int ss;
1485{
2213b721 1486 CORE_ADDR nextadr, instr;
be9a2362
FF		 1487 int val = not_branch;
1488 long offset; /* Must be signed for sign-extend */
1489
1490 if (ss)
1491 {
1492 if (INDIM)
1493 {
2213b721
FF		 1494 nextadr = CORADR((int)(addr + INSTRUCTION_LENGTH*2));
1495 instr = (unsigned)(adj_read_memory_integer (CORADR(addr)));
be9a2362
FF		 1496 }
1497 else
1498 {
2213b721
FF		 1499 nextadr = addr + INSTRUCTION_LENGTH;
1500 instr = (unsigned)(adj_read_memory_integer (addr));
be9a2362
FF		 1501 }
1502 } else {
1503 if (ISDIM(addr))
1504 {
1505 nextadr = CORADR(addr);
2213b721 1506 instr = (unsigned)(adj_read_memory_integer (nextadr));
be9a2362
FF		 1507 }
1508 else
1509 {
1510 nextadr = addr;
2213b721 1511 instr = (unsigned)(adj_read_memory_integer (addr));
be9a2362
FF		 1512 }
1513 }
1514
1515
1516 if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */
1517 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
1518 {
1519 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
1520 val = uncond_d;
1521 else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */
1522 val = cond_d;
1523 else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */
1524 val = cond;
1525
1526 offset = (instr & 0x03ffffff);
1527 if (offset & 0x02000000) /* sign extend? */
1528 offset |= 0xFC000000;
1529 nextadr += (offset << 2);
1530 }
1531 else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */
1532 (instr & 0xFC000000) == 0x40000000) /* bri */
1533 {
1534 if (ss)
1535 {
1536 val = uncond_d;
1537 offset = ((instr & 0x0000F800) >> 11);
1538 nextadr = (read_register(offset) & 0xFFFFFFFC);
1539 } else {
1540 val = uncond_d;
1541 }
1542 }
1543 else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */
1544 {
1545 val = cond;
1546
1547 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
1548 nextadr += (offset << 2);
1549 }
1550 else if ((instr & 0xFC000000) == 0xB4000000) /* bla */
1551 {
1552 val = cond_d;
1553
1554 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
1555 nextadr += (offset << 2);
1556 }
1557
1558 *nextpc = nextadr;
1559 return val;
1560}
2213b721 1561#endif
be9a2362 1562
be9a2362 1563
2213b721 1564/* i860-specific routine to print the register set. Note that we ALWAYS print information
67278683
FF		 1565 on the floating point registers, so we ignore the parameter fpregs.
1566 NOTE also that only integer and floating point registers can be relative to a frame --
1567 see subroutine get_reg (above ) */
1568
2213b721 1569void i860_do_registers_info(regnum,fpregs)
be9a2362
FF		 1570 int regnum;
1571 int fpregs;
1572{
1573 register int i;
1574 unsigned int val;
1575 unsigned int j,k;
1576
2213b721 1577
be9a2362
FF		 1578 if (regnum == -1)
1579 printf_filtered (
1580 "Register Contents (relative to selected stack frame)\n\n");
1581
1582 if (regnum != -1) /* print one register */
1583 {
67278683 1584 val = get_reg(regnum);
be9a2362
FF		 1585 printf("%-4s 0x%08x\t", reg_names[regnum], val);
1586 printf("\n\t"); fflush(stdout);
1587 }
1588 else /* print all registers */
1589 {
1590
1591 printf("\n Control/Status Registers :- \n\t");
1592 for (j=0; j<=DB; j++)
1593 {
67278683 1594 val = get_reg(j);
be9a2362
FF		 1595 printf("%-4s 0x%08x\t", reg_names[j], val);
1596 }
1597 printf("\n\t"); fflush(stdout);
1598
1599 /* EPSR */
67278683 1600 val = get_reg(EPSR);
be9a2362
FF		 1601 printf("%-4s 0x%08x\t", reg_names[EPSR], val);
1602
1603 /* FSR */
67278683 1604 val = get_reg(FSR);
be9a2362
FF		 1605 printf("%-4s 0x%08x\t", reg_names[FSR], val);
1606
1607 /* CCR */
67278683 1608 val = get_reg(CCR);
be9a2362
FF		 1609 printf("%-4s 0x%08x\t", reg_names[CCR], val);
1610 /* BEAR*/
67278683 1611 val = get_reg(BEAR);
be9a2362
FF		 1612 printf("%-4s 0x%08x\t", reg_names[BEAR], val);
1613
1614
1615#ifdef JIM_ADD_PRIV
1616 for (j=P0; j<=P3; j++)
1617 {
67278683 1618 val = get_reg(j);
be9a2362
FF		 1619 printf("%-4s 0x%08x\t", reg_names[j], val);
1620 }
1621#endif
1622
1623 printf("\n Integer Registers :- \n\t");
1624 for (j=R0; j<=R31; j++)
1625 {
2213b721 1626 if (j != IREGS && (j % REGISTER_LENGTH == 0))
be9a2362
FF		 1627 {
1628 printf("\n\t"); fflush(stdout);
1629 }
67278683 1630 val = get_reg(j);
be9a2362
FF		 1631 printf("%-4s 0x%08x\t", reg_names[j], val);
1632 }
1633
1634 printf("\n Floating Registers :- \n\t");
1635 for (j=F0; j<=F31; j++)
1636 {
2213b721 1637 if (j != FREGS && (j % REGISTER_LENGTH == 0))
be9a2362
FF		 1638 {
1639 printf("\n\t"); fflush(stdout);
1640 }
67278683 1641 val = get_reg(j);
be9a2362
FF		 1642 printf("%-4s 0x%08x\t", reg_names[j], val);
1643 }
1644
1645 printf("\n Special Registers :- \n\t");
1646 for (j=SPC_KI; j<=SPC_MERGE; j+=2)
1647 {
1648 unsigned int valh;
1649 if (j == SPC_T)
1650 {
1651 printf("\n\t"); fflush(stdout);
1652 }
67278683
FF		 1653 val = get_reg(j);
1654 valh = get_reg(j+1);
be9a2362
FF		 1655 printf("%-6s 0x%08x %08x\t", reg_names[j], val,valh);
1656 }
1657
1658 printf("\n Graphics Pipeline :- \n");
1659 {
2213b721 1660 unsigned int valh;
be9a2362 1661 j = PSV_I1;
67278683
FF		 1662 val = get_reg(j);
1663 valh = get_reg(j+1);
be9a2362
FF		 1664 printf("\t\t\t%-8s 0x%08x %08x \n", reg_names[j], val,valh);
1665 }
1666
1667 printf(" Memory Load Pipeline :- \n");
2213b721 1668 for (j=PSV_L1; j<=PSV_L3; j+=REGISTER_LENGTH)
be9a2362
FF		 1669 {
1670 unsigned int valh, val2,val3;
67278683
FF		 1671
1672 val = get_reg(j);
1673 valh = get_reg(j+1);
1674 val2 = get_reg(j+2);
1675 val3 = get_reg(j+3);
1676
be9a2362
FF		 1677 printf("\t\t%-8s 0x%08x %08x %08x %08x\n", reg_names[j],
1678 val,valh,val2,val3);
1679 }
1680
1681 printf("\n Adder Pipeline :-\t\tMultiplier Pipeline :-\t\tFSR results :-\n");
1682 for (i=PSV_FSR1,j=PSV_A1,k=PSV_M1; j<=PSV_A3; i++,j+=2,k+=2)
1683 {
1684 unsigned int valh,val2,val3,val4;
67278683
FF		 1685
1686 val4 = get_reg(i);
1687 val = get_reg(j);
1688 valh = get_reg(j+1);
1689 val2 = get_reg(k);
1690 val3 = get_reg(k+1);
1691
be9a2362
FF		 1692 printf(" %-4s 0x%08x %08x\t", reg_names[j], val,valh);
1693 printf("%-4s 0x%08x %08x\t", reg_names[k], val2,val3);
1694 printf("%-4s 0x%08x\n", reg_names[i], val4);
1695 }
1696
1697 }
1698
1699
1700}
1701
be9a2362 1702
be9a2362
FF		 1703
1704/* The following set of routines was adapted from existing code previously
1705 in an i860-specific version of breakpoint.c by Peggy Fieland
1706 ([email protected]) */
2213b721
FF		 1707/* routines to set a data breakpoint by setting the value in the DB register.
1708 Note that "hitting" the breakpoint will generate a data access trap. We
1709 do not have a special trap handler. */
be9a2362
FF		 1710unsigned int dbrkval, dbrkmod;
1711void i860_dbrk_breakpoint()
1712{
1713 BTDEBUG("i860_dbrk_breakpoint was called , dbrkval %x\n", dbrkval);
1714
2213b721 1715 if (dbrkval != 0)
be9a2362
FF		 1716 {
1717 *(int *)&registers[DB<<2] = dbrkval;
1718 }
1719 else
1720 {
1721 *(int *)&registers[DB<<2] = 0;
1722 }
1723
1724 *(int *)&registers[PSR<<2] &= ~3;
1725 *(int *)&registers[PSR<<2] |= dbrkmod;
1726
1727 store_inferior_registers(DB);
1728 store_inferior_registers(PSR);
1729
1730}
1731
2213b721 1732/* set a "read" data breakpoint. */
be9a2362 1733void
67278683 1734d_ro_break_command(char *arg, int num)
be9a2362
FF		 1735{
1736 dbrkval = strtoul(arg, NULL, 0);
1737 dbrkmod = 0x01;
2213b721 1738 BTDEBUG(" ro_dbreak - %x %x\n", dbrkval, dbrkmod);
be9a2362
FF		 1739}
1740
2213b721 1741/* set a "write" data breakpoint. */
be9a2362 1742void
67278683 1743d_wo_break_command(char *arg, int num)
be9a2362
FF		 1744{
1745 dbrkval = strtoul(arg, NULL, 0);
1746 dbrkmod = 0x02;
2213b721 1747 BTDEBUG(" wo_dbreak - %x %x\n", dbrkval, dbrkmod);
be9a2362
FF		 1748}
1749
2213b721 1750/* set a "read/write" data breakpoint. */
be9a2362 1751void
67278683
FF		 1752d_rw_break_command(char *arg, int num)
1753{
1754 dbrkval = strtoul(arg, NULL, 0);
1755 dbrkmod = 0x03;
1756 BTDEBUG(" rw_dbreak - %x %x\n", dbrkval, dbrkmod);
1757 }
be9a2362 1758
2213b721 1759/* clear data breakpoint. */
67278683
FF		 1760 void clear_dbreak(char *arg, int num)
1761 {
1762 dbrkval = 0;
1763 dbrkmod = 0;
1764 }
1765
1766/* i860-specific breakpoint initialization. Includes adding the
1767i860-specific data breakpoint commands. */
1768void i860_init_breakpoints()
1769{
be9a2362
FF		 1770 dbrkval = dbrkmod = 0;
1771 add_com ("dbro", class_breakpoint, d_ro_break_command,
1772 "Set a data breakpoint READ ONLY, 32-bit data element.");
1773 add_com ("dbwo", class_breakpoint, d_wo_break_command,
1774 "Set a data breakpoint WRITE ONLY, 32-bit data element.");
1775 add_com ("dbrw", class_breakpoint, d_rw_break_command,
1776 "Set a data breakpoint READ/WRITE, 32-bit data element.");
1777 add_com ("dclear", class_breakpoint, clear_dbreak,
1778 "clear the current data breakpoint.");
1779 add_com_alias ("dc", "dclear", class_breakpoint, 1);
1780
1781}
1782
2213b721 1783/* i860-specific code to insert a breakpoint. */
be9a2362
FF		 1784int i860_insert_breakpoint(b)
1785struct breakpoint *b;
1786{
1787 int val;
67278683
FF		 1788 int *shadow0, *shadow1, *shadow2, *shadow3;
1789
1790 shadow0 = (int *)&b->shadow_contents[0];
1791 shadow1 = (int *)&b->shadow_contents[4];
1792 shadow2 = (int *)&b->shadow_contents[8];
1793 shadow3 = (int *)&b->shadow_contents[12];
be9a2362
FF		 1794
1795 place_brk( b->address, BREAK_MODE, b );
67278683 1796
be9a2362
FF		 1797 if (b->mode == DIM)
1798 {
1799
67278683 1800 adj_read_memory (b->act_addr[0], shadow0, INSTRUCTION_LENGTH);
2213b721
FF		 1801 val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH);
1802 if (val != 0 ) return val;
67278683 1803 adj_read_memory (b->act_addr[1], shadow1, INSTRUCTION_LENGTH);
2213b721
FF		 1804 /* val = adj_write_memory (b->act_addr[1], float_insn, INSTRUCTION_LENGTH); */
1805 if (val != 0) return val;
be9a2362
FF		 1806 }
1807 else
1808 {
67278683 1809 adj_read_memory (b->act_addr[0], shadow0, INSTRUCTION_LENGTH);
2213b721 1810 val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH);
be9a2362 1811 }
2213b721 1812 if (b->address1 != 0)
be9a2362
FF		 1813 {
1814 if (b->mode == DIM)
1815 {
1816
67278683 1817 adj_read_memory (b->act_addr[2], shadow2, INSTRUCTION_LENGTH);
2213b721 1818 val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH);
be9a2362 1819 if (val) return val;
67278683 1820 adj_read_memory (b->act_addr[3], shadow3, INSTRUCTION_LENGTH);
2213b721
FF		 1821 /* val = adj_write_memory (b->act_addr[3], float_insn, INSTRUCTION_LENGTH); */
1822 if (val != 0) return val;
be9a2362
FF		 1823 }
1824 else
1825 {
67278683 1826 adj_read_memory (b->act_addr[2], shadow0, INSTRUCTION_LENGTH);
2213b721 1827 val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH);
be9a2362
FF		 1828 }
1829 }
2213b721 1830 if (val != 0)
be9a2362 1831 return val;
67278683 1832
be9a2362
FF		 1833 b->inserted = 1;
1834 return 0;
1835}
1836
1837int i860_remove_breakpoint(b)
1838struct breakpoint *b;
1839{
1840 int val;
67278683
FF		 1841 int *shadow0, *shadow1, *shadow2, *shadow3;
1842
1843 shadow0 = (int *)&b->shadow_contents[0];
1844 shadow1 = (int *)&b->shadow_contents[4];
1845 shadow2 = (int *)&b->shadow_contents[8];
1846 shadow3 = (int *)&b->shadow_contents[12];
1847
be9a2362
FF		 1848
1849 if (b->inserted)
1850 {
1851 if (b->mode == DIM)
1852 {
67278683 1853 val =adj_write_memory (b->act_addr[0], shadow0,
2213b721 1854 INSTRUCTION_LENGTH);
67278683 1855 val =adj_write_memory (b->act_addr[1],shadow1,
2213b721
FF		 1856 INSTRUCTION_LENGTH);
1857 if (b->address1 != NULL)
be9a2362 1858 {
67278683 1859 val =adj_write_memory (b->act_addr[2],shadow2,
2213b721 1860 INSTRUCTION_LENGTH);
67278683 1861 val =adj_write_memory (b->act_addr[3], shadow3,
2213b721 1862 INSTRUCTION_LENGTH);
be9a2362
FF		 1863 }
1864 }
1865 else
1866 {
67278683 1867 val =adj_write_memory (b->act_addr[0], shadow0,
2213b721
FF		 1868 INSTRUCTION_LENGTH);
1869 if (b->address1 != NULL)
be9a2362 1870 {
67278683 1871 val =adj_write_memory (b->act_addr[2],shadow0,
2213b721 1872 INSTRUCTION_LENGTH);
be9a2362
FF		 1873 }
1874 }
2213b721 1875 if (val != 0)
be9a2362
FF		 1876 return val;
1877 b->inserted = 0;
be9a2362
FF		 1878 }
1879
1880 return 0;
1881
1882
1883}
1884
1885
1886#ifdef USE_PROC_FS /* Target dependent support for /proc */
1887
1888#include <sys/procfs.h>
1889
1890/* The following routines were added by Peggy Fieland ([email protected])
1891They were adapted from the m-68k versions of the routines .*/
1892
1893/* Given a pointer to a floating point register set in /proc format
1894 (fpregset_t *), unpack the register contents and supply them as gdb's
1895 idea of the current floating point register values. */
1896
1897void
1898supply_fpregset (fpregsetp)
1899fpregset_t *fpregsetp;
1900{
1901 register int regno;
1902
1903 BTDEBUG("supply_fregset called \n");
1904
1905 for (regno = F0 ; regno <= F31 ; regno++)
1906 {
1907 supply_register (regno, (char *) &(fpregsetp -> fpu.r_freg[regno-F0]));
1908 }
1909}
1910
1911/* Given a pointer to a floating point register set in /proc format
1912 (fpregset_t *), update the register specified by REGNO from gdb's idea
1913 of the current floating point register set. If REGNO is -1, update
1914 them all. */
1915
1916void
1917fill_fpregset (fpregsetp, regno)
1918fpregset_t *fpregsetp;
1919int regno;
1920{
1921 int regi;
1922 char *to;
1923 char *from;
1924 extern char registers[];
1925 BTDEBUG("fill_fregset regno %d\n",regno);
1926
1927 for (regi = F0 ; regi <= F31 ; regi++)
1928 {
1929 if ((regno == -1) || (regno == regi))
1930 {
1931 from = (char *) &registers[REGISTER_BYTE (regi)];
1932 to = (char *) &(fpregsetp -> fpu.r_freg[regi-F0]);
1933 bcopy (from, to, REGISTER_RAW_SIZE (regno));
1934 }
1935 }
1936}
1937
1938
1939/* Given a pointer to a general register set in /proc format (gregset_t *),
1940 unpack the register contents and supply them as gdb's idea of the current
1941 register values. */
1942
1943void
1944supply_gregset (gregsetp)
1945gregset_t *gregsetp;
1946{
1947 register int regno;
1948 register greg_t *regp = (greg_t *) gregsetp;
1949
1950 BTDEBUG("supply_gregset called \n");
1951
1952 for (regno = 0 ; regno <= R31 ; regno++)
1953 {
1954 supply_register (regno, (char *) (regp + regno));
1955 }
1956}
1957
2213b721
FF		 1958/* Given a pointer to a general register set in /proc format (gregset_t *),
1959 update the register specified by REGNO from gdb's idea
1960 of the current general register set. If REGNO is -1, update
1961 them all. */
1962
be9a2362
FF		 1963void
1964fill_gregset (gregsetp, regno)
1965gregset_t *gregsetp;
1966int regno;
1967{
1968 int regi;
1969 extern char registers[];
1970 register greg_t *regp = (greg_t *) gregsetp;
1971 BTDEBUG("fill_gregset regno %d \n",regno);
1972
1973 for (regi = 0 ; regi <= R31 ; regi++)
1974 {
1975 if ((regno == -1) || (regno == regi))
1976 {
1977 *(regp + regi) = *(int *) &registers[REGISTER_BYTE (regi)];
1978 }
1979
1980 }
1981}
1982#endif
67278683
FF		 1983
1984
1985/* Push an empty stack frame, to record the current PC, etc. */
1986/* We have this frame with fp pointing to a block where all GDB-visible
1987 registers are stored in the order GDB knows them, and sp at the next
1988 alignment point below fp. Note: fp + NUM_REGS*4 was the old sp
1989 */
1990extern CORE_ADDR text_end;
1991CORE_ADDR dummy_start_addr;
1992void i860_push_frame()
1993{
1994 register CORE_ADDR old_fp = read_register(FP_REGNUM);
1995 register CORE_ADDR old_sp = read_register(SP_REGNUM);
1996 register CORE_ADDR fp ;
1997 extern char registers[];
1998
1999 fp = old_sp - REGISTER_BYTES;
2000 write_memory(fp, registers, REGISTER_BYTES); /* write out old register values */
2001 /* reset FP and SP */
2002 write_register(FP_REGNUM, fp);
2003 write_register(SP_REGNUM, (fp &~ 15)); /* re-align */
2004 call_dummy_set = 1;
2005}
2006/* Discard from the stack the innermost frame,
2007 restoring all saved registers. */
2008
2009void i860_pop_frame()
2010{ register FRAME frame = get_current_frame ();
2011 register CORE_ADDR fp;
2012 struct frame_info *fi;
2013 int i;
2014
2015 fi = get_frame_info (frame);
2016 fp = fi->frame;
2017
2018 if (call_dummy_set && fi -> pc >= call_dummy_start &&
2019 fi -> pc <= call_dummy_start + CALL_DUMMY_LENGTH)
2020 {
2021
2022 read_memory(fp, registers, REGISTER_BYTES);
2023
2024 target_store_registers(-1);
2025
2026 {
2027 /* since we stomped on code that will be executed when we exit the program,
2028 restore it. */
2029 extern REGISTER_TYPE call_save_code[4];
2030
2031 write_memory (call_dummy_start, (char *) call_save_code, 16);
2032
2033 }
2034 call_dummy_set = 0;
2035 }
2036 else
2037 {
2038 register int regnum;
2039 struct frame_saved_regs fsr;
2040 char raw_buffer[12];
2041
2042 get_frame_saved_regs (fi, &fsr);
2043 for (regnum = FP0_REGNUM + 31; regnum >= FP0_REGNUM; regnum--)
2044 if (fsr.regs[regnum])
2045 write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
2046 for (regnum = R31; regnum >= 1; regnum--)
2047 if (fsr.regs[regnum])
2048 if (regnum != SP_REGNUM)
2049 write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
2050 else
2051 write_register (SP_REGNUM, fsr.regs[SP_REGNUM]);
2052 if (fsr.regs[PS_REGNUM])
2053 write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
2054 if (fsr.regs[FPS_REGNUM])
2055 write_register (FPS_REGNUM, read_memory_integer (fsr.regs[FPS_REGNUM],4));
2056 if (fsr.regs[PC_REGNUM])
2057 write_register (PC_REGNUM,CLEAN_PC( read_memory_integer (fsr.regs[PC_REGNUM], 4)));
2058 }
2059
2060 flush_cached_frames ();
2061
2062 set_current_frame (create_new_frame (read_register (FP_REGNUM),
2063 read_pc ()));
2064
2065}
2066
2067CORE_ADDR i860_arg_coerce(nargs, args, struct_return, sp)
2068 int nargs;
2069 value *args;
2070 int struct_return;
2071 CORE_ADDR sp;
2072{
2073
2074 register int scalar;
2075 register enum type_code code2;
2076 register struct type *type;
2077 int i;
2078 value arg;
2079 int num_int_args = 0;
2080 int num_float_args = 0;
2081 int size = 0;
2082 CORE_ADDR arg_ptr;
2083
2084 /* if we return a structure, it's address is in R16, and thus it uses up one of the integer
2085 argument registers. See the ABI. */
2086 if (struct_return)
2087 num_int_args += 1;
2088
2089 /* loop to do the right thing with all the arguments and calculate the size of the memory
2090 argument list. We keep count of the number of integer and the number of float parameters,
2091 as well as the size of the memory argument list. */
2092
2093 for (i = 0; i < nargs; i++)
2094 {
2095
2096 /* NOTE that this is all hunky dory in spite of the fact that we don't actually
2097 have the signature of the called procedure EXCEPT if we are passing in floats!
2098 This is true, since registers are 4 bytes, and the minimum alignment in the
2099 memory argument list is 4 bytes. See the ABI for more gory details. The switch
2100 "ansi-conformant" is an attempt to get around this problem. */
2101
2102 code2 = TYPE_CODE (VALUE_TYPE(args[i]));
2103
2104 /* Only coerce if we've got switch "ansi-conformant" off.
2105 Actually, it's OK ( and probably helpful) to coerce ALL integer arguments
2106 (see comment above), but never mind, we make them the right size in
2107 pass_function_arguments. */
2108
2109 if ((!ansi_conformant) && (code2 != TYPE_CODE_STRUCT))
2110 value_arg_coerce(args[i]);
2111
2112 arg = args[i];
2113 type = VALUE_TYPE(args[i]);
2114
2115 /* All structures are passed by value in the memory argument list. */
2116 if (code2 == TYPE_CODE_STRUCT)
2117 {
2118 size = ALIGN_ARG(size, sizeof(long));
2119 size += TYPE_LENGTH(type);
2120 }
2121 else if (type == builtin_type_float)
2122 {
2123 num_float_args += 1;
2124 if (num_float_args > NUM_FLOAT_ARG_REGS)
2125 {
2126 size = ALIGN_ARG(size, TYPE_LENGTH(type)) ;
2127 size += TYPE_LENGTH(type);
2128 }
2129 }
2130 else if (type == builtin_type_double)
2131 {
2132 /* floating register alignment -- see ABI */
2133 if ((num_float_args%2) != 0)
2134 num_float_args += 1;
2135
2136 num_float_args += 2; /* use up two registers */
2137
2138 if (num_float_args > NUM_FLOAT_ARG_REGS)
2139 {
2140 size = ALIGN_ARG(size, TYPE_LENGTH(type)) ;
2141 size += TYPE_LENGTH(type);
2142 }
2143 }
2144 else
2145 {
2146 int len = max (sizeof(long), TYPE_LENGTH(type));
2147
2148 num_int_args += 1;
2149
2150 if (num_int_args > NUM_INT_ARG_REGS)
2151 {
2152 /* see ABI -- in-memory arguments have AT LEAST word alignment */
2153 if ((TYPE_CODE(type) == TYPE_CODE_INT) ||
2154 (TYPE_CODE(type) == TYPE_CODE_ENUM) ||
2155 (TYPE_CODE(type) == TYPE_CODE_CHAR) ||
2156 (TYPE_CODE(type) == TYPE_CODE_BOOL))
2157 size = ALIGN_ARG(size, len);
2158 else
2159 size = ALIGN_ARG(size, sizeof(long));
2160 size += len;
2161 }
2162 }
2163
2164 }
2165
2166
2167 /* recalculate the stack pointer, leaving enough space for the memory argument list and
2168 realigning the stack pointer. */
2169 if (size != 0)
2170 {
2171 arg_ptr = sp - size;
2172
2173 arg_ptr = arg_ptr & (-16); /* realign stack */
2174 write_register (R28,arg_ptr);
2175 sp = arg_ptr;
2176 }
2177
2178return (sp);
2179
2180}
2181void i860_extract_return_value(type,regbuf,valbuf)
2182struct type *type;
2183char regbuf[REGISTER_BYTES];
2184char *valbuf;
2185{
2186 register int len = TYPE_LENGTH (type);
2187 double tmp_db;
2188 float tmp_flt;
2189
2190 if ((TYPE_CODE(type) == TYPE_CODE_FLT))
2191 {
2192 if (len == sizeof (float))
2193 {
2194 /* FIXME
2195 NOTE that this assumes that the function declaration was ANSI_CONFORMANT --
2196 at the present time I can't think of ANY WAY to disambiguate the two following
2197 cases:
2198 float really_does_return_a_float(float ff)
2199 { ...}
2200 and
2201 float actually_returns_a_double(ff)
2202 float ff;
2203 {...}
2204 */
2205 bcopy ((char *) (regbuf) + REGISTER_BYTE(ADJ_FREG(F8)), (valbuf), TYPE_LENGTH (type)) ;
2206 }
2207 else
2208 bcopy ((char *) (regbuf) + REGISTER_BYTE(F8), (valbuf), TYPE_LENGTH (type)) ;
2209 }
2210 else
2211 bcopy ((char *) (regbuf) + REGISTER_BYTE(R16), (valbuf), TYPE_LENGTH (type));
2212
2213}
2214void i860_store_return_value(type,valbuf)
2215struct type *type;
2216char *valbuf;
2217{
2218 register int len = TYPE_LENGTH (type);
2219 double tmp_db;
2220
2221 if ((TYPE_CODE(type) == TYPE_CODE_FLT) )
2222 {
2223 write_register_bytes (REGISTER_BYTE (F8), valbuf, len);
2224 }
2225 else
2226 write_register_bytes (REGISTER_BYTE (R16), valbuf, TYPE_LENGTH (type));
2227
2228}
ca8820f9 2229
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