]> Git Repo - binutils.git/blame - opcodes/mips-opc.c
projects / binutils.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* som.h (som_symbol_type): Add "stringtab_offset" field.
[binutils.git] / opcodes / mips-opc.c
CommitLineData
45b14705
ILT		 1/* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
111, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21
22#include <stdio.h>
23#include "ansidecl.h"
24#include "opcode/mips.h"
25
26/* Short hand so the lines aren't too long. */
27
2bef2d3e
ILT		 28#define LDD INSN_LOAD_MEMORY_DELAY
29#define LCD INSN_LOAD_COPROC_DELAY
45b14705
ILT		 30#define UBD INSN_UNCOND_BRANCH_DELAY
31#define CBD INSN_COND_BRANCH_DELAY
2bef2d3e
ILT		 32#define COD INSN_COPROC_MOVE_DELAY
33#define CLD INSN_COPROC_MEMORY_DELAY
34#define CBL INSN_COND_BRANCH_LIKELY
9978cd4d 35#define TRAP INSN_TRAP
942a4965 36#define SM INSN_STORE_MEMORY
45b14705
ILT		 37
38#define WR_d INSN_WRITE_GPR_D
39#define WR_t INSN_WRITE_GPR_T
40#define WR_31 INSN_WRITE_GPR_31
41#define WR_D INSN_WRITE_FPR_D
42#define WR_T INSN_WRITE_FPR_T
2bef2d3e 43#define WR_S INSN_WRITE_FPR_S
45b14705
ILT		 44#define RD_s INSN_READ_GPR_S
45#define RD_b INSN_READ_GPR_S
46#define RD_t INSN_READ_GPR_T
47#define RD_S INSN_READ_FPR_S
48#define RD_T INSN_READ_FPR_T
49#define WR_CC INSN_WRITE_COND_CODE
50#define RD_CC INSN_READ_COND_CODE
51#define RD_C0 INSN_COP
52#define RD_C1 INSN_COP
53#define RD_C2 INSN_COP
54#define RD_C3 INSN_COP
55#define WR_C0 INSN_COP
56#define WR_C1 INSN_COP
57#define WR_C2 INSN_COP
58#define WR_C3 INSN_COP
59#define WR_HI INSN_WRITE_HI
60#define WR_LO INSN_WRITE_LO
61#define RD_HI INSN_READ_HI
62#define RD_LO INSN_READ_LO
63
2bef2d3e
ILT		 64#define I2 INSN_ISA2
65#define I3 INSN_ISA3
66
45b14705
ILT		 67/* The order of overloaded instructions matters. Label arguments and
68 register arguments look the same. Instructions that can have either
69 for arguments must apear in the correct order in this table for the
70 assembler to pick the right one. In other words, entries with
71 immediate operands must apear after the same instruction with
72 registers.
73
74 Many instructions are short hand for other instructions (i.e., The
75 jal <register> instruction is short for jalr <register>). */
76
77const struct mips_opcode mips_opcodes[] = {
78/* These instructions appear first so that the disassembler will find
79 them first. The assemblers uses a hash table based on the
80 instruction name anyhow. */
81{"nop", "", 0x00000000, 0xffffffff, 0 },
82{"li", "t,j", 0x24000000, 0xffe00000, WR_t }, /* addiu */
83{"li", "t,i", 0x34000000, 0xffe00000, WR_t }, /* ori */
84{"li", "t,I", 0, (int) M_LI, INSN_MACRO },
85{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s }, /* addu */
86{"b", "p", 0x10000000, 0xffff0000, UBD }, /* beq 0,0 */
9978cd4d 87{"b", "p", 0x04010000, 0xffff0000, UBD }, /* bgez 0 */
a5ba0d3f 88{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31 }, /* bgezal 0 */
45b14705
ILT		 89
90{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO },
91{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S },
92{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S },
45b14705
ILT		 93{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t },
94{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO },
95{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T },
96{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T },
97{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s },
98{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s },
99{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t },
100{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO },
101{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t },
102{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO },
103{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s },
104/* b is at the top of the table. */
105/* bal is at the top of the table. */
106{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 107{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 108{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 109{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 110{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 111{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 112{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC },
2bef2d3e 113{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 114{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC },
2bef2d3e 115{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 116{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC },
2bef2d3e 117{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 118{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC },
2bef2d3e 119{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC|I2 },
45b14705 120{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC },
2bef2d3e
ILT		 121{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC|I2 },
122{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 123{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 124{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t },
125{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO },
2bef2d3e
ILT		 126{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t|I2},
127{"beql", "s,I,p", 2, (int) M_BEQL_I, INSN_MACRO },
45b14705
ILT		 128{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO },
129{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO },
2bef2d3e
ILT		 130{"bgel", "s,t,p", 2, (int) M_BGEL, INSN_MACRO },
131{"bgel", "s,I,p", 2, (int) M_BGEL_I, INSN_MACRO },
45b14705
ILT		 132{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO },
133{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO },
2bef2d3e
ILT		 134{"bgeul", "s,t,p", 2, (int) M_BGEUL, INSN_MACRO },
135{"bgeul", "s,I,p", 2, (int) M_BGEUL_I, INSN_MACRO },
45b14705 136{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s },
9978cd4d 137{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s|I2 },
a5ba0d3f 138{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31 },
9978cd4d 139{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 140{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO },
141{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO },
2bef2d3e
ILT		 142{"bgtl", "s,t,p", 2, (int) M_BGTL, INSN_MACRO },
143{"bgtl", "s,I,p", 2, (int) M_BGTL_I, INSN_MACRO },
45b14705
ILT		 144{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO },
145{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO },
2bef2d3e
ILT		 146{"bgtul", "s,t,p", 2, (int) M_BGTUL, INSN_MACRO },
147{"bgtul", "s,I,p", 2, (int) M_BGTUL_I, INSN_MACRO },
45b14705 148{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 149{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 150{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO },
151{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO },
2bef2d3e
ILT		 152{"blel", "s,t,p", 2, (int) M_BLEL, INSN_MACRO },
153{"blel", "s,I,p", 2, (int) M_BLEL_I, INSN_MACRO },
45b14705
ILT		 154{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO },
155{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO },
2bef2d3e
ILT		 156{"bleul", "s,t,p", 2, (int) M_BLEUL, INSN_MACRO },
157{"bleul", "s,I,p", 2, (int) M_BLEUL_I, INSN_MACRO },
45b14705 158{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 159{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 160{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO },
161{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO },
2bef2d3e
ILT		 162{"bltl", "s,t,p", 2, (int) M_BLTL, INSN_MACRO },
163{"bltl", "s,I,p", 2, (int) M_BLTL_I, INSN_MACRO },
45b14705
ILT		 164{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO },
165{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO },
2bef2d3e
ILT		 166{"bltul", "s,t,p", 2, (int) M_BLTUL, INSN_MACRO },
167{"bltul", "s,I,p", 2, (int) M_BLTUL_I, INSN_MACRO },
45b14705 168{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 169{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s|I2 },
a5ba0d3f 170{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31 },
9978cd4d 171{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|I2 },
2bef2d3e 172{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s },
9978cd4d 173{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s|I2 },
45b14705
ILT		 174{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t },
175{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO },
9978cd4d 176{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t|I2},
2bef2d3e 177{"bnel", "s,I,p", 2, (int) M_BNEL_I, INSN_MACRO },
9978cd4d
ILT		 178{"break", "", 0x0000000d, 0xffffffff, TRAP },
179{"break", "c", 0x0000000d, 0xfc00003f, TRAP },
45b14705
ILT		 180{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC },
181{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC },
182{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC },
183{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC },
184{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC },
185{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC },
186{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC },
187{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC },
188{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC },
189{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC },
190{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC },
191{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC },
192{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC },
193{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC },
194{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC },
195{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC },
196{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC },
197{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC },
198{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC },
199{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC },
200{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC },
201{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC },
202{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC },
203{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC },
204{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC },
205{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC },
206{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC },
207{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC },
208{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC },
209{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC },
210{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC },
211{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC },
942a4965 212{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b|I3 },
2bef2d3e
ILT		 213{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|I3 },
214{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|I3 },
215{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|I2 },
216{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|I2 },
217{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0 },
218{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1 },
219{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1 },
220{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2 },
221{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3 },
45b14705
ILT		 222{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC },
223{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC },
224{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC },
225{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC },
226{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC },
2bef2d3e 227{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|I3 },
45b14705
ILT		 228{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S },
229{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S },
2bef2d3e
ILT		 230{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|I3 },
231{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|I3 },
232{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|I3 },
45b14705
ILT		 233{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S },
234{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S },
235{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S },
236{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S },
a5ba0d3f 237{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO },
2bef2d3e
ILT		 238{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
239{"dadd", "t,r,I", 3, (int) M_DADD_I, INSN_MACRO },
240{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s|I3 },
241{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s|I3 },
242{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
243{"daddu", "t,r,I", 3, (int) M_DADDU_I, INSN_MACRO },
a9c686ad 244/* For ddiv, see the comments about div. */
547998d2 245{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
a9c686ad 246{"ddiv", "d,v,t", 3, (int) M_DDIV_3, INSN_MACRO },
2bef2d3e 247{"ddiv", "d,v,I", 3, (int) M_DDIV_3I, INSN_MACRO },
a9c686ad 248/* For ddivu, see the comments about div. */
547998d2 249{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
a9c686ad 250{"ddivu", "d,v,t", 3, (int) M_DDIVU_3, INSN_MACRO },
2bef2d3e 251{"ddivu", "d,v,I", 3, (int) M_DDIVU_3I, INSN_MACRO },
a9c686ad
ILT		 252/* The MIPS assembler treats the div opcode with two operands as
253 though the first operand appeared twice (the first operand is both
254 a source and a destination). To get the div machine instruction,
547998d2
ILT		 255 you must use an explicit destination of $0. */
256{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
a9c686ad 257{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO },
45b14705
ILT		 258{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO },
259{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T },
260{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T },
a9c686ad 261/* For divu, see the comments about div. */
547998d2 262{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
a9c686ad 263{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO },
45b14705 264{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO },
2bef2d3e
ILT		 265{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0|I3 },
266{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC|I3 },
267{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|I3 },
268{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|I3 },
269{"dmul", "d,v,t", 3, (int) M_DMUL, INSN_MACRO },
270{"dmul", "d,v,I", 3, (int) M_DMUL_I, INSN_MACRO },
271{"dmulo", "d,v,t", 3, (int) M_DMULO, INSN_MACRO },
272{"dmulo", "d,v,I", 3, (int) M_DMULO_I, INSN_MACRO },
273{"dmulou", "d,v,t", 3, (int) M_DMULOU, INSN_MACRO },
274{"dmulou", "d,v,I", 3, (int) M_DMULOU_I, INSN_MACRO },
275{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
276{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
277{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t|I3 }, /* dsub 0 */
278{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t|I3 }, /* dsubu 0*/
547998d2 279{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
2bef2d3e
ILT		 280{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO },
281{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO },
547998d2 282{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|I3 },
2bef2d3e
ILT		 283{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO },
284{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO },
285{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
942a4965 286{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 287{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsllv */
942a4965 288{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t|I3 }, /* dsll32 */
2bef2d3e 289{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 290{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
942a4965 291{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 292{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrav */
942a4965 293{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t|I3 }, /* dsra32 */
2bef2d3e 294{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 295{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3},
942a4965 296{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e 297{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s|I3}, /* dsrlv */
942a4965 298{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t|I3 }, /* dsrl32 */
2bef2d3e 299{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t|I3 },
2bef2d3e
ILT		 300{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
301{"dsub", "d,v,I", 3, (int) M_DSUB_I, INSN_MACRO },
302{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t|I3},
303{"dsubu", "d,v,I", 3, (int) M_DSUBU_I, INSN_MACRO },
304{"eret", "", 0x42000018, 0xffffffff, I3 },
305{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|I3 },
306{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|I3 },
307{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|I2 },
308{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|I2 },
45b14705 309{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s },
942a4965
ILT		 310{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s }, /* jr */
311/* SVR4 PIC code requires special handling for j, so it must be a
312 macro. */
313{"j", "a", 0, (int) M_J_A, INSN_MACRO },
314/* This form of j is used by the disassembler and internally by the
315 assembler, but will never match user input (because the line above
316 will match first). */
45b14705
ILT		 317{"j", "a", 0x08000000, 0xfc000000, UBD },
318{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d },
319{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d },
942a4965
ILT		 320/* SVR4 PIC code requires special handling for jal, so it must be a
321 macro. */
322{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO },
323{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO },
324{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO },
325/* This form of jal is used by the disassembler and internally by the
326 assembler, but will never match user input (because the line above
327 will match first). */
45b14705 328{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31 },
45b14705
ILT		 329{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO },
330{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t },
331{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO },
332{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t },
333{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO },
2bef2d3e 334{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b|I3 },
45b14705
ILT		 335{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO },
336{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO },
2bef2d3e
ILT		 337{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
338{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2},
339{"ldc1", "T,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
340{"ldc1", "E,A(b)", 2, (int) M_LDC1_AB, INSN_MACRO },
942a4965
ILT		 341{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|I2}, /* ldc1 */
342{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO },
343{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO },
2bef2d3e
ILT		 344{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
345{"ldc2", "E,A(b)", 2, (int) M_LDC2_AB, INSN_MACRO },
346{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC|I2},
347{"ldc3", "E,A(b)", 2, (int) M_LDC3_AB, INSN_MACRO },
348{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b|I3},
349{"ldl", "t,A(b)", 3, (int) M_LDL_AB, INSN_MACRO },
350{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b|I3},
351{"ldr", "t,A(b)", 3, (int) M_LDR_AB, INSN_MACRO },
45b14705
ILT		 352{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t },
353{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO },
354{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t },
355{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO },
356/* li is at the start of the table. */
357{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO },
358{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO },
359{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO },
360{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO },
2bef2d3e
ILT		 361{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t|I2},
362{"ll", "t,A(b)", 2, (int) M_LL_AB, INSN_MACRO },
363{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t|I3},
364{"lld", "t,A(b)", 3, (int) M_LLD_AB, INSN_MACRO },
45b14705
ILT		 365{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t },
366{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t },
367{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO },
2bef2d3e 368{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC },
45b14705 369{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO },
2bef2d3e
ILT		 370{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T },
371{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T },
45b14705
ILT		 372{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
373{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
2bef2d3e 374{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T }, /* lwc1 */
45b14705 375{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO },
2bef2d3e 376{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC },
45b14705 377{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO },
2bef2d3e 378{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC },
45b14705
ILT		 379{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO },
380{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t },
381{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO },
2bef2d3e
ILT		 382{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
383{"lcache", "t,A(b)", 2, (int) M_LWL_AB, INSN_MACRO }, /* as lwl */
45b14705
ILT		 384{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t },
385{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO },
2bef2d3e
ILT		 386{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t|I2}, /* same */
387{"flush", "t,A(b)", 2, (int) M_LWR_AB, INSN_MACRO }, /* as lwr */
9978cd4d 388{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t|I3},
2bef2d3e
ILT		 389{"lwu", "t,A(b)", 3, (int) M_LWU_AB, INSN_MACRO },
390{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0 },
391{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
392{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S },
393{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2 },
394{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3 },
45b14705
ILT		 395{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI },
396{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO },
397{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S },
398{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S },
399/* move is at the top of the table. */
400{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC },
2bef2d3e
ILT		 401{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S },
402{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S },
45b14705
ILT		 403{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC },
404{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC },
405{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI },
406{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO },
407{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T },
408{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T },
409{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO },
410{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO },
411{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO },
412{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO },
413{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO },
414{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO },
415{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
416{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
417{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t }, /* sub 0 */
418{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t }, /* subu 0 */
419{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S },
420{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S },
421/* nop is at the start of the table. */
422{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t },
942a4965 423{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
45b14705
ILT		 424{"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t }, /* nor d,s,zero */
425{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t },
426{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
427{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s },
547998d2 428{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
45b14705
ILT		 429{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO },
430{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO },
547998d2 431{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO },
45b14705
ILT		 432{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO },
433{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO },
434{"rfe", "", 0x42000010, 0xffffffff, INSN_RFE },
435{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO },
436{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO },
437{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO },
438{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO },
2bef2d3e
ILT		 439{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|I3 },
440{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|I3 },
441{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|I2 },
442{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|I2 },
942a4965 443{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 444{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO },
942a4965 445{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|RD_b|I2 },
2bef2d3e 446{"sc", "t,A(b)", 2, (int) M_SC_AB, INSN_MACRO },
942a4965 447{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|RD_b|I3 },
2bef2d3e 448{"scd", "t,A(b)", 3, (int) M_SCD_AB, INSN_MACRO },
942a4965 449{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b|I3 },
45b14705
ILT		 450{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO },
451{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO },
942a4965
ILT		 452{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
453{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
2bef2d3e
ILT		 454{"sdc1", "T,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
455{"sdc1", "E,A(b)", 2, (int) M_SDC1_AB, INSN_MACRO },
942a4965 456{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b|I2 },
2bef2d3e 457{"sdc2", "E,A(b)", 2, (int) M_SDC2_AB, INSN_MACRO },
942a4965 458{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b|I2 },
2bef2d3e 459{"sdc3", "E,A(b)", 2, (int) M_SDC3_AB, INSN_MACRO },
942a4965 460{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|I2 },
2bef2d3e
ILT		 461{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO },
462{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO },
942a4965 463{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b|I3 },
2bef2d3e 464{"sdl", "t,A(b)", 3, (int) M_SDL_AB, INSN_MACRO },
942a4965 465{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b|I3 },
2bef2d3e 466{"sdr", "t,A(b)", 3, (int) M_SDR_AB, INSN_MACRO },
45b14705
ILT		 467{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO },
468{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO },
469{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO },
470{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO },
471{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO },
472{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO },
473{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO },
474{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO },
475{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO },
476{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO },
942a4965 477{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b },
45b14705
ILT		 478{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO },
479{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO },
480{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO },
481{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO },
482{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO },
483{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s },
484{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s }, /* sllv */
485{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t },
486{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t },
487{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO },
488{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s },
489{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s },
490{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t },
491{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO },
492{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO },
493{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO },
2bef2d3e 494{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|I2 },
942a4965 495{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|I2 },
45b14705
ILT		 496{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s },
497{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srav */
498{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t },
499{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s },
500{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s }, /* srlv */
501{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t },
502{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t },
503{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO },
504{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T },
505{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T },
506{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t },
507{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO },
942a4965 508{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 509{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO },
942a4965 510{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b },
45b14705 511{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO },
942a4965
ILT		 512{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
513{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b },
45b14705
ILT		 514{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
515{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
942a4965 516{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b }, /* swc1 */
45b14705 517{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO },
942a4965 518{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b },
45b14705 519{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO },
942a4965 520{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b },
45b14705 521{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO },
942a4965 522{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 523{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO },
2bef2d3e
ILT		 524{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
525{"scache", "t,A(b)", 2, (int) M_SWL_AB, INSN_MACRO }, /* as swl */
942a4965 526{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b },
45b14705 527{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO },
2bef2d3e
ILT		 528{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b|I2 }, /* same */
529{"invalidate", "t,A(b)",2, (int) M_SWR_AB, INSN_MACRO }, /* as swr */
530{"sync", "", 0x0000000f, 0xffffffff, I2 },
9978cd4d
ILT		 531{"syscall", "", 0x0000000c, 0xffffffff, TRAP },
532{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP },
533{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP },
534{"teq", "s,t", 0x00000034, 0xfc00003f, RD_s|RD_t|I2|TRAP },
535{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|I2|TRAP }, /* teqi */
2bef2d3e 536{"teq", "s,I", 2, (int) M_TEQ_I, INSN_MACRO },
9978cd4d
ILT		 537{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP },
538{"tge", "s,t", 0x00000030, 0xfc00003f, RD_s|RD_t|I2|TRAP },
539{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgei */
2bef2d3e 540{"tge", "s,I", 2, (int) M_TGE_I, INSN_MACRO },
9978cd4d
ILT		 541{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP },
542{"tgeu", "s,t", 0x00000031, 0xfc00003f, RD_s|RD_t|I2|TRAP },
543{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|I2|TRAP }, /* tgeiu */
2bef2d3e 544{"tgeu", "s,I", 2, (int) M_TGEU_I, INSN_MACRO },
45b14705
ILT		 545{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB },
546{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB },
547{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB },
548{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB },
9978cd4d
ILT		 549{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP },
550{"tlt", "s,t", 0x00000032, 0xfc00003f, RD_s|RD_t|I2|TRAP },
551{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tlti */
2bef2d3e 552{"tlt", "s,I", 2, (int) M_TLT_I, INSN_MACRO },
9978cd4d
ILT		 553{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP },
554{"tltu", "s,t", 0x00000033, 0xfc00003f, RD_s|RD_t|I2|TRAP },
555{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tltiu */
2bef2d3e 556{"tltu", "s,I", 2, (int) M_TLTU_I, INSN_MACRO },
9978cd4d
ILT		 557{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP },
558{"tne", "s,t", 0x00000036, 0xfc00003f, RD_s|RD_t|I2|TRAP },
559{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|I2|TRAP }, /* tnei */
2bef2d3e
ILT		 560{"tne", "s,I", 2, (int) M_TNE_I, INSN_MACRO },
561{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|I3 },
562{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|I3 },
563{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|I2 },
564{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|I2 },
45b14705 565{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO },
2bef2d3e
ILT		 566{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
567{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|I2 },
45b14705
ILT		 568{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO },
569{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO },
570{"ulh", "t,A", 0, (int) M_ULH_A, INSN_MACRO },
571{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO },
572{"ulhu", "t,A", 0, (int) M_ULHU_A, INSN_MACRO },
573{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO },
574{"ulw", "t,A", 0, (int) M_ULW_A, INSN_MACRO },
575{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO },
576{"ush", "t,A", 0, (int) M_USH_A, INSN_MACRO },
577{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO },
578{"usw", "t,A", 0, (int) M_USW_A, INSN_MACRO },
579{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t },
580{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO },
581{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s },
582/* No hazard protection on coprocessor instructions--they shouldn't
583 change the state of the processor and if they do it's up to the
584 user to put in nops as necessary. These are at the end so that the
585 disasembler recognizes more specific versions first. */
586{"c0", "C", 0x42000000, 0xfe000000, 0 },
587{"c1", "C", 0x46000000, 0xfe000000, 0 },
588{"c2", "C", 0x4a000000, 0xfe000000, 0 },
589{"c3", "C", 0x4e000000, 0xfe000000, 0 },
590};
591
592const int bfd_mips_num_opcodes =
593 ((sizeof mips_opcodes) / (sizeof (mips_opcodes[0])));
Empty description
This page took 0.238943 seconds and 4 git commands to generate.