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9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a AC |
2 | |
3 | Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, | |
4 | 2003 Free Software Foundation, Inc. | |
c877c8e6 KB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
05f13b9c EZ |
20 | Foundation, Inc., 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
c877c8e6 KB |
22 | |
23 | #include "defs.h" | |
e162d11b | 24 | #include "gdb_string.h" |
c877c8e6 KB |
25 | #include "frame.h" |
26 | #include "inferior.h" | |
27 | #include "gdbcore.h" | |
4e052eda | 28 | #include "regcache.h" |
383f0f5b | 29 | #include "gdb_assert.h" |
c877c8e6 KB |
30 | |
31 | #include <sys/types.h> | |
32 | #include <sys/param.h> | |
33 | #include <signal.h> | |
34 | #include <sys/user.h> | |
35 | #include <sys/ioctl.h> | |
2555fe1a | 36 | #include "gdb_wait.h" |
c877c8e6 KB |
37 | #include <fcntl.h> |
38 | #include <sys/procfs.h> | |
45229ea4 | 39 | #include <sys/ptrace.h> |
c877c8e6 | 40 | |
c60c0f5f MS |
41 | /* Prototypes for supply_gregset etc. */ |
42 | #include "gregset.h" | |
16333c4f | 43 | #include "ppc-tdep.h" |
c60c0f5f | 44 | |
45229ea4 EZ |
45 | #ifndef PT_READ_U |
46 | #define PT_READ_U PTRACE_PEEKUSR | |
47 | #endif | |
48 | #ifndef PT_WRITE_U | |
49 | #define PT_WRITE_U PTRACE_POKEUSR | |
50 | #endif | |
51 | ||
52 | /* Default the type of the ptrace transfer to int. */ | |
53 | #ifndef PTRACE_XFER_TYPE | |
54 | #define PTRACE_XFER_TYPE int | |
55 | #endif | |
56 | ||
9abe5450 EZ |
57 | /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a |
58 | configure time check. Some older glibc's (for instance 2.2.1) | |
59 | don't have a specific powerpc version of ptrace.h, and fall back on | |
60 | a generic one. In such cases, sys/ptrace.h defines | |
61 | PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that | |
62 | ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and | |
63 | PTRACE_SETVRREGS to be. This also makes a configury check pretty | |
64 | much useless. */ | |
65 | ||
66 | /* These definitions should really come from the glibc header files, | |
67 | but Glibc doesn't know about the vrregs yet. */ | |
68 | #ifndef PTRACE_GETVRREGS | |
69 | #define PTRACE_GETVRREGS 18 | |
70 | #define PTRACE_SETVRREGS 19 | |
71 | #endif | |
72 | ||
73 | /* This oddity is because the Linux kernel defines elf_vrregset_t as | |
74 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
75 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
76 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
77 | flat array of chars, so that it is easier to manipulate for gdb. | |
78 | ||
79 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
80 | which is only 4 bytes long, but is fetched as a 16 bytes | |
81 | quantity. Up to here we have the elf_vrregset_t structure. | |
82 | Appended to this there is space for the VRSAVE register: 4 bytes. | |
83 | Even though this vrsave register is not included in the regset | |
84 | typedef, it is handled by the ptrace requests. | |
85 | ||
86 | Note that GNU/Linux doesn't support little endian PPC hardware, | |
87 | therefore the offset at which the real value of the VSCR register | |
88 | is located will be always 12 bytes. | |
89 | ||
90 | The layout is like this (where x is the actual value of the vscr reg): */ | |
91 | ||
92 | /* *INDENT-OFF* */ | |
93 | /* | |
94 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| | |
95 | <-------> <-------><-------><-> | |
96 | VR0 VR31 VSCR VRSAVE | |
97 | */ | |
98 | /* *INDENT-ON* */ | |
99 | ||
100 | #define SIZEOF_VRREGS 33*16+4 | |
101 | ||
102 | typedef char gdb_vrregset_t[SIZEOF_VRREGS]; | |
103 | ||
104 | /* For runtime check of ptrace support for VRREGS. */ | |
105 | int have_ptrace_getvrregs = 1; | |
106 | ||
c877c8e6 | 107 | int |
fba45db2 | 108 | kernel_u_size (void) |
c877c8e6 KB |
109 | { |
110 | return (sizeof (struct user)); | |
111 | } | |
112 | ||
16333c4f EZ |
113 | /* *INDENT-OFF* */ |
114 | /* registers layout, as presented by the ptrace interface: | |
115 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
116 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
117 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
118 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
119 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
120 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
121 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
122 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
123 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ | |
124 | /* *INDENT_ON * */ | |
c877c8e6 | 125 | |
45229ea4 EZ |
126 | static int |
127 | ppc_register_u_addr (int regno) | |
c877c8e6 | 128 | { |
16333c4f | 129 | int u_addr = -1; |
dc5cfeb6 | 130 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
56d0d96a AC |
131 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
132 | interface, and not the wordsize of the program's ABI. */ | |
133 | int wordsize = sizeof (PTRACE_XFER_TYPE); | |
16333c4f EZ |
134 | |
135 | /* General purpose registers occupy 1 slot each in the buffer */ | |
8bf659e8 JB |
136 | if (regno >= tdep->ppc_gp0_regnum |
137 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 138 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 139 | |
49ff75ad JB |
140 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
141 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
142 | slot each in 64-bit interface. */ | |
383f0f5b JB |
143 | if (tdep->ppc_fp0_regnum >= 0 |
144 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
145 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
146 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f EZ |
147 | |
148 | /* UISA special purpose registers: 1 slot each */ | |
149 | if (regno == PC_REGNUM) | |
49ff75ad | 150 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 151 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 152 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 153 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 154 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 155 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 156 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 157 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 158 | u_addr = PT_CTR * wordsize; |
f8c59253 | 159 | #ifdef PT_MQ |
dc5cfeb6 | 160 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 161 | u_addr = PT_MQ * wordsize; |
f8c59253 | 162 | #endif |
dc5cfeb6 | 163 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 164 | u_addr = PT_MSR * wordsize; |
383f0f5b JB |
165 | if (tdep->ppc_fpscr_regnum >= 0 |
166 | && regno == tdep->ppc_fpscr_regnum) | |
49ff75ad | 167 | u_addr = PT_FPSCR * wordsize; |
16333c4f EZ |
168 | |
169 | return u_addr; | |
c877c8e6 KB |
170 | } |
171 | ||
9abe5450 EZ |
172 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
173 | registers set mechanism, as opposed to the interface for all the | |
174 | other registers, that stores/fetches each register individually. */ | |
175 | static void | |
176 | fetch_altivec_register (int tid, int regno) | |
177 | { | |
178 | int ret; | |
179 | int offset = 0; | |
180 | gdb_vrregset_t regs; | |
181 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
12c266ea | 182 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
9abe5450 EZ |
183 | |
184 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
185 | if (ret < 0) | |
186 | { | |
187 | if (errno == EIO) | |
188 | { | |
189 | have_ptrace_getvrregs = 0; | |
190 | return; | |
191 | } | |
192 | perror_with_name ("Unable to fetch AltiVec register"); | |
193 | } | |
194 | ||
195 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
196 | long on the hardware. We deal only with the lower 4 bytes of the | |
197 | vector. VRSAVE is at the end of the array in a 4 bytes slot, so | |
198 | there is no need to define an offset for it. */ | |
199 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
12c266ea | 200 | offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); |
9abe5450 EZ |
201 | |
202 | supply_register (regno, | |
203 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
204 | } | |
205 | ||
45229ea4 | 206 | static void |
05f13b9c | 207 | fetch_register (int tid, int regno) |
45229ea4 | 208 | { |
366f009f | 209 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 | 210 | /* This isn't really an address. But ptrace thinks of it as one. */ |
0397dee1 | 211 | CORE_ADDR regaddr = ppc_register_u_addr (regno); |
4a19ea35 | 212 | int bytes_transferred; |
45229ea4 | 213 | unsigned int offset; /* Offset of registers within the u area. */ |
d9d9c31f | 214 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 215 | |
9abe5450 EZ |
216 | if (altivec_register_p (regno)) |
217 | { | |
218 | /* If this is the first time through, or if it is not the first | |
219 | time through, and we have comfirmed that there is kernel | |
220 | support for such a ptrace request, then go and fetch the | |
221 | register. */ | |
222 | if (have_ptrace_getvrregs) | |
223 | { | |
224 | fetch_altivec_register (tid, regno); | |
225 | return; | |
226 | } | |
227 | /* If we have discovered that there is no ptrace support for | |
228 | AltiVec registers, fall through and return zeroes, because | |
229 | regaddr will be -1 in this case. */ | |
230 | } | |
231 | ||
45229ea4 EZ |
232 | if (regaddr == -1) |
233 | { | |
12c266ea | 234 | memset (buf, '\0', DEPRECATED_REGISTER_RAW_SIZE (regno)); /* Supply zeroes */ |
45229ea4 EZ |
235 | supply_register (regno, buf); |
236 | return; | |
237 | } | |
238 | ||
56d0d96a AC |
239 | /* Read the raw register using PTRACE_XFER_TYPE sized chunks. On a |
240 | 32-bit platform, 64-bit floating-point registers will require two | |
241 | transfers. */ | |
4a19ea35 | 242 | for (bytes_transferred = 0; |
8327ccee | 243 | bytes_transferred < register_size (current_gdbarch, regno); |
4a19ea35 | 244 | bytes_transferred += sizeof (PTRACE_XFER_TYPE)) |
45229ea4 EZ |
245 | { |
246 | errno = 0; | |
4a19ea35 JB |
247 | *(PTRACE_XFER_TYPE *) & buf[bytes_transferred] |
248 | = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) regaddr, 0); | |
45229ea4 EZ |
249 | regaddr += sizeof (PTRACE_XFER_TYPE); |
250 | if (errno != 0) | |
251 | { | |
bc97b3ba JB |
252 | char message[128]; |
253 | sprintf (message, "reading register %s (#%d)", | |
45229ea4 | 254 | REGISTER_NAME (regno), regno); |
bc97b3ba | 255 | perror_with_name (message); |
45229ea4 EZ |
256 | } |
257 | } | |
56d0d96a | 258 | |
4a19ea35 JB |
259 | /* Now supply the register. Keep in mind that the regcache's idea |
260 | of the register's size may not be a multiple of sizeof | |
261 | (PTRACE_XFER_TYPE). */ | |
262 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) | |
263 | { | |
264 | /* Little-endian values are always found at the left end of the | |
265 | bytes transferred. */ | |
266 | regcache_raw_supply (current_regcache, regno, buf); | |
267 | } | |
268 | else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) | |
269 | { | |
270 | /* Big-endian values are found at the right end of the bytes | |
271 | transferred. */ | |
272 | size_t padding = (bytes_transferred | |
273 | - register_size (current_gdbarch, regno)); | |
274 | regcache_raw_supply (current_regcache, regno, buf + padding); | |
275 | } | |
276 | else | |
277 | gdb_assert (0); | |
45229ea4 EZ |
278 | } |
279 | ||
9abe5450 EZ |
280 | static void |
281 | supply_vrregset (gdb_vrregset_t *vrregsetp) | |
282 | { | |
283 | int i; | |
284 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
285 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
12c266ea AC |
286 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
287 | int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
288 | |
289 | for (i = 0; i < num_of_vrregs; i++) | |
290 | { | |
291 | /* The last 2 registers of this set are only 32 bit long, not | |
292 | 128. However an offset is necessary only for VSCR because it | |
293 | occupies a whole vector, while VRSAVE occupies a full 4 bytes | |
294 | slot. */ | |
295 | if (i == (num_of_vrregs - 2)) | |
296 | supply_register (tdep->ppc_vr0_regnum + i, | |
297 | *vrregsetp + i * vrregsize + offset); | |
298 | else | |
299 | supply_register (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize); | |
300 | } | |
301 | } | |
302 | ||
303 | static void | |
304 | fetch_altivec_registers (int tid) | |
305 | { | |
306 | int ret; | |
307 | gdb_vrregset_t regs; | |
308 | ||
309 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
310 | if (ret < 0) | |
311 | { | |
312 | if (errno == EIO) | |
313 | { | |
314 | have_ptrace_getvrregs = 0; | |
315 | return; | |
316 | } | |
317 | perror_with_name ("Unable to fetch AltiVec registers"); | |
318 | } | |
319 | supply_vrregset (®s); | |
320 | } | |
321 | ||
45229ea4 | 322 | static void |
05f13b9c | 323 | fetch_ppc_registers (int tid) |
45229ea4 EZ |
324 | { |
325 | int i; | |
9abe5450 EZ |
326 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
327 | ||
32b99774 JB |
328 | for (i = 0; i < ppc_num_gprs; i++) |
329 | fetch_register (tid, tdep->ppc_gp0_regnum + i); | |
330 | if (tdep->ppc_fp0_regnum >= 0) | |
331 | for (i = 0; i < ppc_num_fprs; i++) | |
332 | fetch_register (tid, tdep->ppc_fp0_regnum + i); | |
333 | fetch_register (tid, PC_REGNUM); | |
334 | if (tdep->ppc_ps_regnum != -1) | |
335 | fetch_register (tid, tdep->ppc_ps_regnum); | |
336 | if (tdep->ppc_cr_regnum != -1) | |
337 | fetch_register (tid, tdep->ppc_cr_regnum); | |
338 | if (tdep->ppc_lr_regnum != -1) | |
339 | fetch_register (tid, tdep->ppc_lr_regnum); | |
340 | if (tdep->ppc_ctr_regnum != -1) | |
341 | fetch_register (tid, tdep->ppc_ctr_regnum); | |
342 | if (tdep->ppc_xer_regnum != -1) | |
343 | fetch_register (tid, tdep->ppc_xer_regnum); | |
e3f36dbd KB |
344 | if (tdep->ppc_mq_regnum != -1) |
345 | fetch_register (tid, tdep->ppc_mq_regnum); | |
32b99774 JB |
346 | if (tdep->ppc_fpscr_regnum != -1) |
347 | fetch_register (tid, tdep->ppc_fpscr_regnum); | |
9abe5450 EZ |
348 | if (have_ptrace_getvrregs) |
349 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
350 | fetch_altivec_registers (tid); | |
45229ea4 EZ |
351 | } |
352 | ||
353 | /* Fetch registers from the child process. Fetch all registers if | |
354 | regno == -1, otherwise fetch all general registers or all floating | |
355 | point registers depending upon the value of regno. */ | |
356 | void | |
357 | fetch_inferior_registers (int regno) | |
358 | { | |
9abe5450 | 359 | /* Overload thread id onto process id */ |
05f13b9c EZ |
360 | int tid = TIDGET (inferior_ptid); |
361 | ||
362 | /* No thread id, just use process id */ | |
363 | if (tid == 0) | |
364 | tid = PIDGET (inferior_ptid); | |
365 | ||
9abe5450 | 366 | if (regno == -1) |
05f13b9c | 367 | fetch_ppc_registers (tid); |
45229ea4 | 368 | else |
05f13b9c | 369 | fetch_register (tid, regno); |
45229ea4 EZ |
370 | } |
371 | ||
372 | /* Store one register. */ | |
9abe5450 EZ |
373 | static void |
374 | store_altivec_register (int tid, int regno) | |
375 | { | |
376 | int ret; | |
377 | int offset = 0; | |
378 | gdb_vrregset_t regs; | |
379 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
12c266ea | 380 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
9abe5450 EZ |
381 | |
382 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
383 | if (ret < 0) | |
384 | { | |
385 | if (errno == EIO) | |
386 | { | |
387 | have_ptrace_getvrregs = 0; | |
388 | return; | |
389 | } | |
390 | perror_with_name ("Unable to fetch AltiVec register"); | |
391 | } | |
392 | ||
393 | /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes | |
394 | long on the hardware. */ | |
395 | if (regno == (tdep->ppc_vrsave_regnum - 1)) | |
12c266ea | 396 | offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); |
9abe5450 EZ |
397 | |
398 | regcache_collect (regno, | |
399 | regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); | |
400 | ||
401 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
402 | if (ret < 0) | |
403 | perror_with_name ("Unable to store AltiVec register"); | |
404 | } | |
405 | ||
45229ea4 | 406 | static void |
05f13b9c | 407 | store_register (int tid, int regno) |
45229ea4 | 408 | { |
366f009f | 409 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 EZ |
410 | /* This isn't really an address. But ptrace thinks of it as one. */ |
411 | CORE_ADDR regaddr = ppc_register_u_addr (regno); | |
52f0bd74 | 412 | int i; |
4a19ea35 | 413 | size_t bytes_to_transfer; |
d9d9c31f | 414 | char buf[MAX_REGISTER_SIZE]; |
45229ea4 | 415 | |
9abe5450 | 416 | if (altivec_register_p (regno)) |
45229ea4 | 417 | { |
9abe5450 | 418 | store_altivec_register (tid, regno); |
45229ea4 EZ |
419 | return; |
420 | } | |
421 | ||
9abe5450 EZ |
422 | if (regaddr == -1) |
423 | return; | |
424 | ||
4a19ea35 JB |
425 | /* First collect the register. Keep in mind that the regcache's |
426 | idea of the register's size may not be a multiple of sizeof | |
427 | (PTRACE_XFER_TYPE). */ | |
56d0d96a | 428 | memset (buf, 0, sizeof buf); |
4a19ea35 JB |
429 | bytes_to_transfer = align_up (register_size (current_gdbarch, regno), |
430 | sizeof (PTRACE_XFER_TYPE)); | |
431 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
432 | { | |
433 | /* Little-endian values always sit at the left end of the buffer. */ | |
434 | regcache_raw_collect (current_regcache, regno, buf); | |
435 | } | |
436 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
437 | { | |
438 | /* Big-endian values sit at the right end of the buffer. */ | |
439 | size_t padding = (bytes_to_transfer | |
440 | - register_size (current_gdbarch, regno)); | |
441 | regcache_raw_collect (current_regcache, regno, buf + padding); | |
442 | } | |
443 | ||
444 | for (i = 0; i < bytes_to_transfer; i += sizeof (PTRACE_XFER_TYPE)) | |
45229ea4 EZ |
445 | { |
446 | errno = 0; | |
447 | ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr, | |
448 | *(PTRACE_XFER_TYPE *) & buf[i]); | |
449 | regaddr += sizeof (PTRACE_XFER_TYPE); | |
e3f36dbd KB |
450 | |
451 | if (errno == EIO | |
383f0f5b | 452 | && regno == tdep->ppc_fpscr_regnum) |
e3f36dbd KB |
453 | { |
454 | /* Some older kernel versions don't allow fpscr to be written. */ | |
455 | continue; | |
456 | } | |
457 | ||
45229ea4 EZ |
458 | if (errno != 0) |
459 | { | |
bc97b3ba JB |
460 | char message[128]; |
461 | sprintf (message, "writing register %s (#%d)", | |
45229ea4 | 462 | REGISTER_NAME (regno), regno); |
bc97b3ba | 463 | perror_with_name (message); |
45229ea4 EZ |
464 | } |
465 | } | |
466 | } | |
467 | ||
9abe5450 EZ |
468 | static void |
469 | fill_vrregset (gdb_vrregset_t *vrregsetp) | |
470 | { | |
471 | int i; | |
472 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
473 | int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; | |
12c266ea AC |
474 | int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
475 | int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); | |
9abe5450 EZ |
476 | |
477 | for (i = 0; i < num_of_vrregs; i++) | |
478 | { | |
479 | /* The last 2 registers of this set are only 32 bit long, not | |
480 | 128, but only VSCR is fetched as a 16 bytes quantity. */ | |
481 | if (i == (num_of_vrregs - 2)) | |
482 | regcache_collect (tdep->ppc_vr0_regnum + i, | |
483 | *vrregsetp + i * vrregsize + offset); | |
484 | else | |
485 | regcache_collect (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize); | |
486 | } | |
487 | } | |
488 | ||
489 | static void | |
490 | store_altivec_registers (int tid) | |
491 | { | |
492 | int ret; | |
493 | gdb_vrregset_t regs; | |
494 | ||
0897f59b | 495 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); |
9abe5450 EZ |
496 | if (ret < 0) |
497 | { | |
498 | if (errno == EIO) | |
499 | { | |
500 | have_ptrace_getvrregs = 0; | |
501 | return; | |
502 | } | |
503 | perror_with_name ("Couldn't get AltiVec registers"); | |
504 | } | |
505 | ||
506 | fill_vrregset (®s); | |
507 | ||
0897f59b | 508 | if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) |
9abe5450 EZ |
509 | perror_with_name ("Couldn't write AltiVec registers"); |
510 | } | |
511 | ||
45229ea4 | 512 | static void |
05f13b9c | 513 | store_ppc_registers (int tid) |
45229ea4 EZ |
514 | { |
515 | int i; | |
9abe5450 | 516 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
45229ea4 | 517 | |
32b99774 JB |
518 | for (i = 0; i < ppc_num_gprs; i++) |
519 | store_register (tid, tdep->ppc_gp0_regnum + i); | |
520 | if (tdep->ppc_fp0_regnum >= 0) | |
521 | for (i = 0; i < ppc_num_fprs; i++) | |
522 | store_register (tid, tdep->ppc_fp0_regnum + i); | |
523 | store_register (tid, PC_REGNUM); | |
524 | if (tdep->ppc_ps_regnum != -1) | |
525 | store_register (tid, tdep->ppc_ps_regnum); | |
526 | if (tdep->ppc_cr_regnum != -1) | |
527 | store_register (tid, tdep->ppc_cr_regnum); | |
528 | if (tdep->ppc_lr_regnum != -1) | |
529 | store_register (tid, tdep->ppc_lr_regnum); | |
530 | if (tdep->ppc_ctr_regnum != -1) | |
531 | store_register (tid, tdep->ppc_ctr_regnum); | |
532 | if (tdep->ppc_xer_regnum != -1) | |
533 | store_register (tid, tdep->ppc_xer_regnum); | |
e3f36dbd KB |
534 | if (tdep->ppc_mq_regnum != -1) |
535 | store_register (tid, tdep->ppc_mq_regnum); | |
32b99774 JB |
536 | if (tdep->ppc_fpscr_regnum != -1) |
537 | store_register (tid, tdep->ppc_fpscr_regnum); | |
9abe5450 EZ |
538 | if (have_ptrace_getvrregs) |
539 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
540 | store_altivec_registers (tid); | |
45229ea4 EZ |
541 | } |
542 | ||
543 | void | |
544 | store_inferior_registers (int regno) | |
545 | { | |
05f13b9c EZ |
546 | /* Overload thread id onto process id */ |
547 | int tid = TIDGET (inferior_ptid); | |
548 | ||
549 | /* No thread id, just use process id */ | |
550 | if (tid == 0) | |
551 | tid = PIDGET (inferior_ptid); | |
552 | ||
45229ea4 | 553 | if (regno >= 0) |
05f13b9c | 554 | store_register (tid, regno); |
45229ea4 | 555 | else |
05f13b9c | 556 | store_ppc_registers (tid); |
45229ea4 EZ |
557 | } |
558 | ||
50c9bd31 | 559 | void |
8ae45c11 | 560 | supply_gregset (gdb_gregset_t *gregsetp) |
c877c8e6 | 561 | { |
f9be684a AC |
562 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
563 | interface, and not the wordsize of the program's ABI. */ | |
564 | int wordsize = sizeof (PTRACE_XFER_TYPE); | |
565 | ppc_linux_supply_gregset (current_regcache, -1, gregsetp, | |
566 | sizeof (gdb_gregset_t), wordsize); | |
567 | } | |
568 | ||
569 | static void | |
570 | right_fill_reg (int regnum, void *reg) | |
571 | { | |
572 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace | |
573 | interface, and not the wordsize of the program's ABI. */ | |
574 | int wordsize = sizeof (PTRACE_XFER_TYPE); | |
575 | /* Right fill the register. */ | |
576 | regcache_raw_collect (current_regcache, regnum, | |
577 | ((bfd_byte *) reg | |
578 | + wordsize | |
579 | - register_size (current_gdbarch, regnum))); | |
c877c8e6 KB |
580 | } |
581 | ||
fdb28ac4 | 582 | void |
8ae45c11 | 583 | fill_gregset (gdb_gregset_t *gregsetp, int regno) |
fdb28ac4 KB |
584 | { |
585 | int regi; | |
2ac44c70 | 586 | elf_greg_t *regp = (elf_greg_t *) gregsetp; |
dc5cfeb6 | 587 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
f9be684a AC |
588 | const int elf_ngreg = 48; |
589 | ||
590 | ||
591 | /* Start with zeros. */ | |
592 | memset (regp, 0, elf_ngreg * sizeof (*regp)); | |
fdb28ac4 | 593 | |
063715bf | 594 | for (regi = 0; regi < ppc_num_gprs; regi++) |
fdb28ac4 | 595 | { |
cdf2c5f5 JB |
596 | if ((regno == -1) || regno == tdep->ppc_gp0_regnum + regi) |
597 | right_fill_reg (tdep->ppc_gp0_regnum + regi, (regp + PT_R0 + regi)); | |
fdb28ac4 KB |
598 | } |
599 | ||
16333c4f | 600 | if ((regno == -1) || regno == PC_REGNUM) |
f9be684a | 601 | right_fill_reg (PC_REGNUM, regp + PT_NIP); |
05f13b9c | 602 | if ((regno == -1) || regno == tdep->ppc_lr_regnum) |
f9be684a | 603 | right_fill_reg (tdep->ppc_lr_regnum, regp + PT_LNK); |
05f13b9c | 604 | if ((regno == -1) || regno == tdep->ppc_cr_regnum) |
dc5cfeb6 | 605 | regcache_collect (tdep->ppc_cr_regnum, regp + PT_CCR); |
05f13b9c | 606 | if ((regno == -1) || regno == tdep->ppc_xer_regnum) |
dc5cfeb6 | 607 | regcache_collect (tdep->ppc_xer_regnum, regp + PT_XER); |
05f13b9c | 608 | if ((regno == -1) || regno == tdep->ppc_ctr_regnum) |
f9be684a | 609 | right_fill_reg (tdep->ppc_ctr_regnum, regp + PT_CTR); |
f8c59253 | 610 | #ifdef PT_MQ |
e3f36dbd KB |
611 | if (((regno == -1) || regno == tdep->ppc_mq_regnum) |
612 | && (tdep->ppc_mq_regnum != -1)) | |
f9be684a | 613 | right_fill_reg (tdep->ppc_mq_regnum, regp + PT_MQ); |
f8c59253 | 614 | #endif |
05f13b9c | 615 | if ((regno == -1) || regno == tdep->ppc_ps_regnum) |
f9be684a | 616 | right_fill_reg (tdep->ppc_ps_regnum, regp + PT_MSR); |
fdb28ac4 KB |
617 | } |
618 | ||
50c9bd31 | 619 | void |
8ae45c11 | 620 | supply_fpregset (gdb_fpregset_t * fpregsetp) |
c877c8e6 | 621 | { |
f9be684a AC |
622 | ppc_linux_supply_fpregset (NULL, current_regcache, -1, fpregsetp, |
623 | sizeof (gdb_fpregset_t)); | |
c877c8e6 | 624 | } |
fdb28ac4 | 625 | |
9abe5450 EZ |
626 | /* Given a pointer to a floating point register set in /proc format |
627 | (fpregset_t *), update the register specified by REGNO from gdb's | |
628 | idea of the current floating point register set. If REGNO is -1, | |
629 | update them all. */ | |
fdb28ac4 | 630 | void |
8ae45c11 | 631 | fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) |
fdb28ac4 KB |
632 | { |
633 | int regi; | |
e3f36dbd | 634 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
f9be684a | 635 | bfd_byte *fpp = (void *) fpregsetp; |
fdb28ac4 | 636 | |
383f0f5b | 637 | if (ppc_floating_point_unit_p (current_gdbarch)) |
fdb28ac4 | 638 | { |
383f0f5b JB |
639 | for (regi = 0; regi < ppc_num_fprs; regi++) |
640 | { | |
641 | if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi)) | |
642 | regcache_collect (tdep->ppc_fp0_regnum + regi, fpp + 8 * regi); | |
643 | } | |
644 | if (regno == -1 || regno == tdep->ppc_fpscr_regnum) | |
645 | right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32)); | |
fdb28ac4 KB |
646 | } |
647 | } |