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* main.c (main): Make sure command loop is used with cygwin32.
[binutils.git] / gdb / sh-stub.c
CommitLineData
6a4547c0
SS		 1/* sh-stub.c -- debugging stub for the Hitachi-SH.
2
3 NOTE!! This code has to be compiled with optimization, otherwise the
4 function inlining which generates the exception handlers won't work.
5
6*/
7
8/* This is originally based on an m68k software stub written by Glenn
9 Engel at HP, but has changed quite a bit.
10
11 Modifications for the SH by Ben Lee and Steve Chamberlain
12
13*/
14
15/****************************************************************************
16
17 THIS SOFTWARE IS NOT COPYRIGHTED
18
19 HP offers the following for use in the public domain. HP makes no
20 warranty with regard to the software or it's performance and the
21 user accepts the software "AS IS" with all faults.
22
23 HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
24 TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
25 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
26
27****************************************************************************/
28
29
30/* Remote communication protocol.
31
32 A debug packet whose contents are <data>
33 is encapsulated for transmission in the form:
34
35 $ <data> # CSUM1 CSUM2
36
37 <data> must be ASCII alphanumeric and cannot include characters
38 '$' or '#'. If <data> starts with two characters followed by
39 ':', then the existing stubs interpret this as a sequence number.
40
41 CSUM1 and CSUM2 are ascii hex representation of an 8-bit
42 checksum of <data>, the most significant nibble is sent first.
43 the hex digits 0-9,a-f are used.
44
45 Receiver responds with:
46
47 + - if CSUM is correct and ready for next packet
48 - - if CSUM is incorrect
49
50 <data> is as follows:
51 All values are encoded in ascii hex digits.
52
53 Request Packet
54
55 read registers g
56 reply XX....X Each byte of register data
57 is described by two hex digits.
58 Registers are in the internal order
59 for GDB, and the bytes in a register
60 are in the same order the machine uses.
61 or ENN for an error.
62
63 write regs GXX..XX Each byte of register data
64 is described by two hex digits.
65 reply OK for success
66 ENN for an error
67
68 write reg Pn...=r... Write register n... with value r...,
69 which contains two hex digits for each
70 byte in the register (target byte
71 order).
72 reply OK for success
73 ENN for an error
74 (not supported by all stubs).
75
76 read mem mAA..AA,LLLL AA..AA is address, LLLL is length.
77 reply XX..XX XX..XX is mem contents
78 Can be fewer bytes than requested
79 if able to read only part of the data.
80 or ENN NN is errno
81
82 write mem MAA..AA,LLLL:XX..XX
83 AA..AA is address,
84 LLLL is number of bytes,
85 XX..XX is data
86 reply OK for success
87 ENN for an error (this includes the case
88 where only part of the data was
89 written).
90
91 cont cAA..AA AA..AA is address to resume
92 If AA..AA is omitted,
93 resume at same address.
94
95 step sAA..AA AA..AA is address to resume
96 If AA..AA is omitted,
97 resume at same address.
98
99 last signal ? Reply the current reason for stopping.
100 This is the same reply as is generated
101 for step or cont : SAA where AA is the
102 signal number.
103
104 There is no immediate reply to step or cont.
105 The reply comes when the machine stops.
106 It is SAA AA is the "signal number"
107
108 or... TAAn...:r...;n:r...;n...:r...;
109 AA = signal number
110 n... = register number
111 r... = register contents
112 or... WAA The process exited, and AA is
113 the exit status. This is only
114 applicable for certains sorts of
115 targets.
116 kill request k
117
118 toggle debug d toggle debug flag (see 386 & 68k stubs)
119 reset r reset -- see sparc stub.
120 reserved <other> On other requests, the stub should
121 ignore the request and send an empty
122 response ($#<checksum>). This way
123 we can extend the protocol and GDB
124 can tell whether the stub it is
125 talking to uses the old or the new.
126 search tAA:PP,MM Search backwards starting at address
127 AA for a match with pattern PP and
128 mask MM. PP and MM are 4 bytes.
129 Not supported by all stubs.
130
131 general query qXXXX Request info about XXXX.
132 general set QXXXX=yyyy Set value of XXXX to yyyy.
133 query sect offs qOffsets Get section offsets. Reply is
134 Text=xxx;Data=yyy;Bss=zzz
135 console output Otext Send text to stdout. Only comes from
136 remote target.
137
138 Responses can be run-length encoded to save space. A '*' means that
139 the next character is an ASCII encoding giving a repeat count which
140 stands for that many repititions of the character preceding the '*'.
141 The encoding is n+29, yielding a printable character where n >=3
142 (which is where rle starts to win). Don't use an n > 126.
143
144 So
145 "0* " means the same as "0000". */
146
147#include <string.h>
148#include <setjmp.h>
149
150
151
152#define COND_BR_MASK 0xff00
153#define UCOND_DBR_MASK 0xe000
154#define UCOND_RBR_MASK 0xf0df
155#define TRAPA_MASK 0xff00
156
157#define COND_DISP 0x00ff
158#define UCOND_DISP 0x0fff
159#define UCOND_REG 0x0f00
160
161#define BF_INSTR 0x8b00
162#define BT_INSTR 0x8900
163#define BRA_INSTR 0xa000
164#define BSR_INSTR 0xb000
165#define JMP_INSTR 0x402b
166#define JSR_INSTR 0x400b
167#define RTS_INSTR 0x000b
168#define RTE_INSTR 0x002b
169#define TRAPA_INSTR 0xc300
170
171#define SSTEP_INSTR 0xc3ff
172
173#define T_BIT_MASK 0x0001
174/*
175 * BUFMAX defines the maximum number of characters in inbound/outbound
176 * buffers at least NUMREGBYTES*2 are needed for register packets
177 */
178#define BUFMAX 1024
179
180/*
181 * Number of bytes for registers
182 */
183#define NUMREGBYTES 112 /* 92 */
184
185/*
186 * typedef
187 */
188typedef void (*Function) ();
189
190/*
191 * Forward declarations
192 */
193
194static int hex (char);
195static char *mem2hex (char *, char *, int);
196static char *hex2mem (char *, char *, int);
197static int hexToInt (char **, int *);
198static void getpacket (char *);
199static void putpacket (char *);
200static void handle_buserror (void);
201static int computeSignal (int exceptionVector);
202static void handle_exception (int exceptionVector);
203void init_serial();
204
205
206int putDebugChar (char);
207char getDebugChar (void);
208
209/* These are in the file but in asm statements so the compiler can't see them */
210void catch_exception_4 (void);
211void catch_exception_6 (void);
212void catch_exception_9 (void);
213void catch_exception_10 (void);
214void catch_exception_11 (void);
215void catch_exception_32 (void);
216void catch_exception_33 (void);
217void catch_exception_255 (void);
218
219
220
221#define catch_exception_random catch_exception_255 /* Treat all odd ones like 255 */
222
223void breakpoint (void);
224
225
226#define init_stack_size 8*1024 /* if you change this you should also modify BINIT */
227#define stub_stack_size 8*1024
228
229int init_stack[init_stack_size] __attribute__ ((section ("stack"))) = {0};
230int stub_stack[stub_stack_size] __attribute__ ((section ("stack"))) = {0};
231
232typedef struct
233 {
234 void (*func_cold) ();
235 int *stack_cold;
236 void (*func_warm) ();
237 int *stack_warm;
238 void (*(handler[256 - 4])) ();
239 }
240vec_type;
241
242
243void INIT ();
244void BINIT ();
245
246/* When you link take care that this is at address 0 -
247 or wherever your vbr points */
248
249#define CPU_BUS_ERROR_VEC 9
250#define DMA_BUS_ERROR_VEC 10
251#define NMI_VEC 11
252#define INVALID_INSN_VEC 4
253#define INVALID_SLOT_VEC 6
254#define TRAP_VEC 32
255#define IO_VEC 33
256#define USER_VEC 255
257
258
259#define BCR (*(volatile short *)(0x05FFFFA0)) /* Bus control register */
260#define BAS (0x800) /* Byte access select */
261#define WCR1 (*(volatile short *)(0x05ffffA2)) /* Wait state control register */
262
263const vec_type vectable =
264{
265 &BINIT, /* 0: Power-on reset PC */
266 init_stack + init_stack_size, /* 1: Power-on reset SP */
267 &BINIT, /* 2: Manual reset PC */
268 init_stack + init_stack_size, /* 3: Manual reset SP */
269{
270 &catch_exception_4, /* 4: General invalid instruction */
271 &catch_exception_random, /* 5: Reserved for system */
272 &catch_exception_6, /* 6: Invalid slot instruction */
273 &catch_exception_random, /* 7: Reserved for system */
274 &catch_exception_random, /* 8: Reserved for system */
275 &catch_exception_9, /* 9: CPU bus error */
276 &catch_exception_10, /* 10: DMA bus error */
277 &catch_exception_11, /* 11: NMI */
278 &catch_exception_random, /* 12: User break */
279 &catch_exception_random, /* 13: Reserved for system */
280 &catch_exception_random, /* 14: Reserved for system */
281 &catch_exception_random, /* 15: Reserved for system */
282 &catch_exception_random, /* 16: Reserved for system */
283 &catch_exception_random, /* 17: Reserved for system */
284 &catch_exception_random, /* 18: Reserved for system */
285 &catch_exception_random, /* 19: Reserved for system */
286 &catch_exception_random, /* 20: Reserved for system */
287 &catch_exception_random, /* 21: Reserved for system */
288 &catch_exception_random, /* 22: Reserved for system */
289 &catch_exception_random, /* 23: Reserved for system */
290 &catch_exception_random, /* 24: Reserved for system */
291 &catch_exception_random, /* 25: Reserved for system */
292 &catch_exception_random, /* 26: Reserved for system */
293 &catch_exception_random, /* 27: Reserved for system */
294 &catch_exception_random, /* 28: Reserved for system */
295 &catch_exception_random, /* 29: Reserved for system */
296 &catch_exception_random, /* 30: Reserved for system */
297 &catch_exception_random, /* 31: Reserved for system */
298 &catch_exception_32, /* 32: Trap instr (user vectors) */
299 &catch_exception_33, /* 33: Trap instr (user vectors) */
300 &catch_exception_random, /* 34: Trap instr (user vectors) */
301 &catch_exception_random, /* 35: Trap instr (user vectors) */
302 &catch_exception_random, /* 36: Trap instr (user vectors) */
303 &catch_exception_random, /* 37: Trap instr (user vectors) */
304 &catch_exception_random, /* 38: Trap instr (user vectors) */
305 &catch_exception_random, /* 39: Trap instr (user vectors) */
306 &catch_exception_random, /* 40: Trap instr (user vectors) */
307 &catch_exception_random, /* 41: Trap instr (user vectors) */
308 &catch_exception_random, /* 42: Trap instr (user vectors) */
309 &catch_exception_random, /* 43: Trap instr (user vectors) */
310 &catch_exception_random, /* 44: Trap instr (user vectors) */
311 &catch_exception_random, /* 45: Trap instr (user vectors) */
312 &catch_exception_random, /* 46: Trap instr (user vectors) */
313 &catch_exception_random, /* 47: Trap instr (user vectors) */
314 &catch_exception_random, /* 48: Trap instr (user vectors) */
315 &catch_exception_random, /* 49: Trap instr (user vectors) */
316 &catch_exception_random, /* 50: Trap instr (user vectors) */
317 &catch_exception_random, /* 51: Trap instr (user vectors) */
318 &catch_exception_random, /* 52: Trap instr (user vectors) */
319 &catch_exception_random, /* 53: Trap instr (user vectors) */
320 &catch_exception_random, /* 54: Trap instr (user vectors) */
321 &catch_exception_random, /* 55: Trap instr (user vectors) */
322 &catch_exception_random, /* 56: Trap instr (user vectors) */
323 &catch_exception_random, /* 57: Trap instr (user vectors) */
324 &catch_exception_random, /* 58: Trap instr (user vectors) */
325 &catch_exception_random, /* 59: Trap instr (user vectors) */
326 &catch_exception_random, /* 60: Trap instr (user vectors) */
327 &catch_exception_random, /* 61: Trap instr (user vectors) */
328 &catch_exception_random, /* 62: Trap instr (user vectors) */
329 &catch_exception_random, /* 63: Trap instr (user vectors) */
330 &catch_exception_random, /* 64: IRQ0 */
331 &catch_exception_random, /* 65: IRQ1 */
332 &catch_exception_random, /* 66: IRQ2 */
333 &catch_exception_random, /* 67: IRQ3 */
334 &catch_exception_random, /* 68: IRQ4 */
335 &catch_exception_random, /* 69: IRQ5 */
336 &catch_exception_random, /* 70: IRQ6 */
337 &catch_exception_random, /* 71: IRQ7 */
338 &catch_exception_random,
339 &catch_exception_random,
340 &catch_exception_random,
341 &catch_exception_random,
342 &catch_exception_random,
343 &catch_exception_random,
344 &catch_exception_random,
345 &catch_exception_random,
346 &catch_exception_random,
347 &catch_exception_random,
348 &catch_exception_random,
349 &catch_exception_random,
350 &catch_exception_random,
351 &catch_exception_random,
352 &catch_exception_random,
353 &catch_exception_random,
354 &catch_exception_random,
355 &catch_exception_random,
356 &catch_exception_random,
357 &catch_exception_random,
358 &catch_exception_random,
359 &catch_exception_random,
360 &catch_exception_random,
361 &catch_exception_random,
362 &catch_exception_random,
363 &catch_exception_random,
364 &catch_exception_random,
365 &catch_exception_random,
366 &catch_exception_random,
367 &catch_exception_random,
368 &catch_exception_random,
369 &catch_exception_random,
370 &catch_exception_random,
371 &catch_exception_random,
372 &catch_exception_random,
373 &catch_exception_random,
374 &catch_exception_random,
375 &catch_exception_random,
376 &catch_exception_random,
377 &catch_exception_random,
378 &catch_exception_random,
379 &catch_exception_random,
380 &catch_exception_random,
381 &catch_exception_random,
382 &catch_exception_random,
383 &catch_exception_random,
384 &catch_exception_random,
385 &catch_exception_random,
386 &catch_exception_random,
387 &catch_exception_random,
388 &catch_exception_random,
389 &catch_exception_random,
390 &catch_exception_random,
391 &catch_exception_random,
392 &catch_exception_random,
393 &catch_exception_random,
394 &catch_exception_random,
395 &catch_exception_random,
396 &catch_exception_random,
397 &catch_exception_random,
398 &catch_exception_random,
399 &catch_exception_random,
400 &catch_exception_random,
401 &catch_exception_random,
402 &catch_exception_random,
403 &catch_exception_random,
404 &catch_exception_random,
405 &catch_exception_random,
406 &catch_exception_random,
407 &catch_exception_random,
408 &catch_exception_random,
409 &catch_exception_random,
410 &catch_exception_random,
411 &catch_exception_random,
412 &catch_exception_random,
413 &catch_exception_random,
414 &catch_exception_random,
415 &catch_exception_random,
416 &catch_exception_random,
417 &catch_exception_random,
418 &catch_exception_random,
419 &catch_exception_random,
420 &catch_exception_random,
421 &catch_exception_random,
422 &catch_exception_random,
423 &catch_exception_random,
424 &catch_exception_random,
425 &catch_exception_random,
426 &catch_exception_random,
427 &catch_exception_random,
428 &catch_exception_random,
429 &catch_exception_random,
430 &catch_exception_random,
431 &catch_exception_random,
432 &catch_exception_random,
433 &catch_exception_random,
434 &catch_exception_random,
435 &catch_exception_random,
436 &catch_exception_random,
437 &catch_exception_random,
438 &catch_exception_random,
439 &catch_exception_random,
440 &catch_exception_random,
441 &catch_exception_random,
442 &catch_exception_random,
443 &catch_exception_random,
444 &catch_exception_random,
445 &catch_exception_random,
446 &catch_exception_random,
447 &catch_exception_random,
448 &catch_exception_random,
449 &catch_exception_random,
450 &catch_exception_random,
451 &catch_exception_random,
452 &catch_exception_random,
453 &catch_exception_random,
454 &catch_exception_random,
455 &catch_exception_random,
456 &catch_exception_random,
457 &catch_exception_random,
458 &catch_exception_random,
459 &catch_exception_random,
460 &catch_exception_random,
461 &catch_exception_random,
462 &catch_exception_random,
463 &catch_exception_random,
464 &catch_exception_random,
465 &catch_exception_random,
466 &catch_exception_random,
467 &catch_exception_random,
468 &catch_exception_random,
469 &catch_exception_random,
470 &catch_exception_random,
471 &catch_exception_random,
472 &catch_exception_random,
473 &catch_exception_random,
474 &catch_exception_random,
475 &catch_exception_random,
476 &catch_exception_random,
477 &catch_exception_random,
478 &catch_exception_random,
479 &catch_exception_random,
480 &catch_exception_random,
481 &catch_exception_random,
482 &catch_exception_random,
483 &catch_exception_random,
484 &catch_exception_random,
485 &catch_exception_random,
486 &catch_exception_random,
487 &catch_exception_random,
488 &catch_exception_random,
489 &catch_exception_random,
490 &catch_exception_random,
491 &catch_exception_random,
492 &catch_exception_random,
493 &catch_exception_random,
494 &catch_exception_random,
495 &catch_exception_random,
496 &catch_exception_random,
497 &catch_exception_random,
498 &catch_exception_random,
499 &catch_exception_random,
500 &catch_exception_random,
501 &catch_exception_random,
502 &catch_exception_random,
503 &catch_exception_random,
504 &catch_exception_random,
505 &catch_exception_random,
506 &catch_exception_random,
507 &catch_exception_random,
508 &catch_exception_random,
509 &catch_exception_random,
510 &catch_exception_random,
511 &catch_exception_random,
512 &catch_exception_random,
513 &catch_exception_random,
514 &catch_exception_random,
515 &catch_exception_random,
516 &catch_exception_random,
517 &catch_exception_random,
518 &catch_exception_random,
519 &catch_exception_random,
520 &catch_exception_random,
521 &catch_exception_255}};
522
523
524char in_nmi; /* Set when handling an NMI, so we don't reenter */
525int dofault; /* Non zero, bus errors will raise exception */
526
527int *stub_sp;
528
529/* debug > 0 prints ill-formed commands in valid packets & checksum errors */
530int remote_debug;
531
532/* jump buffer used for setjmp/longjmp */
533jmp_buf remcomEnv;
534
535enum regnames
536 {
537 R0, R1, R2, R3, R4, R5, R6, R7,
538 R8, R9, R10, R11, R12, R13, R14,
539 R15, PC, PR, GBR, VBR, MACH, MACL, SR,
540 TICKS, STALLS, CYCLES, INSTS, PLR
541 };
542
543typedef struct
544 {
545 short *memAddr;
546 short oldInstr;
547 }
548stepData;
549
550int registers[NUMREGBYTES / 4];
551stepData instrBuffer;
552char stepped;
553static const char hexchars[] = "0123456789abcdef";
554char remcomInBuffer[BUFMAX];
555char remcomOutBuffer[BUFMAX];
556
557char highhex(int x)
558{
559 return hexchars[(x >> 4) & 0xf];
560}
561
562char lowhex(int x)
563{
564 return hexchars[x & 0xf];
565}
566
567/*
568 * Assembly macros
569 */
570
571#define BREAKPOINT() asm("trapa #0x20"::);
572
573
574/*
575 * Routines to handle hex data
576 */
577
578static int
579hex (char ch)
580{
581 if ((ch >= 'a') && (ch <= 'f'))
582 return (ch - 'a' + 10);
583 if ((ch >= '0') && (ch <= '9'))
584 return (ch - '0');
585 if ((ch >= 'A') && (ch <= 'F'))
586 return (ch - 'A' + 10);
587 return (-1);
588}
589
590/* convert the memory, pointed to by mem into hex, placing result in buf */
591/* return a pointer to the last char put in buf (null) */
592static char *
593mem2hex (char *mem, char *buf, int count)
594{
595 int i;
596 int ch;
597 for (i = 0; i < count; i++)
598 {
599 ch = *mem++;
600 *buf++ = highhex (ch);
601 *buf++ = lowhex (ch);
602 }
603 *buf = 0;
604 return (buf);
605}
606
607/* convert the hex array pointed to by buf into binary, to be placed in mem */
608/* return a pointer to the character after the last byte written */
609
610static char *
611hex2mem (char *buf, char *mem, int count)
612{
613 int i;
614 unsigned char ch;
615 for (i = 0; i < count; i++)
616 {
617 ch = hex (*buf++) << 4;
618 ch = ch + hex (*buf++);
619 *mem++ = ch;
620 }
621 return (mem);
622}
623
624/**********************************************/
625/* WHILE WE FIND NICE HEX CHARS, BUILD AN INT */
626/* RETURN NUMBER OF CHARS PROCESSED */
627/**********************************************/
628static int
629hexToInt (char **ptr, int *intValue)
630{
631 int numChars = 0;
632 int hexValue;
633
634 *intValue = 0;
635
636 while (**ptr)
637 {
638 hexValue = hex (**ptr);
639 if (hexValue >= 0)
640 {
641 *intValue = (*intValue << 4) | hexValue;
642 numChars++;
643 }
644 else
645 break;
646
647 (*ptr)++;
648 }
649
650 return (numChars);
651}
652
653/*
654 * Routines to get and put packets
655 */
656
657/* scan for the sequence $<data>#<checksum> */
658
659static
660void
661getpacket (char *buffer)
662{
663 unsigned char checksum;
664 unsigned char xmitcsum;
665 int i;
666 int count;
667 char ch;
668 do
669 {
670 /* wait around for the start character, ignore all other characters */
671 while ((ch = getDebugChar ()) != '$');
672 checksum = 0;
673 xmitcsum = -1;
674
675 count = 0;
676
677 /* now, read until a # or end of buffer is found */
678 while (count < BUFMAX)
679 {
680 ch = getDebugChar ();
681 if (ch == '#')
682 break;
683 checksum = checksum + ch;
684 buffer[count] = ch;
685 count = count + 1;
686 }
687 buffer[count] = 0;
688
689 if (ch == '#')
690 {
691 xmitcsum = hex (getDebugChar ()) << 4;
692 xmitcsum += hex (getDebugChar ());
693 if (checksum != xmitcsum)
694 putDebugChar ('-'); /* failed checksum */
695 else
696 {
697 putDebugChar ('+'); /* successful transfer */
698 /* if a sequence char is present, reply the sequence ID */
699 if (buffer[2] == ':')
700 {
701 putDebugChar (buffer[0]);
702 putDebugChar (buffer[1]);
703 /* remove sequence chars from buffer */
704 count = strlen (buffer);
705 for (i = 3; i <= count; i++)
706 buffer[i - 3] = buffer[i];
707 }
708 }
709 }
710 }
711 while (checksum != xmitcsum);
712
713}
714
715
716/* send the packet in buffer. The host get's one chance to read it.
717 This routine does not wait for a positive acknowledge. */
718
719static void
720putpacket (register char *buffer)
721{
722 register int checksum;
723 register int count;
724
725 /* $<packet info>#<checksum>. */
726 do
727 {
728 char *src = buffer;
729 putDebugChar ('$');
730 checksum = 0;
731
732 while (*src)
733 {
734 int runlen;
735
736 /* Do run length encoding */
737 for (runlen = 0; runlen < 100; runlen ++)
738 {
739 if (src[0] != src[runlen])
740 {
741 if (runlen > 3)
742 {
743 int encode;
744 /* Got a useful amount */
745 putDebugChar (*src);
746 checksum += *src;
747 putDebugChar ('*');
748 checksum += '*';
749 checksum += (encode = runlen + ' ' - 4);
750 putDebugChar (encode);
751 src += runlen;
752 }
753 else
754 {
755 putDebugChar (*src);
756 checksum += *src;
757 src++;
758 }
759 break;
760 }
761 }
762 }
763
764
765 putDebugChar ('#');
766 putDebugChar (highhex(checksum));
767 putDebugChar (lowhex(checksum));
768 }
769 while (getDebugChar() != '+');
770
771}
772
773
774/* a bus error has occurred, perform a longjmp
775 to return execution and allow handling of the error */
776
777void
778handle_buserror (void)
779{
780 longjmp (remcomEnv, 1);
781}
782
783/*
784 * this function takes the SH-1 exception number and attempts to
785 * translate this number into a unix compatible signal value
786 */
787static int
788computeSignal (int exceptionVector)
789{
790 int sigval;
791 switch (exceptionVector)
792 {
793 case INVALID_INSN_VEC:
794 sigval = 4;
795 break;
796 case INVALID_SLOT_VEC:
797 sigval = 4;
798 break;
799 case CPU_BUS_ERROR_VEC:
800 sigval = 10;
801 break;
802 case DMA_BUS_ERROR_VEC:
803 sigval = 10;
804 break;
805 case NMI_VEC:
806 sigval = 2;
807 break;
808
809 case TRAP_VEC:
810 case USER_VEC:
811 sigval = 5;
812 break;
813
814 default:
815 sigval = 7; /* "software generated"*/
816 break;
817 }
818 return (sigval);
819}
820
821void
822doSStep (void)
823{
824 short *instrMem;
825 int displacement;
826 int reg;
827 unsigned short opcode;
828
829 instrMem = (short *) registers[PC];
830
831 opcode = *instrMem;
832 stepped = 1;
833
834 if ((opcode & COND_BR_MASK) == BT_INSTR)
835 {
836 if (registers[SR] & T_BIT_MASK)
837 {
838 displacement = (opcode & COND_DISP) << 1;
839 if (displacement & 0x80)
840 displacement |= 0xffffff00;
841 /*
842 * Remember PC points to second instr.
843 * after PC of branch ... so add 4
844 */
845 instrMem = (short *) (registers[PC] + displacement + 4);
846 }
847 else
848 instrMem += 1;
849 }
850 else if ((opcode & COND_BR_MASK) == BF_INSTR)
851 {
852 if (registers[SR] & T_BIT_MASK)
853 instrMem += 1;
854 else
855 {
856 displacement = (opcode & COND_DISP) << 1;
857 if (displacement & 0x80)
858 displacement |= 0xffffff00;
859 /*
860 * Remember PC points to second instr.
861 * after PC of branch ... so add 4
862 */
863 instrMem = (short *) (registers[PC] + displacement + 4);
864 }
865 }
866 else if ((opcode & UCOND_DBR_MASK) == BRA_INSTR)
867 {
868 displacement = (opcode & UCOND_DISP) << 1;
869 if (displacement & 0x0800)
870 displacement |= 0xfffff000;
871
872 /*
873 * Remember PC points to second instr.
874 * after PC of branch ... so add 4
875 */
876 instrMem = (short *) (registers[PC] + displacement + 4);
877 }
878 else if ((opcode & UCOND_RBR_MASK) == JSR_INSTR)
879 {
880 reg = (char) ((opcode & UCOND_REG) >> 8);
881
882 instrMem = (short *) registers[reg];
883 }
884 else if (opcode == RTS_INSTR)
885 instrMem = (short *) registers[PR];
886 else if (opcode == RTE_INSTR)
887 instrMem = (short *) registers[15];
888 else if ((opcode & TRAPA_MASK) == TRAPA_INSTR)
889 instrMem = (short *) ((opcode & ~TRAPA_MASK) << 2);
890 else
891 instrMem += 1;
892
893 instrBuffer.memAddr = instrMem;
894 instrBuffer.oldInstr = *instrMem;
895 *instrMem = SSTEP_INSTR;
896}
897
898void
899undoSStep (void)
900{
901 /*
902 If we single stepped,
903 restore the old instruction!
904*/
905 if (stepped)
906 { short *instrMem;
907 instrMem = instrBuffer.memAddr;
908 *instrMem = instrBuffer.oldInstr;
909 }
910 stepped = 0;
911}
912
913/*
914This function does all exception handling. It only does two things -
915it figures out why it was called and tells gdb, and then it reacts
916to gdb's requests.
917
918When in the monitor mode we talk a human on the serial line rather than gdb.
919
920*/
921
922
923void
924gdb_handle_exception (int exceptionVector)
925{
926 int sigval;
927 int addr, length;
928 char *ptr;
929
930 /* reply to host that an exception has occurred */
931 sigval = computeSignal (exceptionVector);
932 remcomOutBuffer[0] = 'S';
933 remcomOutBuffer[1] = highhex(sigval);
934 remcomOutBuffer[2] = lowhex (sigval);
935 remcomOutBuffer[3] = 0;
936
937 putpacket (remcomOutBuffer);
938
939 /*
940 * exception 255 indicates a software trap
941 * inserted in place of code ... so back up
942 * PC by one instruction, since this instruction
943 * will later be replaced by its original one!
944 */
945 if (exceptionVector == 0xff
946 || exceptionVector == 0x20)
947 registers[PC] -= 2;
948
949 /*
950 * Do the thangs needed to undo
951 * any stepping we may have done!
952 */
953 undoSStep ();
954
955 while (1)
956 {
957 remcomOutBuffer[0] = 0;
958 getpacket (remcomInBuffer);
959
960 switch (remcomInBuffer[0])
961 {
962 case '?':
963 remcomOutBuffer[0] = 'S';
964 remcomOutBuffer[1] = highhex (sigval);
965 remcomOutBuffer[2] = lowhex (sigval);
966 remcomOutBuffer[3] = 0;
967 break;
968 case 'd':
969 remote_debug = !(remote_debug); /* toggle debug flag */
970 break;
971 case 'g': /* return the value of the CPU registers */
972 mem2hex ((char *) registers, remcomOutBuffer, NUMREGBYTES);
973 break;
974 case 'G': /* set the value of the CPU registers - return OK */
975 hex2mem (&remcomInBuffer[1], (char *) registers, NUMREGBYTES);
976 strcpy (remcomOutBuffer, "OK");
977 break;
978
979 /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
980 case 'm':
981 if (setjmp (remcomEnv) == 0)
982 {
983 dofault = 0;
984 /* TRY, TO READ %x,%x. IF SUCCEED, SET PTR = 0 */
985 ptr = &remcomInBuffer[1];
986 if (hexToInt (&ptr, &addr))
987 if (*(ptr++) == ',')
988 if (hexToInt (&ptr, &length))
989 {
990 ptr = 0;
991 mem2hex ((char *) addr, remcomOutBuffer, length);
992 }
993 if (ptr)
994 strcpy (remcomOutBuffer, "E01");
995 }
996 else
997 strcpy (remcomOutBuffer, "E03");
998
999 /* restore handler for bus error */
1000 dofault = 1;
1001 break;
1002
1003 /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
1004 case 'M':
1005 if (setjmp (remcomEnv) == 0)
1006 {
1007 dofault = 0;
1008
1009 /* TRY, TO READ '%x,%x:'. IF SUCCEED, SET PTR = 0 */
1010 ptr = &remcomInBuffer[1];
1011 if (hexToInt (&ptr, &addr))
1012 if (*(ptr++) == ',')
1013 if (hexToInt (&ptr, &length))
1014 if (*(ptr++) == ':')
1015 {
1016 hex2mem (ptr, (char *) addr, length);
1017 ptr = 0;
1018 strcpy (remcomOutBuffer, "OK");
1019 }
1020 if (ptr)
1021 strcpy (remcomOutBuffer, "E02");
1022 }
1023 else
1024 strcpy (remcomOutBuffer, "E03");
1025
1026 /* restore handler for bus error */
1027 dofault = 1;
1028 break;
1029
1030 /* cAA..AA Continue at address AA..AA(optional) */
1031 /* sAA..AA Step one instruction from AA..AA(optional) */
1032 case 'c':
1033 case 's':
1034 {
1035 /* tRY, to read optional parameter, pc unchanged if no parm */
1036 ptr = &remcomInBuffer[1];
1037 if (hexToInt (&ptr, &addr))
1038 registers[PC] = addr;
1039
1040 if (remcomInBuffer[0] == 's')
1041 doSStep ();
1042 }
1043 return;
1044 break;
1045
1046 /* kill the program */
1047 case 'k': /* do nothing */
1048 break;
1049 } /* switch */
1050
1051 /* reply to the request */
1052 putpacket (remcomOutBuffer);
1053 }
1054}
1055
1056
1057#define GDBCOOKIE 0x5ac
1058static int ingdbmode;
1059/* We've had an exception - choose to go into the monitor or
1060 the gdb stub */
1061void handle_exception(int exceptionVector)
1062{
1063#ifdef MONITOR
1064 if (ingdbmode != GDBCOOKIE)
1065 monitor_handle_exception (exceptionVector);
1066 else
1067#endif
1068 gdb_handle_exception (exceptionVector);
1069
1070}
1071
1072void
1073gdb_mode()
1074{
1075 ingdbmode = GDBCOOKIE;
1076 breakpoint();
1077}
1078/* This function will generate a breakpoint exception. It is used at the
1079 beginning of a program to sync up with a debugger and can be used
1080 otherwise as a quick means to stop program execution and "break" into
1081 the debugger. */
1082
1083void
1084breakpoint (void)
1085{
1086 BREAKPOINT ();
1087}
1088
1089asm ("_BINIT: mov.l L1,r15");
1090asm ("bra _INIT");
1091asm ("nop");
1092asm ("L1: .long _init_stack + 8*1024*4");
1093void
1094INIT (void)
1095{
1096 /* First turn on the ram */
1097 WCR1 = 0; /* Never sample wait */
1098 BCR = BAS; /* use lowbyte/high byte */
1099
1100 init_serial();
1101
1102#ifdef MONITOR
1103 reset_hook ();
1104#endif
1105
1106
1107 in_nmi = 0;
1108 dofault = 1;
1109 stepped = 0;
1110
1111 stub_sp = stub_stack + stub_stack_size;
1112 breakpoint ();
1113
1114 while (1)
1115 ;
1116}
1117
1118
1119static void sr()
1120{
1121
1122
1123 /* Calling Reset does the same as pressing the button */
1124 asm (".global _Reset
1125 .global _WarmReset
1126_Reset:
1127_WarmReset:
1128 mov.l L_sp,r15
1129 bra _INIT
1130 nop
1131 .align 2
1132L_sp: .long _init_stack + 8000");
1133
1134 asm("saveRegisters:
1135 mov.l @(L_reg, pc), r0
1136 mov.l @r15+, r1 ! pop R0
1137 mov.l r2, @(0x08, r0) ! save R2
1138 mov.l r1, @r0 ! save R0
1139 mov.l @r15+, r1 ! pop R1
1140 mov.l r3, @(0x0c, r0) ! save R3
1141 mov.l r1, @(0x04, r0) ! save R1
1142 mov.l r4, @(0x10, r0) ! save R4
1143 mov.l r5, @(0x14, r0) ! save R5
1144 mov.l r6, @(0x18, r0) ! save R6
1145 mov.l r7, @(0x1c, r0) ! save R7
1146 mov.l r8, @(0x20, r0) ! save R8
1147 mov.l r9, @(0x24, r0) ! save R9
1148 mov.l r10, @(0x28, r0) ! save R10
1149 mov.l r11, @(0x2c, r0) ! save R11
1150 mov.l r12, @(0x30, r0) ! save R12
1151 mov.l r13, @(0x34, r0) ! save R13
1152 mov.l r14, @(0x38, r0) ! save R14
1153 mov.l @r15+, r4 ! save arg to handleException
1154 add #8, r15 ! hide PC/SR values on stack
1155 mov.l r15, @(0x3c, r0) ! save R15
1156 add #-8, r15 ! save still needs old SP value
1157 add #92, r0 ! readjust register pointer
1158 mov r15, r2
1159 add #4, r2
1160 mov.l @r2, r2 ! R2 has SR
1161 mov.l @r15, r1 ! R1 has PC
1162 mov.l r2, @-r0 ! save SR
1163 sts.l macl, @-r0 ! save MACL
1164 sts.l mach, @-r0 ! save MACH
1165 stc.l vbr, @-r0 ! save VBR
1166 stc.l gbr, @-r0 ! save GBR
1167 sts.l pr, @-r0 ! save PR
1168 mov.l @(L_stubstack, pc), r2
1169 mov.l @(L_hdl_except, pc), r3
1170 mov.l @r2, r15
1171 jsr @r3
1172 mov.l r1, @-r0 ! save PC
1173 mov.l @(L_stubstack, pc), r0
1174 mov.l @(L_reg, pc), r1
1175 bra restoreRegisters
1176 mov.l r15, @r0 ! save __stub_stack
1177
1178 .align 2
1179L_reg:
1180 .long _registers
1181L_stubstack:
1182 .long _stub_sp
1183L_hdl_except:
1184 .long _handle_exception");
1185
1186}
1187
1188static void rr()
1189{
1190asm("
1191 .align 2
1192 .global _resume
1193_resume:
1194 mov r4,r1
1195restoreRegisters:
1196 add #8, r1 ! skip to R2
1197 mov.l @r1+, r2 ! restore R2
1198 mov.l @r1+, r3 ! restore R3
1199 mov.l @r1+, r4 ! restore R4
1200 mov.l @r1+, r5 ! restore R5
1201 mov.l @r1+, r6 ! restore R6
1202 mov.l @r1+, r7 ! restore R7
1203 mov.l @r1+, r8 ! restore R8
1204 mov.l @r1+, r9 ! restore R9
1205 mov.l @r1+, r10 ! restore R10
1206 mov.l @r1+, r11 ! restore R11
1207 mov.l @r1+, r12 ! restore R12
1208 mov.l @r1+, r13 ! restore R13
1209 mov.l @r1+, r14 ! restore R14
1210 mov.l @r1+, r15 ! restore programs stack
1211 mov.l @r1+, r0
1212 add #-8, r15 ! uncover PC/SR on stack
1213 mov.l r0, @r15 ! restore PC onto stack
1214 lds.l @r1+, pr ! restore PR
1215 ldc.l @r1+, gbr ! restore GBR
1216 ldc.l @r1+, vbr ! restore VBR
1217 lds.l @r1+, mach ! restore MACH
1218 lds.l @r1+, macl ! restore MACL
1219 mov.l @r1, r0
1220 add #-88, r1 ! readjust reg pointer to R1
1221 mov.l r0, @(4, r15) ! restore SR onto stack+4
1222 mov.l r2, @-r15
1223 mov.l L_in_nmi, r0
1224 mov #0, r2
1225 mov.b r2, @r0
1226 mov.l @r15+, r2
1227 mov.l @r1+, r0 ! restore R0
1228 rte
1229 mov.l @r1, r1 ! restore R1
1230
1231");
1232}
1233
1234
1235static __inline__ void code_for_catch_exception(int n)
1236{
1237 asm(" .globl _catch_exception_%O0" : : "i" (n) );
1238 asm(" _catch_exception_%O0:" :: "i" (n) );
1239
1240 asm(" add #-4, r15 ! reserve spot on stack ");
1241 asm(" mov.l r1, @-r15 ! push R1 ");
1242
1243 if (n == NMI_VEC)
1244 {
1245 /* Special case for NMI - make sure that they don't nest */
1246 asm(" mov.l r0, @-r15 ! push R0");
1247 asm(" mov.l L_in_nmi, r0");
1248 asm(" tas.b @r0 ! Fend off against addtnl NMIs");
1249 asm(" bt noNMI");
1250 asm(" mov.l @r15+, r0");
1251 asm(" mov.l @r15+, r1");
1252 asm(" add #4, r15");
1253 asm(" rte");
1254 asm(" nop");
1255 asm(".align 2");
1256 asm("L_in_nmi: .long _in_nmi");
1257 asm("noNMI:");
1258 }
1259 else
1260 {
1261
1262 if (n == CPU_BUS_ERROR_VEC)
1263 {
1264 /* Exception 9 (bus errors) are disasbleable - so that you
1265 can probe memory and get zero instead of a fault.
1266 Because the vector table may be in ROM we don't revector
1267 the interrupt like all the other stubs, we check in here
1268 */
1269 asm("mov.l L_dofault,r1");
1270 asm("mov.l @r1,r1");
1271 asm("tst r1,r1");
1272 asm("bf faultaway");
1273 asm("bsr _handle_buserror");
1274 asm(".align 2");
1275 asm("L_dofault: .long _dofault");
1276 asm("faultaway:");
1277 }
1278 asm(" mov #15<<4, r1 ");
1279 asm(" ldc r1, sr ! disable interrupts ");
1280 asm(" mov.l r0, @-r15 ! push R0 ");
1281 }
1282
1283 /* Prepare for saving context, we've already pushed r0 and r1, stick exception number
1284 into the frame */
1285 asm(" mov r15, r0 ");
1286 asm(" add #8, r0 ");
1287 asm(" mov %0,r1" :: "i" (n) );
1288 asm(" extu.b r1,r1 ");
1289 asm(" bra saveRegisters ! save register values ");
1290 asm(" mov.l r1, @r0 ! save exception # ");
1291}
1292
1293
1294static void
1295exceptions()
1296{
1297 code_for_catch_exception (CPU_BUS_ERROR_VEC);
1298 code_for_catch_exception (DMA_BUS_ERROR_VEC);
1299 code_for_catch_exception (INVALID_INSN_VEC);
1300 code_for_catch_exception (INVALID_SLOT_VEC);
1301 code_for_catch_exception (NMI_VEC);
1302 code_for_catch_exception (TRAP_VEC);
1303 code_for_catch_exception (USER_VEC);
1304 code_for_catch_exception (IO_VEC);
1305}
1306
1307
1308
1309
1310
1311
1312/* Support for Serial I/O using on chip uart */
1313
1314#define SMR0 (*(volatile char *)(0x05FFFEC0)) /* Channel 0 serial mode register */
1315#define BRR0 (*(volatile char *)(0x05FFFEC1)) /* Channel 0 bit rate register */
1316#define SCR0 (*(volatile char *)(0x05FFFEC2)) /* Channel 0 serial control register */
1317#define TDR0 (*(volatile char *)(0x05FFFEC3)) /* Channel 0 transmit data register */
1318#define SSR0 (*(volatile char *)(0x05FFFEC4)) /* Channel 0 serial status register */
1319#define RDR0 (*(volatile char *)(0x05FFFEC5)) /* Channel 0 receive data register */
1320
1321#define SMR1 (*(volatile char *)(0x05FFFEC8)) /* Channel 1 serial mode register */
1322#define BRR1 (*(volatile char *)(0x05FFFEC9)) /* Channel 1 bit rate register */
1323#define SCR1 (*(volatile char *)(0x05FFFECA)) /* Channel 1 serial control register */
1324#define TDR1 (*(volatile char *)(0x05FFFECB)) /* Channel 1 transmit data register */
1325#define SSR1 (*(volatile char *)(0x05FFFECC)) /* Channel 1 serial status register */
1326#define RDR1 (*(volatile char *)(0x05FFFECD)) /* Channel 1 receive data register */
1327
1328/*
1329 * Serial mode register bits
1330 */
1331
1332#define SYNC_MODE 0x80
1333#define SEVEN_BIT_DATA 0x40
1334#define PARITY_ON 0x20
1335#define ODD_PARITY 0x10
1336#define STOP_BITS_2 0x08
1337#define ENABLE_MULTIP 0x04
1338#define PHI_64 0x03
1339#define PHI_16 0x02
1340#define PHI_4 0x01
1341
1342/*
1343 * Serial control register bits
1344 */
1345#define SCI_TIE 0x80 /* Transmit interrupt enable */
1346#define SCI_RIE 0x40 /* Receive interrupt enable */
1347#define SCI_TE 0x20 /* Transmit enable */
1348#define SCI_RE 0x10 /* Receive enable */
1349#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
1350#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
1351#define SCI_CKE1 0x02 /* Clock enable 1 */
1352#define SCI_CKE0 0x01 /* Clock enable 0 */
1353
1354/*
1355 * Serial status register bits
1356 */
1357#define SCI_TDRE 0x80 /* Transmit data register empty */
1358#define SCI_RDRF 0x40 /* Receive data register full */
1359#define SCI_ORER 0x20 /* Overrun error */
1360#define SCI_FER 0x10 /* Framing error */
1361#define SCI_PER 0x08 /* Parity error */
1362#define SCI_TEND 0x04 /* Transmit end */
1363#define SCI_MPB 0x02 /* Multiprocessor bit */
1364#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
1365
1366
1367/*
1368 * Port B IO Register (PBIOR)
1369 */
1370#define PBIOR (*(volatile char *)(0x05FFFFC6))
1371#define PB15IOR 0x8000
1372#define PB14IOR 0x4000
1373#define PB13IOR 0x2000
1374#define PB12IOR 0x1000
1375#define PB11IOR 0x0800
1376#define PB10IOR 0x0400
1377#define PB9IOR 0x0200
1378#define PB8IOR 0x0100
1379#define PB7IOR 0x0080
1380#define PB6IOR 0x0040
1381#define PB5IOR 0x0020
1382#define PB4IOR 0x0010
1383#define PB3IOR 0x0008
1384#define PB2IOR 0x0004
1385#define PB1IOR 0x0002
1386#define PB0IOR 0x0001
1387
1388/*
1389 * Port B Control Register (PBCR1)
1390 */
1391#define PBCR1 (*(volatile short *)(0x05FFFFCC))
1392#define PB15MD1 0x8000
1393#define PB15MD0 0x4000
1394#define PB14MD1 0x2000
1395#define PB14MD0 0x1000
1396#define PB13MD1 0x0800
1397#define PB13MD0 0x0400
1398#define PB12MD1 0x0200
1399#define PB12MD0 0x0100
1400#define PB11MD1 0x0080
1401#define PB11MD0 0x0040
1402#define PB10MD1 0x0020
1403#define PB10MD0 0x0010
1404#define PB9MD1 0x0008
1405#define PB9MD0 0x0004
1406#define PB8MD1 0x0002
1407#define PB8MD0 0x0001
1408
1409#define PB15MD PB15MD1|PB14MD0
1410#define PB14MD PB14MD1|PB14MD0
1411#define PB13MD PB13MD1|PB13MD0
1412#define PB12MD PB12MD1|PB12MD0
1413#define PB11MD PB11MD1|PB11MD0
1414#define PB10MD PB10MD1|PB10MD0
1415#define PB9MD PB9MD1|PB9MD0
1416#define PB8MD PB8MD1|PB8MD0
1417
1418#define PB_TXD1 PB11MD1
1419#define PB_RXD1 PB10MD1
1420#define PB_TXD0 PB9MD1
1421#define PB_RXD0 PB8MD1
1422
1423/*
1424 * Port B Control Register (PBCR2)
1425 */
1426#define PBCR2 0x05FFFFCE
1427#define PB7MD1 0x8000
1428#define PB7MD0 0x4000
1429#define PB6MD1 0x2000
1430#define PB6MD0 0x1000
1431#define PB5MD1 0x0800
1432#define PB5MD0 0x0400
1433#define PB4MD1 0x0200
1434#define PB4MD0 0x0100
1435#define PB3MD1 0x0080
1436#define PB3MD0 0x0040
1437#define PB2MD1 0x0020
1438#define PB2MD0 0x0010
1439#define PB1MD1 0x0008
1440#define PB1MD0 0x0004
1441#define PB0MD1 0x0002
1442#define PB0MD0 0x0001
1443
1444#define PB7MD PB7MD1|PB7MD0
1445#define PB6MD PB6MD1|PB6MD0
1446#define PB5MD PB5MD1|PB5MD0
1447#define PB4MD PB4MD1|PB4MD0
1448#define PB3MD PB3MD1|PB3MD0
1449#define PB2MD PB2MD1|PB2MD0
1450#define PB1MD PB1MD1|PB1MD0
1451#define PB0MD PB0MD1|PB0MD0
1452
1453
1454#ifdef MHZ
1455#define BPS 32 * 9600 * MHZ / ( BAUD * 10)
1456#else
1457#define BPS 32 /* 9600 for 10 Mhz */
1458#endif
1459
1460char getDebugChar (void);
1461int putDebugChar (char);
1462void handleError (char theSSR);
1463
1464void
1465nop ()
1466{
1467
1468}
1469void
1470init_serial()
1471{
1472 int i;
1473
1474 /* Clear TE and RE in Channel 1's SCR */
1475 SCR1 &= ~(SCI_TE | SCI_RE);
1476
1477 /* Set communication to be async, 8-bit data, no parity, 1 stop bit and use internal clock */
1478
1479 SMR1 = 0;
1480 BRR1 = BPS;
1481
1482 SCR1 &= ~(SCI_CKE1 | SCI_CKE0);
1483
1484 /* let the hardware settle */
1485
1486 for (i = 0; i < 1000; i++)
1487 nop ();
1488
1489 /* Turn on in and out */
1490 SCR1 |= SCI_RE | SCI_TE;
1491
1492 /* Set the PFC to make RXD1 (pin PB8) an input pin and TXD1 (pin PB9) an output pin */
1493 PBCR1 &= ~(PB_TXD1 | PB_RXD1);
1494 PBCR1 |= PB_TXD1 | PB_RXD1;
1495}
1496
1497
1498int
1499getDebugCharReady (void)
1500{
1501 char mySSR;
1502 mySSR = SSR1 & ( SCI_PER | SCI_FER | SCI_ORER );
1503 if ( mySSR )
1504 handleError ( mySSR );
1505 return SSR1 & SCI_RDRF ;
1506}
1507
1508char
1509getDebugChar (void)
1510{
1511 char ch;
1512 char mySSR;
1513
1514 while ( ! getDebugCharReady())
1515 ;
1516
1517 ch = RDR1;
1518 SSR1 &= ~SCI_RDRF;
1519
1520 mySSR = SSR1 & (SCI_PER | SCI_FER | SCI_ORER);
1521
1522 if (mySSR)
1523 handleError (mySSR);
1524
1525 return ch;
1526}
1527
1528int
1529putDebugCharReady()
1530{
1531 return (SSR1 & SCI_TDRE);
1532}
1533
1534int
1535putDebugChar (char ch)
1536{
1537 while (!putDebugCharReady())
1538 ;
1539
1540 /*
1541 * Write data into TDR and clear TDRE
1542 */
1543 TDR1 = ch;
1544 SSR1 &= ~SCI_TDRE;
1545 return 1;
1546}
1547
1548void
1549handleError (char theSSR)
1550{
1551 SSR1 &= ~(SCI_ORER | SCI_PER | SCI_FER);
1552}
1553
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