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[binutils.git] / gdb / sh64-tdep.c
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85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
cf5b2f1b
AC		 2
3 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
4 2002, 2003, 2004 Free Software Foundation, Inc.
55ff77ac
CV		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23/*
24 Contributed by Steve Chamberlain
25 [email protected]
26 */
27
28#include "defs.h"
29#include "frame.h"
30#include "symtab.h"
9ab9195f 31#include "objfiles.h"
55ff77ac
CV		 32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h"
38#include "gdb_string.h"
39#include "arch-utils.h"
40#include "floatformat.h"
41#include "regcache.h"
42#include "doublest.h"
43#include "osabi.h"
44
45#include "elf-bfd.h"
46#include "solib-svr4.h"
47
48/* sh flags */
49#include "elf/sh.h"
50/* registers numbers shared with the simulator */
51#include "gdb/sim-sh.h"
52
7bb11558 53/* Information that is dependent on the processor variant. */
55ff77ac
CV		 54enum sh_abi
55 {
56 SH_ABI_UNKNOWN,
57 SH_ABI_32,
58 SH_ABI_64
59 };
60
61struct gdbarch_tdep
62 {
63 enum sh_abi sh_abi;
64 };
65
66/* Registers of SH5 */
67enum
68 {
69 R0_REGNUM = 0,
70 DEFAULT_RETURN_REGNUM = 2,
71 STRUCT_RETURN_REGNUM = 2,
72 ARG0_REGNUM = 2,
73 ARGLAST_REGNUM = 9,
74 FLOAT_ARGLAST_REGNUM = 11,
75 PR_REGNUM = 18,
76 SR_REGNUM = 65,
77 DR0_REGNUM = 141,
78 DR_LAST_REGNUM = 172,
79 /* FPP stands for Floating Point Pair, to avoid confusion with
80 GDB's FP0_REGNUM, which is the number of the first Floating
81 point register. Unfortunately on the sh5, the floating point
7bb11558 82 registers are called FR, and the floating point pairs are called FP. */
55ff77ac
CV		 83 FPP0_REGNUM = 173,
84 FPP_LAST_REGNUM = 204,
85 FV0_REGNUM = 205,
86 FV_LAST_REGNUM = 220,
87 R0_C_REGNUM = 221,
88 R_LAST_C_REGNUM = 236,
89 PC_C_REGNUM = 237,
90 GBR_C_REGNUM = 238,
91 MACH_C_REGNUM = 239,
92 MACL_C_REGNUM = 240,
93 PR_C_REGNUM = 241,
94 T_C_REGNUM = 242,
95 FPSCR_C_REGNUM = 243,
96 FPUL_C_REGNUM = 244,
97 FP0_C_REGNUM = 245,
98 FP_LAST_C_REGNUM = 260,
99 DR0_C_REGNUM = 261,
100 DR_LAST_C_REGNUM = 268,
101 FV0_C_REGNUM = 269,
102 FV_LAST_C_REGNUM = 272,
103 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
104 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
105 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
106 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
107 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
108 };
109
110
111/* Define other aspects of the stack frame.
112 we keep a copy of the worked out return pc lying around, since it
113 is a useful bit of info */
114
115struct frame_extra_info
116{
117 CORE_ADDR return_pc;
118 int leaf_function;
119 int f_offset;
120};
121
122static const char *
39add00a 123sh64_register_name (int reg_nr)
55ff77ac
CV		 124{
125 static char *register_names[] =
126 {
127 /* SH MEDIA MODE (ISA 32) */
128 /* general registers (64-bit) 0-63 */
129 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
130 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
131 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
132 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
133 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
134 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
135 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
136 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
137
138 /* pc (64-bit) 64 */
139 "pc",
140
141 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
142 "sr", "ssr", "spc",
143
144 /* target registers (64-bit) 68-75*/
145 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
146
147 /* floating point state control register (32-bit) 76 */
148 "fpscr",
149
150 /* single precision floating point registers (32-bit) 77-140*/
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
153 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
154 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
155 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
156 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
157 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
158 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
159
160 /* double precision registers (pseudo) 141-172 */
161 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
162 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
163 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
164 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
165
166 /* floating point pairs (pseudo) 173-204*/
167 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
168 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
169 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
170 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
171
172 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
173 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
174 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
175
176 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
177 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
178 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
179 "pc_c",
180 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
181 "fpscr_c", "fpul_c",
182 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
183 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
184 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
185 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
186 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
187 };
188
189 if (reg_nr < 0)
190 return NULL;
191 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
192 return NULL;
193 return register_names[reg_nr];
194}
195
196#define NUM_PSEUDO_REGS_SH_MEDIA 80
197#define NUM_PSEUDO_REGS_SH_COMPACT 51
198
199/* Macros and functions for setting and testing a bit in a minimal
200 symbol that marks it as 32-bit function. The MSB of the minimal
f594e5e9 201 symbol's "info" field is used for this purpose.
55ff77ac
CV		 202
203 ELF_MAKE_MSYMBOL_SPECIAL
204 tests whether an ELF symbol is "special", i.e. refers
205 to a 32-bit function, and sets a "special" bit in a
206 minimal symbol to mark it as a 32-bit function
f594e5e9 207 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
55ff77ac
CV		 208
209#define MSYMBOL_IS_SPECIAL(msym) \
210 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
211
212static void
213sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
214{
215 if (msym == NULL)
216 return;
217
218 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
219 {
220 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
221 SYMBOL_VALUE_ADDRESS (msym) |= 1;
222 }
223}
224
225/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
226 are some macros to test, set, or clear bit 0 of addresses. */
227#define IS_ISA32_ADDR(addr) ((addr) & 1)
228#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
229#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
230
231static int
232pc_is_isa32 (bfd_vma memaddr)
233{
234 struct minimal_symbol *sym;
235
236 /* If bit 0 of the address is set, assume this is a
7bb11558 237 ISA32 (shmedia) address. */
55ff77ac
CV		 238 if (IS_ISA32_ADDR (memaddr))
239 return 1;
240
241 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
242 the high bit of the info field. Use this to decide if the function is
243 ISA16 or ISA32. */
244 sym = lookup_minimal_symbol_by_pc (memaddr);
245 if (sym)
246 return MSYMBOL_IS_SPECIAL (sym);
247 else
248 return 0;
249}
250
251static const unsigned char *
39add00a 252sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
55ff77ac
CV		 253{
254 /* The BRK instruction for shmedia is
255 01101111 11110101 11111111 11110000
256 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
257 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
258
259 /* The BRK instruction for shcompact is
260 00000000 00111011
261 which translates in big endian mode to 0x0, 0x3b
262 and in little endian mode to 0x3b, 0x0*/
263
264 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
265 {
266 if (pc_is_isa32 (*pcptr))
267 {
268 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
269 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
270 *lenptr = sizeof (big_breakpoint_media);
271 return big_breakpoint_media;
272 }
273 else
274 {
275 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
276 *lenptr = sizeof (big_breakpoint_compact);
277 return big_breakpoint_compact;
278 }
279 }
280 else
281 {
282 if (pc_is_isa32 (*pcptr))
283 {
284 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
285 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
286 *lenptr = sizeof (little_breakpoint_media);
287 return little_breakpoint_media;
288 }
289 else
290 {
291 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
292 *lenptr = sizeof (little_breakpoint_compact);
293 return little_breakpoint_compact;
294 }
295 }
296}
297
298/* Prologue looks like
299 [mov.l <regs>,@-r15]...
300 [sts.l pr,@-r15]
301 [mov.l r14,@-r15]
302 [mov r15,r14]
303
304 Actually it can be more complicated than this. For instance, with
305 newer gcc's:
306
307 mov.l r14,@-r15
308 add #-12,r15
309 mov r15,r14
310 mov r4,r1
311 mov r5,r2
312 mov.l r6,@(4,r14)
313 mov.l r7,@(8,r14)
314 mov.b r1,@r14
315 mov r14,r1
316 mov r14,r1
317 add #2,r1
318 mov.w r2,@r1
319
320 */
321
322/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
323 with l=1 and n = 18 0110101111110001010010100aaa0000 */
324#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
325
326/* STS.L PR,@-r0 0100000000100010
327 r0-4-->r0, PR-->(r0) */
328#define IS_STS_R0(x) ((x) == 0x4022)
329
330/* STS PR, Rm 0000mmmm00101010
331 PR-->Rm */
332#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
333
334/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
335 Rm-->(dispx4+r15) */
336#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
337
338/* MOV.L R14,@(disp,r15) 000111111110dddd
339 R14-->(dispx4+r15) */
340#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
341
342/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
343 R18-->(dispx8+R14) */
344#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
345
346/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
347 R18-->(dispx8+R15) */
348#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
349
350/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
351 R18-->(dispx4+R15) */
352#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
353
354/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
355 R14-->(dispx8+R15) */
356#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
357
358/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
359 R14-->(dispx4+R15) */
360#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
361
362/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
363 R15 + imm --> R15 */
364#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
365
366/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
367 R15 + imm --> R15 */
368#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
369
370/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
371 R15 + R63 --> R14 */
372#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
373
374/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
375 R15 + R63 --> R14 */
376#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
377
378#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
379
380/* MOV #imm, R0 1110 0000 ssss ssss
381 #imm-->R0 */
382#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
383
384/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
385#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
386
387/* ADD r15,r0 0011 0000 1111 1100
388 r15+r0-->r0 */
389#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
390
391/* MOV.L R14 @-R0 0010 0000 1110 0110
392 R14-->(R0-4), R0-4-->R0 */
393#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
394
395/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
7bb11558 396 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 397/* FIXME: Recognize the float and double register moves too! */
398#define IS_MEDIA_IND_ARG_MOV(x) \
399((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
400
401/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
402 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
7bb11558 403 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 404#define IS_MEDIA_ARG_MOV(x) \
405(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
406 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
407
408/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
409/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
410/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
411/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
412/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
413#define IS_MEDIA_MOV_TO_R14(x) \
414((((x) & 0xfffffc0f) == 0xa0e00000) \
415|| (((x) & 0xfffffc0f) == 0xa4e00000) \
416|| (((x) & 0xfffffc0f) == 0xa8e00000) \
417|| (((x) & 0xfffffc0f) == 0xb4e00000) \
418|| (((x) & 0xfffffc0f) == 0xbce00000))
419
420/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
421 where Rm is r2-r9 */
422#define IS_COMPACT_IND_ARG_MOV(x) \
423((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
424
425/* compact direct arg move!
426 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
427#define IS_COMPACT_ARG_MOV(x) \
428(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
429
430/* MOV.B Rm, @R14 0010 1110 mmmm 0000
431 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
432#define IS_COMPACT_MOV_TO_R14(x) \
433((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
434
435#define IS_JSR_R0(x) ((x) == 0x400b)
436#define IS_NOP(x) ((x) == 0x0009)
437
438
439/* MOV r15,r14 0110111011110011
440 r15-->r14 */
441#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
442
443/* ADD #imm,r15 01111111iiiiiiii
444 r15+imm-->r15 */
445#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
446
447/* Skip any prologue before the guts of a function */
448
7bb11558
MS		 449/* Skip the prologue using the debug information. If this fails we'll
450 fall back on the 'guess' method below. */
55ff77ac
CV		 451static CORE_ADDR
452after_prologue (CORE_ADDR pc)
453{
454 struct symtab_and_line sal;
455 CORE_ADDR func_addr, func_end;
456
457 /* If we can not find the symbol in the partial symbol table, then
458 there is no hope we can determine the function's start address
459 with this code. */
460 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
461 return 0;
462
463 /* Get the line associated with FUNC_ADDR. */
464 sal = find_pc_line (func_addr, 0);
465
466 /* There are only two cases to consider. First, the end of the source line
467 is within the function bounds. In that case we return the end of the
468 source line. Second is the end of the source line extends beyond the
469 bounds of the current function. We need to use the slow code to
470 examine instructions in that case. */
471 if (sal.end < func_end)
472 return sal.end;
473 else
474 return 0;
475}
476
477static CORE_ADDR
478look_for_args_moves (CORE_ADDR start_pc, int media_mode)
479{
480 CORE_ADDR here, end;
481 int w;
482 int insn_size = (media_mode ? 4 : 2);
483
484 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
485 {
486 if (media_mode)
487 {
488 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
489 here += insn_size;
490 if (IS_MEDIA_IND_ARG_MOV (w))
491 {
492 /* This must be followed by a store to r14, so the argument
493 is where the debug info says it is. This can happen after
7bb11558 494 the SP has been saved, unfortunately. */
55ff77ac
CV		 495
496 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
497 insn_size);
498 here += insn_size;
499 if (IS_MEDIA_MOV_TO_R14 (next_insn))
500 start_pc = here;
501 }
502 else if (IS_MEDIA_ARG_MOV (w))
503 {
7bb11558 504 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 505 start_pc = here;
506 }
507 else
508 break;
509 }
510 else
511 {
512 w = read_memory_integer (here, insn_size);
513 w = w & 0xffff;
514 here += insn_size;
515 if (IS_COMPACT_IND_ARG_MOV (w))
516 {
517 /* This must be followed by a store to r14, so the argument
518 is where the debug info says it is. This can happen after
7bb11558 519 the SP has been saved, unfortunately. */
55ff77ac
CV		 520
521 int next_insn = 0xffff & read_memory_integer (here, insn_size);
522 here += insn_size;
523 if (IS_COMPACT_MOV_TO_R14 (next_insn))
524 start_pc = here;
525 }
526 else if (IS_COMPACT_ARG_MOV (w))
527 {
7bb11558 528 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 529 start_pc = here;
530 }
531 else if (IS_MOVL_R0 (w))
532 {
533 /* There is a function that gcc calls to get the arguments
534 passed correctly to the function. Only after this
535 function call the arguments will be found at the place
536 where they are supposed to be. This happens in case the
537 argument has to be stored into a 64-bit register (for
538 instance doubles, long longs). SHcompact doesn't have
539 access to the full 64-bits, so we store the register in
540 stack slot and store the address of the stack slot in
541 the register, then do a call through a wrapper that
542 loads the memory value into the register. A SHcompact
543 callee calls an argument decoder
544 (GCC_shcompact_incoming_args) that stores the 64-bit
545 value in a stack slot and stores the address of the
546 stack slot in the register. GCC thinks the argument is
547 just passed by transparent reference, but this is only
548 true after the argument decoder is called. Such a call
7bb11558 549 needs to be considered part of the prologue. */
55ff77ac
CV		 550
551 /* This must be followed by a JSR @r0 instruction and by
552 a NOP instruction. After these, the prologue is over! */
553
554 int next_insn = 0xffff & read_memory_integer (here, insn_size);
555 here += insn_size;
556 if (IS_JSR_R0 (next_insn))
557 {
558 next_insn = 0xffff & read_memory_integer (here, insn_size);
559 here += insn_size;
560
561 if (IS_NOP (next_insn))
562 start_pc = here;
563 }
564 }
565 else
566 break;
567 }
568 }
569
570 return start_pc;
571}
572
573static CORE_ADDR
574sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
575{
576 CORE_ADDR here, end;
577 int updated_fp = 0;
578 int insn_size = 4;
579 int media_mode = 1;
580
581 if (!start_pc)
582 return 0;
583
584 if (pc_is_isa32 (start_pc) == 0)
585 {
586 insn_size = 2;
587 media_mode = 0;
588 }
589
590 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
591 {
592
593 if (media_mode)
594 {
595 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
596 here += insn_size;
597 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
598 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
599 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
600 {
601 start_pc = here;
602 }
603 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
604 {
605 start_pc = here;
606 updated_fp = 1;
607 }
608 else
609 if (updated_fp)
610 {
611 /* Don't bail out yet, we may have arguments stored in
612 registers here, according to the debug info, so that
7bb11558 613 gdb can print the frames correctly. */
55ff77ac
CV		 614 start_pc = look_for_args_moves (here - insn_size, media_mode);
615 break;
616 }
617 }
618 else
619 {
620 int w = 0xffff & read_memory_integer (here, insn_size);
621 here += insn_size;
622
623 if (IS_STS_R0 (w) || IS_STS_PR (w)
624 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
625 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
626 {
627 start_pc = here;
628 }
629 else if (IS_MOV_SP_FP (w))
630 {
631 start_pc = here;
632 updated_fp = 1;
633 }
634 else
635 if (updated_fp)
636 {
637 /* Don't bail out yet, we may have arguments stored in
638 registers here, according to the debug info, so that
7bb11558 639 gdb can print the frames correctly. */
55ff77ac
CV		 640 start_pc = look_for_args_moves (here - insn_size, media_mode);
641 break;
642 }
643 }
644 }
645
646 return start_pc;
647}
648
649static CORE_ADDR
650sh_skip_prologue (CORE_ADDR pc)
651{
652 CORE_ADDR post_prologue_pc;
653
654 /* See if we can determine the end of the prologue via the symbol table.
655 If so, then return either PC, or the PC after the prologue, whichever
656 is greater. */
657 post_prologue_pc = after_prologue (pc);
658
659 /* If after_prologue returned a useful address, then use it. Else
7bb11558 660 fall back on the instruction skipping code. */
55ff77ac
CV		 661 if (post_prologue_pc != 0)
662 return max (pc, post_prologue_pc);
663 else
664 return sh64_skip_prologue_hard_way (pc);
665}
666
667/* Immediately after a function call, return the saved pc.
668 Can't always go through the frames for this because on some machines
669 the new frame is not set up until the new function executes
670 some instructions.
671
672 The return address is the value saved in the PR register + 4 */
673static CORE_ADDR
674sh_saved_pc_after_call (struct frame_info *frame)
675{
676 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
677}
678
679/* Should call_function allocate stack space for a struct return? */
680static int
681sh64_use_struct_convention (int gcc_p, struct type *type)
682{
683 return (TYPE_LENGTH (type) > 8);
684}
685
686/* Store the address of the place in which to copy the structure the
687 subroutine will return. This is called from call_function.
688
689 We store structs through a pointer passed in R2 */
690static void
691sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
692{
693 write_register (STRUCT_RETURN_REGNUM, (addr));
694}
695
696/* Disassemble an instruction. */
697static int
698gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
699{
700 info->endian = TARGET_BYTE_ORDER;
701 return print_insn_sh (memaddr, info);
702}
703
704/* Given a register number RN as it appears in an assembly
705 instruction, find the corresponding register number in the GDB
7bb11558 706 scheme. */
55ff77ac
CV		 707static int
708translate_insn_rn (int rn, int media_mode)
709{
55ff77ac 710 /* FIXME: this assumes that the number rn is for a not pseudo
7bb11558 711 register only. */
55ff77ac
CV		 712 if (media_mode)
713 return rn;
714 else
715 {
7bb11558
MS		 716 /* These registers don't have a corresponding compact one. */
717 /* FIXME: This is probably not enough. */
55ff77ac
CV		 718#if 0
719 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
720 return rn;
721#endif
722 if (rn >= 0 && rn <= R0_C_REGNUM)
723 return R0_C_REGNUM + rn;
724 else
725 return rn;
726 }
727}
728
729/* Given a GDB frame, determine the address of the calling function's
730 frame. This will be used to create a new GDB frame struct, and
731 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
732 will be called for the new frame.
733
734 For us, the frame address is its stack pointer value, so we look up
735 the function prologue to determine the caller's sp value, and return it. */
736static CORE_ADDR
737sh64_frame_chain (struct frame_info *frame)
738{
739 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
740 get_frame_base (frame),
741 get_frame_base (frame)))
7bb11558 742 return get_frame_base (frame); /* dummy frame same as caller's frame */
627b3ba2
AC		 743 if (get_frame_pc (frame)
744 && !deprecated_inside_entry_file (get_frame_pc (frame)))
55ff77ac
CV		 745 {
746 int media_mode = pc_is_isa32 (get_frame_pc (frame));
747 int size;
748 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
749 size = 4;
750 else
7bb11558
MS		 751 size = register_size (current_gdbarch,
752 translate_insn_rn (DEPRECATED_FP_REGNUM,
753 media_mode));
55ff77ac
CV		 754 return read_memory_integer (get_frame_base (frame)
755 + get_frame_extra_info (frame)->f_offset,
756 size);
757 }
758 else
759 return 0;
760}
761
762static CORE_ADDR
763sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
764{
765 int media_mode = 0;
766
767 for (; fi; fi = get_next_frame (fi))
768 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
769 get_frame_base (fi)))
7bb11558
MS		 770 /* When the caller requests PR from the dummy frame, we return
771 PC because that's where the previous routine appears to have
772 done a call from. */
55ff77ac
CV		 773 return deprecated_read_register_dummy (get_frame_pc (fi),
774 get_frame_base (fi), pr_regnum);
775 else
776 {
777 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
778 if (!get_frame_pc (fi))
779 return 0;
780
781 media_mode = pc_is_isa32 (get_frame_pc (fi));
782
1b1d3794 783 if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0)
55ff77ac
CV		 784 {
785 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
786 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
787 ? 4
7bb11558 788 : register_size (current_gdbarch, gdb_reg_num));
1b1d3794 789 return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size);
55ff77ac
CV		 790 }
791 }
792 return read_register (pr_regnum);
793}
794
7bb11558 795/* For vectors of 4 floating point registers. */
55ff77ac
CV		 796static int
797fv_reg_base_num (int fv_regnum)
798{
799 int fp_regnum;
800
801 fp_regnum = FP0_REGNUM +
802 (fv_regnum - FV0_REGNUM) * 4;
803 return fp_regnum;
804}
805
806/* For double precision floating point registers, i.e 2 fp regs.*/
807static int
808dr_reg_base_num (int dr_regnum)
809{
810 int fp_regnum;
811
812 fp_regnum = FP0_REGNUM +
813 (dr_regnum - DR0_REGNUM) * 2;
814 return fp_regnum;
815}
816
817/* For pairs of floating point registers */
818static int
819fpp_reg_base_num (int fpp_regnum)
820{
821 int fp_regnum;
822
823 fp_regnum = FP0_REGNUM +
824 (fpp_regnum - FPP0_REGNUM) * 2;
825 return fp_regnum;
826}
827
828static int
829is_media_pseudo (int rn)
830{
2a314ed5 831 return (rn >= DR0_REGNUM && rn <= FV_LAST_REGNUM);
55ff77ac
CV		 832}
833
55ff77ac
CV		 834static int
835sh64_media_reg_base_num (int reg_nr)
836{
837 int base_regnum = -1;
55ff77ac
CV		 838
839 if (reg_nr >= DR0_REGNUM
840 && reg_nr <= DR_LAST_REGNUM)
841 base_regnum = dr_reg_base_num (reg_nr);
842
843 else if (reg_nr >= FPP0_REGNUM
844 && reg_nr <= FPP_LAST_REGNUM)
845 base_regnum = fpp_reg_base_num (reg_nr);
846
847 else if (reg_nr >= FV0_REGNUM
848 && reg_nr <= FV_LAST_REGNUM)
849 base_regnum = fv_reg_base_num (reg_nr);
850
851 return base_regnum;
852}
853
854/* *INDENT-OFF* */
855/*
856 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
857 GDB_REGNUM BASE_REGNUM
858 r0_c 221 0
859 r1_c 222 1
860 r2_c 223 2
861 r3_c 224 3
862 r4_c 225 4
863 r5_c 226 5
864 r6_c 227 6
865 r7_c 228 7
866 r8_c 229 8
867 r9_c 230 9
868 r10_c 231 10
869 r11_c 232 11
870 r12_c 233 12
871 r13_c 234 13
872 r14_c 235 14
873 r15_c 236 15
874
875 pc_c 237 64
876 gbr_c 238 16
877 mach_c 239 17
878 macl_c 240 17
879 pr_c 241 18
880 t_c 242 19
881 fpscr_c 243 76
882 fpul_c 244 109
883
884 fr0_c 245 77
885 fr1_c 246 78
886 fr2_c 247 79
887 fr3_c 248 80
888 fr4_c 249 81
889 fr5_c 250 82
890 fr6_c 251 83
891 fr7_c 252 84
892 fr8_c 253 85
893 fr9_c 254 86
894 fr10_c 255 87
895 fr11_c 256 88
896 fr12_c 257 89
897 fr13_c 258 90
898 fr14_c 259 91
899 fr15_c 260 92
900
901 dr0_c 261 77
902 dr2_c 262 79
903 dr4_c 263 81
904 dr6_c 264 83
905 dr8_c 265 85
906 dr10_c 266 87
907 dr12_c 267 89
908 dr14_c 268 91
909
910 fv0_c 269 77
911 fv4_c 270 81
912 fv8_c 271 85
913 fv12_c 272 91
914*/
915/* *INDENT-ON* */
916static int
917sh64_compact_reg_base_num (int reg_nr)
918{
919 int base_regnum = -1;
55ff77ac
CV		 920
921 /* general register N maps to general register N */
922 if (reg_nr >= R0_C_REGNUM
923 && reg_nr <= R_LAST_C_REGNUM)
924 base_regnum = reg_nr - R0_C_REGNUM;
925
926 /* floating point register N maps to floating point register N */
927 else if (reg_nr >= FP0_C_REGNUM
928 && reg_nr <= FP_LAST_C_REGNUM)
929 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
930
931 /* double prec register N maps to base regnum for double prec register N */
932 else if (reg_nr >= DR0_C_REGNUM
933 && reg_nr <= DR_LAST_C_REGNUM)
934 base_regnum = dr_reg_base_num (DR0_REGNUM
935 + reg_nr - DR0_C_REGNUM);
936
937 /* vector N maps to base regnum for vector register N */
938 else if (reg_nr >= FV0_C_REGNUM
939 && reg_nr <= FV_LAST_C_REGNUM)
940 base_regnum = fv_reg_base_num (FV0_REGNUM
941 + reg_nr - FV0_C_REGNUM);
942
943 else if (reg_nr == PC_C_REGNUM)
944 base_regnum = PC_REGNUM;
945
946 else if (reg_nr == GBR_C_REGNUM)
947 base_regnum = 16;
948
949 else if (reg_nr == MACH_C_REGNUM
950 || reg_nr == MACL_C_REGNUM)
951 base_regnum = 17;
952
953 else if (reg_nr == PR_C_REGNUM)
954 base_regnum = 18;
955
956 else if (reg_nr == T_C_REGNUM)
957 base_regnum = 19;
958
959 else if (reg_nr == FPSCR_C_REGNUM)
7bb11558 960 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
55ff77ac
CV		 961
962 else if (reg_nr == FPUL_C_REGNUM)
963 base_regnum = FP0_REGNUM + 32;
964
965 return base_regnum;
966}
967
968/* Given a register number RN (according to the gdb scheme) , return
969 its corresponding architectural register. In media mode, only a
970 subset of the registers is pseudo registers. For compact mode, all
7bb11558 971 the registers are pseudo. */
55ff77ac
CV		 972static int
973translate_rn_to_arch_reg_num (int rn, int media_mode)
974{
975
976 if (media_mode)
977 {
978 if (!is_media_pseudo (rn))
979 return rn;
980 else
981 return sh64_media_reg_base_num (rn);
982 }
983 else
7bb11558 984 /* All compact registers are pseudo. */
55ff77ac
CV		 985 return sh64_compact_reg_base_num (rn);
986}
987
988static int
989sign_extend (int value, int bits)
990{
991 value = value & ((1 << bits) - 1);
992 return (value & (1 << (bits - 1))
993 ? value | (~((1 << bits) - 1))
994 : value);
995}
996
997static void
998sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
999{
1000 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1001 int rn;
1002 int have_fp = 0;
1003 int fp_regnum;
1004 int sp_regnum;
1005 int depth;
1006 int pc;
1007 int opc;
1008 int insn;
1009 int r0_val = 0;
1010 int media_mode = 0;
1011 int insn_size;
1012 int gdb_register_number;
1013 int register_number;
2a314ed5
MS		 1014 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1015 get_frame_base (fi));
7bb11558 1016 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac 1017
1b1d3794 1018 if (deprecated_get_frame_saved_regs (fi) == NULL)
55ff77ac
CV		 1019 frame_saved_regs_zalloc (fi);
1020 else
1b1d3794 1021 memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1022
1023 if (dummy_regs)
1024 {
1025 /* DANGER! This is ONLY going to work if the char buffer format of
1026 the saved registers is byte-for-byte identical to the
1027 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1b1d3794 1028 memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1029 return;
1030 }
1031
1032 get_frame_extra_info (fi)->leaf_function = 1;
1033 get_frame_extra_info (fi)->f_offset = 0;
1034
1035 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1036 where[rn] = -1;
1037
1038 depth = 0;
1039
1040 /* Loop around examining the prologue insns until we find something
1041 that does not appear to be part of the prologue. But give up
7bb11558 1042 after 20 of them, since we're getting silly then. */
55ff77ac
CV		 1043
1044 pc = get_frame_func (fi);
1045 if (!pc)
1046 {
1047 deprecated_update_frame_pc_hack (fi, 0);
1048 return;
1049 }
1050
1051 if (pc_is_isa32 (pc))
1052 {
1053 media_mode = 1;
1054 insn_size = 4;
1055 }
1056 else
1057 {
1058 media_mode = 0;
1059 insn_size = 2;
1060 }
1061
1062 /* The frame pointer register is general register 14 in shmedia and
1063 shcompact modes. In sh compact it is a pseudo register. Same goes
7bb11558 1064 for the stack pointer register, which is register 15. */
55ff77ac
CV		 1065 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1066 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1067
1068 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1069 {
1070 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1071 insn_size);
1072
1073 if (media_mode == 0)
1074 {
1075 if (IS_STS_PR (insn))
1076 {
1077 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1078 if (IS_MOV_TO_R15 (next_insn))
1079 {
1080 int reg_nr = PR_C_REGNUM;
1081
1082 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1083 get_frame_extra_info (fi)->leaf_function = 0;
1084 pc += insn_size;
1085 }
1086 }
1087 else if (IS_MOV_R14 (insn))
1088 {
1089 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1090 }
1091
1092 else if (IS_MOV_R0 (insn))
1093 {
1094 /* Put in R0 the offset from SP at which to store some
1095 registers. We are interested in this value, because it
1096 will tell us where the given registers are stored within
1097 the frame. */
1098 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1099 }
1100 else if (IS_ADD_SP_R0 (insn))
1101 {
1102 /* This instruction still prepares r0, but we don't care.
7bb11558 1103 We already have the offset in r0_val. */
55ff77ac
CV		 1104 }
1105 else if (IS_STS_R0 (insn))
1106 {
1107 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1108 int reg_nr = PR_C_REGNUM;
1109 where[reg_nr] = depth - (r0_val - 4);
1110 r0_val -= 4;
1111 get_frame_extra_info (fi)->leaf_function = 0;
1112 }
1113 else if (IS_MOV_R14_R0 (insn))
1114 {
1115 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1116 where[fp_regnum] = depth - (r0_val - 4);
1117 r0_val -= 4;
1118 }
1119
1120 else if (IS_ADD_SP (insn))
1121 {
1122 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1123 }
1124 else if (IS_MOV_SP_FP (insn))
1125 break;
1126 }
1127 else
1128 {
1129 if (IS_ADDIL_SP_MEDIA (insn)
1130 || IS_ADDI_SP_MEDIA (insn))
1131 {
1132 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1133 }
1134
1135 else if (IS_STQ_R18_R15 (insn))
1136 {
1137 where[PR_REGNUM] =
1138 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1139 get_frame_extra_info (fi)->leaf_function = 0;
1140 }
1141
1142 else if (IS_STL_R18_R15 (insn))
1143 {
1144 where[PR_REGNUM] =
1145 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1146 get_frame_extra_info (fi)->leaf_function = 0;
1147 }
1148
1149 else if (IS_STQ_R14_R15 (insn))
1150 {
1151 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1152 }
1153
1154 else if (IS_STL_R14_R15 (insn))
1155 {
1156 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1157 }
1158
1159 else if (IS_MOV_SP_FP_MEDIA (insn))
1160 break;
1161 }
1162 }
1163
7bb11558 1164 /* Now we know how deep things are, we can work out their addresses. */
55ff77ac
CV		 1165 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1166 {
1167 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1168
1169 if (where[rn] >= 0)
1170 {
1171 if (rn == fp_regnum)
1172 have_fp = 1;
1173
1174 /* Watch out! saved_regs is only for the real registers, and
7bb11558
MS		 1175 doesn't include space for the pseudo registers. */
1176 deprecated_get_frame_saved_regs (fi)[register_number]
1177 = get_frame_base (fi) - where[rn] + depth;
55ff77ac
CV		 1178 }
1179 else
7bb11558 1180 deprecated_get_frame_saved_regs (fi)[register_number] = 0;
55ff77ac
CV		 1181 }
1182
1183 if (have_fp)
1184 {
1185 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1186 shcompact 15 is the arch register corresponding to the pseudo
7bb11558 1187 register r15 which still is the SP register. */
55ff77ac 1188 /* The place on the stack where fp is stored contains the sp of
7bb11558 1189 the caller. */
55ff77ac
CV		 1190 /* Again, saved_registers contains only space for the real
1191 registers, so we store in DEPRECATED_FP_REGNUM position. */
1192 int size;
1193 if (tdep->sh_abi == SH_ABI_32)
1194 size = 4;
1195 else
7bb11558
MS		 1196 size = register_size (current_gdbarch, fp_regnum);
1197 deprecated_get_frame_saved_regs (fi)[sp_regnum]
1198 = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum],
1199 size);
55ff77ac
CV		 1200 }
1201 else
1b1d3794 1202 deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
55ff77ac 1203
7bb11558 1204 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
55ff77ac
CV		 1205}
1206
1207/* Initialize the extra info saved in a FRAME */
1208static void
1209sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1210{
1211 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1212
1213 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1214
1215 if (get_next_frame (fi))
1216 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1217
1218 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1219 get_frame_base (fi)))
1220 {
1221 /* We need to setup fi->frame here because call_function_by_hand
1222 gets it wrong by assuming it's always FP. */
1223 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1224 get_frame_extra_info (fi)->return_pc =
1225 deprecated_read_register_dummy (get_frame_pc (fi),
1226 get_frame_base (fi), PC_REGNUM);
1227 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1228 get_frame_extra_info (fi)->leaf_function = 0;
1229 return;
1230 }
1231 else
1232 {
1233 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1234 get_frame_extra_info (fi)->return_pc =
1235 sh64_get_saved_pr (fi, PR_REGNUM);
1236 }
1237}
1238
1239static void
1240sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1241 struct frame_info *frame, int regnum,
1242 enum lval_type *lval)
1243{
1244 int media_mode;
1245 int live_regnum = regnum;
7bb11558 1246 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1247
1248 if (!target_has_registers)
1249 error ("No registers.");
1250
1251 /* Normal systems don't optimize out things with register numbers. */
1252 if (optimized != NULL)
1253 *optimized = 0;
1254
1255 if (addrp) /* default assumption: not found in memory */
1256 *addrp = 0;
1257
1258 if (raw_buffer)
1259 memset (raw_buffer, 0, sizeof (raw_buffer));
1260
1261 /* We must do this here, before the following while loop changes
1262 frame, and makes it NULL. If this is a media register number,
1263 but we are in compact mode, it will become the corresponding
1264 compact pseudo register. If there is no corresponding compact
1265 pseudo-register what do we do?*/
1266 media_mode = pc_is_isa32 (get_frame_pc (frame));
1267 live_regnum = translate_insn_rn (regnum, media_mode);
1268
1269 /* Note: since the current frame's registers could only have been
1270 saved by frames INTERIOR TO the current frame, we skip examining
1271 the current frame itself: otherwise, we would be getting the
1272 previous frame's registers which were saved by the current frame. */
1273
1274 while (frame && ((frame = get_next_frame (frame)) != NULL))
1275 {
1276 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1277 get_frame_base (frame),
1278 get_frame_base (frame)))
1279 {
1280 if (lval) /* found it in a CALL_DUMMY frame */
1281 *lval = not_lval;
1282 if (raw_buffer)
1283 memcpy (raw_buffer,
1284 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
62700349 1285 + DEPRECATED_REGISTER_BYTE (regnum)),
7bb11558 1286 register_size (current_gdbarch, regnum));
55ff77ac
CV		 1287 return;
1288 }
1289
1290 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1b1d3794
AC		 1291 if (deprecated_get_frame_saved_regs (frame) != NULL
1292 && deprecated_get_frame_saved_regs (frame)[regnum] != 0)
55ff77ac
CV		 1293 {
1294 if (lval) /* found it saved on the stack */
1295 *lval = lval_memory;
1296 if (regnum == SP_REGNUM)
1297 {
1298 if (raw_buffer) /* SP register treated specially */
7bb11558
MS		 1299 store_unsigned_integer (raw_buffer,
1300 register_size (current_gdbarch,
1301 regnum),
1b1d3794 1302 deprecated_get_frame_saved_regs (frame)[regnum]);
55ff77ac
CV		 1303 }
1304 else
1305 { /* any other register */
1306
1307 if (addrp)
1b1d3794 1308 *addrp = deprecated_get_frame_saved_regs (frame)[regnum];
55ff77ac
CV		 1309 if (raw_buffer)
1310 {
1311 int size;
1312 if (tdep->sh_abi == SH_ABI_32
1313 && (live_regnum == DEPRECATED_FP_REGNUM
1314 || live_regnum == PR_REGNUM))
1315 size = 4;
1316 else
7bb11558 1317 size = register_size (current_gdbarch, live_regnum);
55ff77ac 1318 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
39add00a
MS		 1319 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
1320 raw_buffer, size);
55ff77ac 1321 else
1b1d3794 1322 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac 1323 raw_buffer
7bb11558 1324 + register_size (current_gdbarch, live_regnum)
55ff77ac
CV		 1325 - size,
1326 size);
1327 }
1328 }
1329 return;
1330 }
1331 }
1332
1333 /* If we get thru the loop to this point, it means the register was
1334 not saved in any frame. Return the actual live-register value. */
1335
1336 if (lval) /* found it in a live register */
1337 *lval = lval_register;
1338 if (addrp)
62700349 1339 *addrp = DEPRECATED_REGISTER_BYTE (live_regnum);
55ff77ac
CV		 1340 if (raw_buffer)
1341 deprecated_read_register_gen (live_regnum, raw_buffer);
1342}
1343
1344static CORE_ADDR
07be497a 1345sh64_extract_struct_value_address (struct regcache *regcache)
55ff77ac 1346{
07be497a
AC		 1347 /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return
1348 address regster is preserved across function calls? Probably
1349 not, making this function wrong. */
1350 ULONGEST val;
1351 regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val);
1352 return val;
55ff77ac
CV		 1353}
1354
1355static CORE_ADDR
1356sh_frame_saved_pc (struct frame_info *frame)
1357{
1358 return (get_frame_extra_info (frame)->return_pc);
1359}
1360
1361/* Discard from the stack the innermost frame, restoring all saved registers.
7bb11558 1362 Used in the 'return' command. */
55ff77ac
CV		 1363static void
1364sh64_pop_frame (void)
1365{
52f0bd74
AC		 1366 struct frame_info *frame = get_current_frame ();
1367 CORE_ADDR fp;
1368 int regnum;
7bb11558 1369 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1370
1371 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1372
1373 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1374 get_frame_base (frame),
1375 get_frame_base (frame)))
8adf9e78 1376 deprecated_pop_dummy_frame ();
55ff77ac
CV		 1377 else
1378 {
1379 fp = get_frame_base (frame);
1380 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1381
1382 /* Copy regs from where they were saved in the frame */
1383 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1b1d3794 1384 if (deprecated_get_frame_saved_regs (frame)[regnum])
55ff77ac
CV		 1385 {
1386 int size;
1387 if (tdep->sh_abi == SH_ABI_32
1388 && (regnum == DEPRECATED_FP_REGNUM
1389 || regnum == PR_REGNUM))
1390 size = 4;
1391 else
7bb11558
MS		 1392 size = register_size (current_gdbarch,
1393 translate_insn_rn (regnum, media_mode));
55ff77ac 1394 write_register (regnum,
1b1d3794 1395 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac
CV		 1396 size));
1397 }
1398
1399 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1400 write_register (SP_REGNUM, fp + 8);
1401 }
1402 flush_cached_frames ();
1403}
1404
1405static CORE_ADDR
1406sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1407{
1408 return sp & ~3;
1409}
1410
1411/* Function: push_arguments
1412 Setup the function arguments for calling a function in the inferior.
1413
85a453d5 1414 On the Renesas SH architecture, there are four registers (R4 to R7)
55ff77ac
CV		 1415 which are dedicated for passing function arguments. Up to the first
1416 four arguments (depending on size) may go into these registers.
1417 The rest go on the stack.
1418
1419 Arguments that are smaller than 4 bytes will still take up a whole
1420 register or a whole 32-bit word on the stack, and will be
1421 right-justified in the register or the stack word. This includes
1422 chars, shorts, and small aggregate types.
1423
1424 Arguments that are larger than 4 bytes may be split between two or
1425 more registers. If there are not enough registers free, an argument
1426 may be passed partly in a register (or registers), and partly on the
1427 stack. This includes doubles, long longs, and larger aggregates.
1428 As far as I know, there is no upper limit to the size of aggregates
1429 that will be passed in this way; in other words, the convention of
1430 passing a pointer to a large aggregate instead of a copy is not used.
1431
1432 An exceptional case exists for struct arguments (and possibly other
1433 aggregates such as arrays) if the size is larger than 4 bytes but
1434 not a multiple of 4 bytes. In this case the argument is never split
1435 between the registers and the stack, but instead is copied in its
1436 entirety onto the stack, AND also copied into as many registers as
1437 there is room for. In other words, space in registers permitting,
1438 two copies of the same argument are passed in. As far as I can tell,
1439 only the one on the stack is used, although that may be a function
1440 of the level of compiler optimization. I suspect this is a compiler
1441 bug. Arguments of these odd sizes are left-justified within the
1442 word (as opposed to arguments smaller than 4 bytes, which are
1443 right-justified).
1444
1445 If the function is to return an aggregate type such as a struct, it
1446 is either returned in the normal return value register R0 (if its
1447 size is no greater than one byte), or else the caller must allocate
1448 space into which the callee will copy the return value (if the size
1449 is greater than one byte). In this case, a pointer to the return
1450 value location is passed into the callee in register R2, which does
1451 not displace any of the other arguments passed in via registers R4
1452 to R7. */
1453
1454/* R2-R9 for integer types and integer equivalent (char, pointers) and
1455 non-scalar (struct, union) elements (even if the elements are
1456 floats).
1457 FR0-FR11 for single precision floating point (float)
1458 DR0-DR10 for double precision floating point (double)
1459
1460 If a float is argument number 3 (for instance) and arguments number
1461 1,2, and 4 are integer, the mapping will be:
1462 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1463
1464 If a float is argument number 10 (for instance) and arguments number
1465 1 through 10 are integer, the mapping will be:
1466 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1467 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1468 I.e. there is hole in the stack.
1469
1470 Different rules apply for variable arguments functions, and for functions
7bb11558 1471 for which the prototype is not known. */
55ff77ac
CV		 1472
1473static CORE_ADDR
1474sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1475 int struct_return, CORE_ADDR struct_addr)
1476{
1477 int stack_offset, stack_alloc;
1478 int int_argreg;
1479 int float_argreg;
1480 int double_argreg;
1481 int float_arg_index = 0;
1482 int double_arg_index = 0;
1483 int argnum;
1484 struct type *type;
1485 CORE_ADDR regval;
1486 char *val;
1487 char valbuf[8];
1488 char valbuf_tmp[8];
1489 int len;
1490 int argreg_size;
1491 int fp_args[12];
55ff77ac
CV		 1492
1493 memset (fp_args, 0, sizeof (fp_args));
1494
1495 /* first force sp to a 8-byte alignment */
1496 sp = sp & ~7;
1497
1498 /* The "struct return pointer" pseudo-argument has its own dedicated
1499 register */
1500
1501 if (struct_return)
1502 write_register (STRUCT_RETURN_REGNUM, struct_addr);
1503
1504 /* Now make sure there's space on the stack */
1505 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1506 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
1507 sp -= stack_alloc; /* make room on stack for args */
1508
1509 /* Now load as many as possible of the first arguments into
1510 registers, and push the rest onto the stack. There are 64 bytes
1511 in eight registers available. Loop thru args from first to last. */
1512
1513 int_argreg = ARG0_REGNUM;
1514 float_argreg = FP0_REGNUM;
1515 double_argreg = DR0_REGNUM;
1516
1517 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1518 {
1519 type = VALUE_TYPE (args[argnum]);
1520 len = TYPE_LENGTH (type);
1521 memset (valbuf, 0, sizeof (valbuf));
1522
1523 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1524 {
7bb11558 1525 argreg_size = register_size (current_gdbarch, int_argreg);
55ff77ac
CV		 1526
1527 if (len < argreg_size)
1528 {
1529 /* value gets right-justified in the register or stack word */
1530 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1531 memcpy (valbuf + argreg_size - len,
1532 (char *) VALUE_CONTENTS (args[argnum]), len);
1533 else
1534 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
1535
1536 val = valbuf;
1537 }
1538 else
1539 val = (char *) VALUE_CONTENTS (args[argnum]);
1540
1541 while (len > 0)
1542 {
1543 if (int_argreg > ARGLAST_REGNUM)
1544 {
1545 /* must go on the stack */
1546 write_memory (sp + stack_offset, val, argreg_size);
1547 stack_offset += 8;/*argreg_size;*/
1548 }
1549 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1550 That's because some *&^%$ things get passed on the stack
1551 AND in the registers! */
1552 if (int_argreg <= ARGLAST_REGNUM)
1553 {
1554 /* there's room in a register */
1555 regval = extract_unsigned_integer (val, argreg_size);
1556 write_register (int_argreg, regval);
1557 }
1558 /* Store the value 8 bytes at a time. This means that
1559 things larger than 8 bytes may go partly in registers
1560 and partly on the stack. FIXME: argreg is incremented
7bb11558 1561 before we use its size. */
55ff77ac
CV		 1562 len -= argreg_size;
1563 val += argreg_size;
1564 int_argreg++;
1565 }
1566 }
1567 else
1568 {
1569 val = (char *) VALUE_CONTENTS (args[argnum]);
1570 if (len == 4)
1571 {
1572 /* Where is it going to be stored? */
1573 while (fp_args[float_arg_index])
1574 float_arg_index ++;
1575
1576 /* Now float_argreg points to the register where it
1577 should be stored. Are we still within the allowed
1578 register set? */
1579 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1580 {
1581 /* Goes in FR0...FR11 */
1582 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
1583 val);
1584 fp_args[float_arg_index] = 1;
7bb11558 1585 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1586 int_argreg ++;
1587 }
1588 else
1589 ;
1590 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1591 necessary spilling on the stack. */
55ff77ac
CV		 1592
1593 }
1594 else if (len == 8)
1595 {
1596 /* Where is it going to be stored? */
1597 while (fp_args[double_arg_index])
1598 double_arg_index += 2;
1599 /* Now double_argreg points to the register
1600 where it should be stored.
1601 Are we still within the allowed register set? */
1602 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1603 {
1604 /* Goes in DR0...DR10 */
1605 /* The numbering of the DRi registers is consecutive,
7bb11558 1606 i.e. includes odd numbers. */
55ff77ac
CV		 1607 int double_register_offset = double_arg_index / 2;
1608 int regnum = DR0_REGNUM +
1609 double_register_offset;
1610#if 0
1611 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1612 {
1613 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
1614 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
1615 type, val,
1616 valbuf_tmp);
1617 val = valbuf_tmp;
1618 }
1619#endif
1620 /* Note: must use write_register_gen here instead
1621 of regcache_raw_write, because
1622 regcache_raw_write works only for real
1623 registers, not pseudo. write_register_gen will
1624 call the gdbarch function to do register
1625 writes, and that will properly know how to deal
7bb11558 1626 with pseudoregs. */
55ff77ac
CV		 1627 deprecated_write_register_gen (regnum, val);
1628 fp_args[double_arg_index] = 1;
1629 fp_args[double_arg_index + 1] = 1;
7bb11558 1630 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1631 int_argreg ++;
1632 }
1633 else
1634 ;
1635 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1636 necessary spilling on the stack. */
55ff77ac
CV		 1637 }
1638 }
1639 }
1640 return sp;
1641}
1642
1643/* Function: push_return_address (pc)
1644 Set up the return address for the inferior function call.
1645 Needed for targets where we don't actually execute a JSR/BSR instruction */
1646
1647static CORE_ADDR
1648sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1649{
e8a7b686 1650 write_register (PR_REGNUM, entry_point_address ());
55ff77ac
CV		 1651 return sp;
1652}
1653
1654/* Find a function's return value in the appropriate registers (in
1655 regbuf), and copy it into valbuf. Extract from an array REGBUF
1656 containing the (raw) register state a function return value of type
1657 TYPE, and copy that, in virtual format, into VALBUF. */
1658static void
1659sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1660{
1661 int offset;
1662 int return_register;
1663 int len = TYPE_LENGTH (type);
55ff77ac
CV		 1664
1665 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1666 {
1667 if (len == 4)
1668 {
1669 /* Return value stored in FP0_REGNUM */
1670 return_register = FP0_REGNUM;
62700349 1671 offset = DEPRECATED_REGISTER_BYTE (return_register);
7bb11558 1672 memcpy (valbuf, (char *) regbuf + offset, len);
55ff77ac
CV		 1673 }
1674 else if (len == 8)
1675 {
1676 /* return value stored in DR0_REGNUM */
1677 DOUBLEST val;
1678
1679 return_register = DR0_REGNUM;
62700349 1680 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1681
1682 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1683 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1684 (char *) regbuf + offset, &val);
1685 else
1686 floatformat_to_doublest (&floatformat_ieee_double_big,
1687 (char *) regbuf + offset, &val);
7bb11558 1688 store_typed_floating (valbuf, type, val);
55ff77ac
CV		 1689 }
1690 }
1691 else
1692 {
1693 if (len <= 8)
1694 {
1695 /* Result is in register 2. If smaller than 8 bytes, it is padded
7bb11558 1696 at the most significant end. */
55ff77ac
CV		 1697 return_register = DEFAULT_RETURN_REGNUM;
1698 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
62700349 1699 offset = DEPRECATED_REGISTER_BYTE (return_register) +
7bb11558 1700 register_size (current_gdbarch, return_register) - len;
55ff77ac 1701 else
62700349 1702 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1703 memcpy (valbuf, (char *) regbuf + offset, len);
1704 }
1705 else
1706 error ("bad size for return value");
1707 }
1708}
1709
1710/* Write into appropriate registers a function return value
1711 of type TYPE, given in virtual format.
1712 If the architecture is sh4 or sh3e, store a function's return value
1713 in the R0 general register or in the FP0 floating point register,
1714 depending on the type of the return value. In all the other cases
7bb11558 1715 the result is stored in r0, left-justified. */
55ff77ac
CV		 1716
1717static void
1718sh64_store_return_value (struct type *type, char *valbuf)
1719{
7bb11558 1720 char buf[64]; /* more than enough... */
55ff77ac
CV		 1721 int len = TYPE_LENGTH (type);
1722
1723 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1724 {
1725 if (len == 4)
1726 {
1727 /* Return value stored in FP0_REGNUM */
1728 deprecated_write_register_gen (FP0_REGNUM, valbuf);
1729 }
1730 if (len == 8)
1731 {
1732 /* return value stored in DR0_REGNUM */
1733 /* FIXME: Implement */
1734 }
1735 }
1736 else
1737 {
1738 int return_register = DEFAULT_RETURN_REGNUM;
1739 int offset = 0;
1740
7bb11558 1741 if (len <= register_size (current_gdbarch, return_register))
55ff77ac 1742 {
7bb11558
MS		 1743 /* Pad with zeros. */
1744 memset (buf, 0, register_size (current_gdbarch, return_register));
55ff77ac 1745 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
7bb11558
MS		 1746 offset = 0; /*register_size (current_gdbarch,
1747 return_register) - len;*/
55ff77ac 1748 else
7bb11558 1749 offset = register_size (current_gdbarch, return_register) - len;
55ff77ac
CV		 1750
1751 memcpy (buf + offset, valbuf, len);
1752 deprecated_write_register_gen (return_register, buf);
1753 }
1754 else
1755 deprecated_write_register_gen (return_register, valbuf);
1756 }
1757}
1758
1759static void
1760sh64_show_media_regs (void)
1761{
1762 int i;
55ff77ac
CV		 1763
1764 printf_filtered ("PC=%s SR=%016llx \n",
1765 paddr (read_register (PC_REGNUM)),
1766 (long long) read_register (SR_REGNUM));
1767
1768 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1769 (long long) read_register (SSR_REGNUM),
1770 (long long) read_register (SPC_REGNUM));
1771 printf_filtered ("FPSCR=%016lx\n ",
1772 (long) read_register (FPSCR_REGNUM));
1773
1774 for (i = 0; i < 64; i = i + 4)
1775 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1776 i, i + 3,
1777 (long long) read_register (i + 0),
1778 (long long) read_register (i + 1),
1779 (long long) read_register (i + 2),
1780 (long long) read_register (i + 3));
1781
1782 printf_filtered ("\n");
1783
1784 for (i = 0; i < 64; i = i + 8)
1785 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1786 i, i + 7,
1787 (long) read_register (FP0_REGNUM + i + 0),
1788 (long) read_register (FP0_REGNUM + i + 1),
1789 (long) read_register (FP0_REGNUM + i + 2),
1790 (long) read_register (FP0_REGNUM + i + 3),
1791 (long) read_register (FP0_REGNUM + i + 4),
1792 (long) read_register (FP0_REGNUM + i + 5),
1793 (long) read_register (FP0_REGNUM + i + 6),
1794 (long) read_register (FP0_REGNUM + i + 7));
1795}
1796
1797static void
1798sh64_show_compact_regs (void)
1799{
1800 int i;
55ff77ac
CV		 1801
1802 printf_filtered ("PC=%s \n",
1803 paddr (read_register (PC_C_REGNUM)));
1804
1805 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1806 (long) read_register (GBR_C_REGNUM),
1807 (long) read_register (MACH_C_REGNUM),
1808 (long) read_register (MACL_C_REGNUM),
1809 (long) read_register (PR_C_REGNUM),
1810 (long) read_register (T_C_REGNUM));
1811 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1812 (long) read_register (FPSCR_C_REGNUM),
1813 (long) read_register (FPUL_C_REGNUM));
1814
1815 for (i = 0; i < 16; i = i + 4)
1816 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1817 i, i + 3,
1818 (long) read_register (i + 0),
1819 (long) read_register (i + 1),
1820 (long) read_register (i + 2),
1821 (long) read_register (i + 3));
1822
1823 printf_filtered ("\n");
1824
1825 for (i = 0; i < 16; i = i + 8)
1826 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1827 i, i + 7,
1828 (long) read_register (FP0_REGNUM + i + 0),
1829 (long) read_register (FP0_REGNUM + i + 1),
1830 (long) read_register (FP0_REGNUM + i + 2),
1831 (long) read_register (FP0_REGNUM + i + 3),
1832 (long) read_register (FP0_REGNUM + i + 4),
1833 (long) read_register (FP0_REGNUM + i + 5),
1834 (long) read_register (FP0_REGNUM + i + 6),
1835 (long) read_register (FP0_REGNUM + i + 7));
1836}
1837
7bb11558
MS		 1838/* FIXME!!! This only shows the registers for shmedia, excluding the
1839 pseudo registers. */
55ff77ac
CV		 1840void
1841sh64_show_regs (void)
1842{
1843 if (deprecated_selected_frame
1844 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1845 sh64_show_media_regs ();
1846 else
1847 sh64_show_compact_regs ();
1848}
1849
1850/* *INDENT-OFF* */
1851/*
1852 SH MEDIA MODE (ISA 32)
1853 general registers (64-bit) 0-63
18540 r0, r1, r2, r3, r4, r5, r6, r7,
185564 r8, r9, r10, r11, r12, r13, r14, r15,
1856128 r16, r17, r18, r19, r20, r21, r22, r23,
1857192 r24, r25, r26, r27, r28, r29, r30, r31,
1858256 r32, r33, r34, r35, r36, r37, r38, r39,
1859320 r40, r41, r42, r43, r44, r45, r46, r47,
1860384 r48, r49, r50, r51, r52, r53, r54, r55,
1861448 r56, r57, r58, r59, r60, r61, r62, r63,
1862
1863 pc (64-bit) 64
1864512 pc,
1865
1866 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1867520 sr, ssr, spc,
1868
1869 target registers (64-bit) 68-75
1870544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1871
1872 floating point state control register (32-bit) 76
1873608 fpscr,
1874
1875 single precision floating point registers (32-bit) 77-140
1876612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1877644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1878676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1879708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1880740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1881772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1882804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1883836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1884
1885TOTAL SPACE FOR REGISTERS: 868 bytes
1886
1887From here on they are all pseudo registers: no memory allocated.
1888REGISTER_BYTE returns the register byte for the base register.
1889
1890 double precision registers (pseudo) 141-172
1891 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1892 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1893 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1894 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1895
1896 floating point pairs (pseudo) 173-204
1897 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1898 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1899 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1900 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1901
1902 floating point vectors (4 floating point regs) (pseudo) 205-220
1903 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1904 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1905
1906 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1907 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1908 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1909 pc_c,
1910 gbr_c, mach_c, macl_c, pr_c, t_c,
1911 fpscr_c, fpul_c,
1912 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1913 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1914 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1915 fv0_c, fv4_c, fv8_c, fv12_c
1916*/
1917/* *INDENT-ON* */
1918static int
39add00a 1919sh64_register_byte (int reg_nr)
55ff77ac
CV		 1920{
1921 int base_regnum = -1;
55ff77ac
CV		 1922
1923 /* If it is a pseudo register, get the number of the first floating
7bb11558 1924 point register that is part of it. */
55ff77ac
CV		 1925 if (reg_nr >= DR0_REGNUM
1926 && reg_nr <= DR_LAST_REGNUM)
1927 base_regnum = dr_reg_base_num (reg_nr);
1928
1929 else if (reg_nr >= FPP0_REGNUM
1930 && reg_nr <= FPP_LAST_REGNUM)
1931 base_regnum = fpp_reg_base_num (reg_nr);
1932
1933 else if (reg_nr >= FV0_REGNUM
1934 && reg_nr <= FV_LAST_REGNUM)
1935 base_regnum = fv_reg_base_num (reg_nr);
1936
1937 /* sh compact pseudo register. FPSCR is a pathological case, need to
7bb11558 1938 treat it as special. */
55ff77ac
CV		 1939 else if ((reg_nr >= R0_C_REGNUM
1940 && reg_nr <= FV_LAST_C_REGNUM)
1941 && reg_nr != FPSCR_C_REGNUM)
1942 base_regnum = sh64_compact_reg_base_num (reg_nr);
1943
7bb11558
MS		 1944 /* Now return the offset in bytes within the register cache. */
1945 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
55ff77ac
CV		 1946 if (reg_nr >= DR0_REGNUM
1947 && reg_nr <= FV_LAST_REGNUM)
1948 return (base_regnum - FP0_REGNUM + 1) * 4
1949 + (TR7_REGNUM + 1) * 8;
1950
1951 /* sh compact pseudo register: general register */
1952 if ((reg_nr >= R0_C_REGNUM
1953 && reg_nr <= R_LAST_C_REGNUM))
1954 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1955 ? base_regnum * 8 + 4
1956 : base_regnum * 8);
1957
1958 /* sh compact pseudo register: */
1959 if (reg_nr == PC_C_REGNUM
1960 || reg_nr == GBR_C_REGNUM
1961 || reg_nr == MACL_C_REGNUM
1962 || reg_nr == PR_C_REGNUM)
1963 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1964 ? base_regnum * 8 + 4
1965 : base_regnum * 8);
1966
1967 if (reg_nr == MACH_C_REGNUM)
1968 return base_regnum * 8;
1969
1970 if (reg_nr == T_C_REGNUM)
1971 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
1972
1973 /* sh compact pseudo register: floating point register */
1974 else if (reg_nr >= FP0_C_REGNUM
1975 && reg_nr <= FV_LAST_C_REGNUM)
1976 return (base_regnum - FP0_REGNUM) * 4
1977 + (TR7_REGNUM + 1) * 8 + 4;
1978
1979 else if (reg_nr == FPSCR_C_REGNUM)
1980 /* This is complicated, for now return the beginning of the
7bb11558 1981 architectural FPSCR register. */
55ff77ac
CV		 1982 return (TR7_REGNUM + 1) * 8;
1983
1984 else if (reg_nr == FPUL_C_REGNUM)
1985 return ((base_regnum - FP0_REGNUM) * 4 +
1986 (TR7_REGNUM + 1) * 8 + 4);
1987
7bb11558
MS		 1988 /* It is not a pseudo register. */
1989 /* It is a 64 bit register. */
55ff77ac
CV		 1990 else if (reg_nr <= TR7_REGNUM)
1991 return reg_nr * 8;
1992
7bb11558 1993 /* It is a 32 bit register. */
55ff77ac
CV		 1994 else if (reg_nr == FPSCR_REGNUM)
1995 return (FPSCR_REGNUM * 8);
1996
1997 /* It is floating point 32-bit register */
1998 else
1999 return ((TR7_REGNUM + 1) * 8
2000 + (reg_nr - FP0_REGNUM + 1) * 4);
2001}
2002
55ff77ac 2003static struct type *
39add00a 2004sh64_build_float_register_type (int high)
55ff77ac
CV		 2005{
2006 struct type *temp;
2007
2008 temp = create_range_type (NULL, builtin_type_int, 0, high);
2009 return create_array_type (NULL, builtin_type_float, temp);
2010}
2011
7bb11558
MS		 2012/* Return the GDB type object for the "standard" data type
2013 of data in register REG_NR. */
55ff77ac 2014static struct type *
7bb11558 2015sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
55ff77ac 2016{
55ff77ac
CV		 2017 if ((reg_nr >= FP0_REGNUM
2018 && reg_nr <= FP_LAST_REGNUM)
2019 || (reg_nr >= FP0_C_REGNUM
2020 && reg_nr <= FP_LAST_C_REGNUM))
2021 return builtin_type_float;
2022 else if ((reg_nr >= DR0_REGNUM
2023 && reg_nr <= DR_LAST_REGNUM)
2024 || (reg_nr >= DR0_C_REGNUM
2025 && reg_nr <= DR_LAST_C_REGNUM))
2026 return builtin_type_double;
2027 else if (reg_nr >= FPP0_REGNUM
2028 && reg_nr <= FPP_LAST_REGNUM)
39add00a 2029 return sh64_build_float_register_type (1);
55ff77ac
CV		 2030 else if ((reg_nr >= FV0_REGNUM
2031 && reg_nr <= FV_LAST_REGNUM)
2032 ||(reg_nr >= FV0_C_REGNUM
2033 && reg_nr <= FV_LAST_C_REGNUM))
39add00a 2034 return sh64_build_float_register_type (3);
55ff77ac
CV		 2035 else if (reg_nr == FPSCR_REGNUM)
2036 return builtin_type_int;
2037 else if (reg_nr >= R0_C_REGNUM
2038 && reg_nr < FP0_C_REGNUM)
2039 return builtin_type_int;
2040 else
2041 return builtin_type_long_long;
2042}
2043
2044static void
39add00a 2045sh64_register_convert_to_virtual (int regnum, struct type *type,
55ff77ac
CV		 2046 char *from, char *to)
2047{
55ff77ac
CV		 2048 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2049 {
7bb11558
MS		 2050 /* It is a no-op. */
2051 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2052 return;
2053 }
2054
2055 if ((regnum >= DR0_REGNUM
2056 && regnum <= DR_LAST_REGNUM)
2057 || (regnum >= DR0_C_REGNUM
2058 && regnum <= DR_LAST_C_REGNUM))
2059 {
2060 DOUBLEST val;
7bb11558
MS		 2061 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2062 from, &val);
39add00a 2063 store_typed_floating (to, type, val);
55ff77ac
CV		 2064 }
2065 else
39add00a 2066 error ("sh64_register_convert_to_virtual called with non DR register number");
55ff77ac
CV		 2067}
2068
2069static void
39add00a 2070sh64_register_convert_to_raw (struct type *type, int regnum,
55ff77ac
CV		 2071 const void *from, void *to)
2072{
55ff77ac
CV		 2073 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2074 {
7bb11558
MS		 2075 /* It is a no-op. */
2076 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2077 return;
2078 }
2079
2080 if ((regnum >= DR0_REGNUM
2081 && regnum <= DR_LAST_REGNUM)
2082 || (regnum >= DR0_C_REGNUM
2083 && regnum <= DR_LAST_C_REGNUM))
2084 {
2085 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
7bb11558
MS		 2086 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2087 &val, to);
55ff77ac
CV		 2088 }
2089 else
39add00a 2090 error ("sh64_register_convert_to_raw called with non DR register number");
55ff77ac
CV		 2091}
2092
2093static void
2094sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2095 int reg_nr, void *buffer)
2096{
2097 int base_regnum;
2098 int portion;
2099 int offset = 0;
2100 char temp_buffer[MAX_REGISTER_SIZE];
55ff77ac
CV		 2101
2102 if (reg_nr >= DR0_REGNUM
2103 && reg_nr <= DR_LAST_REGNUM)
2104 {
2105 base_regnum = dr_reg_base_num (reg_nr);
2106
7bb11558 2107 /* Build the value in the provided buffer. */
55ff77ac 2108 /* DR regs are double precision registers obtained by
7bb11558 2109 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2110 for (portion = 0; portion < 2; portion++)
2111 regcache_raw_read (regcache, base_regnum + portion,
2112 (temp_buffer
7bb11558 2113 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2114
7bb11558 2115 /* We must pay attention to the endianness. */
39add00a
MS		 2116 sh64_register_convert_to_virtual (reg_nr,
2117 gdbarch_register_type (gdbarch,
2118 reg_nr),
2119 temp_buffer, buffer);
55ff77ac
CV		 2120
2121 }
2122
2123 else if (reg_nr >= FPP0_REGNUM
2124 && reg_nr <= FPP_LAST_REGNUM)
2125 {
2126 base_regnum = fpp_reg_base_num (reg_nr);
2127
7bb11558 2128 /* Build the value in the provided buffer. */
55ff77ac 2129 /* FPP regs are pairs of single precision registers obtained by
7bb11558 2130 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2131 for (portion = 0; portion < 2; portion++)
2132 regcache_raw_read (regcache, base_regnum + portion,
2133 ((char *) buffer
7bb11558 2134 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2135 }
2136
2137 else if (reg_nr >= FV0_REGNUM
2138 && reg_nr <= FV_LAST_REGNUM)
2139 {
2140 base_regnum = fv_reg_base_num (reg_nr);
2141
7bb11558 2142 /* Build the value in the provided buffer. */
55ff77ac 2143 /* FV regs are vectors of single precision registers obtained by
7bb11558 2144 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2145 for (portion = 0; portion < 4; portion++)
2146 regcache_raw_read (regcache, base_regnum + portion,
2147 ((char *) buffer
7bb11558 2148 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2149 }
2150
2151 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
2152 else if (reg_nr >= R0_C_REGNUM
2153 && reg_nr <= T_C_REGNUM)
2154 {
2155 base_regnum = sh64_compact_reg_base_num (reg_nr);
2156
7bb11558 2157 /* Build the value in the provided buffer. */
55ff77ac
CV		 2158 regcache_raw_read (regcache, base_regnum, temp_buffer);
2159 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2160 offset = 4;
2161 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
2162 }
2163
2164 else if (reg_nr >= FP0_C_REGNUM
2165 && reg_nr <= FP_LAST_C_REGNUM)
2166 {
2167 base_regnum = sh64_compact_reg_base_num (reg_nr);
2168
7bb11558 2169 /* Build the value in the provided buffer. */
55ff77ac 2170 /* Floating point registers map 1-1 to the media fp regs,
7bb11558 2171 they have the same size and endianness. */
55ff77ac
CV		 2172 regcache_raw_read (regcache, base_regnum, buffer);
2173 }
2174
2175 else if (reg_nr >= DR0_C_REGNUM
2176 && reg_nr <= DR_LAST_C_REGNUM)
2177 {
2178 base_regnum = sh64_compact_reg_base_num (reg_nr);
2179
2180 /* DR_C regs are double precision registers obtained by
7bb11558 2181 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2182 for (portion = 0; portion < 2; portion++)
2183 regcache_raw_read (regcache, base_regnum + portion,
2184 (temp_buffer
7bb11558 2185 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2186
7bb11558 2187 /* We must pay attention to the endianness. */
39add00a
MS		 2188 sh64_register_convert_to_virtual (reg_nr,
2189 gdbarch_register_type (gdbarch,
2190 reg_nr),
2191 temp_buffer, buffer);
55ff77ac
CV		 2192 }
2193
2194 else if (reg_nr >= FV0_C_REGNUM
2195 && reg_nr <= FV_LAST_C_REGNUM)
2196 {
2197 base_regnum = sh64_compact_reg_base_num (reg_nr);
2198
7bb11558 2199 /* Build the value in the provided buffer. */
55ff77ac 2200 /* FV_C regs are vectors of single precision registers obtained by
7bb11558 2201 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2202 for (portion = 0; portion < 4; portion++)
2203 regcache_raw_read (regcache, base_regnum + portion,
2204 ((char *) buffer
7bb11558 2205 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2206 }
2207
2208 else if (reg_nr == FPSCR_C_REGNUM)
2209 {
2210 int fpscr_base_regnum;
2211 int sr_base_regnum;
2212 unsigned int fpscr_value;
2213 unsigned int sr_value;
2214 unsigned int fpscr_c_value;
2215 unsigned int fpscr_c_part1_value;
2216 unsigned int fpscr_c_part2_value;
2217
2218 fpscr_base_regnum = FPSCR_REGNUM;
2219 sr_base_regnum = SR_REGNUM;
2220
7bb11558 2221 /* Build the value in the provided buffer. */
55ff77ac
CV		 2222 /* FPSCR_C is a very weird register that contains sparse bits
2223 from the FPSCR and the SR architectural registers.
2224 Specifically: */
2225 /* *INDENT-OFF* */
2226 /*
2227 FPSRC_C bit
2228 0 Bit 0 of FPSCR
2229 1 reserved
2230 2-17 Bit 2-18 of FPSCR
2231 18-20 Bits 12,13,14 of SR
2232 21-31 reserved
2233 */
2234 /* *INDENT-ON* */
2235 /* Get FPSCR into a local buffer */
2236 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
7bb11558 2237 /* Get value as an int. */
55ff77ac
CV		 2238 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2239 /* Get SR into a local buffer */
2240 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
7bb11558 2241 /* Get value as an int. */
55ff77ac 2242 sr_value = extract_unsigned_integer (temp_buffer, 4);
7bb11558 2243 /* Build the new value. */
55ff77ac
CV		 2244 fpscr_c_part1_value = fpscr_value & 0x3fffd;
2245 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
2246 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
2247 /* Store that in out buffer!!! */
2248 store_unsigned_integer (buffer, 4, fpscr_c_value);
7bb11558 2249 /* FIXME There is surely an endianness gotcha here. */
55ff77ac
CV		 2250 }
2251
2252 else if (reg_nr == FPUL_C_REGNUM)
2253 {
2254 base_regnum = sh64_compact_reg_base_num (reg_nr);
2255
2256 /* FPUL_C register is floating point register 32,
7bb11558 2257 same size, same endianness. */
55ff77ac
CV		 2258 regcache_raw_read (regcache, base_regnum, buffer);
2259 }
2260}
2261
2262static void
2263sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2264 int reg_nr, const void *buffer)
2265{
2266 int base_regnum, portion;
2267 int offset;
2268 char temp_buffer[MAX_REGISTER_SIZE];
55ff77ac
CV		 2269
2270 if (reg_nr >= DR0_REGNUM
2271 && reg_nr <= DR_LAST_REGNUM)
2272 {
2273 base_regnum = dr_reg_base_num (reg_nr);
7bb11558 2274 /* We must pay attention to the endianness. */
39add00a
MS		 2275 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
2276 reg_nr,
2277 buffer, temp_buffer);
55ff77ac
CV		 2278
2279 /* Write the real regs for which this one is an alias. */
2280 for (portion = 0; portion < 2; portion++)
2281 regcache_raw_write (regcache, base_regnum + portion,
2282 (temp_buffer
7bb11558
MS		 2283 + register_size (gdbarch,
2284 base_regnum) * portion));
55ff77ac
CV		 2285 }
2286
2287 else if (reg_nr >= FPP0_REGNUM
2288 && reg_nr <= FPP_LAST_REGNUM)
2289 {
2290 base_regnum = fpp_reg_base_num (reg_nr);
2291
2292 /* Write the real regs for which this one is an alias. */
2293 for (portion = 0; portion < 2; portion++)
2294 regcache_raw_write (regcache, base_regnum + portion,
2295 ((char *) buffer
7bb11558
MS		 2296 + register_size (gdbarch,
2297 base_regnum) * portion));
55ff77ac
CV		 2298 }
2299
2300 else if (reg_nr >= FV0_REGNUM
2301 && reg_nr <= FV_LAST_REGNUM)
2302 {
2303 base_regnum = fv_reg_base_num (reg_nr);
2304
2305 /* Write the real regs for which this one is an alias. */
2306 for (portion = 0; portion < 4; portion++)
2307 regcache_raw_write (regcache, base_regnum + portion,
2308 ((char *) buffer
7bb11558
MS		 2309 + register_size (gdbarch,
2310 base_regnum) * portion));
55ff77ac
CV		 2311 }
2312
2313 /* sh compact general pseudo registers. 1-to-1 with a shmedia
2314 register but only 4 bytes of it. */
2315 else if (reg_nr >= R0_C_REGNUM
2316 && reg_nr <= T_C_REGNUM)
2317 {
2318 base_regnum = sh64_compact_reg_base_num (reg_nr);
7bb11558 2319 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
55ff77ac
CV		 2320 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2321 offset = 4;
2322 else
2323 offset = 0;
2324 /* Let's read the value of the base register into a temporary
2325 buffer, so that overwriting the last four bytes with the new
7bb11558 2326 value of the pseudo will leave the upper 4 bytes unchanged. */
55ff77ac
CV		 2327 regcache_raw_read (regcache, base_regnum, temp_buffer);
2328 /* Write as an 8 byte quantity */
2329 memcpy (temp_buffer + offset, buffer, 4);
2330 regcache_raw_write (regcache, base_regnum, temp_buffer);
2331 }
2332
2333 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
7bb11558 2334 registers. Both are 4 bytes. */
55ff77ac
CV		 2335 else if (reg_nr >= FP0_C_REGNUM
2336 && reg_nr <= FP_LAST_C_REGNUM)
2337 {
2338 base_regnum = sh64_compact_reg_base_num (reg_nr);
2339 regcache_raw_write (regcache, base_regnum, buffer);
2340 }
2341
2342 else if (reg_nr >= DR0_C_REGNUM
2343 && reg_nr <= DR_LAST_C_REGNUM)
2344 {
2345 base_regnum = sh64_compact_reg_base_num (reg_nr);
2346 for (portion = 0; portion < 2; portion++)
2347 {
7bb11558 2348 /* We must pay attention to the endianness. */
39add00a
MS		 2349 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2350 reg_nr),
2351 reg_nr,
2352 buffer, temp_buffer);
55ff77ac
CV		 2353
2354 regcache_raw_write (regcache, base_regnum + portion,
2355 (temp_buffer
7bb11558
MS		 2356 + register_size (gdbarch,
2357 base_regnum) * portion));
55ff77ac
CV		 2358 }
2359 }
2360
2361 else if (reg_nr >= FV0_C_REGNUM
2362 && reg_nr <= FV_LAST_C_REGNUM)
2363 {
2364 base_regnum = sh64_compact_reg_base_num (reg_nr);
2365
2366 for (portion = 0; portion < 4; portion++)
2367 {
2368 regcache_raw_write (regcache, base_regnum + portion,
2369 ((char *) buffer
7bb11558
MS		 2370 + register_size (gdbarch,
2371 base_regnum) * portion));
55ff77ac
CV		 2372 }
2373 }
2374
2375 else if (reg_nr == FPSCR_C_REGNUM)
2376 {
2377 int fpscr_base_regnum;
2378 int sr_base_regnum;
2379 unsigned int fpscr_value;
2380 unsigned int sr_value;
2381 unsigned int old_fpscr_value;
2382 unsigned int old_sr_value;
2383 unsigned int fpscr_c_value;
2384 unsigned int fpscr_mask;
2385 unsigned int sr_mask;
2386
2387 fpscr_base_regnum = FPSCR_REGNUM;
2388 sr_base_regnum = SR_REGNUM;
2389
2390 /* FPSCR_C is a very weird register that contains sparse bits
2391 from the FPSCR and the SR architectural registers.
2392 Specifically: */
2393 /* *INDENT-OFF* */
2394 /*
2395 FPSRC_C bit
2396 0 Bit 0 of FPSCR
2397 1 reserved
2398 2-17 Bit 2-18 of FPSCR
2399 18-20 Bits 12,13,14 of SR
2400 21-31 reserved
2401 */
2402 /* *INDENT-ON* */
7bb11558 2403 /* Get value as an int. */
55ff77ac
CV		 2404 fpscr_c_value = extract_unsigned_integer (buffer, 4);
2405
7bb11558 2406 /* Build the new values. */
55ff77ac
CV		 2407 fpscr_mask = 0x0003fffd;
2408 sr_mask = 0x001c0000;
2409
2410 fpscr_value = fpscr_c_value & fpscr_mask;
2411 sr_value = (fpscr_value & sr_mask) >> 6;
2412
2413 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2414 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2415 old_fpscr_value &= 0xfffc0002;
2416 fpscr_value |= old_fpscr_value;
2417 store_unsigned_integer (temp_buffer, 4, fpscr_value);
2418 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
2419
2420 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2421 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
2422 old_sr_value &= 0xffff8fff;
2423 sr_value |= old_sr_value;
2424 store_unsigned_integer (temp_buffer, 4, sr_value);
2425 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
2426 }
2427
2428 else if (reg_nr == FPUL_C_REGNUM)
2429 {
2430 base_regnum = sh64_compact_reg_base_num (reg_nr);
2431 regcache_raw_write (regcache, base_regnum, buffer);
2432 }
2433}
2434
7bb11558 2435/* Floating point vector of 4 float registers. */
55ff77ac
CV		 2436static void
2437do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2438 int fv_regnum)
2439{
2440 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
2441 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2442 fv_regnum - FV0_REGNUM,
2443 (int) read_register (first_fp_reg_num),
2444 (int) read_register (first_fp_reg_num + 1),
2445 (int) read_register (first_fp_reg_num + 2),
2446 (int) read_register (first_fp_reg_num + 3));
2447}
2448
7bb11558 2449/* Floating point vector of 4 float registers, compact mode. */
55ff77ac
CV		 2450static void
2451do_fv_c_register_info (int fv_regnum)
2452{
2453 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
2454 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2455 fv_regnum - FV0_C_REGNUM,
2456 (int) read_register (first_fp_reg_num),
2457 (int) read_register (first_fp_reg_num + 1),
2458 (int) read_register (first_fp_reg_num + 2),
2459 (int) read_register (first_fp_reg_num + 3));
2460}
2461
2462/* Pairs of single regs. The DR are instead double precision
7bb11558 2463 registers. */
55ff77ac
CV		 2464static void
2465do_fpp_register_info (int fpp_regnum)
2466{
2467 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
2468
2469 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
2470 fpp_regnum - FPP0_REGNUM,
2471 (int) read_register (first_fp_reg_num),
2472 (int) read_register (first_fp_reg_num + 1));
2473}
2474
7bb11558 2475/* Double precision registers. */
55ff77ac
CV		 2476static void
2477do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2478 int dr_regnum)
2479{
2480 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
2481
2482 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
2483 dr_regnum - DR0_REGNUM,
2484 (int) read_register (first_fp_reg_num),
2485 (int) read_register (first_fp_reg_num + 1));
2486}
2487
7bb11558 2488/* Double precision registers, compact mode. */
55ff77ac
CV		 2489static void
2490do_dr_c_register_info (int dr_regnum)
2491{
2492 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
2493
2494 printf_filtered ("dr%d_c\t0x%08x%08x\n",
2495 dr_regnum - DR0_C_REGNUM,
2496 (int) read_register (first_fp_reg_num),
2497 (int) read_register (first_fp_reg_num +1));
2498}
2499
7bb11558 2500/* General register in compact mode. */
55ff77ac
CV		 2501static void
2502do_r_c_register_info (int r_c_regnum)
2503{
2504 int regnum = sh64_compact_reg_base_num (r_c_regnum);
2505
2506 printf_filtered ("r%d_c\t0x%08x\n",
2507 r_c_regnum - R0_C_REGNUM,
2508 /*FIXME!!!*/ (int) read_register (regnum));
2509}
2510
2511/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
7bb11558
MS		 2512 shmedia REGISTERS. */
2513/* Control registers, compact mode. */
55ff77ac
CV		 2514static void
2515do_cr_c_register_info (int cr_c_regnum)
2516{
2517 switch (cr_c_regnum)
2518 {
2519 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2520 break;
2521 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2522 break;
2523 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2524 break;
2525 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2526 break;
2527 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2528 break;
2529 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2530 break;
2531 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2532 break;
2533 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
2534 break;
2535 }
2536}
2537
2538static void
2539sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2540{ /* do values for FP (float) regs */
2541 char *raw_buffer;
2542 double flt; /* double extracted from raw hex data */
2543 int inv;
2544 int j;
2545
7bb11558 2546 /* Allocate space for the float. */
55ff77ac
CV		 2547 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2548
2549 /* Get the data in raw format. */
2550 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2551 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2552
2553 /* Get the register as a number */
2554 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2555
7bb11558 2556 /* Print the name and some spaces. */
55ff77ac
CV		 2557 fputs_filtered (REGISTER_NAME (regnum), file);
2558 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2559
7bb11558 2560 /* Print the value. */
55ff77ac
CV		 2561 if (inv)
2562 fprintf_filtered (file, "<invalid float>");
2563 else
2564 fprintf_filtered (file, "%-10.9g", flt);
2565
7bb11558 2566 /* Print the fp register as hex. */
55ff77ac
CV		 2567 fprintf_filtered (file, "\t(raw 0x");
2568 for (j = 0; j < register_size (gdbarch, regnum); j++)
2569 {
aa1ee363 2570 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
55ff77ac
CV		 2571 : register_size (gdbarch, regnum) - 1 - j;
2572 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2573 }
2574 fprintf_filtered (file, ")");
2575 fprintf_filtered (file, "\n");
2576}
2577
2578static void
2579sh64_do_pseudo_register (int regnum)
2580{
7bb11558 2581 /* All the sh64-compact mode registers are pseudo registers. */
55ff77ac
CV		 2582
2583 if (regnum < NUM_REGS
2584 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
2585 internal_error (__FILE__, __LINE__,
2586 "Invalid pseudo register number %d\n", regnum);
2587
2588 else if ((regnum >= DR0_REGNUM
2589 && regnum <= DR_LAST_REGNUM))
2590 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
2591
2592 else if ((regnum >= DR0_C_REGNUM
2593 && regnum <= DR_LAST_C_REGNUM))
2594 do_dr_c_register_info (regnum);
2595
2596 else if ((regnum >= FV0_REGNUM
2597 && regnum <= FV_LAST_REGNUM))
2598 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
2599
2600 else if ((regnum >= FV0_C_REGNUM
2601 && regnum <= FV_LAST_C_REGNUM))
2602 do_fv_c_register_info (regnum);
2603
2604 else if (regnum >= FPP0_REGNUM
2605 && regnum <= FPP_LAST_REGNUM)
2606 do_fpp_register_info (regnum);
2607
2608 else if (regnum >= R0_C_REGNUM
2609 && regnum <= R_LAST_C_REGNUM)
7bb11558
MS		 2610 /* FIXME, this function will not print the right format. */
2611 do_r_c_register_info (regnum);
55ff77ac
CV		 2612 else if (regnum >= FP0_C_REGNUM
2613 && regnum <= FP_LAST_C_REGNUM)
7bb11558
MS		 2614 /* This should work also for pseudoregs. */
2615 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum);
55ff77ac
CV		 2616 else if (regnum >= PC_C_REGNUM
2617 && regnum <= FPUL_C_REGNUM)
2618 do_cr_c_register_info (regnum);
55ff77ac
CV		 2619}
2620
2621static void
2622sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2623{
2624 char raw_buffer[MAX_REGISTER_SIZE];
2625
2626 fputs_filtered (REGISTER_NAME (regnum), file);
2627 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2628
2629 /* Get the data in raw format. */
2630 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2631 fprintf_filtered (file, "*value not available*\n");
2632
2633 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2634 file, 'x', 1, 0, Val_pretty_default);
2635 fprintf_filtered (file, "\t");
2636 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2637 file, 0, 1, 0, Val_pretty_default);
2638 fprintf_filtered (file, "\n");
2639}
2640
2641static void
2642sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2643{
2644 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2645 internal_error (__FILE__, __LINE__,
2646 "Invalid register number %d\n", regnum);
2647
2648 else if (regnum >= 0 && regnum < NUM_REGS)
2649 {
2650 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2651 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2652 else
2653 sh_do_register (gdbarch, file, regnum); /* All other regs */
2654 }
2655
2656 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2657 sh64_do_pseudo_register (regnum);
2658}
2659
2660static void
2661sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2662 struct frame_info *frame, int regnum, int fpregs)
2663{
2664 if (regnum != -1) /* do one specified register */
2665 {
2666 if (*(REGISTER_NAME (regnum)) == '\0')
2667 error ("Not a valid register for the current processor type");
2668
2669 sh_print_register (gdbarch, file, regnum);
2670 }
2671 else
2672 /* do all (or most) registers */
2673 {
2674 regnum = 0;
2675 while (regnum < NUM_REGS)
2676 {
2677 /* If the register name is empty, it is undefined for this
2678 processor, so don't display anything. */
2679 if (REGISTER_NAME (regnum) == NULL
2680 || *(REGISTER_NAME (regnum)) == '\0')
2681 {
2682 regnum++;
2683 continue;
2684 }
2685
2686 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2687 {
2688 if (fpregs)
2689 {
2690 /* true for "INFO ALL-REGISTERS" command */
2691 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2692 regnum ++;
2693 }
2694 else
2695 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2696 }
2697 else
2698 {
2699 sh_do_register (gdbarch, file, regnum); /* All other regs */
2700 regnum++;
2701 }
2702 }
2703
2704 if (fpregs)
2705 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2706 {
2707 sh64_do_pseudo_register (regnum);
2708 regnum++;
2709 }
2710 }
2711}
2712
2713static void
2714sh_compact_do_registers_info (int regnum, int fpregs)
2715{
55ff77ac
CV		 2716 if (regnum != -1) /* do one specified register */
2717 {
2718 if (*(REGISTER_NAME (regnum)) == '\0')
2719 error ("Not a valid register for the current processor type");
2720
2721 if (regnum >= 0 && regnum < R0_C_REGNUM)
2722 error ("Not a valid register for the current processor mode.");
2723
2724 sh_print_register (current_gdbarch, gdb_stdout, regnum);
2725 }
2726 else
2727 /* do all compact registers */
2728 {
2729 regnum = R0_C_REGNUM;
2730 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2731 {
2732 sh64_do_pseudo_register (regnum);
2733 regnum++;
2734 }
2735 }
2736}
2737
2738static void
2739sh64_do_registers_info (int regnum, int fpregs)
2740{
2741 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2742 sh_print_registers_info (current_gdbarch, gdb_stdout,
2743 deprecated_selected_frame, regnum, fpregs);
2744 else
7bb11558 2745 sh_compact_do_registers_info (regnum, fpregs);
55ff77ac
CV		 2746}
2747
2748#ifdef SVR4_SHARED_LIBS
2749
2750/* Fetch (and possibly build) an appropriate link_map_offsets structure
2751 for native i386 linux targets using the struct offsets defined in
2752 link.h (but without actual reference to that file).
2753
2754 This makes it possible to access i386-linux shared libraries from
2755 a gdb that was not built on an i386-linux host (for cross debugging).
2756 */
2757
2758struct link_map_offsets *
2759sh_linux_svr4_fetch_link_map_offsets (void)
2760{
2761 static struct link_map_offsets lmo;
2762 static struct link_map_offsets *lmp = 0;
2763
2764 if (lmp == 0)
2765 {
2766 lmp = &lmo;
2767
2768 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2769
2770 lmo.r_map_offset = 4;
2771 lmo.r_map_size = 4;
2772
2773 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2774
2775 lmo.l_addr_offset = 0;
2776 lmo.l_addr_size = 4;
2777
2778 lmo.l_name_offset = 4;
2779 lmo.l_name_size = 4;
2780
2781 lmo.l_next_offset = 12;
2782 lmo.l_next_size = 4;
2783
2784 lmo.l_prev_offset = 16;
2785 lmo.l_prev_size = 4;
2786 }
2787
2788 return lmp;
2789}
2790#endif /* SVR4_SHARED_LIBS */
2791
2792gdbarch_init_ftype sh64_gdbarch_init;
2793
2794struct gdbarch *
2795sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2796{
2797 static LONGEST sh64_call_dummy_words[] = {0};
2798 struct gdbarch *gdbarch;
2799 struct gdbarch_tdep *tdep;
2800
2801 /* If there is already a candidate, use it. */
2802 arches = gdbarch_list_lookup_by_info (arches, &info);
2803 if (arches != NULL)
2804 return arches->gdbarch;
2805
2806 /* None found, create a new architecture from the information
7bb11558 2807 provided. */
55ff77ac
CV		 2808 tdep = XMALLOC (struct gdbarch_tdep);
2809 gdbarch = gdbarch_alloc (&info, tdep);
2810
2811 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2812 ready to unwind the PC first (see frame.c:get_prev_frame()). */
0968aa8c 2813 set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default);
55ff77ac
CV		 2814
2815 /* Determine the ABI */
2816 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2817 {
7bb11558 2818 /* If the ABI is the 64-bit one, it can only be sh-media. */
55ff77ac
CV		 2819 tdep->sh_abi = SH_ABI_64;
2820 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2821 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2822 }
2823 else
2824 {
2825 /* If the ABI is the 32-bit one it could be either media or
7bb11558 2826 compact. */
55ff77ac
CV		 2827 tdep->sh_abi = SH_ABI_32;
2828 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2829 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2830 }
2831
2832 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2833 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2834 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2835 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2836 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2837 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2838
2839 set_gdbarch_sp_regnum (gdbarch, 15);
2840 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
2841
2842 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2843 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2844
2845 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2846
2847 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2848 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
55ff77ac 2849
19772a2c 2850 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, legacy_frameless_look_for_prologue);
55ff77ac
CV		 2851 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2852
2853 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2854 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2855 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2856
2857 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
2858 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2859 set_gdbarch_pc_regnum (gdbarch, 64);
2860
7bb11558
MS		 2861 /* The number of real registers is the same whether we are in
2862 ISA16(compact) or ISA32(media). */
55ff77ac 2863 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
55ff77ac
CV		 2864 set_gdbarch_deprecated_register_bytes (gdbarch,
2865 ((SIM_SH64_NR_FP_REGS + 1) * 4)
2866 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
2867
39add00a 2868 set_gdbarch_register_name (gdbarch, sh64_register_name);
7bb11558 2869 set_gdbarch_register_type (gdbarch, sh64_register_type);
55ff77ac 2870 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
39add00a 2871 set_gdbarch_deprecated_register_byte (gdbarch, sh64_register_byte);
55ff77ac
CV		 2872 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2873 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2874
2875 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
2876 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
39add00a 2877 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
55ff77ac
CV		 2878 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
2879 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
2880
2881 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
2882 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
2883 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
2884 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
2885 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
2886 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
2887 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
2888 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
74055713 2889 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
55ff77ac
CV		 2890 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
2891 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
2892 set_gdbarch_elf_make_msymbol_special (gdbarch,
2893 sh64_elf_make_msymbol_special);
2894
2895 /* Hook in ABI-specific overrides, if they have been registered. */
2896 gdbarch_init_osabi (info, gdbarch);
2897
2898 return gdbarch;
2899}
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