[binutils.git] / gdb / ppc-tdep.h

/* Target-dependent code for GDB, the GNU debugger.

   Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street, Fifth Floor,
   Boston, MA 02110-1301, USA.  */

#ifndef PPC_TDEP_H
#define PPC_TDEP_H

struct gdbarch;
struct frame_info;
struct value;
struct regcache;
struct type;

/* From ppc-linux-tdep.c... */
enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
							struct type *valtype,
							struct regcache *regcache,
							gdb_byte *readbuf,
							const gdb_byte *writebuf);
enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
							       struct type *valtype,
							       struct regcache *regcache,
							       gdb_byte *readbuf,
							       const gdb_byte *writebuf);
CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					struct value *function,
					struct regcache *regcache,
					CORE_ADDR bp_addr, int nargs,
					struct value **args, CORE_ADDR sp,
					int struct_return,
					CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
					  struct value *function,
					  struct regcache *regcache,
					  CORE_ADDR bp_addr, int nargs,
					  struct value **args, CORE_ADDR sp,
					  int struct_return,
					  CORE_ADDR struct_addr);
CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
						    CORE_ADDR bpaddr);
int ppc_linux_memory_remove_breakpoint (CORE_ADDR addr,
					gdb_byte *contents_cache);
struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
void ppc_linux_supply_gregset (struct regcache *regcache,
			       int regnum, const void *gregs, size_t size,
			       int wordsize);
void ppc_linux_supply_fpregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t size);

enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
							  struct type *valtype,
							  struct regcache *regcache,
							  gdb_byte *readbuf,
							  const gdb_byte *writebuf);

/* From rs6000-tdep.c... */
int altivec_register_p (int regno);
int spe_register_p (int regno);

/* Return non-zero if the architecture described by GDBARCH has
   floating-point registers (f0 --- f31 and fpscr).  */
int ppc_floating_point_unit_p (struct gdbarch *gdbarch);

/* Register set description.  */

struct ppc_reg_offsets
{
  /* General-purpose registers.  */
  int r0_offset;
  int pc_offset;
  int ps_offset;
  int cr_offset;
  int lr_offset;
  int ctr_offset;
  int xer_offset;
  int mq_offset;

  /* Floating-point registers.  */
  int f0_offset;
  int fpscr_offset;

  /* AltiVec registers.  */
  int vr0_offset;
  int vscr_offset;
  int vrsave_offset;
};

/* Supply register REGNUM in the general-purpose register set REGSET
   from the buffer specified by GREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_gregset (const struct regset *regset,
				struct regcache *regcache,
				int regnum, const void *gregs, size_t len);

/* Supply register REGNUM in the floating-point register set REGSET
   from the buffer specified by FPREGS and LEN to register cache
   REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */

extern void ppc_supply_fpregset (const struct regset *regset,
				 struct regcache *regcache,
				 int regnum, const void *fpregs, size_t len);

/* Collect register REGNUM in the general-purpose register set
   REGSET. from register cache REGCACHE into the buffer specified by
   GREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_gregset (const struct regset *regset,
				 const struct regcache *regcache,
				 int regnum, void *gregs, size_t len);

/* Collect register REGNUM in the floating-point register set
   REGSET. from register cache REGCACHE into the buffer specified by
   FPREGS and LEN.  If REGNUM is -1, do this for all registers in
   REGSET.  */

extern void ppc_collect_fpregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *fpregs, size_t len);

/* Private data that this module attaches to struct gdbarch. */

struct gdbarch_tdep
  {
    int wordsize;              /* size in bytes of fixed-point word */
    const struct reg *regs;    /* from current variant */
    int ppc_gp0_regnum;		/* GPR register 0 */
    int ppc_toc_regnum;		/* TOC register */
    int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
    int ppc_cr_regnum;		/* Condition register */
    int ppc_lr_regnum;		/* Link register */
    int ppc_ctr_regnum;		/* Count register */
    int ppc_xer_regnum;		/* Integer exception register */

    /* Not all PPC and RS6000 variants will have the registers
       represented below.  A -1 is used to indicate that the register
       is not present in this variant.  */

    /* Floating-point registers.  */
    int ppc_fp0_regnum;         /* floating-point register 0 */
    int ppc_fpscr_regnum;	/* fp status and condition register */

    /* Segment registers.  */
    int ppc_sr0_regnum;         /* segment register 0 */

    /* Multiplier-Quotient Register (older POWER architectures only).  */
    int ppc_mq_regnum;

    /* Altivec registers.  */
    int ppc_vr0_regnum;		/* First AltiVec register */
    int ppc_vrsave_regnum;	/* Last AltiVec register */

    /* SPE registers.  */
    int ppc_ev0_upper_regnum;   /* First GPR upper half register */
    int ppc_ev0_regnum;         /* First ev register */
    int ppc_ev31_regnum;        /* Last ev register */
    int ppc_acc_regnum;         /* SPE 'acc' register */
    int ppc_spefscr_regnum;     /* SPE 'spefscr' register */

    /* Offset to ABI specific location where link register is saved.  */
    int lr_frame_offset;	

    /* An array of integers, such that sim_regno[I] is the simulator
       register number for GDB register number I, or -1 if the
       simulator does not implement that register.  */
    int *sim_regno;
};


/* Constants for register set sizes.  */
enum
  {
    ppc_num_gprs = 32,          /* 32 general-purpose registers */
    ppc_num_fprs = 32,          /* 32 floating-point registers */
    ppc_num_srs = 16,           /* 16 segment registers */
    ppc_num_vrs = 32            /* 32 Altivec vector registers */
  };


/* Constants for SPR register numbers.  These are *not* GDB register
   numbers: they are the numbers used in the PowerPC ISA itself to
   refer to these registers.

   This table includes all the SPRs from all the variants I could find
   documentation for.

   There may be registers from different PowerPC variants assigned the
   same number, but that's fine: GDB and the SIM always use the
   numbers in the context of a particular variant, so it's not
   ambiguous.

   We need to deviate from the naming pattern when variants have
   special-purpose registers of the same name, but with different
   numbers.  Fortunately, this is rare: look below to see how we
   handle the 'tcr' registers on the 403/403GX and 602.  */

enum
  {
    ppc_spr_mq        =    0,
    ppc_spr_xer       =    1,
    ppc_spr_rtcu      =    4,
    ppc_spr_rtcl      =    5,
    ppc_spr_lr        =    8,
    ppc_spr_ctr       =    9,
    ppc_spr_cnt       =    9,
    ppc_spr_dsisr     =   18,
    ppc_spr_dar       =   19,
    ppc_spr_dec       =   22,
    ppc_spr_sdr1      =   25,
    ppc_spr_srr0      =   26,
    ppc_spr_srr1      =   27,
    ppc_spr_eie       =   80,
    ppc_spr_eid       =   81,
    ppc_spr_nri       =   82,
    ppc_spr_sp        =  102,
    ppc_spr_cmpa      =  144,
    ppc_spr_cmpb      =  145,
    ppc_spr_cmpc      =  146,
    ppc_spr_cmpd      =  147,
    ppc_spr_icr       =  148,
    ppc_spr_der       =  149,
    ppc_spr_counta    =  150,
    ppc_spr_countb    =  151,
    ppc_spr_cmpe      =  152,
    ppc_spr_cmpf      =  153,
    ppc_spr_cmpg      =  154,
    ppc_spr_cmph      =  155,
    ppc_spr_lctrl1    =  156,
    ppc_spr_lctrl2    =  157,
    ppc_spr_ictrl     =  158,
    ppc_spr_bar       =  159,
    ppc_spr_vrsave    =  256,
    ppc_spr_sprg0     =  272,
    ppc_spr_sprg1     =  273,
    ppc_spr_sprg2     =  274,
    ppc_spr_sprg3     =  275,
    ppc_spr_asr       =  280,
    ppc_spr_ear       =  282,
    ppc_spr_tbl       =  284,
    ppc_spr_tbu       =  285,
    ppc_spr_pvr       =  287,
    ppc_spr_spefscr   =  512,
    ppc_spr_ibat0u    =  528,
    ppc_spr_ibat0l    =  529,
    ppc_spr_ibat1u    =  530,
    ppc_spr_ibat1l    =  531,
    ppc_spr_ibat2u    =  532,
    ppc_spr_ibat2l    =  533,
    ppc_spr_ibat3u    =  534,
    ppc_spr_ibat3l    =  535,
    ppc_spr_dbat0u    =  536,
    ppc_spr_dbat0l    =  537,
    ppc_spr_dbat1u    =  538,
    ppc_spr_dbat1l    =  539,
    ppc_spr_dbat2u    =  540,
    ppc_spr_dbat2l    =  541,
    ppc_spr_dbat3u    =  542,
    ppc_spr_dbat3l    =  543,
    ppc_spr_ic_cst    =  560,
    ppc_spr_ic_adr    =  561,
    ppc_spr_ic_dat    =  562,
    ppc_spr_dc_cst    =  568,
    ppc_spr_dc_adr    =  569,
    ppc_spr_dc_dat    =  570,
    ppc_spr_dpdr      =  630,
    ppc_spr_dpir      =  631,
    ppc_spr_immr      =  638,
    ppc_spr_mi_ctr    =  784,
    ppc_spr_mi_ap     =  786,
    ppc_spr_mi_epn    =  787,
    ppc_spr_mi_twc    =  789,
    ppc_spr_mi_rpn    =  790,
    ppc_spr_mi_cam    =  816,
    ppc_spr_mi_ram0   =  817,
    ppc_spr_mi_ram1   =  818,
    ppc_spr_md_ctr    =  792,
    ppc_spr_m_casid   =  793,
    ppc_spr_md_ap     =  794,
    ppc_spr_md_epn    =  795,
    ppc_spr_m_twb     =  796,
    ppc_spr_md_twc    =  797,
    ppc_spr_md_rpn    =  798,
    ppc_spr_m_tw      =  799,
    ppc_spr_mi_dbcam  =  816,
    ppc_spr_mi_dbram0 =  817,
    ppc_spr_mi_dbram1 =  818,
    ppc_spr_md_dbcam  =  824,
    ppc_spr_md_cam    =  824,
    ppc_spr_md_dbram0 =  825,
    ppc_spr_md_ram0   =  825,
    ppc_spr_md_dbram1 =  826,
    ppc_spr_md_ram1   =  826,
    ppc_spr_ummcr0    =  936,
    ppc_spr_upmc1     =  937,
    ppc_spr_upmc2     =  938,
    ppc_spr_usia      =  939,
    ppc_spr_ummcr1    =  940,
    ppc_spr_upmc3     =  941,
    ppc_spr_upmc4     =  942,
    ppc_spr_zpr       =  944,
    ppc_spr_pid       =  945,
    ppc_spr_mmcr0     =  952,
    ppc_spr_pmc1      =  953,
    ppc_spr_sgr       =  953,
    ppc_spr_pmc2      =  954,
    ppc_spr_dcwr      =  954,
    ppc_spr_sia       =  955,
    ppc_spr_mmcr1     =  956,
    ppc_spr_pmc3      =  957,
    ppc_spr_pmc4      =  958,
    ppc_spr_sda       =  959,
    ppc_spr_tbhu      =  972,
    ppc_spr_tblu      =  973,
    ppc_spr_dmiss     =  976,
    ppc_spr_dcmp      =  977,
    ppc_spr_hash1     =  978,
    ppc_spr_hash2     =  979,
    ppc_spr_icdbdr    =  979,
    ppc_spr_imiss     =  980,
    ppc_spr_esr       =  980,
    ppc_spr_icmp      =  981,
    ppc_spr_dear      =  981,
    ppc_spr_rpa       =  982,
    ppc_spr_evpr      =  982,
    ppc_spr_cdbcr     =  983,
    ppc_spr_tsr       =  984,
    ppc_spr_602_tcr   =  984,
    ppc_spr_403_tcr   =  986,
    ppc_spr_ibr       =  986,
    ppc_spr_pit       =  987,
    ppc_spr_esasrr    =  988,
    ppc_spr_tbhi      =  988,
    ppc_spr_tblo      =  989,
    ppc_spr_srr2      =  990,
    ppc_spr_sebr      =  990,
    ppc_spr_srr3      =  991,
    ppc_spr_ser       =  991,
    ppc_spr_hid0      = 1008,
    ppc_spr_dbsr      = 1008,
    ppc_spr_hid1      = 1009,
    ppc_spr_iabr      = 1010,
    ppc_spr_dbcr      = 1010,
    ppc_spr_iac1      = 1012,
    ppc_spr_dabr      = 1013,
    ppc_spr_iac2      = 1013,
    ppc_spr_dac1      = 1014,
    ppc_spr_dac2      = 1015,
    ppc_spr_l2cr      = 1017,
    ppc_spr_dccr      = 1018,
    ppc_spr_ictc      = 1019,
    ppc_spr_iccr      = 1019,
    ppc_spr_thrm1     = 1020,
    ppc_spr_pbl1      = 1020,
    ppc_spr_thrm2     = 1021,
    ppc_spr_pbu1      = 1021,
    ppc_spr_thrm3     = 1022,
    ppc_spr_pbl2      = 1022,
    ppc_spr_fpecr     = 1022,
    ppc_spr_lt        = 1022,
    ppc_spr_pir       = 1023,
    ppc_spr_pbu2      = 1023
  };

/* Instruction size.  */
#define PPC_INSN_SIZE 4

/* Estimate for the maximum number of instrctions in a function epilogue.  */
#define PPC_MAX_EPILOGUE_INSTRUCTIONS  52

#endif /* ppc-tdep.h */
Commit	Line	Data
9aa1e687	1	/* Target-dependent code for GDB, the GNU debugger.
f9be684a	2
197e01b6	3	Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005
a0c75879	4	Free Software Foundation, Inc.
9aa1e687 KB	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
197e01b6 EZ	20	Foundation, Inc., 51 Franklin Street, Fifth Floor,
197e01b6 EZ	21	Boston, MA 02110-1301, USA. */
9aa1e687	22
3a1c5313 AC	23	#ifndef PPC_TDEP_H
	24	#define PPC_TDEP_H
	25
da3331ec	26	struct gdbarch;
3a1c5313 AC	27	struct frame_info;
3a1c5313 AC	28	struct value;
4a4b3fed	29	struct regcache;
221c12ff	30	struct type;
3a1c5313	31
9aa1e687	32	/* From ppc-linux-tdep.c... */
05580c65 AC	33	enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
	34	struct type *valtype,
	35	struct regcache *regcache,
50fd1280 AC	36	gdb_byte *readbuf,
50fd1280 AC	37	const gdb_byte *writebuf);
05580c65 AC	38	enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
	39	struct type *valtype,
	40	struct regcache *regcache,
50fd1280 AC	41	gdb_byte *readbuf,
50fd1280 AC	42	const gdb_byte *writebuf);
77b2b6d4	43	CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	44	struct value *function,
77b2b6d4 AC	45	struct regcache *regcache,
	46	CORE_ADDR bp_addr, int nargs,
	47	struct value **args, CORE_ADDR sp,
	48	int struct_return,
	49	CORE_ADDR struct_addr);
8be9034a	50	CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
7d9b040b	51	struct value *function,
8be9034a AC	52	struct regcache *regcache,
	53	CORE_ADDR bp_addr, int nargs,
	54	struct value **args, CORE_ADDR sp,
	55	int struct_return,
	56	CORE_ADDR struct_addr);
6066c3de AC	57	CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
6066c3de AC	58	CORE_ADDR bpaddr);
50fd1280 AC	59	int ppc_linux_memory_remove_breakpoint (CORE_ADDR addr,
50fd1280 AC	60	gdb_byte *contents_cache);
6ded7999	61	struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
f9be684a AC	62	void ppc_linux_supply_gregset (struct regcache *regcache,
	63	int regnum, const void *gregs, size_t size,
	64	int wordsize);
	65	void ppc_linux_supply_fpregset (const struct regset *regset,
	66	struct regcache *regcache,
	67	int regnum, const void *gregs, size_t size);
9aa1e687	68
05580c65 AC	69	enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
	70	struct type *valtype,
	71	struct regcache *regcache,
50fd1280 AC	72	gdb_byte *readbuf,
50fd1280 AC	73	const gdb_byte *writebuf);
9aa1e687 KB	74
9aa1e687 KB	75	/* From rs6000-tdep.c... */
1fcc0bb8	76	int altivec_register_p (int regno);
867e2dc5	77	int spe_register_p (int regno);
9aa1e687	78
383f0f5b JB	79	/* Return non-zero if the architecture described by GDBARCH has
383f0f5b JB	80	floating-point registers (f0 --- f31 and fpscr). */
0a613259 AC	81	int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
0a613259 AC	82
d195bc9f MK	83	/* Register set description. */
	84
	85	struct ppc_reg_offsets
	86	{
	87	/* General-purpose registers. */
	88	int r0_offset;
	89	int pc_offset;
	90	int ps_offset;
	91	int cr_offset;
	92	int lr_offset;
	93	int ctr_offset;
	94	int xer_offset;
	95	int mq_offset;
	96
	97	/* Floating-point registers. */
	98	int f0_offset;
	99	int fpscr_offset;
	100
	101	/* AltiVec registers. */
	102	int vr0_offset;
	103	int vscr_offset;
	104	int vrsave_offset;
	105	};
	106
	107	/* Supply register REGNUM in the general-purpose register set REGSET
	108	from the buffer specified by GREGS and LEN to register cache
	109	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	110
	111	extern void ppc_supply_gregset (const struct regset *regset,
	112	struct regcache *regcache,
	113	int regnum, const void *gregs, size_t len);
	114
	115	/* Supply register REGNUM in the floating-point register set REGSET
	116	from the buffer specified by FPREGS and LEN to register cache
	117	REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
	118
	119	extern void ppc_supply_fpregset (const struct regset *regset,
	120	struct regcache *regcache,
	121	int regnum, const void *fpregs, size_t len);
	122
	123	/* Collect register REGNUM in the general-purpose register set
	124	REGSET. from register cache REGCACHE into the buffer specified by
	125	GREGS and LEN. If REGNUM is -1, do this for all registers in
	126	REGSET. */
	127
	128	extern void ppc_collect_gregset (const struct regset *regset,
	129	const struct regcache *regcache,
	130	int regnum, void *gregs, size_t len);
	131
	132	/* Collect register REGNUM in the floating-point register set
	133	REGSET. from register cache REGCACHE into the buffer specified by
	134	FPREGS and LEN. If REGNUM is -1, do this for all registers in
	135	REGSET. */
	136
	137	extern void ppc_collect_fpregset (const struct regset *regset,
	138	const struct regcache *regcache,
	139	int regnum, void *fpregs, size_t len);
	140
2188cbdd EZ	141	/* Private data that this module attaches to struct gdbarch. */
	142
	143	struct gdbarch_tdep
	144	{
	145	int wordsize; /* size in bytes of fixed-point word */
2188cbdd EZ	146	const struct reg regs; / from current variant */
2188cbdd EZ	147	int ppc_gp0_regnum; /* GPR register 0 */
2188cbdd EZ	148	int ppc_toc_regnum; /* TOC register */
	149	int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
	150	int ppc_cr_regnum; /* Condition register */
	151	int ppc_lr_regnum; /* Link register */
	152	int ppc_ctr_regnum; /* Count register */
	153	int ppc_xer_regnum; /* Integer exception register */
383f0f5b	154
826d5376 PG	155	/* Not all PPC and RS6000 variants will have the registers
	156	represented below. A -1 is used to indicate that the register
	157	is not present in this variant. */
	158
	159	/* Floating-point registers. */
366f009f	160	int ppc_fp0_regnum; /* floating-point register 0 */
826d5376 PG	161	int ppc_fpscr_regnum; /* fp status and condition register */
	162
	163	/* Segment registers. */
	164	int ppc_sr0_regnum; /* segment register 0 */
383f0f5b	165
826d5376 PG	166	/* Multiplier-Quotient Register (older POWER architectures only). */
826d5376 PG	167	int ppc_mq_regnum;
f86a7158	168
826d5376	169	/* Altivec registers. */
1fcc0bb8 EZ	170	int ppc_vr0_regnum; /* First AltiVec register */
1fcc0bb8 EZ	171	int ppc_vrsave_regnum; /* Last AltiVec register */
826d5376 PG	172
826d5376 PG	173	/* SPE registers. */
6ced10dd	174	int ppc_ev0_upper_regnum; /* First GPR upper half register */
c8001721 EZ	175	int ppc_ev0_regnum; /* First ev register */
c8001721 EZ	176	int ppc_ev31_regnum; /* Last ev register */
867e2dc5 JB	177	int ppc_acc_regnum; /* SPE 'acc' register */
867e2dc5 JB	178	int ppc_spefscr_regnum; /* SPE 'spefscr' register */
826d5376 PG	179
	180	/* Offset to ABI specific location where link register is saved. */
	181	int lr_frame_offset;
9f643768 JB	182
	183	/* An array of integers, such that sim_regno[I] is the simulator
	184	register number for GDB register number I, or -1 if the
	185	simulator does not implement that register. */
	186	int *sim_regno;
2188cbdd	187	};
3a1c5313	188
b967e06f JB	189
	190	/* Constants for register set sizes. */
	191	enum
	192	{
8bf659e8	193	ppc_num_gprs = 32, /* 32 general-purpose registers */
cc98b5cc	194	ppc_num_fprs = 32, /* 32 floating-point registers */
8f088af7	195	ppc_num_srs = 16, /* 16 segment registers */
cc98b5cc	196	ppc_num_vrs = 32 /* 32 Altivec vector registers */
b967e06f JB	197	};
b967e06f JB	198
0ea0ec5f JB	199
	200	/* Constants for SPR register numbers. These are not GDB register
	201	numbers: they are the numbers used in the PowerPC ISA itself to
	202	refer to these registers.
	203
	204	This table includes all the SPRs from all the variants I could find
	205	documentation for.
	206
	207	There may be registers from different PowerPC variants assigned the
	208	same number, but that's fine: GDB and the SIM always use the
	209	numbers in the context of a particular variant, so it's not
	210	ambiguous.
	211
	212	We need to deviate from the naming pattern when variants have
	213	special-purpose registers of the same name, but with different
	214	numbers. Fortunately, this is rare: look below to see how we
	215	handle the 'tcr' registers on the 403/403GX and 602. */
	216
	217	enum
	218	{
	219	ppc_spr_mq = 0,
	220	ppc_spr_xer = 1,
	221	ppc_spr_rtcu = 4,
	222	ppc_spr_rtcl = 5,
	223	ppc_spr_lr = 8,
	224	ppc_spr_ctr = 9,
	225	ppc_spr_cnt = 9,
	226	ppc_spr_dsisr = 18,
	227	ppc_spr_dar = 19,
	228	ppc_spr_dec = 22,
	229	ppc_spr_sdr1 = 25,
	230	ppc_spr_srr0 = 26,
	231	ppc_spr_srr1 = 27,
	232	ppc_spr_eie = 80,
	233	ppc_spr_eid = 81,
	234	ppc_spr_nri = 82,
	235	ppc_spr_sp = 102,
	236	ppc_spr_cmpa = 144,
	237	ppc_spr_cmpb = 145,
	238	ppc_spr_cmpc = 146,
	239	ppc_spr_cmpd = 147,
	240	ppc_spr_icr = 148,
	241	ppc_spr_der = 149,
	242	ppc_spr_counta = 150,
	243	ppc_spr_countb = 151,
	244	ppc_spr_cmpe = 152,
	245	ppc_spr_cmpf = 153,
	246	ppc_spr_cmpg = 154,
	247	ppc_spr_cmph = 155,
	248	ppc_spr_lctrl1 = 156,
	249	ppc_spr_lctrl2 = 157,
	250	ppc_spr_ictrl = 158,
	251	ppc_spr_bar = 159,
	252	ppc_spr_vrsave = 256,
	253	ppc_spr_sprg0 = 272,
	254	ppc_spr_sprg1 = 273,
	255	ppc_spr_sprg2 = 274,
	256	ppc_spr_sprg3 = 275,
5109a438	257	ppc_spr_asr = 280,
0ea0ec5f JB	258	ppc_spr_ear = 282,
	259	ppc_spr_tbl = 284,
	260	ppc_spr_tbu = 285,
	261	ppc_spr_pvr = 287,
	262	ppc_spr_spefscr = 512,
	263	ppc_spr_ibat0u = 528,
	264	ppc_spr_ibat0l = 529,
	265	ppc_spr_ibat1u = 530,
	266	ppc_spr_ibat1l = 531,
	267	ppc_spr_ibat2u = 532,
	268	ppc_spr_ibat2l = 533,
	269	ppc_spr_ibat3u = 534,
	270	ppc_spr_ibat3l = 535,
	271	ppc_spr_dbat0u = 536,
	272	ppc_spr_dbat0l = 537,
	273	ppc_spr_dbat1u = 538,
	274	ppc_spr_dbat1l = 539,
	275	ppc_spr_dbat2u = 540,
	276	ppc_spr_dbat2l = 541,
	277	ppc_spr_dbat3u = 542,
	278	ppc_spr_dbat3l = 543,
	279	ppc_spr_ic_cst = 560,
	280	ppc_spr_ic_adr = 561,
	281	ppc_spr_ic_dat = 562,
	282	ppc_spr_dc_cst = 568,
	283	ppc_spr_dc_adr = 569,
	284	ppc_spr_dc_dat = 570,
	285	ppc_spr_dpdr = 630,
	286	ppc_spr_dpir = 631,
	287	ppc_spr_immr = 638,
	288	ppc_spr_mi_ctr = 784,
	289	ppc_spr_mi_ap = 786,
	290	ppc_spr_mi_epn = 787,
	291	ppc_spr_mi_twc = 789,
	292	ppc_spr_mi_rpn = 790,
	293	ppc_spr_mi_cam = 816,
	294	ppc_spr_mi_ram0 = 817,
	295	ppc_spr_mi_ram1 = 818,
	296	ppc_spr_md_ctr = 792,
	297	ppc_spr_m_casid = 793,
	298	ppc_spr_md_ap = 794,
	299	ppc_spr_md_epn = 795,
5109a438	300	ppc_spr_m_twb = 796,
0ea0ec5f JB	301	ppc_spr_md_twc = 797,
	302	ppc_spr_md_rpn = 798,
	303	ppc_spr_m_tw = 799,
5109a438 JB	304	ppc_spr_mi_dbcam = 816,
	305	ppc_spr_mi_dbram0 = 817,
	306	ppc_spr_mi_dbram1 = 818,
0ea0ec5f	307	ppc_spr_md_dbcam = 824,
5109a438	308	ppc_spr_md_cam = 824,
0ea0ec5f	309	ppc_spr_md_dbram0 = 825,
5109a438	310	ppc_spr_md_ram0 = 825,
0ea0ec5f	311	ppc_spr_md_dbram1 = 826,
5109a438	312	ppc_spr_md_ram1 = 826,
0ea0ec5f JB	313	ppc_spr_ummcr0 = 936,
	314	ppc_spr_upmc1 = 937,
	315	ppc_spr_upmc2 = 938,
	316	ppc_spr_usia = 939,
	317	ppc_spr_ummcr1 = 940,
	318	ppc_spr_upmc3 = 941,
	319	ppc_spr_upmc4 = 942,
	320	ppc_spr_zpr = 944,
	321	ppc_spr_pid = 945,
	322	ppc_spr_mmcr0 = 952,
	323	ppc_spr_pmc1 = 953,
	324	ppc_spr_sgr = 953,
	325	ppc_spr_pmc2 = 954,
	326	ppc_spr_dcwr = 954,
	327	ppc_spr_sia = 955,
	328	ppc_spr_mmcr1 = 956,
	329	ppc_spr_pmc3 = 957,
	330	ppc_spr_pmc4 = 958,
	331	ppc_spr_sda = 959,
	332	ppc_spr_tbhu = 972,
	333	ppc_spr_tblu = 973,
	334	ppc_spr_dmiss = 976,
	335	ppc_spr_dcmp = 977,
	336	ppc_spr_hash1 = 978,
	337	ppc_spr_hash2 = 979,
	338	ppc_spr_icdbdr = 979,
	339	ppc_spr_imiss = 980,
	340	ppc_spr_esr = 980,
	341	ppc_spr_icmp = 981,
	342	ppc_spr_dear = 981,
	343	ppc_spr_rpa = 982,
	344	ppc_spr_evpr = 982,
	345	ppc_spr_cdbcr = 983,
	346	ppc_spr_tsr = 984,
	347	ppc_spr_602_tcr = 984,
	348	ppc_spr_403_tcr = 986,
	349	ppc_spr_ibr = 986,
	350	ppc_spr_pit = 987,
	351	ppc_spr_esasrr = 988,
	352	ppc_spr_tbhi = 988,
	353	ppc_spr_tblo = 989,
	354	ppc_spr_srr2 = 990,
	355	ppc_spr_sebr = 990,
	356	ppc_spr_srr3 = 991,
	357	ppc_spr_ser = 991,
	358	ppc_spr_hid0 = 1008,
	359	ppc_spr_dbsr = 1008,
	360	ppc_spr_hid1 = 1009,
	361	ppc_spr_iabr = 1010,
	362	ppc_spr_dbcr = 1010,
	363	ppc_spr_iac1 = 1012,
	364	ppc_spr_dabr = 1013,
	365	ppc_spr_iac2 = 1013,
	366	ppc_spr_dac1 = 1014,
	367	ppc_spr_dac2 = 1015,
	368	ppc_spr_l2cr = 1017,
	369	ppc_spr_dccr = 1018,
	370	ppc_spr_ictc = 1019,
	371	ppc_spr_iccr = 1019,
	372	ppc_spr_thrm1 = 1020,
	373	ppc_spr_pbl1 = 1020,
	374	ppc_spr_thrm2 = 1021,
	375	ppc_spr_pbu1 = 1021,
	376	ppc_spr_thrm3 = 1022,
377	ppc_spr_pbl2 = 1022,
378	ppc_spr_fpecr = 1022,
379	ppc_spr_lt = 1022,
380	ppc_spr_pir = 1023,
381	ppc_spr_pbu2 = 1023
382	};
383
a0c75879 MK	384	/* Instruction size. */
	385	#define PPC_INSN_SIZE 4
	386
0d1243d9 PG	387	/* Estimate for the maximum number of instrctions in a function epilogue. */
	388	#define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
	389
a0c75879	390	#endif /* ppc-tdep.h */