[binutils.git] / include / opcode / ChangeLog

2004-11-08  Inderpreet Singh   <[email protected]>
	    Vineet Sharma      <[email protected]>

	* maxq.h: New file: Disassembly information for the maxq port.

2004-11-05  H.J. Lu  <[email protected]>

	* i386.h (i386_optab): Put back "movzb".

2004-11-04  Hans-Peter Nilsson  <[email protected]>

	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	comments.  Remove member cris_ver_sim.  Add members
	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	(struct cris_support_reg, struct cris_cond15): New types.
	(cris_conds15): Declare.
	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	SIZE_FIELD_UNSIGNED.

2004-11-04 Jan Beulich <[email protected]>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

2004-10-07  Tomer Levi  <[email protected]>

	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	instruction type.

2004-09-30  Paul Brook  <[email protected]>

	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.

2004-09-11  Theodore A. Roth  <[email protected]>

	* avr.h: Add support for
	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.

2004-09-09  Segher Boessenkool  <[email protected]>

	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.

2004-08-24  Dmitry Diky  <[email protected]>

	* msp430.h (msp430_opc): Add new instructions.
	(msp430_rcodes): Declare new instructions.
	(msp430_hcodes): Likewise..

2004-08-13  Nick Clifton  <[email protected]>

	PR/301
	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	processors.

2004-08-30  Michal Ludvig  <[email protected]>

	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

2004-07-22  H.J. Lu  <[email protected]>

	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

2004-07-21  Jan Beulich  <[email protected]>

	* i386.h: Adjust instruction descriptions to better match the
	specification.

2004-07-16  Richard Earnshaw  <[email protected]>

	* arm.h: Remove all old content.  Replace with architecture defines
	from gas/config/tc-arm.c.

2004-07-09  Andreas Schwab  <[email protected]>

	* m68k.h: Fix comment.

2004-07-07  Tomer Levi  <[email protected]>

	* crx.h: New file.

2004-06-24  Alan Modra  <[email protected]>

	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

2004-05-24  Peter Barada  <[email protected]>

	* m68k.h: Add 'size' to m68k_opcode.

2004-05-05  Peter Barada  <[email protected]>

	* m68k.h: Switch from ColdFire chip name to core variant.

2004-04-22  Peter Barada  <[email protected]>

	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
	descriptions for new EMAC cases.
	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	handle Motorola MAC syntax.
	Allow disassembly of ColdFire V4e object files.

2004-03-16  Alan Modra  <[email protected]>

	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

2004-03-12  Jakub Jelinek  <[email protected]>

	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.

2004-03-12  Michal Ludvig  <[email protected]>

	* i386.h (i386_optab): Added xstore as an alias for xstorerng.

2004-03-12  Michal Ludvig  <[email protected]>

	* i386.h (i386_optab): Added xstore/xcrypt insns.

2004-02-09  Anil Paranjpe  <[email protected]>

	* h8300.h (32bit ldc/stc): Add relaxing support.

2004-01-12  Anil Paranjpe  <[email protected]>

	* h8300.h (BITOP): Pass MEMRELAX flag.

2004-01-09  Anil Paranjpe  <[email protected]>

	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	except for the H8S.

For older changes see ChangeLog-9103
\f
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Commit	Line	Data
7499d566 NC	1	2004-11-08 Inderpreet Singh <[email protected]>
	2	Vineet Sharma <[email protected]>
	3
	4	* maxq.h: New file: Disassembly information for the maxq port.
	5
bcb9eebe L	6	2004-11-05 H.J. Lu <[email protected]>
	7
	8	* i386.h (i386_optab): Put back "movzb".
	9
94bb3d38 HPN	10	2004-11-04 Hans-Peter Nilsson <[email protected]>
	11
	12	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	13	comments. Remove member cris_ver_sim. Add members
	14	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	15	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	16	(struct cris_support_reg, struct cris_cond15): New types.
	17	(cris_conds15): Declare.
	18	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	19	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	20	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	21	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	22	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	23	SIZE_FIELD_UNSIGNED.
	24
9306ca4a JB	25	2004-11-04 Jan Beulich <[email protected]>
	26
	27	* i386.h (sldx_Suf): Remove.
	28	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	29	(q_FP): Define, implying no REX64.
	30	(x_FP, sl_FP): Imply FloatMF.
	31	(i386_optab): Split reg and mem forms of moving from segment registers
	32	so that the memory forms can ignore the 16-/32-bit operand size
	33	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	34	all non-floating-point instructions. Unite 32- and 64-bit forms of
	35	movsx, movzx, and movd. Adjust floating point operations for the above
	36	changes to the *FP macros. Add DefaultSize to floating point control
	37	insns operating on larger memory ranges. Remove left over comments
	38	hinting at certain insns being Intel-syntax ones where the ones
	39	actually meant are already gone.
	40
48c9f030 NC	41	2004-10-07 Tomer Levi <[email protected]>
	42
	43	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	44	instruction type.
	45
0dd132b6 NC	46	2004-09-30 Paul Brook <[email protected]>
	47
	48	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	49	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
	50
23794b24 MM	51	2004-09-11 Theodore A. Roth <[email protected]>
	52
	53	* avr.h: Add support for
	54	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
	55
2a309db0 AM	56	2004-09-09 Segher Boessenkool <[email protected]>
	57
	58	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
	59
b18c562e NC	60	2004-08-24 Dmitry Diky <[email protected]>
	61
	62	* msp430.h (msp430_opc): Add new instructions.
	63	(msp430_rcodes): Declare new instructions.
	64	(msp430_hcodes): Likewise..
	65
45d313cd NC	66	2004-08-13 Nick Clifton <[email protected]>
	67
	68	PR/301
	69	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	70	processors.
	71
30d1c836 ML	72	2004-08-30 Michal Ludvig <[email protected]>
	73
	74	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
	75
9a45f1c2 L	76	2004-07-22 H.J. Lu <[email protected]>
	77
	78	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
	79
543613e9 NC	80	2004-07-21 Jan Beulich <[email protected]>
	81
	82	* i386.h: Adjust instruction descriptions to better match the
	83	specification.
	84
b781e558 RE	85	2004-07-16 Richard Earnshaw <[email protected]>
	86
	87	* arm.h: Remove all old content. Replace with architecture defines
	88	from gas/config/tc-arm.c.
	89
8577e690 AS	90	2004-07-09 Andreas Schwab <[email protected]>
	91
	92	* m68k.h: Fix comment.
	93
1fe1f39c NC	94	2004-07-07 Tomer Levi <[email protected]>
	95
	96	* crx.h: New file.
	97
1d9f512f AM	98	2004-06-24 Alan Modra <[email protected]>
	99
	100	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
	101
be8c092b NC	102	2004-05-24 Peter Barada <[email protected]>
	103
	104	* m68k.h: Add 'size' to m68k_opcode.
	105
6b6e92f4 NC	106	2004-05-05 Peter Barada <[email protected]>
	107
	108	* m68k.h: Switch from ColdFire chip name to core variant.
	109
	110	2004-04-22 Peter Barada <[email protected]>
fd99574b NC	111
	112	* m68k.h: Add mcfmac/mcfemac definitions. Update operand
	113	descriptions for new EMAC cases.
	114	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	115	handle Motorola MAC syntax.
	116	Allow disassembly of ColdFire V4e object files.
	117
fdd12ef3 AM	118	2004-03-16 Alan Modra <[email protected]>
	119
	120	* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
	121
3922a64c L	122	2004-03-12 Jakub Jelinek <[email protected]>
	123
	124	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
	125
1f45d988 ML	126	2004-03-12 Michal Ludvig <[email protected]>
	127
	128	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
	129
0f10071e ML	130	2004-03-12 Michal Ludvig <[email protected]>
	131
	132	* i386.h (i386_optab): Added xstore/xcrypt insns.
	133
3255318a NC	134	2004-02-09 Anil Paranjpe <[email protected]>
	135
	136	* h8300.h (32bit ldc/stc): Add relaxing support.
	137
ca9a79a1	138	2004-01-12 Anil Paranjpe <[email protected]>
fdd12ef3	139
ca9a79a1 NC	140	* h8300.h (BITOP): Pass MEMRELAX flag.
ca9a79a1 NC	141
875a0b14 NC	142	2004-01-09 Anil Paranjpe <[email protected]>
	143
	144	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	145	except for the H8S.
252b5132	146
c9e214e5	147	For older changes see ChangeLog-9103
252b5132 RH	148	\f
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