[binutils.git] / gas / config / tc-i960.h

/* tc-i960.h - Basic 80960 instruction formats.
   Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc.
   
   This file is part of GAS, the GNU Assembler.
   
   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as
   published by the Free Software Foundation; either version 2,
   or (at your option) any later version.
   
   GAS is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public
   License along with GAS; see the file COPYING.  If not, write
   to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */

#ifndef TC_I960
#define TC_I960 1

/*
 * The 'COJ' instructions are actually COBR instructions with the 'b' in
 * the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if necessary:
 * if the displacement will not fit in 13 bits, the assembler will replace them
 * with the corresponding compare and branch instructions.
 *
 * All of the 'MEMn' instructions are the same format; the 'n' in the name
 * indicates the default index scale factor (the size of the datum operated on).
 *
 * The FBRA formats are not actually an instruction format.  They are the
 * "convenience directives" for branching on floating-point comparisons,
 * each of which generates 2 instructions (a 'bno' and one other branch).
 *
 * The CALLJ format is not actually an instruction format.  It indicates that
 * the instruction generated (a CTRL-format 'call') should have its relocation
 * specially flagged for link-time replacement with a 'bal' or 'calls' if
 * appropriate.
 */ 

/* tailor gas */
#define SYMBOLS_NEED_BACKPOINTERS
#define LOCAL_LABELS_FB
#define WANT_BITFIELDS

/* tailor the coff format */
#define OBJ_COFF_SECTION_HEADER_HAS_ALIGNMENT
#define OBJ_COFF_MAX_AUXENTRIES	(2)

/* other */
#define CTRL	0
#define COBR	1
#define COJ	2
#define REG	3
#define MEM1	4
#define MEM2	5
#define MEM4	6
#define MEM8	7
#define MEM12	8
#define MEM16	9
#define FBRA	10
#define CALLJ	11

/* Masks for the mode bits in REG format instructions */
#define M1		0x0800
#define M2		0x1000
#define M3		0x2000

/* Generate the 12-bit opcode for a REG format instruction by placing the 
 * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
 * 7-10.
 */

#define REG_OPC(opc)	((opc & 0xff0) << 20) | ((opc & 0xf) << 7)

/* Generate a template for a REG format instruction:  place the opcode bits
 * in the appropriate fields and OR in mode bits for the operands that will not
 * be used.  I.e.,
 *		set m1=1, if src1 will not be used
 *		set m2=1, if src2 will not be used
 *		set m3=1, if dst  will not be used
 *
 * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
 * The information is also useful to us because some 1-operand REG instructions
 * use the src1 field, others the dst field; and some 2-operand REG instructions
 * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
 */
#define R_0(opc)	( REG_OPC(opc) | M1 | M2 | M3 )	/* No operands      */
#define R_1(opc)	( REG_OPC(opc) | M2 | M3 )	/* 1 operand: src1  */
#define R_1D(opc)	( REG_OPC(opc) | M1 | M2 )	/* 1 operand: dst   */
#define R_2(opc)	( REG_OPC(opc) | M3 )		/* 2 ops: src1/src2 */
#define R_2D(opc)	( REG_OPC(opc) | M2 )		/* 2 ops: src1/dst  */
#define R_3(opc)	( REG_OPC(opc) )		/* 3 operands       */

/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
 *
 * Interpret names as follows:
 *	R:   global or local register only
 *	RS:  global, local, or (if target allows) special-function register only
 *	RL:  global or local register, or integer literal
 *	RSL: global, local, or (if target allows) special-function register;
 *		or integer literal
 *	F:   global, local, or floating-point register
 *	FL:  global, local, or floating-point register; or literal (including
 *		floating point)
 *
 * A number appended to a name indicates that registers must be aligned,
 * as follows:
 *	2: register number must be multiple of 2
 *	4: register number must be multiple of 4
 */

#define SFR	0x10		/* Mask for the "sfr-OK" bit */
#define LIT	0x08		/* Mask for the "literal-OK" bit */
#define FP	0x04		/* Mask for "floating-point-OK" bit */

/* This macro ors the bits together.  Note that 'align' is a mask
 * for the low 0, 1, or 2 bits of the register number, as appropriate.
 */
#define OP(align,lit,fp,sfr)	( align | lit | fp | sfr )

#define R	OP( 0, 0,   0,  0   )
#define RS	OP( 0, 0,   0,  SFR )
#define RL	OP( 0, LIT, 0,  0   )
#define RSL	OP( 0, LIT, 0,  SFR )
#define F	OP( 0, 0,   FP, 0   )
#define FL	OP( 0, LIT, FP, 0   )
#define R2	OP( 1, 0,   0,  0   )
#define RL2	OP( 1, LIT, 0,  0   )
#define F2	OP( 1, 0,   FP, 0   )
#define FL2	OP( 1, LIT, FP, 0   )
#define R4	OP( 3, 0,   0,  0   )
#define RL4	OP( 3, LIT, 0,  0   )
#define F4	OP( 3, 0,   FP, 0   )
#define FL4	OP( 3, LIT, FP, 0   )

#define M	0x7f	/* Memory operand (MEMA & MEMB format instructions) */

/* Macros to extract info from the register operand descriptor byte 'od'.
 */
#define SFR_OK(od)	(od & SFR)	/* TRUE if sfr operand allowed */
#define LIT_OK(od)	(od & LIT)	/* TRUE if literal operand allowed */
#define FP_OK(od)	(od & FP)	/* TRUE if floating-point op allowed */
#define REG_ALIGN(od,n)	((od & 0x3 & n) == 0)
/* TRUE if reg #n is properly aligned */
#define MEMOP(od)	(od == M)	/* TRUE if operand is a memory operand*/

/* Classes of 960 intructions:
 *	- each instruction falls into one class.
 *	- each target architecture supports one or more classes.
 *
 * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
 */
#define I_BASE	0x01	/* 80960 base instruction set	*/
#define I_CX	0x02	/* 80960Cx instruction		*/
#define I_DEC	0x04	/* Decimal instruction		*/
#define I_FP	0x08	/* Floating point instruction	*/
#define I_KX	0x10	/* 80960Kx instruction		*/
#define I_MIL	0x20	/* Military instruction		*/

/* MEANING OF 'n_other' in the symbol record.
 *
 * If non-zero, the 'n_other' fields indicates either a leaf procedure or
 * a system procedure, as follows:
 *
 *	1 <= n_other <= 32 :
 *		The symbol is the entry point to a system procedure.
 *		'n_value' is the address of the entry, as for any other
 *		procedure.  The system procedure number (which can be used in
 *		a 'calls' instruction) is (n_other-1).  These entries come from
 *		'.sysproc' directives.
 *
 *	n_other == N_CALLNAME
 *		the symbol is the 'call' entry point to a leaf procedure.
 *		The *next* symbol in the symbol table must be the corresponding
 *		'bal' entry point to the procedure (see following).  These
 *		entries come from '.leafproc' directives in which two different
 *		symbols are specified (the first one is represented here).
 *	
 *
 *	n_other == N_BALNAME
 *		the symbol is the 'bal' entry point to a leaf procedure.
 *		These entries result from '.leafproc' directives in which only
 *		one symbol is specified, or in which the same symbol is
 *		specified twice.
 *
 * Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry,
 * but not every N_BALNAME entry must have an N_CALLNAME entry.
 */
#define	N_CALLNAME	(-1)
#define	N_BALNAME	(-2)


/* i960 uses a custom relocation record. */

/* let obj-aout.h know */
#define CUSTOM_RELOC_FORMAT 1
/* let a.out.gnu.h know */
#define N_RELOCATION_INFO_DECLARED 1
struct relocation_info {
	int	 r_address;	/* File address of item to be relocated	*/
	unsigned
    r_index:24,/* Index of symbol on which relocation is based*/
    r_pcrel:1,	/* 1 => relocate PC-relative; else absolute
		 *	On i960, pc-relative implies 24-bit
		 *	address, absolute implies 32-bit.
		 */
    r_length:2,	/* Number of bytes to relocate:
		 *	0 => 1 byte
		 *	1 => 2 bytes
		 *	2 => 4 bytes -- only value used for i960
		 */
    r_extern:1,
    r_bsr:1,	/* Something for the GNU NS32K assembler */
    r_disp:1,	/* Something for the GNU NS32K assembler */
    r_callj:1,	/* 1 if relocation target is an i960 'callj' */
    nuthin:1;	/* Unused				*/
};

/* hacks for tracking callj's */
#if defined(OBJ_AOUT) | defined(OBJ_BOUT)

#define TC_S_IS_SYSPROC(s)	((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
#define TC_S_IS_BALNAME(s)	(S_GET_OTHER(s) == N_BALNAME)
#define TC_S_IS_CALLNAME(s)	(S_GET_OTHER(s) == N_CALLNAME)
#define TC_S_IS_BADPROC(s)	((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))

#define TC_S_SET_SYSPROC(s, p)	(S_SET_OTHER((s), (p)+1))
#define TC_S_GET_SYSPROC(s)	(S_GET_OTHER(s)-1)

#define TC_S_FORCE_TO_BALNAME(s)	(S_SET_OTHER((s), N_BALNAME))
#define TC_S_FORCE_TO_CALLNAME(s)	(S_SET_OTHER((s), N_CALLNAME))
#define TC_S_FORCE_TO_SYSPROC(s)	{;}

#elif defined(OBJ_COFF)

#define TC_S_IS_SYSPROC(s)	(S_GET_STORAGE_CLASS(s) == C_SCALL)
#define TC_S_IS_BALNAME(s)	(SF_GET_BALNAME(s))
#define TC_S_IS_CALLNAME(s)	(SF_GET_CALLNAME(s))
#define TC_S_IS_BADPROC(s)	(TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))

#define TC_S_SET_SYSPROC(s, p)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
#define TC_S_GET_SYSPROC(s)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)

#define TC_S_FORCE_TO_BALNAME(s)	(SF_SET_BALNAME(s))
#define TC_S_FORCE_TO_CALLNAME(s)	(SF_SET_CALLNAME(s))
#define TC_S_FORCE_TO_SYSPROC(s)	(S_SET_STORAGE_CLASS((s), C_SCALL))

#else /* switch on OBJ */
you lose
#endif /* witch on OBJ */
    
#ifdef __STDC__
    
    void brtab_emit(void);
void reloc_callj(); /* this is really reloc_callj(fixS *fixP) but I don't want to change header inclusion order. */
void tc_set_bal_of_call(); /* this is really tc_set_bal_of_call(symbolS *callP, symbolS *balP) */

#else /* __STDC__ */

void brtab_emit();
void reloc_callj();
void tc_set_bal_of_call();

#endif /* __STDC__ */

char *_tc_get_bal_of_call(); /* this is really symbolS *tc_get_bal_of_call(symbolS *callP). */
#define tc_get_bal_of_call(c)	((symbolS *) _tc_get_bal_of_call(c))
#endif

/*
 * Local Variables:
 * comment-column: 0
 * fill-column: 131
 * End:
 */

/* end of tc-i960.h */
Commit	Line	Data
fecd2382 RP	1	/* tc-i960.h - Basic 80960 instruction formats.
fecd2382 RP	2	Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc.
a39116f1 RP	3
	4	This file is part of GAS, the GNU Assembler.
	5
	6	GAS is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as
	8	published by the Free Software Foundation; either version 2,
	9	or (at your option) any later version.
	10
	11	GAS is distributed in the hope that it will be useful, but
	12	WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	14	the GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public
	17	License along with GAS; see the file COPYING. If not, write
	18	to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
	19
	20	#ifndef TC_I960
	21	#define TC_I960 1
fecd2382 RP	22
	23	/*
	24	* The 'COJ' instructions are actually COBR instructions with the 'b' in
	25	* the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary:
	26	* if the displacement will not fit in 13 bits, the assembler will replace them
	27	* with the corresponding compare and branch instructions.
	28	*
	29	* All of the 'MEMn' instructions are the same format; the 'n' in the name
	30	* indicates the default index scale factor (the size of the datum operated on).
	31	*
	32	* The FBRA formats are not actually an instruction format. They are the
	33	* "convenience directives" for branching on floating-point comparisons,
	34	* each of which generates 2 instructions (a 'bno' and one other branch).
	35	*
	36	* The CALLJ format is not actually an instruction format. It indicates that
	37	* the instruction generated (a CTRL-format 'call') should have its relocation
	38	* specially flagged for link-time replacement with a 'bal' or 'calls' if
	39	* appropriate.
	40	*/
	41
a39116f1	42	/* tailor gas */
fecd2382 RP	43	#define SYMBOLS_NEED_BACKPOINTERS
	44	#define LOCAL_LABELS_FB
	45	#define WANT_BITFIELDS
	46
a39116f1	47	/* tailor the coff format */
fecd2382 RP	48	#define OBJ_COFF_SECTION_HEADER_HAS_ALIGNMENT
	49	#define OBJ_COFF_MAX_AUXENTRIES (2)
	50
a39116f1	51	/* other */
fecd2382 RP	52	#define CTRL 0
	53	#define COBR 1
	54	#define COJ 2
	55	#define REG 3
	56	#define MEM1 4
	57	#define MEM2 5
	58	#define MEM4 6
	59	#define MEM8 7
	60	#define MEM12 8
	61	#define MEM16 9
	62	#define FBRA 10
	63	#define CALLJ 11
	64
	65	/* Masks for the mode bits in REG format instructions */
	66	#define M1 0x0800
	67	#define M2 0x1000
	68	#define M3 0x2000
	69
	70	/* Generate the 12-bit opcode for a REG format instruction by placing the
	71	* high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
	72	* 7-10.
	73	*/
	74
	75	#define REG_OPC(opc) ((opc & 0xff0) << 20) \| ((opc & 0xf) << 7)
	76
	77	/* Generate a template for a REG format instruction: place the opcode bits
	78	* in the appropriate fields and OR in mode bits for the operands that will not
	79	* be used. I.e.,
	80	* set m1=1, if src1 will not be used
	81	* set m2=1, if src2 will not be used
	82	* set m3=1, if dst will not be used
	83	*
	84	* Setting the "unused" mode bits to 1 speeds up instruction execution(!).
	85	* The information is also useful to us because some 1-operand REG instructions
	86	* use the src1 field, others the dst field; and some 2-operand REG instructions
	87	* use src1/src2, others src1/dst. The set mode bits enable us to distinguish.
	88	*/
	89	#define R_0(opc) ( REG_OPC(opc) \| M1 \| M2 \| M3 ) /* No operands */
	90	#define R_1(opc) ( REG_OPC(opc) \| M2 \| M3 ) /* 1 operand: src1 */
	91	#define R_1D(opc) ( REG_OPC(opc) \| M1 \| M2 ) /* 1 operand: dst */
	92	#define R_2(opc) ( REG_OPC(opc) \| M3 ) /* 2 ops: src1/src2 */
	93	#define R_2D(opc) ( REG_OPC(opc) \| M2 ) /* 2 ops: src1/dst */
	94	#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */
	95
	96	/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
	97	*
	98	* Interpret names as follows:
	99	* R: global or local register only
	100	* RS: global, local, or (if target allows) special-function register only
	101	* RL: global or local register, or integer literal
	102	* RSL: global, local, or (if target allows) special-function register;
	103	* or integer literal
	104	* F: global, local, or floating-point register
	105	* FL: global, local, or floating-point register; or literal (including
	106	* floating point)
	107	*
	108	* A number appended to a name indicates that registers must be aligned,
	109	* as follows:
	110	* 2: register number must be multiple of 2
	111	* 4: register number must be multiple of 4
	112	*/
	113
	114	#define SFR 0x10 /* Mask for the "sfr-OK" bit */
	115	#define LIT 0x08 /* Mask for the "literal-OK" bit */
116	#define FP 0x04 /* Mask for "floating-point-OK" bit */
117
118	/* This macro ors the bits together. Note that 'align' is a mask
119	* for the low 0, 1, or 2 bits of the register number, as appropriate.
120	*/
121	#define OP(align,lit,fp,sfr) ( align \| lit \| fp \| sfr )
122
123	#define R OP( 0, 0, 0, 0 )
124	#define RS OP( 0, 0, 0, SFR )
125	#define RL OP( 0, LIT, 0, 0 )
126	#define RSL OP( 0, LIT, 0, SFR )
127	#define F OP( 0, 0, FP, 0 )
128	#define FL OP( 0, LIT, FP, 0 )
129	#define R2 OP( 1, 0, 0, 0 )
130	#define RL2 OP( 1, LIT, 0, 0 )
131	#define F2 OP( 1, 0, FP, 0 )
132	#define FL2 OP( 1, LIT, FP, 0 )
133	#define R4 OP( 3, 0, 0, 0 )
134	#define RL4 OP( 3, LIT, 0, 0 )
135	#define F4 OP( 3, 0, FP, 0 )
136	#define FL4 OP( 3, LIT, FP, 0 )
137
138	#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */
139
140	/* Macros to extract info from the register operand descriptor byte 'od'.
141	*/
142	#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */
143	#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */
144	#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */
145	#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0)
a39116f1	146	/* TRUE if reg #n is properly aligned */
fecd2382 RP	147	#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/
	148
	149	/* Classes of 960 intructions:
	150	* - each instruction falls into one class.
	151	* - each target architecture supports one or more classes.
	152	*
	153	* EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass().
	154	*/
	155	#define I_BASE 0x01 /* 80960 base instruction set */
	156	#define I_CX 0x02 /* 80960Cx instruction */
	157	#define I_DEC 0x04 /* Decimal instruction */
	158	#define I_FP 0x08 /* Floating point instruction */
	159	#define I_KX 0x10 /* 80960Kx instruction */
	160	#define I_MIL 0x20 /* Military instruction */
	161
	162	/* MEANING OF 'n_other' in the symbol record.
	163	*
	164	* If non-zero, the 'n_other' fields indicates either a leaf procedure or
	165	* a system procedure, as follows:
	166	*
	167	* 1 <= n_other <= 32 :
	168	* The symbol is the entry point to a system procedure.
	169	* 'n_value' is the address of the entry, as for any other
	170	* procedure. The system procedure number (which can be used in
	171	* a 'calls' instruction) is (n_other-1). These entries come from
	172	* '.sysproc' directives.
	173	*
	174	* n_other == N_CALLNAME
	175	* the symbol is the 'call' entry point to a leaf procedure.
	176	* The next symbol in the symbol table must be the corresponding
	177	* 'bal' entry point to the procedure (see following). These
	178	* entries come from '.leafproc' directives in which two different
	179	* symbols are specified (the first one is represented here).
	180	*
	181	*
	182	* n_other == N_BALNAME
	183	* the symbol is the 'bal' entry point to a leaf procedure.
	184	* These entries result from '.leafproc' directives in which only
	185	* one symbol is specified, or in which the same symbol is
	186	* specified twice.
	187	*
	188	* Note that an N_CALLNAME entry must have a corresponding N_BALNAME entry,
	189	* but not every N_BALNAME entry must have an N_CALLNAME entry.
	190	*/
	191	#define N_CALLNAME (-1)
	192	#define N_BALNAME (-2)
	193
	194
a39116f1	195	/* i960 uses a custom relocation record. */
fecd2382	196
a39116f1	197	/* let obj-aout.h know */
fecd2382	198	#define CUSTOM_RELOC_FORMAT 1
a39116f1	199	/* let a.out.gnu.h know */
fecd2382 RP	200	#define N_RELOCATION_INFO_DECLARED 1
	201	struct relocation_info {
	202	int r_address; /* File address of item to be relocated */
	203	unsigned
a39116f1 RP	204	r_index:24,/* Index of symbol on which relocation is based*/
	205	r_pcrel:1, /* 1 => relocate PC-relative; else absolute
	206	* On i960, pc-relative implies 24-bit
	207	* address, absolute implies 32-bit.
	208	*/
	209	r_length:2, /* Number of bytes to relocate:
	210	* 0 => 1 byte
	211	* 1 => 2 bytes
	212	* 2 => 4 bytes -- only value used for i960
	213	*/
	214	r_extern:1,
	215	r_bsr:1, /* Something for the GNU NS32K assembler */
	216	r_disp:1, /* Something for the GNU NS32K assembler */
	217	r_callj:1, /* 1 if relocation target is an i960 'callj' */
	218	nuthin:1; /* Unused */
fecd2382 RP	219	};
fecd2382 RP	220
a39116f1	221	/* hacks for tracking callj's */
fecd2382 RP	222	#if defined(OBJ_AOUT) \| defined(OBJ_BOUT)
	223
	224	#define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
	225	#define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME)
	226	#define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME)
	227	#define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
	228
	229	#define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1))
	230	#define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1)
	231
	232	#define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME))
	233	#define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME))
	234	#define TC_S_FORCE_TO_SYSPROC(s) {;}
	235
	236	#elif defined(OBJ_COFF)
	237
	238	#define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL)
	239	#define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s))
	240	#define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s))
	241	#define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
	242
	243	#define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
	244	#define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
	245
	246	#define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s))
	247	#define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s))
	248	#define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL))
	249
	250	#else /* switch on OBJ */
	251	you lose
	252	#endif /* witch on OBJ */
a39116f1	253
fecd2382	254	#ifdef __STDC__
a39116f1 RP	255
a39116f1 RP	256	void brtab_emit(void);
fecd2382 RP	257	void reloc_callj(); /* this is really reloc_callj(fixS fixP) but I don't want to change header inclusion order. /
	258	void tc_set_bal_of_call(); /* this is really tc_set_bal_of_call(symbolS callP, symbolS balP) */
	259
	260	#else /* __STDC__ */
	261
	262	void brtab_emit();
	263	void reloc_callj();
	264	void tc_set_bal_of_call();
	265
	266	#endif /* __STDC__ */
	267
	268	char _tc_get_bal_of_call(); / this is really symbolS tc_get_bal_of_call(symbolS callP). */
	269	#define tc_get_bal_of_call(c) ((symbolS *) _tc_get_bal_of_call(c))
8b228fe9	270	#endif
fecd2382 RP	271
	272	/*
	273	* Local Variables:
	274	* comment-column: 0
	275	* fill-column: 131
	276	* End:
	277	*/
	278
8b228fe9	279	/* end of tc-i960.h */