projects / binutils.git / blame
| Commit | Line | Data |
|---|---|---|
| 252b5132 | 1 | /* ppc-opc.c -- PowerPC opcode list |
| 6ba045b1 | 2 | Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001 |
| 060d22b0 | 3 | Free Software Foundation, Inc. |
| 252b5132 RH |
4 | Written by Ian Lance Taylor, Cygnus Support |
| 5 | ||
| 6 | This file is part of GDB, GAS, and the GNU binutils. | |
| 7 | ||
| 8 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
| 9 | them and/or modify them under the terms of the GNU General Public | |
| 10 | License as published by the Free Software Foundation; either version | |
| 11 | 2, or (at your option) any later version. | |
| 12 | ||
| 13 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
| 14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
| 15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
| 16 | the GNU General Public License for more details. | |
| 17 | ||
| 18 | You should have received a copy of the GNU General Public License | |
| 19 | along with this file; see the file COPYING. If not, write to the Free | |
| 20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
| 21 | 02111-1307, USA. */ | |
| 22 | ||
| 23 | #include <stdio.h> | |
| 0d8dfecf | 24 | #include "sysdep.h" |
| 252b5132 RH |
25 | #include "opcode/ppc.h" |
| 26 | #include "opintl.h" | |
| 27 | ||
| 28 | /* This file holds the PowerPC opcode table. The opcode table | |
| 29 | includes almost all of the extended instruction mnemonics. This | |
| 30 | permits the disassembler to use them, and simplifies the assembler | |
| 31 | logic, at the cost of increasing the table size. The table is | |
| 32 | strictly constant data, so the compiler should be able to put it in | |
| 33 | the .text section. | |
| 34 | ||
| 35 | This file also holds the operand table. All knowledge about | |
| 36 | inserting operands into instructions and vice-versa is kept in this | |
| 37 | file. */ | |
| 38 | \f | |
| 39 | /* Local insertion and extraction functions. */ | |
| 40 | ||
| 41 | static unsigned long insert_bat PARAMS ((unsigned long, long, const char **)); | |
| 42 | static long extract_bat PARAMS ((unsigned long, int *)); | |
| 43 | static unsigned long insert_bba PARAMS ((unsigned long, long, const char **)); | |
| 44 | static long extract_bba PARAMS ((unsigned long, int *)); | |
| 45 | static unsigned long insert_bd PARAMS ((unsigned long, long, const char **)); | |
| 46 | static long extract_bd PARAMS ((unsigned long, int *)); | |
| 47 | static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **)); | |
| 48 | static long extract_bdm PARAMS ((unsigned long, int *)); | |
| 49 | static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **)); | |
| 50 | static long extract_bdp PARAMS ((unsigned long, int *)); | |
| 51 | static int valid_bo PARAMS ((long)); | |
| 52 | static unsigned long insert_bo PARAMS ((unsigned long, long, const char **)); | |
| 53 | static long extract_bo PARAMS ((unsigned long, int *)); | |
| 54 | static unsigned long insert_boe PARAMS ((unsigned long, long, const char **)); | |
| 55 | static long extract_boe PARAMS ((unsigned long, int *)); | |
| 56 | static unsigned long insert_ds PARAMS ((unsigned long, long, const char **)); | |
| 57 | static long extract_ds PARAMS ((unsigned long, int *)); | |
| 58 | static unsigned long insert_li PARAMS ((unsigned long, long, const char **)); | |
| 59 | static long extract_li PARAMS ((unsigned long, int *)); | |
| 60 | static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **)); | |
| 61 | static long extract_mbe PARAMS ((unsigned long, int *)); | |
| 62 | static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **)); | |
| 63 | static long extract_mb6 PARAMS ((unsigned long, int *)); | |
| 64 | static unsigned long insert_nb PARAMS ((unsigned long, long, const char **)); | |
| 65 | static long extract_nb PARAMS ((unsigned long, int *)); | |
| 66 | static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **)); | |
| 67 | static long extract_nsi PARAMS ((unsigned long, int *)); | |
| 68 | static unsigned long insert_ral PARAMS ((unsigned long, long, const char **)); | |
| 69 | static unsigned long insert_ram PARAMS ((unsigned long, long, const char **)); | |
| 70 | static unsigned long insert_ras PARAMS ((unsigned long, long, const char **)); | |
| 71 | static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **)); | |
| 72 | static long extract_rbs PARAMS ((unsigned long, int *)); | |
| 73 | static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **)); | |
| 74 | static long extract_sh6 PARAMS ((unsigned long, int *)); | |
| 75 | static unsigned long insert_spr PARAMS ((unsigned long, long, const char **)); | |
| 76 | static long extract_spr PARAMS ((unsigned long, int *)); | |
| 77 | static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **)); | |
| 78 | static long extract_tbr PARAMS ((unsigned long, int *)); | |
| 79 | \f | |
| 80 | /* The operands table. | |
| 81 | ||
| 82 | The fields are bits, shift, insert, extract, flags. | |
| 83 | ||
| 84 | We used to put parens around the various additions, like the one | |
| 85 | for BA just below. However, that caused trouble with feeble | |
| 86 | compilers with a limit on depth of a parenthesized expression, like | |
| 87 | (reportedly) the compiler in Microsoft Developer Studio 5. So we | |
| 88 | omit the parens, since the macros are never used in a context where | |
| 89 | the addition will be ambiguous. */ | |
| 90 | ||
| 91 | const struct powerpc_operand powerpc_operands[] = | |
| 92 | { | |
| 93 | /* The zero index is used to indicate the end of the list of | |
| 94 | operands. */ | |
| 95 | #define UNUSED 0 | |
| 11b37b7b | 96 | { 0, 0, 0, 0, 0 }, |
| 252b5132 RH |
97 | |
| 98 | /* The BA field in an XL form instruction. */ | |
| 99 | #define BA UNUSED + 1 | |
| 100 | #define BA_MASK (0x1f << 16) | |
| 11b37b7b | 101 | { 5, 16, 0, 0, PPC_OPERAND_CR }, |
| 252b5132 RH |
102 | |
| 103 | /* The BA field in an XL form instruction when it must be the same | |
| 104 | as the BT field in the same instruction. */ | |
| 105 | #define BAT BA + 1 | |
| 11b37b7b | 106 | { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, |
| 252b5132 RH |
107 | |
| 108 | /* The BB field in an XL form instruction. */ | |
| 109 | #define BB BAT + 1 | |
| 110 | #define BB_MASK (0x1f << 11) | |
| 11b37b7b | 111 | { 5, 11, 0, 0, PPC_OPERAND_CR }, |
| 252b5132 RH |
112 | |
| 113 | /* The BB field in an XL form instruction when it must be the same | |
| 114 | as the BA field in the same instruction. */ | |
| 115 | #define BBA BB + 1 | |
| 11b37b7b | 116 | { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, |
| 252b5132 RH |
117 | |
| 118 | /* The BD field in a B form instruction. The lower two bits are | |
| 119 | forced to zero. */ | |
| 120 | #define BD BBA + 1 | |
| 11b37b7b | 121 | { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| 252b5132 RH |
122 | |
| 123 | /* The BD field in a B form instruction when absolute addressing is | |
| 124 | used. */ | |
| 125 | #define BDA BD + 1 | |
| 11b37b7b | 126 | { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
| 252b5132 RH |
127 | |
| 128 | /* The BD field in a B form instruction when the - modifier is used. | |
| 129 | This sets the y bit of the BO field appropriately. */ | |
| 130 | #define BDM BDA + 1 | |
| 11b37b7b AM |
131 | { 16, 0, insert_bdm, extract_bdm, |
| 132 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
| 252b5132 RH |
133 | |
| 134 | /* The BD field in a B form instruction when the - modifier is used | |
| 135 | and absolute address is used. */ | |
| 136 | #define BDMA BDM + 1 | |
| 11b37b7b AM |
137 | { 16, 0, insert_bdm, extract_bdm, |
| 138 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
| 252b5132 RH |
139 | |
| 140 | /* The BD field in a B form instruction when the + modifier is used. | |
| 141 | This sets the y bit of the BO field appropriately. */ | |
| 142 | #define BDP BDMA + 1 | |
| 11b37b7b AM |
143 | { 16, 0, insert_bdp, extract_bdp, |
| 144 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, | |
| 252b5132 RH |
145 | |
| 146 | /* The BD field in a B form instruction when the + modifier is used | |
| 147 | and absolute addressing is used. */ | |
| 148 | #define BDPA BDP + 1 | |
| 11b37b7b AM |
149 | { 16, 0, insert_bdp, extract_bdp, |
| 150 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, | |
| 252b5132 RH |
151 | |
| 152 | /* The BF field in an X or XL form instruction. */ | |
| 153 | #define BF BDPA + 1 | |
| 11b37b7b | 154 | { 3, 23, 0, 0, PPC_OPERAND_CR }, |
| 252b5132 RH |
155 | |
| 156 | /* An optional BF field. This is used for comparison instructions, | |
| 157 | in which an omitted BF field is taken as zero. */ | |
| 158 | #define OBF BF + 1 | |
| 11b37b7b | 159 | { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
| 252b5132 RH |
160 | |
| 161 | /* The BFA field in an X or XL form instruction. */ | |
| 162 | #define BFA OBF + 1 | |
| 11b37b7b | 163 | { 3, 18, 0, 0, PPC_OPERAND_CR }, |
| 252b5132 RH |
164 | |
| 165 | /* The BI field in a B form or XL form instruction. */ | |
| 166 | #define BI BFA + 1 | |
| 167 | #define BI_MASK (0x1f << 16) | |
| 11b37b7b | 168 | { 5, 16, 0, 0, PPC_OPERAND_CR }, |
| 252b5132 RH |
169 | |
| 170 | /* The BO field in a B form instruction. Certain values are | |
| 171 | illegal. */ | |
| 172 | #define BO BI + 1 | |
| 173 | #define BO_MASK (0x1f << 21) | |
| 11b37b7b | 174 | { 5, 21, insert_bo, extract_bo, 0 }, |
| 252b5132 RH |
175 | |
| 176 | /* The BO field in a B form instruction when the + or - modifier is | |
| 177 | used. This is like the BO field, but it must be even. */ | |
| 178 | #define BOE BO + 1 | |
| 11b37b7b | 179 | { 5, 21, insert_boe, extract_boe, 0 }, |
| 252b5132 RH |
180 | |
| 181 | /* The BT field in an X or XL form instruction. */ | |
| 182 | #define BT BOE + 1 | |
| 11b37b7b | 183 | { 5, 21, 0, 0, PPC_OPERAND_CR }, |
| 252b5132 RH |
184 | |
| 185 | /* The condition register number portion of the BI field in a B form | |
| 186 | or XL form instruction. This is used for the extended | |
| 187 | conditional branch mnemonics, which set the lower two bits of the | |
| 188 | BI field. This field is optional. */ | |
| 189 | #define CR BT + 1 | |
| 11b37b7b | 190 | { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
| 252b5132 RH |
191 | |
| 192 | /* The D field in a D form instruction. This is a displacement off | |
| 193 | a register, and implies that the next operand is a register in | |
| 194 | parentheses. */ | |
| 195 | #define D CR + 1 | |
| 11b37b7b | 196 | { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
| 252b5132 RH |
197 | |
| 198 | /* The DS field in a DS form instruction. This is like D, but the | |
| 199 | lower two bits are forced to zero. */ | |
| 200 | #define DS D + 1 | |
| 6ba045b1 AM |
201 | { 16, 0, insert_ds, extract_ds, |
| 202 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, | |
| 252b5132 RH |
203 | |
| 204 | /* The E field in a wrteei instruction. */ | |
| 205 | #define E DS + 1 | |
| 11b37b7b | 206 | { 1, 15, 0, 0, 0 }, |
| 252b5132 RH |
207 | |
| 208 | /* The FL1 field in a POWER SC form instruction. */ | |
| 209 | #define FL1 E + 1 | |
| 11b37b7b | 210 | { 4, 12, 0, 0, 0 }, |
| 252b5132 RH |
211 | |
| 212 | /* The FL2 field in a POWER SC form instruction. */ | |
| 213 | #define FL2 FL1 + 1 | |
| 11b37b7b | 214 | { 3, 2, 0, 0, 0 }, |
| 252b5132 RH |
215 | |
| 216 | /* The FLM field in an XFL form instruction. */ | |
| 217 | #define FLM FL2 + 1 | |
| 11b37b7b | 218 | { 8, 17, 0, 0, 0 }, |
| 252b5132 RH |
219 | |
| 220 | /* The FRA field in an X or A form instruction. */ | |
| 221 | #define FRA FLM + 1 | |
| 222 | #define FRA_MASK (0x1f << 16) | |
| 11b37b7b | 223 | { 5, 16, 0, 0, PPC_OPERAND_FPR }, |
| 252b5132 RH |
224 | |
| 225 | /* The FRB field in an X or A form instruction. */ | |
| 226 | #define FRB FRA + 1 | |
| 227 | #define FRB_MASK (0x1f << 11) | |
| 11b37b7b | 228 | { 5, 11, 0, 0, PPC_OPERAND_FPR }, |
| 252b5132 RH |
229 | |
| 230 | /* The FRC field in an A form instruction. */ | |
| 231 | #define FRC FRB + 1 | |
| 232 | #define FRC_MASK (0x1f << 6) | |
| 11b37b7b | 233 | { 5, 6, 0, 0, PPC_OPERAND_FPR }, |
| 252b5132 RH |
234 | |
| 235 | /* The FRS field in an X form instruction or the FRT field in a D, X | |
| 236 | or A form instruction. */ | |
| 237 | #define FRS FRC + 1 | |
| 238 | #define FRT FRS | |
| 11b37b7b | 239 | { 5, 21, 0, 0, PPC_OPERAND_FPR }, |
| 252b5132 RH |
240 | |
| 241 | /* The FXM field in an XFX instruction. */ | |
| 242 | #define FXM FRS + 1 | |
| 243 | #define FXM_MASK (0xff << 12) | |
| 11b37b7b | 244 | { 8, 12, 0, 0, 0 }, |
| 252b5132 RH |
245 | |
| 246 | /* The L field in a D or X form instruction. */ | |
| 247 | #define L FXM + 1 | |
| 11b37b7b | 248 | { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, |
| 252b5132 RH |
249 | |
| 250 | /* The LEV field in a POWER SC form instruction. */ | |
| 251 | #define LEV L + 1 | |
| 11b37b7b | 252 | { 7, 5, 0, 0, 0 }, |
| 252b5132 RH |
253 | |
| 254 | /* The LI field in an I form instruction. The lower two bits are | |
| 255 | forced to zero. */ | |
| 256 | #define LI LEV + 1 | |
| 11b37b7b | 257 | { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| 252b5132 RH |
258 | |
| 259 | /* The LI field in an I form instruction when used as an absolute | |
| 260 | address. */ | |
| 261 | #define LIA LI + 1 | |
| 11b37b7b | 262 | { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
| 252b5132 | 263 | |
| 6ba045b1 AM |
264 | /* The LS field in an X (sync) form instruction. */ |
| 265 | #define LS LIA + 1 | |
| 266 | { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL }, | |
| 267 | ||
| 252b5132 | 268 | /* The MB field in an M form instruction. */ |
| 6ba045b1 | 269 | #define MB LS + 1 |
| 252b5132 | 270 | #define MB_MASK (0x1f << 6) |
| 11b37b7b | 271 | { 5, 6, 0, 0, 0 }, |
| 252b5132 RH |
272 | |
| 273 | /* The ME field in an M form instruction. */ | |
| 274 | #define ME MB + 1 | |
| 275 | #define ME_MASK (0x1f << 1) | |
| 11b37b7b | 276 | { 5, 1, 0, 0, 0 }, |
| 252b5132 RH |
277 | |
| 278 | /* The MB and ME fields in an M form instruction expressed a single | |
| 279 | operand which is a bitmask indicating which bits to select. This | |
| 280 | is a two operand form using PPC_OPERAND_NEXT. See the | |
| 281 | description in opcode/ppc.h for what this means. */ | |
| 282 | #define MBE ME + 1 | |
| 11b37b7b AM |
283 | { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
| 284 | { 32, 0, insert_mbe, extract_mbe, 0 }, | |
| 252b5132 RH |
285 | |
| 286 | /* The MB or ME field in an MD or MDS form instruction. The high | |
| 287 | bit is wrapped to the low end. */ | |
| 288 | #define MB6 MBE + 2 | |
| 289 | #define ME6 MB6 | |
| 290 | #define MB6_MASK (0x3f << 5) | |
| 11b37b7b | 291 | { 6, 5, insert_mb6, extract_mb6, 0 }, |
| 252b5132 RH |
292 | |
| 293 | /* The NB field in an X form instruction. The value 32 is stored as | |
| 294 | 0. */ | |
| 295 | #define NB MB6 + 1 | |
| 11b37b7b | 296 | { 6, 11, insert_nb, extract_nb, 0 }, |
| 252b5132 RH |
297 | |
| 298 | /* The NSI field in a D form instruction. This is the same as the | |
| 299 | SI field, only negated. */ | |
| 300 | #define NSI NB + 1 | |
| 301 | { 16, 0, insert_nsi, extract_nsi, | |
| 11b37b7b | 302 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
| 252b5132 RH |
303 | |
| 304 | /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ | |
| 305 | #define RA NSI + 1 | |
| 306 | #define RA_MASK (0x1f << 16) | |
| 11b37b7b | 307 | { 5, 16, 0, 0, PPC_OPERAND_GPR }, |
| 252b5132 RH |
308 | |
| 309 | /* The RA field in a D or X form instruction which is an updating | |
| 310 | load, which means that the RA field may not be zero and may not | |
| 311 | equal the RT field. */ | |
| 312 | #define RAL RA + 1 | |
| 11b37b7b | 313 | { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, |
| 252b5132 RH |
314 | |
| 315 | /* The RA field in an lmw instruction, which has special value | |
| 316 | restrictions. */ | |
| 317 | #define RAM RAL + 1 | |
| 11b37b7b | 318 | { 5, 16, insert_ram, 0, PPC_OPERAND_GPR }, |
| 252b5132 RH |
319 | |
| 320 | /* The RA field in a D or X form instruction which is an updating | |
| 321 | store or an updating floating point load, which means that the RA | |
| 322 | field may not be zero. */ | |
| 323 | #define RAS RAM + 1 | |
| 11b37b7b | 324 | { 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, |
| 252b5132 RH |
325 | |
| 326 | /* The RB field in an X, XO, M, or MDS form instruction. */ | |
| 327 | #define RB RAS + 1 | |
| 328 | #define RB_MASK (0x1f << 11) | |
| 11b37b7b | 329 | { 5, 11, 0, 0, PPC_OPERAND_GPR }, |
| 252b5132 RH |
330 | |
| 331 | /* The RB field in an X form instruction when it must be the same as | |
| 332 | the RS field in the instruction. This is used for extended | |
| 333 | mnemonics like mr. */ | |
| 334 | #define RBS RB + 1 | |
| 11b37b7b | 335 | { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, |
| 252b5132 RH |
336 | |
| 337 | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form | |
| 338 | instruction or the RT field in a D, DS, X, XFX or XO form | |
| 339 | instruction. */ | |
| 340 | #define RS RBS + 1 | |
| 341 | #define RT RS | |
| 342 | #define RT_MASK (0x1f << 21) | |
| 11b37b7b | 343 | { 5, 21, 0, 0, PPC_OPERAND_GPR }, |
| 252b5132 RH |
344 | |
| 345 | /* The SH field in an X or M form instruction. */ | |
| 346 | #define SH RS + 1 | |
| 347 | #define SH_MASK (0x1f << 11) | |
| 11b37b7b | 348 | { 5, 11, 0, 0, 0 }, |
| 252b5132 RH |
349 | |
| 350 | /* The SH field in an MD form instruction. This is split. */ | |
| 351 | #define SH6 SH + 1 | |
| 352 | #define SH6_MASK ((0x1f << 11) | (1 << 1)) | |
| 11b37b7b | 353 | { 6, 1, insert_sh6, extract_sh6, 0 }, |
| 252b5132 RH |
354 | |
| 355 | /* The SI field in a D form instruction. */ | |
| 356 | #define SI SH6 + 1 | |
| 11b37b7b | 357 | { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, |
| 252b5132 RH |
358 | |
| 359 | /* The SI field in a D form instruction when we accept a wide range | |
| 360 | of positive values. */ | |
| 361 | #define SISIGNOPT SI + 1 | |
| 11b37b7b | 362 | { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
| 252b5132 RH |
363 | |
| 364 | /* The SPR field in an XFX form instruction. This is flipped--the | |
| 365 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
| 366 | #define SPR SISIGNOPT + 1 | |
| 367 | #define SPR_MASK (0x3ff << 11) | |
| 11b37b7b | 368 | { 10, 11, insert_spr, extract_spr, 0 }, |
| 252b5132 RH |
369 | |
| 370 | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ | |
| 371 | #define SPRBAT SPR + 1 | |
| 372 | #define SPRBAT_MASK (0x3 << 17) | |
| 11b37b7b | 373 | { 2, 17, 0, 0, 0 }, |
| 252b5132 RH |
374 | |
| 375 | /* The SPRG register number in an XFX form m[ft]sprg instruction. */ | |
| 376 | #define SPRG SPRBAT + 1 | |
| 377 | #define SPRG_MASK (0x3 << 16) | |
| 11b37b7b | 378 | { 2, 16, 0, 0, 0 }, |
| 252b5132 RH |
379 | |
| 380 | /* The SR field in an X form instruction. */ | |
| 381 | #define SR SPRG + 1 | |
| 11b37b7b | 382 | { 4, 16, 0, 0, 0 }, |
| 252b5132 RH |
383 | |
| 384 | /* The SV field in a POWER SC form instruction. */ | |
| 385 | #define SV SR + 1 | |
| 11b37b7b | 386 | { 14, 2, 0, 0, 0 }, |
| 252b5132 RH |
387 | |
| 388 | /* The TBR field in an XFX form instruction. This is like the SPR | |
| 389 | field, but it is optional. */ | |
| 390 | #define TBR SV + 1 | |
| 11b37b7b | 391 | { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, |
| 252b5132 RH |
392 | |
| 393 | /* The TO field in a D or X form instruction. */ | |
| 394 | #define TO TBR + 1 | |
| 395 | #define TO_MASK (0x1f << 21) | |
| 11b37b7b | 396 | { 5, 21, 0, 0, 0 }, |
| 252b5132 RH |
397 | |
| 398 | /* The U field in an X form instruction. */ | |
| 399 | #define U TO + 1 | |
| 11b37b7b | 400 | { 4, 12, 0, 0, 0 }, |
| 252b5132 RH |
401 | |
| 402 | /* The UI field in a D form instruction. */ | |
| 403 | #define UI U + 1 | |
| 11b37b7b | 404 | { 16, 0, 0, 0, 0 }, |
| 786e2c0f C |
405 | |
| 406 | /* The VA field in a VA, VX or VXR form instruction. */ | |
| 407 | #define VA UI + 1 | |
| 408 | #define VA_MASK (0x1f << 16) | |
| 6ba045b1 | 409 | { 5, 16, 0, 0, PPC_OPERAND_VR }, |
| 786e2c0f C |
410 | |
| 411 | /* The VB field in a VA, VX or VXR form instruction. */ | |
| 412 | #define VB VA + 1 | |
| 413 | #define VB_MASK (0x1f << 11) | |
| 6ba045b1 | 414 | { 5, 11, 0, 0, PPC_OPERAND_VR }, |
| 786e2c0f C |
415 | |
| 416 | /* The VC field in a VA form instruction. */ | |
| 417 | #define VC VB + 1 | |
| 418 | #define VC_MASK (0x1f << 6) | |
| 6ba045b1 | 419 | { 5, 6, 0, 0, PPC_OPERAND_VR }, |
| 786e2c0f C |
420 | |
| 421 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */ | |
| 422 | #define VD VC + 1 | |
| 423 | #define VS VD | |
| 424 | #define VD_MASK (0x1f << 21) | |
| 6ba045b1 | 425 | { 5, 21, 0, 0, PPC_OPERAND_VR }, |
| 786e2c0f C |
426 | |
| 427 | /* The SIMM field in a VX form instruction. */ | |
| 428 | #define SIMM VD + 1 | |
| 11b37b7b | 429 | { 5, 16, 0, 0, PPC_OPERAND_SIGNED}, |
| 786e2c0f C |
430 | |
| 431 | /* The UIMM field in a VX form instruction. */ | |
| 432 | #define UIMM SIMM + 1 | |
| 11b37b7b | 433 | { 5, 16, 0, 0, 0 }, |
| 786e2c0f C |
434 | |
| 435 | /* The SHB field in a VA form instruction. */ | |
| 436 | #define SHB UIMM + 1 | |
| 11b37b7b | 437 | { 4, 6, 0, 0, 0 }, |
| 252b5132 RH |
438 | }; |
| 439 | ||
| 440 | /* The functions used to insert and extract complicated operands. */ | |
| 441 | ||
| 442 | /* The BA field in an XL form instruction when it must be the same as | |
| 443 | the BT field in the same instruction. This operand is marked FAKE. | |
| 444 | The insertion function just copies the BT field into the BA field, | |
| 445 | and the extraction function just checks that the fields are the | |
| 446 | same. */ | |
| 447 | ||
| 448 | /*ARGSUSED*/ | |
| 449 | static unsigned long | |
| 450 | insert_bat (insn, value, errmsg) | |
| 451 | unsigned long insn; | |
| 9aaaa291 ILT |
452 | long value ATTRIBUTE_UNUSED; |
| 453 | const char **errmsg ATTRIBUTE_UNUSED; | |
| 252b5132 RH |
454 | { |
| 455 | return insn | (((insn >> 21) & 0x1f) << 16); | |
| 456 | } | |
| 457 | ||
| 458 | static long | |
| 459 | extract_bat (insn, invalid) | |
| 460 | unsigned long insn; | |
| 461 | int *invalid; | |
| 462 | { | |
| 463 | if (invalid != (int *) NULL | |
| 464 | && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) | |
| 465 | *invalid = 1; | |
| 466 | return 0; | |
| 467 | } | |
| 468 | ||
| 469 | /* The BB field in an XL form instruction when it must be the same as | |
| 470 | the BA field in the same instruction. This operand is marked FAKE. | |
| 471 | The insertion function just copies the BA field into the BB field, | |
| 472 | and the extraction function just checks that the fields are the | |
| 473 | same. */ | |
| 474 | ||
| 475 | /*ARGSUSED*/ | |
| 476 | static unsigned long | |
| 477 | insert_bba (insn, value, errmsg) | |
| 478 | unsigned long insn; | |
| 9aaaa291 ILT |
479 | long value ATTRIBUTE_UNUSED; |
| 480 | const char **errmsg ATTRIBUTE_UNUSED; | |
| 252b5132 RH |
481 | { |
| 482 | return insn | (((insn >> 16) & 0x1f) << 11); | |
| 483 | } | |
| 484 | ||
| 485 | static long | |
| 486 | extract_bba (insn, invalid) | |
| 487 | unsigned long insn; | |
| 488 | int *invalid; | |
| 489 | { | |
| 490 | if (invalid != (int *) NULL | |
| 491 | && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) | |
| 492 | *invalid = 1; | |
| 493 | return 0; | |
| 494 | } | |
| 495 | ||
| 496 | /* The BD field in a B form instruction. The lower two bits are | |
| 497 | forced to zero. */ | |
| 498 | ||
| 499 | /*ARGSUSED*/ | |
| 500 | static unsigned long | |
| 501 | insert_bd (insn, value, errmsg) | |
| 502 | unsigned long insn; | |
| 503 | long value; | |
| 9aaaa291 | 504 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
505 | { |
| 506 | return insn | (value & 0xfffc); | |
| 507 | } | |
| 508 | ||
| 509 | /*ARGSUSED*/ | |
| 510 | static long | |
| 511 | extract_bd (insn, invalid) | |
| 512 | unsigned long insn; | |
| 9aaaa291 | 513 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
514 | { |
| 515 | if ((insn & 0x8000) != 0) | |
| 516 | return (insn & 0xfffc) - 0x10000; | |
| 517 | else | |
| 518 | return insn & 0xfffc; | |
| 519 | } | |
| 520 | ||
| 521 | /* The BD field in a B form instruction when the - modifier is used. | |
| 522 | This modifier means that the branch is not expected to be taken. | |
| 523 | We must set the y bit of the BO field to 1 if the offset is | |
| 524 | negative. When extracting, we require that the y bit be 1 and that | |
| 525 | the offset be positive, since if the y bit is 0 we just want to | |
| 526 | print the normal form of the instruction. */ | |
| 527 | ||
| 528 | /*ARGSUSED*/ | |
| 529 | static unsigned long | |
| 530 | insert_bdm (insn, value, errmsg) | |
| 531 | unsigned long insn; | |
| 532 | long value; | |
| 9aaaa291 | 533 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
534 | { |
| 535 | if ((value & 0x8000) != 0) | |
| 536 | insn |= 1 << 21; | |
| 537 | return insn | (value & 0xfffc); | |
| 538 | } | |
| 539 | ||
| 540 | static long | |
| 541 | extract_bdm (insn, invalid) | |
| 542 | unsigned long insn; | |
| 543 | int *invalid; | |
| 544 | { | |
| 545 | if (invalid != (int *) NULL | |
| 546 | && ((insn & (1 << 21)) == 0 | |
| 547 | || (insn & (1 << 15)) == 0)) | |
| 548 | *invalid = 1; | |
| 549 | if ((insn & 0x8000) != 0) | |
| 550 | return (insn & 0xfffc) - 0x10000; | |
| 551 | else | |
| 552 | return insn & 0xfffc; | |
| 553 | } | |
| 554 | ||
| 555 | /* The BD field in a B form instruction when the + modifier is used. | |
| 556 | This is like BDM, above, except that the branch is expected to be | |
| 557 | taken. */ | |
| 558 | ||
| 559 | /*ARGSUSED*/ | |
| 560 | static unsigned long | |
| 561 | insert_bdp (insn, value, errmsg) | |
| 562 | unsigned long insn; | |
| 563 | long value; | |
| 9aaaa291 | 564 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
565 | { |
| 566 | if ((value & 0x8000) == 0) | |
| 567 | insn |= 1 << 21; | |
| 568 | return insn | (value & 0xfffc); | |
| 569 | } | |
| 570 | ||
| 571 | static long | |
| 572 | extract_bdp (insn, invalid) | |
| 573 | unsigned long insn; | |
| 574 | int *invalid; | |
| 575 | { | |
| 576 | if (invalid != (int *) NULL | |
| 577 | && ((insn & (1 << 21)) == 0 | |
| 578 | || (insn & (1 << 15)) != 0)) | |
| 579 | *invalid = 1; | |
| 580 | if ((insn & 0x8000) != 0) | |
| 581 | return (insn & 0xfffc) - 0x10000; | |
| 582 | else | |
| 583 | return insn & 0xfffc; | |
| 584 | } | |
| 585 | ||
| 586 | /* Check for legal values of a BO field. */ | |
| 587 | ||
| 588 | static int | |
| 589 | valid_bo (value) | |
| 590 | long value; | |
| 591 | { | |
| 592 | /* Certain encodings have bits that are required to be zero. These | |
| 593 | are (z must be zero, y may be anything): | |
| 594 | 001zy | |
| 595 | 011zy | |
| 596 | 1z00y | |
| 597 | 1z01y | |
| 598 | 1z1zz | |
| 599 | */ | |
| 600 | switch (value & 0x14) | |
| 601 | { | |
| 602 | default: | |
| 603 | case 0: | |
| 604 | return 1; | |
| 605 | case 0x4: | |
| 606 | return (value & 0x2) == 0; | |
| 607 | case 0x10: | |
| 608 | return (value & 0x8) == 0; | |
| 609 | case 0x14: | |
| 610 | return value == 0x14; | |
| 611 | } | |
| 612 | } | |
| 613 | ||
| 614 | /* The BO field in a B form instruction. Warn about attempts to set | |
| 615 | the field to an illegal value. */ | |
| 616 | ||
| 617 | static unsigned long | |
| 618 | insert_bo (insn, value, errmsg) | |
| 619 | unsigned long insn; | |
| 620 | long value; | |
| 621 | const char **errmsg; | |
| 622 | { | |
| 623 | if (errmsg != (const char **) NULL | |
| 624 | && ! valid_bo (value)) | |
| 625 | *errmsg = _("invalid conditional option"); | |
| 626 | return insn | ((value & 0x1f) << 21); | |
| 627 | } | |
| 628 | ||
| 629 | static long | |
| 630 | extract_bo (insn, invalid) | |
| 631 | unsigned long insn; | |
| 632 | int *invalid; | |
| 633 | { | |
| 634 | long value; | |
| 635 | ||
| 636 | value = (insn >> 21) & 0x1f; | |
| 637 | if (invalid != (int *) NULL | |
| 638 | && ! valid_bo (value)) | |
| 639 | *invalid = 1; | |
| 640 | return value; | |
| 641 | } | |
| 642 | ||
| 643 | /* The BO field in a B form instruction when the + or - modifier is | |
| 644 | used. This is like the BO field, but it must be even. When | |
| 645 | extracting it, we force it to be even. */ | |
| 646 | ||
| 647 | static unsigned long | |
| 648 | insert_boe (insn, value, errmsg) | |
| 649 | unsigned long insn; | |
| 650 | long value; | |
| 651 | const char **errmsg; | |
| 652 | { | |
| 653 | if (errmsg != (const char **) NULL) | |
| 654 | { | |
| 655 | if (! valid_bo (value)) | |
| 656 | *errmsg = _("invalid conditional option"); | |
| 657 | else if ((value & 1) != 0) | |
| 658 | *errmsg = _("attempt to set y bit when using + or - modifier"); | |
| 659 | } | |
| 660 | return insn | ((value & 0x1f) << 21); | |
| 661 | } | |
| 662 | ||
| 663 | static long | |
| 664 | extract_boe (insn, invalid) | |
| 665 | unsigned long insn; | |
| 666 | int *invalid; | |
| 667 | { | |
| 668 | long value; | |
| 669 | ||
| 670 | value = (insn >> 21) & 0x1f; | |
| 671 | if (invalid != (int *) NULL | |
| 672 | && ! valid_bo (value)) | |
| 673 | *invalid = 1; | |
| 674 | return value & 0x1e; | |
| 675 | } | |
| 676 | ||
| 677 | /* The DS field in a DS form instruction. This is like D, but the | |
| 678 | lower two bits are forced to zero. */ | |
| 679 | ||
| 680 | /*ARGSUSED*/ | |
| 681 | static unsigned long | |
| 682 | insert_ds (insn, value, errmsg) | |
| 683 | unsigned long insn; | |
| 684 | long value; | |
| 9aaaa291 | 685 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 | 686 | { |
| 6ba045b1 AM |
687 | if ((value & 3) != 0 && errmsg != NULL) |
| 688 | *errmsg = _("offset not a multiple of 4"); | |
| 252b5132 RH |
689 | return insn | (value & 0xfffc); |
| 690 | } | |
| 691 | ||
| 692 | /*ARGSUSED*/ | |
| 693 | static long | |
| 694 | extract_ds (insn, invalid) | |
| 695 | unsigned long insn; | |
| 9aaaa291 | 696 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
697 | { |
| 698 | if ((insn & 0x8000) != 0) | |
| 699 | return (insn & 0xfffc) - 0x10000; | |
| 700 | else | |
| 701 | return insn & 0xfffc; | |
| 702 | } | |
| 703 | ||
| 704 | /* The LI field in an I form instruction. The lower two bits are | |
| 705 | forced to zero. */ | |
| 706 | ||
| 707 | /*ARGSUSED*/ | |
| 708 | static unsigned long | |
| 709 | insert_li (insn, value, errmsg) | |
| 710 | unsigned long insn; | |
| 711 | long value; | |
| 712 | const char **errmsg; | |
| 713 | { | |
| 714 | if ((value & 3) != 0 && errmsg != (const char **) NULL) | |
| 715 | *errmsg = _("ignoring least significant bits in branch offset"); | |
| 716 | return insn | (value & 0x3fffffc); | |
| 717 | } | |
| 718 | ||
| 719 | /*ARGSUSED*/ | |
| 720 | static long | |
| 721 | extract_li (insn, invalid) | |
| 722 | unsigned long insn; | |
| 9aaaa291 | 723 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
724 | { |
| 725 | if ((insn & 0x2000000) != 0) | |
| 726 | return (insn & 0x3fffffc) - 0x4000000; | |
| 727 | else | |
| 728 | return insn & 0x3fffffc; | |
| 729 | } | |
| 730 | ||
| 731 | /* The MB and ME fields in an M form instruction expressed as a single | |
| 732 | operand which is itself a bitmask. The extraction function always | |
| 733 | marks it as invalid, since we never want to recognize an | |
| 734 | instruction which uses a field of this type. */ | |
| 735 | ||
| 736 | static unsigned long | |
| 737 | insert_mbe (insn, value, errmsg) | |
| 738 | unsigned long insn; | |
| 739 | long value; | |
| 740 | const char **errmsg; | |
| 741 | { | |
| 742 | unsigned long uval, mask; | |
| 743 | int mb, me, mx, count, last; | |
| 744 | ||
| 745 | uval = value; | |
| 746 | ||
| 747 | if (uval == 0) | |
| 748 | { | |
| 749 | if (errmsg != (const char **) NULL) | |
| 750 | *errmsg = _("illegal bitmask"); | |
| 751 | return insn; | |
| 752 | } | |
| 753 | ||
| 754 | mb = 0; | |
| 755 | me = 32; | |
| 756 | if ((uval & 1) != 0) | |
| 757 | last = 1; | |
| 758 | else | |
| 759 | last = 0; | |
| 760 | count = 0; | |
| 761 | ||
| 762 | /* mb: location of last 0->1 transition */ | |
| 763 | /* me: location of last 1->0 transition */ | |
| 764 | /* count: # transitions */ | |
| 765 | ||
| 3eb9799d | 766 | for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1) |
| 252b5132 RH |
767 | { |
| 768 | if ((uval & mask) && !last) | |
| 769 | { | |
| 770 | ++count; | |
| 771 | mb = mx; | |
| 772 | last = 1; | |
| 773 | } | |
| 774 | else if (!(uval & mask) && last) | |
| 775 | { | |
| 776 | ++count; | |
| 777 | me = mx; | |
| 778 | last = 0; | |
| 779 | } | |
| 780 | } | |
| 781 | if (me == 0) | |
| 782 | me = 32; | |
| 783 | ||
| 784 | if (count != 2 && (count != 0 || ! last)) | |
| 785 | { | |
| 786 | if (errmsg != (const char **) NULL) | |
| 787 | *errmsg = _("illegal bitmask"); | |
| 788 | } | |
| 789 | ||
| 790 | return insn | (mb << 6) | ((me - 1) << 1); | |
| 791 | } | |
| 792 | ||
| 793 | static long | |
| 794 | extract_mbe (insn, invalid) | |
| 795 | unsigned long insn; | |
| 796 | int *invalid; | |
| 797 | { | |
| 798 | long ret; | |
| 799 | int mb, me; | |
| 800 | int i; | |
| 801 | ||
| 802 | if (invalid != (int *) NULL) | |
| 803 | *invalid = 1; | |
| 804 | ||
| 805 | mb = (insn >> 6) & 0x1f; | |
| 806 | me = (insn >> 1) & 0x1f; | |
| 807 | if (mb < me + 1) | |
| 808 | { | |
| 809 | ret = 0; | |
| 810 | for (i = mb; i <= me; i++) | |
| 811 | ret |= (long) 1 << (31 - i); | |
| 812 | } | |
| 813 | else if (mb == me + 1) | |
| 814 | ret = ~0; | |
| 815 | else /* (mb > me + 1) */ | |
| 816 | { | |
| 817 | ret = ~ (long) 0; | |
| 818 | for (i = me + 1; i < mb; i++) | |
| 819 | ret &= ~ ((long) 1 << (31 - i)); | |
| 820 | } | |
| 821 | return ret; | |
| 822 | } | |
| 823 | ||
| 824 | /* The MB or ME field in an MD or MDS form instruction. The high bit | |
| 825 | is wrapped to the low end. */ | |
| 826 | ||
| 827 | /*ARGSUSED*/ | |
| 828 | static unsigned long | |
| 829 | insert_mb6 (insn, value, errmsg) | |
| 830 | unsigned long insn; | |
| 831 | long value; | |
| 9aaaa291 | 832 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
833 | { |
| 834 | return insn | ((value & 0x1f) << 6) | (value & 0x20); | |
| 835 | } | |
| 836 | ||
| 837 | /*ARGSUSED*/ | |
| 838 | static long | |
| 839 | extract_mb6 (insn, invalid) | |
| 840 | unsigned long insn; | |
| 9aaaa291 | 841 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
842 | { |
| 843 | return ((insn >> 6) & 0x1f) | (insn & 0x20); | |
| 844 | } | |
| 845 | ||
| 846 | /* The NB field in an X form instruction. The value 32 is stored as | |
| 847 | 0. */ | |
| 848 | ||
| 849 | static unsigned long | |
| 850 | insert_nb (insn, value, errmsg) | |
| 851 | unsigned long insn; | |
| 852 | long value; | |
| 853 | const char **errmsg; | |
| 854 | { | |
| 855 | if (value < 0 || value > 32) | |
| 856 | *errmsg = _("value out of range"); | |
| 857 | if (value == 32) | |
| 858 | value = 0; | |
| 859 | return insn | ((value & 0x1f) << 11); | |
| 860 | } | |
| 861 | ||
| 862 | /*ARGSUSED*/ | |
| 863 | static long | |
| 864 | extract_nb (insn, invalid) | |
| 865 | unsigned long insn; | |
| 9aaaa291 | 866 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
867 | { |
| 868 | long ret; | |
| 869 | ||
| 870 | ret = (insn >> 11) & 0x1f; | |
| 871 | if (ret == 0) | |
| 872 | ret = 32; | |
| 873 | return ret; | |
| 874 | } | |
| 875 | ||
| 876 | /* The NSI field in a D form instruction. This is the same as the SI | |
| 877 | field, only negated. The extraction function always marks it as | |
| 878 | invalid, since we never want to recognize an instruction which uses | |
| 879 | a field of this type. */ | |
| 880 | ||
| 881 | /*ARGSUSED*/ | |
| 882 | static unsigned long | |
| 883 | insert_nsi (insn, value, errmsg) | |
| 884 | unsigned long insn; | |
| 885 | long value; | |
| 9aaaa291 | 886 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
887 | { |
| 888 | return insn | ((- value) & 0xffff); | |
| 889 | } | |
| 890 | ||
| 891 | static long | |
| 892 | extract_nsi (insn, invalid) | |
| 893 | unsigned long insn; | |
| 894 | int *invalid; | |
| 895 | { | |
| 896 | if (invalid != (int *) NULL) | |
| 897 | *invalid = 1; | |
| 898 | if ((insn & 0x8000) != 0) | |
| 899 | return - ((long)(insn & 0xffff) - 0x10000); | |
| 900 | else | |
| 901 | return - (long)(insn & 0xffff); | |
| 902 | } | |
| 903 | ||
| 904 | /* The RA field in a D or X form instruction which is an updating | |
| 905 | load, which means that the RA field may not be zero and may not | |
| 906 | equal the RT field. */ | |
| 907 | ||
| 908 | static unsigned long | |
| 909 | insert_ral (insn, value, errmsg) | |
| 910 | unsigned long insn; | |
| 911 | long value; | |
| 912 | const char **errmsg; | |
| 913 | { | |
| 914 | if (value == 0 | |
| 915 | || (unsigned long) value == ((insn >> 21) & 0x1f)) | |
| 916 | *errmsg = "invalid register operand when updating"; | |
| 917 | return insn | ((value & 0x1f) << 16); | |
| 918 | } | |
| 919 | ||
| 920 | /* The RA field in an lmw instruction, which has special value | |
| 921 | restrictions. */ | |
| 922 | ||
| 923 | static unsigned long | |
| 924 | insert_ram (insn, value, errmsg) | |
| 925 | unsigned long insn; | |
| 926 | long value; | |
| 927 | const char **errmsg; | |
| 928 | { | |
| 929 | if ((unsigned long) value >= ((insn >> 21) & 0x1f)) | |
| 930 | *errmsg = _("index register in load range"); | |
| 931 | return insn | ((value & 0x1f) << 16); | |
| 932 | } | |
| 933 | ||
| 934 | /* The RA field in a D or X form instruction which is an updating | |
| 935 | store or an updating floating point load, which means that the RA | |
| 936 | field may not be zero. */ | |
| 937 | ||
| 938 | static unsigned long | |
| 939 | insert_ras (insn, value, errmsg) | |
| 940 | unsigned long insn; | |
| 941 | long value; | |
| 942 | const char **errmsg; | |
| 943 | { | |
| 944 | if (value == 0) | |
| 945 | *errmsg = _("invalid register operand when updating"); | |
| 946 | return insn | ((value & 0x1f) << 16); | |
| 947 | } | |
| 948 | ||
| 949 | /* The RB field in an X form instruction when it must be the same as | |
| 950 | the RS field in the instruction. This is used for extended | |
| 951 | mnemonics like mr. This operand is marked FAKE. The insertion | |
| 952 | function just copies the BT field into the BA field, and the | |
| 953 | extraction function just checks that the fields are the same. */ | |
| 954 | ||
| 955 | /*ARGSUSED*/ | |
| 956 | static unsigned long | |
| 957 | insert_rbs (insn, value, errmsg) | |
| 958 | unsigned long insn; | |
| 9aaaa291 ILT |
959 | long value ATTRIBUTE_UNUSED; |
| 960 | const char **errmsg ATTRIBUTE_UNUSED; | |
| 252b5132 RH |
961 | { |
| 962 | return insn | (((insn >> 21) & 0x1f) << 11); | |
| 963 | } | |
| 964 | ||
| 965 | static long | |
| 966 | extract_rbs (insn, invalid) | |
| 967 | unsigned long insn; | |
| 968 | int *invalid; | |
| 969 | { | |
| 970 | if (invalid != (int *) NULL | |
| 971 | && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) | |
| 972 | *invalid = 1; | |
| 973 | return 0; | |
| 974 | } | |
| 975 | ||
| 976 | /* The SH field in an MD form instruction. This is split. */ | |
| 977 | ||
| 978 | /*ARGSUSED*/ | |
| 979 | static unsigned long | |
| 980 | insert_sh6 (insn, value, errmsg) | |
| 981 | unsigned long insn; | |
| 982 | long value; | |
| 9aaaa291 | 983 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
984 | { |
| 985 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); | |
| 986 | } | |
| 987 | ||
| 988 | /*ARGSUSED*/ | |
| 989 | static long | |
| 990 | extract_sh6 (insn, invalid) | |
| 991 | unsigned long insn; | |
| 9aaaa291 | 992 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
993 | { |
| 994 | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); | |
| 995 | } | |
| 996 | ||
| 997 | /* The SPR field in an XFX form instruction. This is flipped--the | |
| 998 | lower 5 bits are stored in the upper 5 and vice- versa. */ | |
| 999 | ||
| 1000 | static unsigned long | |
| 1001 | insert_spr (insn, value, errmsg) | |
| 1002 | unsigned long insn; | |
| 1003 | long value; | |
| 9aaaa291 | 1004 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
1005 | { |
| 1006 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
| 1007 | } | |
| 1008 | ||
| 1009 | static long | |
| 1010 | extract_spr (insn, invalid) | |
| 1011 | unsigned long insn; | |
| 9aaaa291 | 1012 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
1013 | { |
| 1014 | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); | |
| 1015 | } | |
| 1016 | ||
| 1017 | /* The TBR field in an XFX instruction. This is just like SPR, but it | |
| 1018 | is optional. When TBR is omitted, it must be inserted as 268 (the | |
| 1019 | magic number of the TB register). These functions treat 0 | |
| 1020 | (indicating an omitted optional operand) as 268. This means that | |
| 1021 | ``mftb 4,0'' is not handled correctly. This does not matter very | |
| 1022 | much, since the architecture manual does not define mftb as | |
| 1023 | accepting any values other than 268 or 269. */ | |
| 1024 | ||
| 1025 | #define TB (268) | |
| 1026 | ||
| 1027 | static unsigned long | |
| 1028 | insert_tbr (insn, value, errmsg) | |
| 1029 | unsigned long insn; | |
| 1030 | long value; | |
| 9aaaa291 | 1031 | const char **errmsg ATTRIBUTE_UNUSED; |
| 252b5132 RH |
1032 | { |
| 1033 | if (value == 0) | |
| 1034 | value = TB; | |
| 1035 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); | |
| 1036 | } | |
| 1037 | ||
| 1038 | static long | |
| 1039 | extract_tbr (insn, invalid) | |
| 1040 | unsigned long insn; | |
| 9aaaa291 | 1041 | int *invalid ATTRIBUTE_UNUSED; |
| 252b5132 RH |
1042 | { |
| 1043 | long ret; | |
| 1044 | ||
| 1045 | ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); | |
| 1046 | if (ret == TB) | |
| 1047 | ret = 0; | |
| 1048 | return ret; | |
| 1049 | } | |
| 1050 | \f | |
| 1051 | /* Macros used to form opcodes. */ | |
| 1052 | ||
| 1053 | /* The main opcode. */ | |
| 1054 | #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) | |
| 1055 | #define OP_MASK OP (0x3f) | |
| 1056 | ||
| 1057 | /* The main opcode combined with a trap code in the TO field of a D | |
| 1058 | form instruction. Used for extended mnemonics for the trap | |
| 1059 | instructions. */ | |
| 1060 | #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) | |
| 1061 | #define OPTO_MASK (OP_MASK | TO_MASK) | |
| 1062 | ||
| 1063 | /* The main opcode combined with a comparison size bit in the L field | |
| 1064 | of a D form or X form instruction. Used for extended mnemonics for | |
| 1065 | the comparison instructions. */ | |
| 1066 | #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) | |
| 1067 | #define OPL_MASK OPL (0x3f,1) | |
| 1068 | ||
| 1069 | /* An A form instruction. */ | |
| 1070 | #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) | |
| 1071 | #define A_MASK A (0x3f, 0x1f, 1) | |
| 1072 | ||
| 1073 | /* An A_MASK with the FRB field fixed. */ | |
| 1074 | #define AFRB_MASK (A_MASK | FRB_MASK) | |
| 1075 | ||
| 1076 | /* An A_MASK with the FRC field fixed. */ | |
| 1077 | #define AFRC_MASK (A_MASK | FRC_MASK) | |
| 1078 | ||
| 1079 | /* An A_MASK with the FRA and FRC fields fixed. */ | |
| 1080 | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) | |
| 1081 | ||
| 1082 | /* A B form instruction. */ | |
| 1083 | #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) | |
| 1084 | #define B_MASK B (0x3f, 1, 1) | |
| 1085 | ||
| 1086 | /* A B form instruction setting the BO field. */ | |
| 1087 | #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) | |
| 1088 | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) | |
| 1089 | ||
| 1090 | /* A BBO_MASK with the y bit of the BO field removed. This permits | |
| 1091 | matching a conditional branch regardless of the setting of the y | |
| 1092 | bit. */ | |
| 1093 | #define Y_MASK (((unsigned long)1) << 21) | |
| 1094 | #define BBOY_MASK (BBO_MASK &~ Y_MASK) | |
| 1095 | ||
| 1096 | /* A B form instruction setting the BO field and the condition bits of | |
| 1097 | the BI field. */ | |
| 1098 | #define BBOCB(op, bo, cb, aa, lk) \ | |
| 1099 | (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) | |
| 1100 | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) | |
| 1101 | ||
| 1102 | /* A BBOCB_MASK with the y bit of the BO field removed. */ | |
| 1103 | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) | |
| 1104 | ||
| 1105 | /* A BBOYCB_MASK in which the BI field is fixed. */ | |
| 1106 | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) | |
| 1107 | ||
| 1108 | /* The main opcode mask with the RA field clear. */ | |
| 1109 | #define DRA_MASK (OP_MASK | RA_MASK) | |
| 1110 | ||
| 1111 | /* A DS form instruction. */ | |
| 1112 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) | |
| 1113 | #define DS_MASK DSO (0x3f, 3) | |
| 1114 | ||
| 1115 | /* An M form instruction. */ | |
| 1116 | #define M(op, rc) (OP (op) | ((rc) & 1)) | |
| 1117 | #define M_MASK M (0x3f, 1) | |
| 1118 | ||
| 1119 | /* An M form instruction with the ME field specified. */ | |
| 1120 | #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) | |
| 1121 | ||
| 1122 | /* An M_MASK with the MB and ME fields fixed. */ | |
| 1123 | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) | |
| 1124 | ||
| 1125 | /* An M_MASK with the SH and ME fields fixed. */ | |
| 1126 | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) | |
| 1127 | ||
| 1128 | /* An MD form instruction. */ | |
| 1129 | #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) | |
| 1130 | #define MD_MASK MD (0x3f, 0x7, 1) | |
| 1131 | ||
| 1132 | /* An MD_MASK with the MB field fixed. */ | |
| 1133 | #define MDMB_MASK (MD_MASK | MB6_MASK) | |
| 1134 | ||
| 1135 | /* An MD_MASK with the SH field fixed. */ | |
| 1136 | #define MDSH_MASK (MD_MASK | SH6_MASK) | |
| 1137 | ||
| 1138 | /* An MDS form instruction. */ | |
| 1139 | #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) | |
| 1140 | #define MDS_MASK MDS (0x3f, 0xf, 1) | |
| 1141 | ||
| 1142 | /* An MDS_MASK with the MB field fixed. */ | |
| 1143 | #define MDSMB_MASK (MDS_MASK | MB6_MASK) | |
| 1144 | ||
| 1145 | /* An SC form instruction. */ | |
| 1146 | #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) | |
| 1147 | #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) | |
| 1148 | ||
| 786e2c0f C |
1149 | /* An VX form instruction. */ |
| 1150 | #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) | |
| 1151 | ||
| 1152 | /* The mask for an VX form instruction. */ | |
| 1153 | #define VX_MASK VX(0x3f, 0x7ff) | |
| 1154 | ||
| 1155 | /* An VA form instruction. */ | |
| 1156 | #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f)) | |
| 1157 | ||
| 1158 | /* The mask for an VA form instruction. */ | |
| 1159 | #define VXA_MASK VXA(0x3f, 0x7f) | |
| 1160 | ||
| 1161 | /* An VXR form instruction. */ | |
| 1162 | #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) | |
| 1163 | ||
| 1164 | /* The mask for a VXR form instruction. */ | |
| 1165 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) | |
| 1166 | ||
| 252b5132 RH |
1167 | /* An X form instruction. */ |
| 1168 | #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) | |
| 1169 | ||
| 1170 | /* An X form instruction with the RC bit specified. */ | |
| 1171 | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) | |
| 1172 | ||
| 1173 | /* The mask for an X form instruction. */ | |
| 1174 | #define X_MASK XRC (0x3f, 0x3ff, 1) | |
| 1175 | ||
| 1176 | /* An X_MASK with the RA field fixed. */ | |
| 1177 | #define XRA_MASK (X_MASK | RA_MASK) | |
| 1178 | ||
| 1179 | /* An X_MASK with the RB field fixed. */ | |
| 1180 | #define XRB_MASK (X_MASK | RB_MASK) | |
| 1181 | ||
| 1182 | /* An X_MASK with the RT field fixed. */ | |
| 1183 | #define XRT_MASK (X_MASK | RT_MASK) | |
| 1184 | ||
| 1185 | /* An X_MASK with the RA and RB fields fixed. */ | |
| 1186 | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) | |
| 1187 | ||
| 1188 | /* An X_MASK with the RT and RA fields fixed. */ | |
| 1189 | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) | |
| 1190 | ||
| 1191 | /* An X form comparison instruction. */ | |
| 1192 | #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) | |
| 1193 | ||
| 1194 | /* The mask for an X form comparison instruction. */ | |
| 1195 | #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) | |
| 1196 | ||
| 1197 | /* The mask for an X form comparison instruction with the L field | |
| 1198 | fixed. */ | |
| 1199 | #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) | |
| 1200 | ||
| 1201 | /* An X form trap instruction with the TO field specified. */ | |
| 1202 | #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) | |
| 1203 | #define XTO_MASK (X_MASK | TO_MASK) | |
| 1204 | ||
| e0c21649 GK |
1205 | /* An X form tlb instruction with the SH field specified. */ |
| 1206 | #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) | |
| 1207 | #define XTLB_MASK (X_MASK | SH_MASK) | |
| 1208 | ||
| 6ba045b1 AM |
1209 | /* An X form sync instruction. */ |
| 1210 | #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) | |
| 1211 | ||
| 1212 | /* An X form sync instruction with everything filled in except the LS field. */ | |
| 1213 | #define XSYNC_MASK (0xff9fffff) | |
| 1214 | ||
| 252b5132 RH |
1215 | /* An XFL form instruction. */ |
| 1216 | #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) | |
| 1217 | #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) | |
| 1218 | ||
| 1219 | /* An XL form instruction with the LK field set to 0. */ | |
| 1220 | #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) | |
| 1221 | ||
| 1222 | /* An XL form instruction which uses the LK field. */ | |
| 1223 | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) | |
| 1224 | ||
| 1225 | /* The mask for an XL form instruction. */ | |
| 1226 | #define XL_MASK XLLK (0x3f, 0x3ff, 1) | |
| 1227 | ||
| 1228 | /* An XL form instruction which explicitly sets the BO field. */ | |
| 1229 | #define XLO(op, bo, xop, lk) \ | |
| 1230 | (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) | |
| 1231 | #define XLO_MASK (XL_MASK | BO_MASK) | |
| 1232 | ||
| 1233 | /* An XL form instruction which explicitly sets the y bit of the BO | |
| 1234 | field. */ | |
| 1235 | #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) | |
| 1236 | #define XLYLK_MASK (XL_MASK | Y_MASK) | |
| 1237 | ||
| 1238 | /* An XL form instruction which sets the BO field and the condition | |
| 1239 | bits of the BI field. */ | |
| 1240 | #define XLOCB(op, bo, cb, xop, lk) \ | |
| 1241 | (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) | |
| 1242 | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) | |
| 1243 | ||
| 1244 | /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ | |
| 1245 | #define XLBB_MASK (XL_MASK | BB_MASK) | |
| 1246 | #define XLYBB_MASK (XLYLK_MASK | BB_MASK) | |
| 1247 | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) | |
| 1248 | ||
| 1249 | /* An XL_MASK with the BO and BB fields fixed. */ | |
| 1250 | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) | |
| 1251 | ||
| 1252 | /* An XL_MASK with the BO, BI and BB fields fixed. */ | |
| 1253 | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) | |
| 1254 | ||
| 1255 | /* An XO form instruction. */ | |
| 1256 | #define XO(op, xop, oe, rc) \ | |
| 1257 | (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) | |
| 1258 | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) | |
| 1259 | ||
| 1260 | /* An XO_MASK with the RB field fixed. */ | |
| 1261 | #define XORB_MASK (XO_MASK | RB_MASK) | |
| 1262 | ||
| 1263 | /* An XS form instruction. */ | |
| 1264 | #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) | |
| 1265 | #define XS_MASK XS (0x3f, 0x1ff, 1) | |
| 1266 | ||
| 1267 | /* A mask for the FXM version of an XFX form instruction. */ | |
| 1268 | #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11)) | |
| 1269 | ||
| 1270 | /* An XFX form instruction with the FXM field filled in. */ | |
| 1271 | #define XFXM(op, xop, fxm) \ | |
| 1272 | (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12)) | |
| 1273 | ||
| 1274 | /* An XFX form instruction with the SPR field filled in. */ | |
| 1275 | #define XSPR(op, xop, spr) \ | |
| 1276 | (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) | |
| 1277 | #define XSPR_MASK (X_MASK | SPR_MASK) | |
| 1278 | ||
| 1279 | /* An XFX form instruction with the SPR field filled in except for the | |
| 1280 | SPRBAT field. */ | |
| 1281 | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) | |
| 1282 | ||
| 1283 | /* An XFX form instruction with the SPR field filled in except for the | |
| 1284 | SPRG field. */ | |
| 1285 | #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) | |
| 1286 | ||
| 1287 | /* An X form instruction with everything filled in except the E field. */ | |
| 1288 | #define XE_MASK (0xffff7fff) | |
| 1289 | ||
| 1290 | /* The BO encodings used in extended conditional branch mnemonics. */ | |
| 1291 | #define BODNZF (0x0) | |
| 1292 | #define BODNZFP (0x1) | |
| 1293 | #define BODZF (0x2) | |
| 1294 | #define BODZFP (0x3) | |
| 1295 | #define BOF (0x4) | |
| 1296 | #define BOFP (0x5) | |
| 1297 | #define BODNZT (0x8) | |
| 1298 | #define BODNZTP (0x9) | |
| 1299 | #define BODZT (0xa) | |
| 1300 | #define BODZTP (0xb) | |
| 1301 | #define BOT (0xc) | |
| 1302 | #define BOTP (0xd) | |
| 1303 | #define BODNZ (0x10) | |
| 1304 | #define BODNZP (0x11) | |
| 1305 | #define BODZ (0x12) | |
| 1306 | #define BODZP (0x13) | |
| 1307 | #define BOU (0x14) | |
| 1308 | ||
| 1309 | /* The BI condition bit encodings used in extended conditional branch | |
| 1310 | mnemonics. */ | |
| 1311 | #define CBLT (0) | |
| 1312 | #define CBGT (1) | |
| 1313 | #define CBEQ (2) | |
| 1314 | #define CBSO (3) | |
| 1315 | ||
| 1316 | /* The TO encodings used in extended trap mnemonics. */ | |
| 1317 | #define TOLGT (0x1) | |
| 1318 | #define TOLLT (0x2) | |
| 1319 | #define TOEQ (0x4) | |
| 1320 | #define TOLGE (0x5) | |
| 1321 | #define TOLNL (0x5) | |
| 1322 | #define TOLLE (0x6) | |
| 1323 | #define TOLNG (0x6) | |
| 1324 | #define TOGT (0x8) | |
| 1325 | #define TOGE (0xc) | |
| 1326 | #define TONL (0xc) | |
| 1327 | #define TOLT (0x10) | |
| 1328 | #define TOLE (0x14) | |
| 1329 | #define TONG (0x14) | |
| 1330 | #define TONE (0x18) | |
| 1331 | #define TOU (0x1f) | |
| 1332 | \f | |
| 1333 | /* Smaller names for the flags so each entry in the opcodes table will | |
| 1334 | fit on a single line. */ | |
| 1335 | #undef PPC | |
| 1336 | #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY | |
| 1337 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | |
| 1338 | #define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY | |
| 1339 | #define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY | |
| 1340 | #define PPCONLY PPC_OPCODE_PPC | |
| 1341 | #define PPC403 PPC | |
| e0c21649 | 1342 | #define PPC405 PPC403 |
| 252b5132 RH |
1343 | #define PPC750 PPC |
| 1344 | #define PPC860 PPC | |
| 786e2c0f | 1345 | #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY |
| 252b5132 RH |
1346 | #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY |
| 1347 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY | |
| 1348 | #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY | |
| 1349 | #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32 | |
| 1350 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | |
| 1351 | #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32 | |
| 1352 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY | |
| 1353 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | |
| 1354 | #define MFDEC1 PPC_OPCODE_POWER | |
| 1355 | #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | |
| 1356 | \f | |
| 1357 | /* The opcode table. | |
| 1358 | ||
| 1359 | The format of the opcode table is: | |
| 1360 | ||
| 1361 | NAME OPCODE MASK FLAGS { OPERANDS } | |
| 1362 | ||
| 1363 | NAME is the name of the instruction. | |
| 1364 | OPCODE is the instruction opcode. | |
| 1365 | MASK is the opcode mask; this is used to tell the disassembler | |
| 1366 | which bits in the actual opcode must match OPCODE. | |
| 1367 | FLAGS are flags indicated what processors support the instruction. | |
| 1368 | OPERANDS is the list of operands. | |
| 1369 | ||
| 1370 | The disassembler reads the table in order and prints the first | |
| 1371 | instruction which matches, so this table is sorted to put more | |
| 1372 | specific instructions before more general instructions. It is also | |
| 1373 | sorted by major opcode. */ | |
| 1374 | ||
| 1375 | const struct powerpc_opcode powerpc_opcodes[] = { | |
| 1376 | { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1377 | { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1378 | { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1379 | { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1380 | { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1381 | { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1382 | { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1383 | { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1384 | { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1385 | { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1386 | { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1387 | { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1388 | { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1389 | { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, | |
| 1390 | { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, | |
| 1391 | ||
| 1392 | { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1393 | { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1394 | { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1395 | { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1396 | { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1397 | { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1398 | { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1399 | { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1400 | { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1401 | { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1402 | { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1403 | { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1404 | { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1405 | { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1406 | { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1407 | { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1408 | { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1409 | { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1410 | { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1411 | { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1412 | { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1413 | { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1414 | { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1415 | { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1416 | { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1417 | { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1418 | { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, | |
| 1419 | { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, | |
| 1420 | { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, | |
| 1421 | { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, | |
| e0c21649 GK |
1422 | |
| 1423 | { "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1424 | { "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1425 | { "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1426 | { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1427 | { "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1428 | { "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1429 | { "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1430 | { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1431 | { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1432 | { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1433 | { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1434 | { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1435 | { "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1436 | { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1437 | { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1438 | { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1439 | { "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1440 | { "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1441 | { "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1442 | { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1443 | { "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1444 | { "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1445 | { "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1446 | { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1447 | { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1448 | { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1449 | { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1450 | { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1451 | { "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1452 | { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1453 | { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1454 | { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1455 | { "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1456 | { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1457 | { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1458 | { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1459 | { "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1460 | { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1461 | { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1462 | { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1463 | { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1464 | { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1465 | { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1466 | { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1467 | { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1468 | { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1469 | { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1470 | { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1471 | { "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1472 | { "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1473 | { "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1474 | { "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1475 | { "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1476 | { "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1477 | { "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1478 | { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1479 | { "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1480 | { "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1481 | { "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1482 | { "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } }, | |
| 1483 | { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1484 | { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1485 | { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1486 | { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1487 | { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1488 | { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1489 | { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1490 | { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1491 | { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1492 | { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1493 | { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1494 | { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1495 | { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1496 | { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1497 | { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1498 | { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1499 | { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1500 | { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1501 | { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1502 | { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1503 | { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1504 | { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1505 | { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 1506 | { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } }, | |
| 786e2c0f C |
1507 | { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, |
| 1508 | { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } }, | |
| 1509 | { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1510 | { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1511 | { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1512 | { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1513 | { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1514 | { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1515 | { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1516 | { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1517 | { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1518 | { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1519 | { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1520 | { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1521 | { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1522 | { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1523 | { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1524 | { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1525 | { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1526 | { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1527 | { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1528 | { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, | |
| 1529 | { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, | |
| 1530 | { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1531 | { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1532 | { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1533 | { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1534 | { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1535 | { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1536 | { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1537 | { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1538 | { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1539 | { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1540 | { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1541 | { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1542 | { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1543 | { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1544 | { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1545 | { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1546 | { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1547 | { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1548 | { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1549 | { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1550 | { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1551 | { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1552 | { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1553 | { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1554 | { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1555 | { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1556 | { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, | |
| 1557 | { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, | |
| 1558 | { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1559 | { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1560 | { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1561 | { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1562 | { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1563 | { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1564 | { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1565 | { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1566 | { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1567 | { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1568 | { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1569 | { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1570 | { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1571 | { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1572 | { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1573 | { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1574 | { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1575 | { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1576 | { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1577 | { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1578 | { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1579 | { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1580 | { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1581 | { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1582 | { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1583 | { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1584 | { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1585 | { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1586 | { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| d2f75a6f GK |
1587 | { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1588 | { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1589 | { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 786e2c0f C |
1590 | { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1591 | { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1592 | { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1593 | { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1594 | { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1595 | { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1596 | { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1597 | { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1598 | { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, | |
| 1599 | { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1600 | { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1601 | { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1602 | { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1603 | { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1604 | { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1605 | { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1606 | { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1607 | { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1608 | { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1609 | { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1610 | { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1611 | { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1612 | { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1613 | { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1614 | { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1615 | { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1616 | { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1617 | { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1618 | { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1619 | { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1620 | { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, | |
| 1621 | { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1622 | { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1623 | { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, | |
| 1624 | { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1625 | { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1da5001c | 1626 | { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 786e2c0f C |
1627 | { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1628 | { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, | |
| 1629 | { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, | |
| 1630 | { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, | |
| 1631 | { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, | |
| 1632 | { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, | |
| 1633 | { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1634 | { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1635 | { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1636 | { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1637 | { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1638 | { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1639 | { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1640 | { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1641 | { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1642 | { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1643 | { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1644 | { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1645 | { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1646 | { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1647 | { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1648 | { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1649 | { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1650 | { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1651 | { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1652 | { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1653 | { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1654 | { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1655 | { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1656 | { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 1657 | { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1658 | { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1659 | { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1660 | { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1661 | { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1662 | { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, | |
| 1663 | { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, | |
| 252b5132 RH |
1664 | |
| 1665 | { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, | |
| 1666 | { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, | |
| 1667 | ||
| 1668 | { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, | |
| 1669 | { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, | |
| 1670 | ||
| 1671 | { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, | |
| 1672 | ||
| 1673 | { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, | |
| 1674 | { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, | |
| 1675 | { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } }, | |
| 1676 | { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, | |
| 1677 | ||
| 1678 | { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, | |
| 1679 | { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, | |
| 1680 | { "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } }, | |
| 1681 | { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, | |
| 1682 | ||
| 1683 | { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, | |
| 1684 | { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, | |
| 1685 | { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, | |
| 1686 | ||
| 1687 | { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, | |
| 1688 | { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, | |
| 1689 | { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, | |
| 1690 | ||
| 1691 | { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, | |
| 1692 | { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, | |
| 1693 | { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } }, | |
| 1694 | { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } }, | |
| 1695 | { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } }, | |
| 1696 | { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, | |
| 1697 | ||
| 1698 | { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, | |
| 1699 | { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, | |
| 1700 | { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } }, | |
| 1701 | { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } }, | |
| 1702 | { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } }, | |
| 1703 | ||
| d2f75a6f GK |
1704 | { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } }, |
| 1705 | { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } }, | |
| 252b5132 RH |
1706 | { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BD } }, |
| 1707 | { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM, { BD } }, | |
| d2f75a6f GK |
1708 | { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } }, |
| 1709 | { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } }, | |
| 252b5132 RH |
1710 | { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BD } }, |
| 1711 | { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM, { BD } }, | |
| d2f75a6f GK |
1712 | { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } }, |
| 1713 | { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } }, | |
| 252b5132 RH |
1714 | { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDA } }, |
| 1715 | { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM, { BDA } }, | |
| d2f75a6f GK |
1716 | { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } }, |
| 1717 | { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } }, | |
| 252b5132 RH |
1718 | { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDA } }, |
| 1719 | { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM, { BDA } }, | |
| d2f75a6f GK |
1720 | { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } }, |
| 1721 | { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } }, | |
| 252b5132 | 1722 | { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, COM, { BD } }, |
| d2f75a6f GK |
1723 | { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } }, |
| 1724 | { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } }, | |
| 252b5132 | 1725 | { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, COM, { BD } }, |
| d2f75a6f GK |
1726 | { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } }, |
| 1727 | { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } }, | |
| 252b5132 | 1728 | { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, COM, { BDA } }, |
| d2f75a6f GK |
1729 | { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } }, |
| 1730 | { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } }, | |
| 252b5132 | 1731 | { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, COM, { BDA } }, |
| d2f75a6f GK |
1732 | { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, |
| 1733 | { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1734 | { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1735 | { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1736 | { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1737 | { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1738 | { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1739 | { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1740 | { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1741 | { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1742 | { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1743 | { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1744 | { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1745 | { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1746 | { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1747 | { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1748 | { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1749 | { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1750 | { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1751 | { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1752 | { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1753 | { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1754 | { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1755 | { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1756 | { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1757 | { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1758 | { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1759 | { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1760 | { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1761 | { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1762 | { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1763 | { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1764 | { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1765 | { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1766 | { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1767 | { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1768 | { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1769 | { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1770 | { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1771 | { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1772 | { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1773 | { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1774 | { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1775 | { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1776 | { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1777 | { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1778 | { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1779 | { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1780 | { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1781 | { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1782 | { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } }, | |
| 1783 | { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1784 | { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1785 | { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } }, | |
| 1786 | { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1787 | { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1788 | { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } }, | |
| 1789 | { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1790 | { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1791 | { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } }, | |
| 1792 | { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1793 | { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1794 | { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1795 | { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1796 | { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1797 | { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1798 | { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1799 | { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1800 | { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1801 | { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1802 | { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1803 | { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1804 | { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1805 | { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1806 | { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1807 | { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1808 | { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1809 | { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1810 | { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1811 | { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1812 | { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1813 | { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1814 | { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1815 | { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1816 | { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1817 | { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1818 | { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1819 | { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1820 | { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1821 | { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1822 | { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1823 | { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1824 | { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1825 | { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1826 | { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1827 | { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1828 | { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1829 | { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1830 | { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1831 | { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1832 | { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1833 | { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1834 | { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1835 | { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1836 | { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1837 | { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1838 | { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1839 | { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1840 | { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1841 | { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1842 | { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1843 | { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1844 | { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1845 | { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1846 | { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1847 | { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1848 | { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1849 | { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1850 | { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1851 | { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1852 | { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1853 | { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1854 | { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1855 | { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1856 | { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1857 | { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } }, | |
| 1858 | { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1859 | { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1860 | { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1861 | { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1862 | { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1863 | { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } }, | |
| 1864 | { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1865 | { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1866 | { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } }, | |
| 1867 | { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, | |
| 1868 | { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, | |
| 1869 | { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } }, | |
| 1870 | { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1871 | { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1872 | { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } }, | |
| 1873 | { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, | |
| 1874 | { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, | |
| 1875 | { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } }, | |
| 1876 | { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, | |
| 1877 | { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1878 | { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1879 | { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1880 | { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1881 | { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1882 | { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1883 | { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1884 | { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1885 | { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1886 | { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1887 | { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1888 | { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1889 | { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1890 | { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1891 | { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1892 | { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1893 | { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1894 | { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1895 | { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1896 | { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1897 | { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1898 | { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1899 | { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1900 | { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1901 | { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 RH |
1902 | { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1903 | { "bbt", BBO(16,BOT,0,0), BBOY_MASK, PWRCOM, { BI, BD } }, | |
| d2f75a6f GK |
1904 | { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1905 | { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 RH |
1906 | { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1907 | { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, PWRCOM, { BI, BD } }, | |
| d2f75a6f GK |
1908 | { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1909 | { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 RH |
1910 | { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1911 | { "bbta", BBO(16,BOT,1,0), BBOY_MASK, PWRCOM, { BI, BDA } }, | |
| d2f75a6f GK |
1912 | { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1913 | { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 RH |
1914 | { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1915 | { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, PWRCOM, { BI, BDA } }, | |
| d2f75a6f GK |
1916 | { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1917 | { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 RH |
1918 | { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1919 | { "bbf", BBO(16,BOF,0,0), BBOY_MASK, PWRCOM, { BI, BD } }, | |
| d2f75a6f GK |
1920 | { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1921 | { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 RH |
1922 | { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1923 | { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, PWRCOM, { BI, BD } }, | |
| d2f75a6f GK |
1924 | { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1925 | { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 RH |
1926 | { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1927 | { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, PWRCOM, { BI, BDA } }, | |
| d2f75a6f GK |
1928 | { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1929 | { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 RH |
1930 | { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1931 | { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, PWRCOM, { BI, BDA } }, | |
| d2f75a6f GK |
1932 | { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1933 | { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1934 | { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1935 | { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1936 | { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1937 | { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1938 | { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1939 | { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1940 | { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1941 | { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1942 | { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1943 | { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1944 | { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1945 | { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1946 | { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1947 | { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, |
| 1948 | { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, | |
| 252b5132 | 1949 | { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| d2f75a6f GK |
1950 | { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1951 | { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1952 | { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1953 | { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, |
| 1954 | { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, | |
| 252b5132 | 1955 | { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| d2f75a6f GK |
1956 | { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
| 1957 | { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, | |
| 252b5132 | 1958 | { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, |
| d2f75a6f GK |
1959 | { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
| 1960 | { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, | |
| 252b5132 | 1961 | { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, |
| d2f75a6f GK |
1962 | { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
| 1963 | { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, | |
| 252b5132 | 1964 | { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, |
| d2f75a6f GK |
1965 | { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
| 1966 | { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, | |
| 252b5132 RH |
1967 | { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, |
| 1968 | ||
| 1969 | { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, | |
| 1970 | { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, | |
| 1971 | { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, | |
| 1972 | { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, | |
| 1973 | { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, | |
| 1974 | ||
| 1975 | { "b", B(18,0,0), B_MASK, COM, { LI } }, | |
| 1976 | { "bl", B(18,0,1), B_MASK, COM, { LI } }, | |
| 1977 | { "ba", B(18,1,0), B_MASK, COM, { LIA } }, | |
| 1978 | { "bla", B(18,1,1), B_MASK, COM, { LIA } }, | |
| 1979 | ||
| 1980 | { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, | |
| 1981 | ||
| 1982 | { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, | |
| 1983 | { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, | |
| 1984 | { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, | |
| 1985 | { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, | |
| 1986 | { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, | |
| d2f75a6f GK |
1987 | { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1988 | { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, | |
| 252b5132 | 1989 | { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| d2f75a6f GK |
1990 | { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1991 | { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, | |
| 252b5132 | 1992 | { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| d2f75a6f GK |
1993 | { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1994 | { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, | |
| 252b5132 | 1995 | { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| d2f75a6f GK |
1996 | { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1997 | { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, | |
| 252b5132 | 1998 | { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
1999 | { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2000 | { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2001 | { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2002 | { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2003 | { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2004 | { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2005 | { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2006 | { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2007 | { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2008 | { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2009 | { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2010 | { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2011 | { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2012 | { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2013 | { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2014 | { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2015 | { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2016 | { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2017 | { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2018 | { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2019 | { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2020 | { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2021 | { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2022 | { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2023 | { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2024 | { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2025 | { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2026 | { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2027 | { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2028 | { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2029 | { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2030 | { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2031 | { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2032 | { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2033 | { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2034 | { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2035 | { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2036 | { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2037 | { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2038 | { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2039 | { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2040 | { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2041 | { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2042 | { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2043 | { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2044 | { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2045 | { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2046 | { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2047 | { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2048 | { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2049 | { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2050 | { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2051 | { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2052 | { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2053 | { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2054 | { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2055 | { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2056 | { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2057 | { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2058 | { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2059 | { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2060 | { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2061 | { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2062 | { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2063 | { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2064 | { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2065 | { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2066 | { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2067 | { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2068 | { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2069 | { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2070 | { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2071 | { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2072 | { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2073 | { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2074 | { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2075 | { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2076 | { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2077 | { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2078 | { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2079 | { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2080 | { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2081 | { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2082 | { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 RH |
2083 | { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 2084 | { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2085 | { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2086 | { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2087 | { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2088 | { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2089 | { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2090 | { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2091 | { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2092 | { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 RH |
2093 | { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, |
| 2094 | { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| d2f75a6f GK |
2095 | { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2096 | { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 RH |
2097 | { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, |
| 2098 | { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| d2f75a6f GK |
2099 | { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2100 | { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 RH |
2101 | { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, |
| 2102 | { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| d2f75a6f GK |
2103 | { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2104 | { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 RH |
2105 | { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, |
| 2106 | { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| d2f75a6f GK |
2107 | { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2108 | { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2109 | { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2110 | { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2111 | { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } }, | |
| 252b5132 | 2112 | { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2113 | { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2114 | { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2115 | { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2116 | { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2117 | { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } }, | |
| 252b5132 | 2118 | { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2119 | { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2120 | { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2121 | { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2122 | { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2123 | { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2124 | { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2125 | { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2126 | { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2127 | { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2128 | { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2129 | { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 RH |
2130 | { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } }, |
| 2131 | { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } }, | |
| d2f75a6f GK |
2132 | { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 2133 | { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, | |
| 2134 | { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, | |
| 2135 | { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, | |
| 252b5132 RH |
2136 | { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
| 2137 | { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, | |
| 2138 | ||
| f509565f GK |
2139 | { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, |
| 2140 | ||
| 252b5132 RH |
2141 | { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, |
| 2142 | { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, | |
| 2143 | ||
| 2144 | { "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, | |
| e0c21649 | 2145 | { "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } }, |
| 252b5132 RH |
2146 | |
| 2147 | { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, | |
| 2148 | ||
| 2149 | { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, | |
| 2150 | ||
| 2151 | { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, | |
| 2152 | { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, | |
| 2153 | ||
| 2154 | { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, | |
| 2155 | { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, | |
| 2156 | ||
| 2157 | { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, | |
| 2158 | ||
| 2159 | { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, | |
| 2160 | ||
| 2161 | { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, | |
| 2162 | { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, | |
| 2163 | ||
| 2164 | { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, | |
| 2165 | ||
| 2166 | { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, | |
| 2167 | { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, | |
| 2168 | ||
| 2169 | { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, | |
| 2170 | { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, | |
| 2171 | { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| d2f75a6f GK |
2172 | { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2173 | { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2174 | { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2175 | { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2176 | { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2177 | { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2178 | { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2179 | { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2180 | { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2181 | { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2182 | { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2183 | { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2184 | { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2185 | { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2186 | { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2187 | { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2188 | { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2189 | { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2190 | { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2191 | { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2192 | { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2193 | { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2194 | { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2195 | { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2196 | { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2197 | { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2198 | { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2199 | { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2200 | { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2201 | { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2202 | { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2203 | { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2204 | { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2205 | { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2206 | { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2207 | { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2208 | { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2209 | { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2210 | { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2211 | { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2212 | { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2213 | { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2214 | { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2215 | { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2216 | { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2217 | { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2218 | { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2219 | { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2220 | { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2221 | { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2222 | { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2223 | { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2224 | { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2225 | { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2226 | { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2227 | { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2228 | { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2229 | { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2230 | { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2231 | { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2232 | { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2233 | { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2234 | { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2235 | { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2236 | { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2237 | { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2238 | { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2239 | { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2240 | { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| d2f75a6f GK |
2241 | { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 2242 | { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, | |
| 252b5132 | 2243 | { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2244 | { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2245 | { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2246 | { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2247 | { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2248 | { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2249 | { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2250 | { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2251 | { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2252 | { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| d2f75a6f GK |
2253 | { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 2254 | { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, { BI } }, | |
| 252b5132 | 2255 | { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, |
| d2f75a6f GK |
2256 | { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 2257 | { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, | |
| 252b5132 | 2258 | { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } }, |
| d2f75a6f GK |
2259 | { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 2260 | { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, | |
| 252b5132 RH |
2261 | { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
| 2262 | { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, | |
| 2263 | ||
| 2264 | { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, | |
| 2265 | { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, | |
| 2266 | ||
| 2267 | { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, | |
| 2268 | { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, | |
| 2269 | ||
| 2270 | { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, | |
| 2271 | { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, | |
| 2272 | { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, | |
| 2273 | { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, | |
| 2274 | { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, | |
| 2275 | { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, | |
| 2276 | { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, | |
| 2277 | { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, | |
| 2278 | ||
| 2279 | { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, | |
| 2280 | { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, | |
| 2281 | ||
| 2282 | { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, | |
| 2283 | { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, | |
| 2284 | { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, | |
| 2285 | { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, | |
| 2286 | { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, | |
| 2287 | { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, | |
| 2288 | ||
| 2289 | { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, | |
| 2290 | { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, | |
| 2291 | { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, | |
| 2292 | ||
| 2293 | { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, | |
| 2294 | { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, | |
| 2295 | ||
| 2296 | { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, | |
| 2297 | { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, | |
| 2298 | ||
| 2299 | { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, | |
| 2300 | { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, | |
| 2301 | ||
| 2302 | { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, | |
| 2303 | { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, | |
| 2304 | ||
| 2305 | { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, | |
| 2306 | { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, | |
| 2307 | ||
| 2308 | { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, | |
| 2309 | { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, | |
| 2310 | { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, | |
| 2311 | { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, | |
| 2312 | { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, | |
| 2313 | { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, | |
| 2314 | ||
| 2315 | { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, | |
| 2316 | { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, | |
| 2317 | ||
| 2318 | { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, | |
| 2319 | { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, | |
| 2320 | ||
| 2321 | { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, | |
| 2322 | { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, | |
| 2323 | ||
| 2324 | { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, | |
| 2325 | { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, | |
| 2326 | { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, | |
| 2327 | { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, | |
| 2328 | ||
| 2329 | { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, | |
| 2330 | { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, | |
| 2331 | ||
| 2332 | { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, | |
| 2333 | { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, | |
| 2334 | { "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, | |
| 2335 | { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, | |
| 2336 | ||
| 2337 | { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2338 | { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2339 | { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2340 | { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2341 | { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2342 | { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2343 | { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2344 | { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2345 | { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2346 | { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2347 | { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2348 | { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2349 | { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2350 | { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2351 | { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2352 | { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2353 | { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2354 | { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2355 | { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2356 | { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2357 | { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2358 | { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2359 | { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2360 | { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2361 | { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2362 | { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2363 | { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, | |
| 2364 | { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, | |
| 2365 | { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, | |
| 2366 | { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, | |
| 2367 | { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, | |
| 2368 | ||
| 2369 | { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2370 | { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2371 | { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, | |
| 2372 | { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2373 | { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2374 | { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, | |
| 2375 | { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2376 | { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2377 | { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, | |
| 2378 | { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2379 | { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2380 | { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, | |
| 2381 | ||
| 2382 | { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2383 | { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2384 | ||
| 2385 | { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2386 | { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2387 | { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2388 | { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2389 | { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2390 | { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2391 | { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2392 | { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2393 | ||
| 2394 | { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2395 | { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2396 | ||
| 2397 | { "mfcr", X(31,19), XRARB_MASK, COM, { RT } }, | |
| 2398 | ||
| 2399 | { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, | |
| 2400 | ||
| 2401 | { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } }, | |
| 2402 | ||
| 2403 | { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2404 | { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2405 | ||
| 2406 | { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, | |
| 2407 | { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, | |
| 2408 | { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, | |
| 2409 | { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, | |
| 2410 | ||
| 2411 | { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, | |
| 2412 | { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, | |
| 2413 | { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, | |
| 2414 | { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, | |
| 2415 | ||
| 2416 | { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, | |
| 2417 | { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, | |
| 2418 | ||
| 2419 | { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, | |
| 2420 | { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, | |
| 2421 | ||
| 2422 | { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, | |
| 2423 | { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, | |
| 2424 | ||
| 2425 | { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, | |
| 2426 | { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, | |
| 2427 | { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, | |
| 2428 | { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, | |
| 2429 | ||
| 2430 | { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2431 | { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, | |
| 2432 | { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2433 | { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, | |
| 2434 | { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2435 | { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, | |
| 2436 | { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2437 | { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, | |
| 2438 | ||
| 2439 | { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, | |
| 2440 | ||
| 2441 | { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, | |
| 2442 | ||
| 2443 | { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, | |
| 2444 | { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2445 | ||
| 2446 | { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, | |
| 2447 | { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, | |
| 2448 | ||
| 2449 | { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, | |
| 2450 | { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, | |
| 2451 | ||
| 2452 | { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, | |
| 2453 | { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, | |
| 2454 | { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, | |
| 2455 | { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, | |
| 2456 | { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, | |
| 2457 | { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, | |
| 2458 | { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, | |
| 2459 | { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, | |
| 2460 | { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, | |
| 2461 | { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, | |
| 2462 | { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, | |
| 2463 | { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, | |
| 2464 | { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, | |
| 2465 | { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, | |
| 2466 | { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, | |
| 2467 | ||
| 2468 | { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2469 | { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2470 | ||
| 2471 | { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2472 | { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2473 | ||
| f509565f GK |
2474 | { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, |
| 2475 | ||
| 252b5132 RH |
2476 | { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, |
| 2477 | ||
| 2478 | { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } }, | |
| 2479 | ||
| 2480 | { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, | |
| 2481 | ||
| 2482 | { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } }, | |
| 2483 | ||
| 2484 | { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, | |
| 2485 | { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, | |
| 2486 | { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, | |
| 2487 | { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, | |
| 2488 | ||
| 2489 | { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2490 | { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2491 | { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2492 | { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2493 | ||
| f509565f GK |
2494 | { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, |
| 2495 | ||
| 2dd46b8b | 2496 | { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, |
| 252b5132 RH |
2497 | |
| 2498 | { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, | |
| 2499 | ||
| 2500 | { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, | |
| 2501 | { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, | |
| 2502 | { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, | |
| 2503 | { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, | |
| 2504 | ||
| 2505 | { "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } }, | |
| 2506 | ||
| 2507 | { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2508 | { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2509 | { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2510 | { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2511 | { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2512 | { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2513 | { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2514 | { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2515 | ||
| 2516 | { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2517 | { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2518 | { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2519 | { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2520 | { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2521 | { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2522 | { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2523 | { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2524 | ||
| 2525 | { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }}, | |
| 2526 | { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, | |
| 2527 | ||
| 2528 | { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, | |
| 2529 | ||
| 2530 | { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } }, | |
| 2531 | ||
| 2532 | { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, | |
| 2533 | ||
| 2534 | { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } }, | |
| 2535 | { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, | |
| 2536 | ||
| 2537 | { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, | |
| 2538 | { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, | |
| 2539 | ||
| 2540 | { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, | |
| 2541 | { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, | |
| 2542 | ||
| 2543 | { "wrteei", X(31,163), XE_MASK, PPC403, { E } }, | |
| 2544 | ||
| f509565f GK |
2545 | { "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } }, |
| 2546 | ||
| 252b5132 RH |
2547 | { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, |
| 2548 | ||
| 2549 | { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, | |
| 2550 | { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } }, | |
| 2551 | ||
| 2552 | { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, | |
| 2553 | { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, | |
| 2554 | ||
| 2555 | { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2556 | { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2557 | { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2558 | { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2559 | { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2560 | { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2561 | { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2562 | { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2563 | ||
| 2564 | { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2565 | { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2566 | { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2567 | { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2568 | { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2569 | { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2570 | { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2571 | { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2572 | ||
| 2573 | { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, | |
| 2574 | ||
| 2575 | { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } }, | |
| 2576 | ||
| 2577 | { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, | |
| 2578 | ||
| 2579 | { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, | |
| 2580 | { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, | |
| 2581 | ||
| 2582 | { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, | |
| 2583 | { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, | |
| 2584 | ||
| 2585 | { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2586 | { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2587 | { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2588 | { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2589 | { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2590 | { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2591 | { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2592 | { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2593 | ||
| 2594 | { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2595 | { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2596 | { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2597 | { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2598 | ||
| 2599 | { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2600 | { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2601 | { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2602 | { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2603 | { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2604 | { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2605 | { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, | |
| 2606 | { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, | |
| 2607 | ||
| 2608 | { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2609 | { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2610 | { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2611 | { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2612 | { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2613 | { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2614 | { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2615 | { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2616 | ||
| 2617 | { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, | |
| 2618 | { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, | |
| 2619 | ||
| 2620 | { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } }, | |
| 2621 | ||
| 2622 | { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, | |
| 2623 | ||
| 2624 | { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, | |
| 2625 | { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, | |
| 2626 | ||
| 2627 | { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2628 | { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2629 | { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2630 | { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2631 | ||
| 2632 | { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2633 | { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2634 | { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2635 | { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2636 | { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2637 | { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2638 | { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, | |
| 2639 | { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, | |
| 2640 | ||
| 2641 | { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, | |
| 2642 | { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, | |
| 2643 | ||
| 2644 | { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } }, | |
| 2645 | ||
| 2646 | { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } }, | |
| 2647 | ||
| e0c21649 | 2648 | { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, |
| 252b5132 RH |
2649 | |
| 2650 | { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, | |
| 2651 | { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, | |
| 2652 | ||
| 2653 | { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } }, | |
| 2654 | { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } }, | |
| 2655 | ||
| 2656 | { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, | |
| 2657 | ||
| 2658 | { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, | |
| 2659 | ||
| 2660 | { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, | |
| 2661 | { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, | |
| 2662 | ||
| 2663 | { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, | |
| 2664 | { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, | |
| 2665 | { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, | |
| 2666 | { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, | |
| 2667 | { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, | |
| 2668 | { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, | |
| 2669 | { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, | |
| 2670 | { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, | |
| 2671 | { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, | |
| 2672 | { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, | |
| 2673 | { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, | |
| 2674 | { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, | |
| 2675 | { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, | |
| 2676 | { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, | |
| 2677 | { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, | |
| 2678 | { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, | |
| 2679 | { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, | |
| 2680 | { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, | |
| 2681 | { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, | |
| 2682 | { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, | |
| 2683 | { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, | |
| 2684 | { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, | |
| 2685 | { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, | |
| 2686 | { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, | |
| 2687 | { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, | |
| 2688 | { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, | |
| 2689 | { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, | |
| 2690 | { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, | |
| 2691 | { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, | |
| 2692 | { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, | |
| 2693 | { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, | |
| 2694 | { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, | |
| 2695 | { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, | |
| 2696 | { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, | |
| e0c21649 | 2697 | { "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } }, |
| 252b5132 RH |
2698 | |
| 2699 | { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2700 | { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2701 | { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2702 | { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2703 | ||
| 2704 | { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, | |
| 2705 | { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, | |
| 2706 | { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, | |
| 2707 | { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, | |
| 2708 | { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, | |
| 2709 | { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, | |
| 2710 | { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, | |
| 2711 | { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, | |
| 2712 | { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, | |
| 2713 | { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, | |
| 2714 | { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, | |
| 2715 | { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, | |
| 2716 | { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, | |
| 2717 | { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, | |
| 2718 | { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, | |
| 2719 | { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, | |
| 2720 | { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, | |
| 2721 | { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, | |
| 2722 | { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, | |
| 2723 | { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, | |
| 2724 | { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, | |
| 2725 | { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, | |
| 2726 | { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, | |
| 2727 | { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, | |
| 2728 | { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, | |
| 2729 | { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, | |
| 2730 | { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, | |
| 2731 | { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, | |
| 2732 | { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, | |
| 2733 | { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, | |
| 2734 | { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, | |
| e0c21649 GK |
2735 | { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } }, |
| 2736 | { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, | |
| 2737 | { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, | |
| 2738 | { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } }, | |
| 252b5132 RH |
2739 | { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, |
| 2740 | { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, | |
| 2741 | { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, | |
| 2742 | { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, | |
| 2743 | { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, | |
| 2744 | { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, | |
| 2745 | { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, | |
| 2746 | { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, | |
| 2747 | { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, | |
| 2748 | { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, | |
| 2749 | { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, | |
| 2750 | { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, | |
| 2751 | { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, | |
| 2752 | { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, | |
| 2753 | { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, | |
| 2754 | { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, | |
| 2755 | { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, | |
| 2756 | { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, | |
| 2757 | { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, | |
| 2758 | { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, | |
| 2759 | { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, | |
| 2760 | { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, | |
| 2761 | { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, | |
| 2762 | { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, | |
| 2763 | { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, | |
| 2764 | { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, | |
| 2765 | { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, | |
| 2766 | { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, | |
| 2767 | { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, | |
| 2768 | { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, | |
| 2769 | { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, | |
| 2770 | { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, | |
| 2771 | { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, | |
| 2772 | { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, | |
| 2773 | { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, | |
| 2774 | { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, | |
| 2775 | { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, | |
| 2776 | { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, | |
| 2777 | { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, | |
| 2778 | { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, | |
| e0c21649 GK |
2779 | { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, |
| 2780 | { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, | |
| 2781 | { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, | |
| 2782 | { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, | |
| 252b5132 RH |
2783 | { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, |
| 2784 | { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, | |
| 2785 | { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, | |
| 2786 | { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, | |
| 2787 | { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, | |
| 2788 | { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, | |
| 2789 | { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, | |
| e0c21649 GK |
2790 | { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, |
| 2791 | { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, | |
| 2792 | { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, | |
| 2793 | { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, | |
| 252b5132 RH |
2794 | { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, |
| 2795 | { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, | |
| e0c21649 | 2796 | { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, |
| 252b5132 | 2797 | { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, |
| e0c21649 | 2798 | { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, |
| 252b5132 | 2799 | { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, |
| e0c21649 | 2800 | { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, |
| 252b5132 | 2801 | { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, |
| e0c21649 | 2802 | { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, |
| 252b5132 | 2803 | { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, |
| e0c21649 | 2804 | { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, |
| 252b5132 RH |
2805 | { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, |
| 2806 | { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, | |
| 2807 | { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, | |
| 2808 | { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, | |
| 2809 | { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, | |
| 2810 | { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, | |
| 2811 | { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, | |
| 2812 | { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, | |
| 2813 | { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, | |
| 2814 | { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, | |
| 2815 | { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, | |
| 2816 | { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, | |
| 2817 | { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, | |
| e0c21649 | 2818 | { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, |
| 252b5132 RH |
2819 | { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, |
| 2820 | { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, | |
| 2821 | { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, | |
| 2822 | { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, | |
| 2823 | { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, | |
| 2824 | { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, | |
| 2825 | { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, | |
| 2826 | { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, | |
| 2827 | { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, | |
| 2828 | { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, | |
| 2829 | { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, | |
| 2830 | { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, | |
| 2831 | { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, | |
| 2832 | { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, | |
| 2833 | { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, | |
| 2834 | { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, | |
| 2835 | ||
| 2836 | { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, | |
| 2837 | ||
| 2838 | { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, | |
| 2839 | ||
| e0c21649 | 2840 | { "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } }, |
| 252b5132 RH |
2841 | |
| 2842 | { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, | |
| 2843 | { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, | |
| 2844 | { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, | |
| 2845 | { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, | |
| 2846 | ||
| 2847 | { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2848 | { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2849 | { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, | |
| 2850 | { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, | |
| 2851 | ||
| 2852 | { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, | |
| 2853 | ||
| e0c21649 | 2854 | { "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } }, |
| 252b5132 RH |
2855 | { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, |
| 2856 | { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, | |
| 2857 | ||
| 2858 | { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, | |
| 2859 | ||
| 2860 | { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, | |
| 2861 | ||
| 6ba045b1 AM |
2862 | { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, |
| 2863 | ||
| 252b5132 RH |
2864 | { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, |
| 2865 | ||
| 2866 | { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, | |
| 2867 | ||
| 2868 | { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, | |
| 2869 | ||
| 2870 | { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, | |
| 2871 | ||
| 2872 | { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, | |
| 2873 | ||
| 2874 | { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, | |
| 2875 | { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, | |
| 2876 | ||
| 2877 | { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, | |
| 2878 | { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, | |
| 2879 | ||
| 2880 | { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, | |
| 2881 | ||
| 2882 | { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, | |
| 2883 | ||
| 2884 | { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, | |
| 2885 | ||
| 2886 | { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, | |
| 2887 | { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, | |
| 2888 | { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, | |
| 2889 | { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, | |
| 2890 | ||
| 2891 | { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } }, | |
| 2892 | { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } }, | |
| 2893 | { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } }, | |
| 2894 | { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } }, | |
| 2895 | { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } }, | |
| 2896 | { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } }, | |
| 2897 | { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } }, | |
| 2898 | { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } }, | |
| 2899 | { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } }, | |
| 2900 | { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } }, | |
| 2901 | { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } }, | |
| 2902 | { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } }, | |
| 2903 | { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } }, | |
| 2904 | { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } }, | |
| 2905 | { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } }, | |
| 2906 | { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } }, | |
| 2907 | { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } }, | |
| 2908 | { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } }, | |
| 2909 | { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } }, | |
| 2910 | { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } }, | |
| 2911 | { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } }, | |
| 2912 | { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } }, | |
| 2913 | { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } }, | |
| 2914 | { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } }, | |
| 2915 | { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } }, | |
| 2916 | { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } }, | |
| 2917 | { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } }, | |
| 2918 | { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } }, | |
| 2919 | { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } }, | |
| 2920 | { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } }, | |
| 2921 | { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } }, | |
| 2922 | { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } }, | |
| 2923 | { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } }, | |
| 2924 | { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } }, | |
| e0c21649 | 2925 | { "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } }, |
| 252b5132 RH |
2926 | |
| 2927 | { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2928 | { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2929 | { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2930 | { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 2931 | ||
| 2932 | { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2933 | { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2934 | { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2935 | { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 2936 | ||
| 2937 | { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, | |
| 2938 | { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, | |
| 2939 | { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, | |
| 2940 | { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, | |
| 2941 | { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, | |
| 2942 | { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, | |
| 2943 | { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, | |
| 2944 | { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, | |
| 2945 | { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, | |
| 2946 | { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, | |
| 2947 | { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, | |
| 2948 | { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, | |
| 2949 | { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, | |
| 2950 | { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, | |
| 2951 | { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } }, | |
| 2952 | { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } }, | |
| 2953 | { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } }, | |
| 2954 | { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } }, | |
| 2955 | { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } }, | |
| 2956 | { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } }, | |
| 2957 | { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } }, | |
| 2958 | { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } }, | |
| 2959 | { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } }, | |
| 2960 | { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } }, | |
| 2961 | { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } }, | |
| 2962 | { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } }, | |
| 2963 | { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } }, | |
| 2964 | { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } }, | |
| 2965 | { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } }, | |
| 2966 | { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } }, | |
| 2967 | { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, | |
| 2968 | { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } }, | |
| 2969 | { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } }, | |
| 2970 | { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } }, | |
| 2971 | { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } }, | |
| e0c21649 GK |
2972 | { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } }, |
| 2973 | { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } }, | |
| 2974 | { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } }, | |
| 2975 | { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } }, | |
| 252b5132 RH |
2976 | { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, |
| 2977 | { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, | |
| 2978 | { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, | |
| 2979 | { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, | |
| 2980 | { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, | |
| 2981 | { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, | |
| 2982 | { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, | |
| 2983 | { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, | |
| 2984 | { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } }, | |
| 2985 | { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } }, | |
| e0c21649 GK |
2986 | { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } }, |
| 2987 | { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } }, | |
| 2988 | { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } }, | |
| 2989 | { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } }, | |
| 2990 | { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } }, | |
| 2991 | { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } }, | |
| 2992 | { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } }, | |
| 2993 | { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } }, | |
| 2994 | { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } }, | |
| 2995 | { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } }, | |
| 252b5132 RH |
2996 | { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } }, |
| 2997 | { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } }, | |
| e0c21649 | 2998 | { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } }, |
| 252b5132 RH |
2999 | { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } }, |
| 3000 | { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } }, | |
| 3001 | { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } }, | |
| 3002 | { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } }, | |
| 3003 | { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } }, | |
| 3004 | { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } }, | |
| 3005 | { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } }, | |
| 3006 | { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } }, | |
| 3007 | { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } }, | |
| 3008 | { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } }, | |
| e0c21649 | 3009 | { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } }, |
| 252b5132 RH |
3010 | { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } }, |
| 3011 | { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } }, | |
| 3012 | { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } }, | |
| 3013 | { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } }, | |
| 3014 | { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } }, | |
| 3015 | { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } }, | |
| 3016 | { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } }, | |
| 3017 | { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } }, | |
| 3018 | { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } }, | |
| 3019 | { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } }, | |
| 24a7a601 C |
3020 | { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } }, |
| 3021 | { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } }, | |
| 3022 | { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } }, | |
| 3023 | { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } }, | |
| 3024 | { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } }, | |
| 3025 | { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } }, | |
| 3026 | { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } }, | |
| 3027 | { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } }, | |
| 3028 | { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } }, | |
| 3029 | { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } }, | |
| 3030 | { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } }, | |
| 3031 | { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } }, | |
| 3032 | { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } }, | |
| 3033 | { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } }, | |
| 3034 | { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } }, | |
| 3035 | { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } }, | |
| 3036 | { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } }, | |
| 3037 | { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } }, | |
| 3038 | { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } }, | |
| 252b5132 RH |
3039 | { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, |
| 3040 | ||
| 3041 | { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, | |
| 3042 | ||
| 3043 | { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, | |
| 3044 | { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, | |
| 3045 | ||
| 4db3857a | 3046 | { "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }}, |
| 252b5132 RH |
3047 | |
| 3048 | { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, | |
| 3049 | { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, | |
| 3050 | { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, | |
| 3051 | { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, | |
| 3052 | ||
| 3053 | { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 3054 | { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 3055 | { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 3056 | { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, | |
| 3057 | ||
| 3058 | { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 3059 | { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 3060 | { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, | |
| 3061 | { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, | |
| 3062 | ||
| 3063 | { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, | |
| 3064 | ||
| 3065 | { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, | |
| 3066 | ||
| 3067 | { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, | |
| 3068 | ||
| 3069 | { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, | |
| 3070 | ||
| 3071 | { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } }, | |
| 3072 | { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, | |
| 3073 | ||
| 3074 | { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } }, | |
| 3075 | { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, | |
| 3076 | ||
| 3077 | { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } }, | |
| 3078 | ||
| 3079 | { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, | |
| 3080 | { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, | |
| 3081 | { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, | |
| 3082 | { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, | |
| 3083 | ||
| 3084 | { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3085 | { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3086 | ||
| 3087 | { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, | |
| 3088 | { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, | |
| 3089 | ||
| 3090 | { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3091 | { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3092 | ||
| 3093 | { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, | |
| 3094 | ||
| 3095 | { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, | |
| 3096 | ||
| 3097 | { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, | |
| 3098 | ||
| 3099 | { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, | |
| 3100 | { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } }, | |
| 3101 | ||
| 6ba045b1 AM |
3102 | { "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } }, |
| 3103 | { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, | |
| 3104 | { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, | |
| 252b5132 RH |
3105 | { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, |
| 3106 | ||
| 3107 | { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, | |
| 3108 | ||
| 3109 | { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, | |
| 3110 | ||
| 3111 | { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, | |
| 3112 | ||
| 3113 | { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, | |
| 3114 | ||
| 3115 | { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, | |
| 3116 | ||
| 3117 | { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } }, | |
| 3118 | { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } }, | |
| 3119 | ||
| 3120 | { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } }, | |
| 3121 | { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } }, | |
| 3122 | ||
| 3123 | { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } }, | |
| 3124 | ||
| 3125 | { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3126 | { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3127 | ||
| 3128 | { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3129 | { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3130 | ||
| 3131 | { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, | |
| 3132 | ||
| 3133 | { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, | |
| 3134 | { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, | |
| 3135 | ||
| 3136 | { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } }, | |
| 3137 | { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } }, | |
| 3138 | ||
| 3139 | { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } }, | |
| 3140 | ||
| 3141 | { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3142 | { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3143 | ||
| 3144 | { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3145 | { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3146 | ||
| e0c21649 GK |
3147 | { "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } }, |
| 3148 | ||
| 252b5132 RH |
3149 | { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, |
| 3150 | ||
| 3151 | { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, | |
| 3152 | { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, | |
| 3153 | ||
| 3154 | { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } }, | |
| 3155 | ||
| 3156 | { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, | |
| 3157 | { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, | |
| 3158 | { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, | |
| 3159 | { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, | |
| 3160 | ||
| 3161 | { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, | |
| 3162 | { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, | |
| 3163 | ||
| 3164 | { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, | |
| 3165 | ||
| 3166 | { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, | |
| 3167 | { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, | |
| 3168 | { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, | |
| 3169 | { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, | |
| 3170 | ||
| 6ba045b1 AM |
3171 | { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, |
| 3172 | ||
| 252b5132 RH |
3173 | { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, |
| 3174 | ||
| 3175 | { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, | |
| 3176 | { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, | |
| 3177 | ||
| 6ba045b1 AM |
3178 | { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, |
| 3179 | ||
| 252b5132 RH |
3180 | { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } }, |
| 3181 | ||
| 3182 | { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3183 | { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3184 | ||
| 3185 | { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, | |
| 3186 | { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, | |
| 3187 | ||
| 3188 | { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, | |
| 3189 | { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, | |
| 3190 | { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, | |
| 3191 | { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, | |
| 3192 | ||
| e0c21649 GK |
3193 | { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, |
| 3194 | { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, | |
| 252b5132 RH |
3195 | { "tlbre", X(31,946), X_MASK, PPC403, { RT, RA, SH } }, |
| 3196 | ||
| 3197 | { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, | |
| 3198 | { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, | |
| 3199 | ||
| 3200 | { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, | |
| 3201 | { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, | |
| 3202 | ||
| e0c21649 | 3203 | { "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } }, |
| 252b5132 RH |
3204 | |
| 3205 | { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, | |
| e0c21649 GK |
3206 | |
| 3207 | { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, | |
| 3208 | { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, | |
| 252b5132 RH |
3209 | { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } }, |
| 3210 | ||
| 3211 | { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, | |
| 3212 | ||
| 3213 | { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, | |
| 3214 | ||
| 3215 | { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } }, | |
| 3216 | { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } }, | |
| 3217 | ||
| 3218 | { "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } }, | |
| 3219 | ||
| 3220 | { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, | |
| 3221 | ||
| 3222 | { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, | |
| 3223 | { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, | |
| 3224 | ||
| 786e2c0f C |
3225 | { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 3226 | { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, | |
| 3227 | { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, | |
| 3228 | { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, | |
| 3229 | { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, | |
| 3230 | { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, | |
| 3231 | { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, | |
| 3232 | { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, | |
| 3233 | { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, | |
| 3234 | { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, | |
| 3235 | { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, | |
| 3236 | { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, | |
| 3237 | ||
| 252b5132 RH |
3238 | { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } }, |
| 3239 | { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } }, | |
| 3240 | ||
| 3241 | { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, | |
| 3242 | { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } }, | |
| 3243 | ||
| 3244 | { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } }, | |
| 3245 | ||
| 3246 | { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, | |
| 3247 | ||
| 3248 | { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } }, | |
| 3249 | { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } }, | |
| 3250 | ||
| 3251 | { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, | |
| 3252 | { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } }, | |
| 3253 | ||
| 3254 | { "stb", OP(38), OP_MASK, COM, { RS, D, RA } }, | |
| 3255 | ||
| 3256 | { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, | |
| 3257 | ||
| 3258 | { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } }, | |
| 3259 | ||
| 3260 | { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, | |
| 3261 | ||
| 3262 | { "lha", OP(42), OP_MASK, COM, { RT, D, RA } }, | |
| 3263 | ||
| 3264 | { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, | |
| 3265 | ||
| 3266 | { "sth", OP(44), OP_MASK, COM, { RS, D, RA } }, | |
| 3267 | ||
| 3268 | { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, | |
| 3269 | ||
| 3270 | { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, | |
| 3271 | { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } }, | |
| 3272 | ||
| 3273 | { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } }, | |
| 3274 | { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } }, | |
| 3275 | ||
| 3276 | { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } }, | |
| 3277 | ||
| 3278 | { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, | |
| 3279 | ||
| 3280 | { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } }, | |
| 3281 | ||
| 3282 | { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, | |
| 3283 | ||
| 3284 | { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } }, | |
| 3285 | ||
| 3286 | { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, | |
| 3287 | ||
| 3288 | { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } }, | |
| 3289 | ||
| 3290 | { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, | |
| 3291 | ||
| 3292 | { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, | |
| 3293 | ||
| 3294 | { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, | |
| 3295 | ||
| 3296 | { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } }, | |
| 3297 | ||
| 3298 | { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, | |
| 3299 | ||
| 3300 | { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } }, | |
| 3301 | ||
| 3302 | { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, | |
| 3303 | { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, | |
| 3304 | ||
| 3305 | { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, | |
| 3306 | { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, | |
| 3307 | ||
| 3308 | { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, | |
| 3309 | { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, | |
| 3310 | ||
| 3311 | { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, | |
| 3312 | { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, | |
| 3313 | ||
| 3314 | { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, | |
| 3315 | { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, | |
| 3316 | ||
| 3317 | { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, | |
| 3318 | { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, | |
| 3319 | ||
| 3320 | { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3321 | { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3322 | ||
| 3323 | { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3324 | { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3325 | ||
| 3326 | { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3327 | { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3328 | ||
| 3329 | { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3330 | { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3331 | ||
| 3332 | { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, | |
| 3333 | ||
| 3334 | { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, | |
| 3335 | ||
| 3336 | { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } }, | |
| 3337 | ||
| 3338 | { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, | |
| 3339 | ||
| 3340 | { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, | |
| 3341 | ||
| 3342 | { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, | |
| 3343 | { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, | |
| 3344 | ||
| 3345 | { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, | |
| 3346 | { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, | |
| 3347 | { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, | |
| 3348 | { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, | |
| 3349 | ||
| 3350 | { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, | |
| 3351 | { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, | |
| 3352 | { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, | |
| 3353 | { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, | |
| 3354 | ||
| 3355 | { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, | |
| 3356 | { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, | |
| 3357 | { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, | |
| 3358 | { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, | |
| 3359 | ||
| 3360 | { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, | |
| 3361 | { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, | |
| 3362 | { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, | |
| 3363 | { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, | |
| 3364 | ||
| 3365 | { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, | |
| 3366 | { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, | |
| 3367 | { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, | |
| 3368 | { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, | |
| 3369 | ||
| 3370 | { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, | |
| 3371 | { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, | |
| 3372 | ||
| 3373 | { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3374 | { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, | |
| 3375 | ||
| 3376 | { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, | |
| 3377 | { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, | |
| 3378 | { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, | |
| 3379 | { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, | |
| 3380 | ||
| 3381 | { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, | |
| 3382 | { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, | |
| 3383 | ||
| 3384 | { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3385 | { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3386 | { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3387 | { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3388 | ||
| 3389 | { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3390 | { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3391 | { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3392 | { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3393 | ||
| 3394 | { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3395 | { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3396 | { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3397 | { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3398 | ||
| 3399 | { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3400 | { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3401 | { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, | |
| 3402 | { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, | |
| 3403 | ||
| 3404 | { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, | |
| 3405 | ||
| 3406 | { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, | |
| 3407 | { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, | |
| 3408 | ||
| 3409 | { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, | |
| 3410 | { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, | |
| 3411 | ||
| 3412 | { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, | |
| 3413 | ||
| 3414 | { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, | |
| 3415 | { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, | |
| 3416 | ||
| 3417 | { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, | |
| 3418 | { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, | |
| 3419 | ||
| 3420 | { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, | |
| 3421 | { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, | |
| 3422 | ||
| 3423 | { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, | |
| 3424 | { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, | |
| 3425 | ||
| 3426 | { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, | |
| 3427 | { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, | |
| 3428 | ||
| 3429 | { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, | |
| 3430 | { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, | |
| 3431 | ||
| 3432 | { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, | |
| 3433 | { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, | |
| 3434 | ||
| 3435 | { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, | |
| 3436 | { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, | |
| 3437 | ||
| 3438 | { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, | |
| 3439 | { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, | |
| 3440 | ||
| 3441 | { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, | |
| 3442 | { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, | |
| 3443 | ||
| 3444 | }; | |
| 3445 | ||
| 3446 | const int powerpc_num_opcodes = | |
| 3447 | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); | |
| 3448 | \f | |
| 3449 | /* The macro table. This is only used by the assembler. */ | |
| 3450 | ||
| 3451 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 | |
| 3452 | when x=0; 32-x when x is between 1 and 31; are negative if x is | |
| 3453 | negative; and are 32 or more otherwise. This is what you want | |
| 3454 | when, for instance, you are emulating a right shift by a | |
| 3455 | rotate-left-and-mask, because the underlying instructions support | |
| 3456 | shifts of size 0 but not shifts of size 32. By comparison, when | |
| 3457 | extracting x bits from some word you want to use just 32-x, because | |
| 3458 | the underlying instructions don't support extracting 0 bits but do | |
| 3459 | support extracting the whole word (32 bits in this case). */ | |
| 3460 | ||
| 3461 | const struct powerpc_macro powerpc_macros[] = { | |
| 3462 | { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, | |
| 3463 | { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, | |
| 3464 | { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, | |
| 3465 | { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, | |
| 3466 | { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, | |
| 3467 | { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, | |
| 3468 | { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, | |
| 3469 | { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, | |
| 3470 | { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, | |
| 3471 | { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, | |
| 3472 | { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, | |
| 3473 | { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, | |
| 3474 | { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, | |
| 3475 | { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, | |
| 3476 | { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, | |
| 3477 | { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, | |
| 3478 | ||
| 3479 | { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, | |
| 3480 | { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, | |
| 3481 | { "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, | |
| 3482 | { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, | |
| 3483 | { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, | |
| 3484 | { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, | |
| 3485 | { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, | |
| 3486 | { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, | |
| 3487 | { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, | |
| 3488 | { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, | |
| 3489 | { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, | |
| 3490 | { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, | |
| 3491 | { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, | |
| 3492 | { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, | |
| 3493 | { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, | |
| 3494 | { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, | |
| 3495 | { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, | |
| 3496 | { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, | |
| 3497 | { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, | |
| 3498 | { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, | |
| 3499 | { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, | |
| 3500 | { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, | |
| 3501 | ||
| 3502 | }; | |
| 3503 | ||
| 3504 | const int powerpc_num_macros = | |
| 3505 | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); |