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Add support for sparc compare-and-branch instructions.
[binutils.git] / gas / config / tc-sparc.c
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252b5132 1/* tc-sparc.c -- Assemble for the SPARC
f7e42eb4 2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
9e8c70f9
DM		 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011
e0c6ed95 5 Free Software Foundation, Inc.
252b5132
RH		 6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
4b4da160
NC		 20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "subsegs.h"
26
27#include "opcode/sparc.h"
364b6d8b 28#include "dw2gencfi.h"
252b5132
RH		 29
30#ifdef OBJ_ELF
31#include "elf/sparc.h"
732d96b6 32#include "dwarf2dbg.h"
252b5132
RH		 33#endif
34
6c1b24e4
AO		 35/* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38#define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39#define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40
5a49b8ac
AM		 41static int sparc_ip (char *, const struct sparc_opcode **);
42static int parse_keyword_arg (int (*) (const char *), char **, int *);
43static int parse_const_expr_arg (char **, int *);
44static int get_expression (char *);
252b5132
RH		 45
46/* Default architecture. */
47/* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
50#ifndef DEFAULT_ARCH
51#define DEFAULT_ARCH "sparclite"
52#endif
53static char *default_arch = DEFAULT_ARCH;
54
55/* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 have been set. */
57static int default_init_p;
58
59/* Current architecture. We don't bump up unless necessary. */
60static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
61
62/* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67static enum sparc_opcode_arch_val max_architecture;
68
69/* Either 32 or 64, selects file format. */
70static int sparc_arch_size;
71/* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73static int default_arch_size;
74
75#ifdef OBJ_ELF
76/* The currently selected v9 memory model. Currently only used for
77 ELF. */
78static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
9e8c70f9
DM		 79
80#ifndef TE_SOLARIS
81/* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83static int hwcap_seen;
84#endif
252b5132
RH		 85#endif
86
4bafe00e
DM		 87static int hwcap_allowed;
88
252b5132
RH		 89static int architecture_requested;
90static int warn_on_bump;
91
92/* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94static enum sparc_opcode_arch_val warn_after_architecture;
95
6d8809aa
RH		 96/* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98static int no_undeclared_regs;
99
6faf3d66
JJ		 100/* Non-zero if we should try to relax jumps and calls. */
101static int sparc_relax;
102
252b5132
RH		 103/* Non-zero if we are generating PIC code. */
104int sparc_pic_code;
105
106/* Non-zero if we should give an error when misaligned data is seen. */
107static int enforce_aligned_data;
108
109extern int target_big_endian;
110
111static int target_little_endian_data;
112
6d8809aa
RH		 113/* Symbols for global registers on v9. */
114static symbolS *globals[8];
115
364b6d8b
JJ		 116/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117int sparc_cie_data_alignment;
118
252b5132
RH		 119/* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123#ifndef INSN_BIG_ENDIAN
124#define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127#endif
128
e0c6ed95 129/* Handle of the OPCODE hash table. */
252b5132
RH		 130static struct hash_control *op_hash;
131
5a49b8ac
AM		 132static void s_data1 (void);
133static void s_seg (int);
134static void s_proc (int);
135static void s_reserve (int);
136static void s_common (int);
137static void s_empty (int);
138static void s_uacons (int);
139static void s_ncons (int);
a7982600 140#ifdef OBJ_ELF
5a49b8ac 141static void s_register (int);
a7982600 142#endif
252b5132
RH		 143
144const pseudo_typeS md_pseudo_table[] =
145{
e0c6ed95 146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
252b5132
RH		 147 {"common", s_common, 0},
148 {"empty", s_empty, 0},
149 {"global", s_globl, 0},
150 {"half", cons, 2},
cf9a1301 151 {"nword", s_ncons, 0},
252b5132
RH		 152 {"optim", s_ignore, 0},
153 {"proc", s_proc, 0},
154 {"reserve", s_reserve, 0},
155 {"seg", s_seg, 0},
156 {"skip", s_space, 0},
157 {"word", cons, 4},
158 {"xword", cons, 8},
159 {"uahalf", s_uacons, 2},
160 {"uaword", s_uacons, 4},
161 {"uaxword", s_uacons, 8},
162#ifdef OBJ_ELF
e0c6ed95 163 /* These are specific to sparc/svr4. */
252b5132
RH		 164 {"2byte", s_uacons, 2},
165 {"4byte", s_uacons, 4},
166 {"8byte", s_uacons, 8},
6d8809aa 167 {"register", s_register, 0},
252b5132
RH		 168#endif
169 {NULL, 0, 0},
170};
171
252b5132 172/* This array holds the chars that always start a comment. If the
e0c6ed95
AM		 173 pre-processor is disabled, these aren't very useful. */
174const char comment_chars[] = "!"; /* JF removed '|' from
175 comment_chars. */
252b5132
RH		 176
177/* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
e0c6ed95 179 .line and .file directives will appear in the pre-processed output. */
252b5132
RH		 180/* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
e0c6ed95 182 #NO_APP at the beginning of its output. */
252b5132 183/* Also note that comments started like this one will always
e0c6ed95 184 work if '/' isn't otherwise defined. */
252b5132
RH		 185const char line_comment_chars[] = "#";
186
63a0b638 187const char line_separator_chars[] = ";";
252b5132 188
e0c6ed95
AM		 189/* Chars that can be used to separate mant from exp in floating point
190 nums. */
252b5132
RH		 191const char EXP_CHARS[] = "eE";
192
e0c6ed95
AM		 193/* Chars that mean this number is a floating point constant.
194 As in 0f12.456
195 or 0d1.2345e12 */
252b5132
RH		 196const char FLT_CHARS[] = "rRsSfFdDxXpP";
197
198/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
201
74b56d1f 202#define isoctal(c) ((unsigned) ((c) - '0') < 8)
252b5132
RH		 203
204struct sparc_it
205 {
206 char *error;
207 unsigned long opcode;
208 struct nlist *nlistp;
209 expressionS exp;
cf9a1301 210 expressionS exp2;
252b5132
RH		 211 int pcrel;
212 bfd_reloc_code_real_type reloc;
213 };
214
215struct sparc_it the_insn, set_insn;
216
5a49b8ac 217static void output_insn (const struct sparc_opcode *, struct sparc_it *);
252b5132
RH		 218\f
219/* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
222 and file formats. */
223
224enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
19f7b010 225 v8plusa, v9, v9a, v9b, v9_64};
252b5132
RH		 226
227static struct sparc_arch {
228 char *name;
229 char *opcode_arch;
230 enum sparc_arch_types arch_type;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size;
234 /* Allowable arg to -A? */
235 int user_option_p;
4bafe00e 236 int hwcap_allowed;
252b5132 237} sparc_arch_table[] = {
4bafe00e
DM		 238 { "v6", "v6", v6, 0, 1, 0 },
239 { "v7", "v7", v7, 0, 1, 0 },
ec668d69
DM		 240 { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
241 { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
242 { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
243 { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
244 { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
245 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
246 { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
247 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
698544e1 248 { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
ec668d69
DM		 249 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
250 { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
251 { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
252 { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
253 { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
254 { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
255 { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
256 { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
257 { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
698544e1
DM		 258 { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
259 { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
ec668d69
DM		 260 { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
261 { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
262 { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
263 { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
264 { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
698544e1
DM		 265 { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
266 { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND },
252b5132
RH		 267 /* This exists to allow configure.in/Makefile.in to pass one
268 value to specify both the default machine and default word size. */
ec668d69 269 { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
4bafe00e 270 { NULL, NULL, v8, 0, 0, 0 }
252b5132
RH		 271};
272
273/* Variant of default_arch */
274static enum sparc_arch_types default_arch_type;
275
276static struct sparc_arch *
5a49b8ac 277lookup_arch (char *name)
252b5132
RH		 278{
279 struct sparc_arch *sa;
280
281 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
282 if (strcmp (sa->name, name) == 0)
283 break;
284 if (sa->name == NULL)
285 return NULL;
286 return sa;
287}
288
289/* Initialize the default opcode arch and word size from the default
290 architecture name. */
291
292static void
5a49b8ac 293init_default_arch (void)
252b5132
RH		 294{
295 struct sparc_arch *sa = lookup_arch (default_arch);
296
297 if (sa == NULL
298 || sa->default_arch_size == 0)
299 as_fatal (_("Invalid default architecture, broken assembler."));
300
301 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
302 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
303 as_fatal (_("Bad opcode table, broken assembler."));
304 default_arch_size = sparc_arch_size = sa->default_arch_size;
305 default_init_p = 1;
306 default_arch_type = sa->arch_type;
307}
308
309/* Called by TARGET_FORMAT. */
310
311const char *
5a49b8ac 312sparc_target_format (void)
252b5132
RH		 313{
314 /* We don't get a chance to initialize anything before we're called,
315 so handle that now. */
316 if (! default_init_p)
317 init_default_arch ();
318
319#ifdef OBJ_AOUT
320#ifdef TE_NetBSD
321 return "a.out-sparc-netbsd";
322#else
323#ifdef TE_SPARCAOUT
324 if (target_big_endian)
325 return "a.out-sunos-big";
326 else if (default_arch_type == sparc86x && target_little_endian_data)
327 return "a.out-sunos-big";
ab3e48dc
KH		 328 else
329 return "a.out-sparc-little";
252b5132
RH		 330#else
331 return "a.out-sunos-big";
332#endif
333#endif
334#endif
335
336#ifdef OBJ_BOUT
337 return "b.out.big";
338#endif
339
340#ifdef OBJ_COFF
341#ifdef TE_LYNX
342 return "coff-sparc-lynx";
343#else
344 return "coff-sparc";
345#endif
346#endif
347
910600e9
RS		 348#ifdef TE_VXWORKS
349 return "elf32-sparc-vxworks";
350#endif
351
252b5132 352#ifdef OBJ_ELF
71a75f6f 353 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
252b5132
RH		 354#endif
355
356 abort ();
357}
358\f
e0c6ed95 359/* md_parse_option
252b5132
RH		 360 * Invocation line includes a switch not recognized by the base assembler.
361 * See if it's a processor-specific option. These are:
362 *
363 * -bump
364 * Warn on architecture bumps. See also -A.
365 *
366 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
367 * Standard 32 bit architectures.
19f7b010 368 * -Av9, -Av9a, -Av9b
252b5132
RH		 369 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
370 * This used to only mean 64 bits, but properly specifying it
371 * complicated gcc's ASM_SPECs, so now opcode selection is
372 * specified orthogonally to word size (except when specifying
373 * the default, but that is an internal implementation detail).
19f7b010
JJ		 374 * -Av8plus, -Av8plusa, -Av8plusb
375 * Same as -Av9{,a,b}.
376 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
377 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
378 * assembler.
379 * -xarch=v9, -xarch=v9a, -xarch=v9b
380 * Same as -Av9{,a,b} -64, for compatibility with Sun's
c2158c24 381 * assembler.
252b5132
RH		 382 *
383 * Select the architecture and possibly the file format.
384 * Instructions or features not supported by the selected
385 * architecture cause fatal errors.
386 *
387 * The default is to start at v6, and bump the architecture up
388 * whenever an instruction is seen at a higher level. In 32 bit
389 * environments, v9 is not bumped up to, the user must pass
19f7b010 390 * -Av8plus{,a,b}.
252b5132
RH		 391 *
392 * If -bump is specified, a warning is printing when bumping to
393 * higher levels.
394 *
395 * If an architecture is specified, all instructions must match
396 * that architecture. Any higher level instructions are flagged
397 * as errors. Note that in the 32 bit environment specifying
398 * -Av8plus does not automatically create a v8plus object file, a
399 * v9 insn must be seen.
400 *
401 * If both an architecture and -bump are specified, the
402 * architecture starts at the specified level, but bumps are
403 * warnings. Note that we can't set `current_architecture' to
404 * the requested level in this case: in the 32 bit environment,
405 * we still must avoid creating v8plus object files unless v9
406 * insns are seen.
407 *
408 * Note:
409 * Bumping between incompatible architectures is always an
410 * error. For example, from sparclite to v9.
411 */
412
413#ifdef OBJ_ELF
5a38dc70 414const char *md_shortopts = "A:K:VQ:sq";
252b5132
RH		 415#else
416#ifdef OBJ_AOUT
5a38dc70 417const char *md_shortopts = "A:k";
252b5132 418#else
5a38dc70 419const char *md_shortopts = "A:";
252b5132
RH		 420#endif
421#endif
422struct option md_longopts[] = {
423#define OPTION_BUMP (OPTION_MD_BASE)
424 {"bump", no_argument, NULL, OPTION_BUMP},
425#define OPTION_SPARC (OPTION_MD_BASE + 1)
426 {"sparc", no_argument, NULL, OPTION_SPARC},
427#define OPTION_XARCH (OPTION_MD_BASE + 2)
428 {"xarch", required_argument, NULL, OPTION_XARCH},
429#ifdef OBJ_ELF
430#define OPTION_32 (OPTION_MD_BASE + 3)
431 {"32", no_argument, NULL, OPTION_32},
432#define OPTION_64 (OPTION_MD_BASE + 4)
433 {"64", no_argument, NULL, OPTION_64},
434#define OPTION_TSO (OPTION_MD_BASE + 5)
435 {"TSO", no_argument, NULL, OPTION_TSO},
436#define OPTION_PSO (OPTION_MD_BASE + 6)
437 {"PSO", no_argument, NULL, OPTION_PSO},
438#define OPTION_RMO (OPTION_MD_BASE + 7)
439 {"RMO", no_argument, NULL, OPTION_RMO},
440#endif
441#ifdef SPARC_BIENDIAN
442#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
443 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
444#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
445 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
446#endif
447#define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
448 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
449#define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
450 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
6d8809aa
RH		 451#ifdef OBJ_ELF
452#define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
453 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
a25fe906
ILT		 454#define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
455 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
6d8809aa 456#endif
6faf3d66
JJ		 457#define OPTION_RELAX (OPTION_MD_BASE + 14)
458 {"relax", no_argument, NULL, OPTION_RELAX},
459#define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
460 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
252b5132
RH		 461 {NULL, no_argument, NULL, 0}
462};
e0c6ed95
AM		 463
464size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 465
466int
5a49b8ac 467md_parse_option (int c, char *arg)
252b5132
RH		 468{
469 /* We don't get a chance to initialize anything before we're called,
470 so handle that now. */
471 if (! default_init_p)
472 init_default_arch ();
473
474 switch (c)
475 {
476 case OPTION_BUMP:
477 warn_on_bump = 1;
478 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
479 break;
480
481 case OPTION_XARCH:
c2158c24
JJ		 482#ifdef OBJ_ELF
483 if (strncmp (arg, "v9", 2) != 0)
484 md_parse_option (OPTION_32, NULL);
485 else
486 md_parse_option (OPTION_64, NULL);
487#endif
e0c6ed95 488 /* Fall through. */
252b5132
RH		 489
490 case 'A':
491 {
492 struct sparc_arch *sa;
493 enum sparc_opcode_arch_val opcode_arch;
494
495 sa = lookup_arch (arg);
496 if (sa == NULL
497 || ! sa->user_option_p)
498 {
c2158c24
JJ		 499 if (c == OPTION_XARCH)
500 as_bad (_("invalid architecture -xarch=%s"), arg);
501 else
502 as_bad (_("invalid architecture -A%s"), arg);
252b5132
RH		 503 return 0;
504 }
505
506 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
507 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
508 as_fatal (_("Bad opcode table, broken assembler."));
509
4bafe00e
DM		 510 if (!architecture_requested
511 || opcode_arch > max_architecture)
512 max_architecture = opcode_arch;
513 hwcap_allowed |= sa->hwcap_allowed;
252b5132
RH		 514 architecture_requested = 1;
515 }
516 break;
517
518 case OPTION_SPARC:
519 /* Ignore -sparc, used by SunOS make default .s.o rule. */
520 break;
521
522 case OPTION_ENFORCE_ALIGNED_DATA:
523 enforce_aligned_data = 1;
524 break;
525
526#ifdef SPARC_BIENDIAN
527 case OPTION_LITTLE_ENDIAN:
528 target_big_endian = 0;
529 if (default_arch_type != sparclet)
530 as_fatal ("This target does not support -EL");
531 break;
532 case OPTION_LITTLE_ENDIAN_DATA:
533 target_little_endian_data = 1;
534 target_big_endian = 0;
535 if (default_arch_type != sparc86x
536 && default_arch_type != v9)
537 as_fatal ("This target does not support --little-endian-data");
538 break;
539 case OPTION_BIG_ENDIAN:
540 target_big_endian = 1;
541 break;
542#endif
543
544#ifdef OBJ_AOUT
545 case 'k':
546 sparc_pic_code = 1;
547 break;
548#endif
549
550#ifdef OBJ_ELF
551 case OPTION_32:
552 case OPTION_64:
553 {
554 const char **list, **l;
555
556 sparc_arch_size = c == OPTION_32 ? 32 : 64;
557 list = bfd_target_list ();
558 for (l = list; *l != NULL; l++)
559 {
560 if (sparc_arch_size == 32)
561 {
71a75f6f 562 if (CONST_STRNEQ (*l, "elf32-sparc"))
252b5132
RH		 563 break;
564 }
565 else
566 {
71a75f6f 567 if (CONST_STRNEQ (*l, "elf64-sparc"))
252b5132
RH		 568 break;
569 }
570 }
571 if (*l == NULL)
572 as_fatal (_("No compiled in support for %d bit object file format"),
573 sparc_arch_size);
574 free (list);
b7cac25f
DM		 575
576 if (sparc_arch_size == 64
577 && max_architecture < SPARC_OPCODE_ARCH_V9)
578 max_architecture = SPARC_OPCODE_ARCH_V9;
252b5132
RH		 579 }
580 break;
581
582 case OPTION_TSO:
583 sparc_memory_model = MM_TSO;
584 break;
585
586 case OPTION_PSO:
587 sparc_memory_model = MM_PSO;
588 break;
589
590 case OPTION_RMO:
591 sparc_memory_model = MM_RMO;
592 break;
593
594 case 'V':
595 print_version_id ();
596 break;
597
598 case 'Q':
599 /* Qy - do emit .comment
e0c6ed95 600 Qn - do not emit .comment. */
252b5132
RH		 601 break;
602
603 case 's':
e0c6ed95 604 /* Use .stab instead of .stab.excl. */
252b5132
RH		 605 break;
606
607 case 'q':
e0c6ed95 608 /* quick -- Native assembler does fewer checks. */
252b5132
RH		 609 break;
610
611 case 'K':
612 if (strcmp (arg, "PIC") != 0)
613 as_warn (_("Unrecognized option following -K"));
614 else
615 sparc_pic_code = 1;
616 break;
6d8809aa
RH		 617
618 case OPTION_NO_UNDECLARED_REGS:
619 no_undeclared_regs = 1;
620 break;
a25fe906
ILT		 621
622 case OPTION_UNDECLARED_REGS:
623 no_undeclared_regs = 0;
624 break;
252b5132
RH		 625#endif
626
6faf3d66
JJ		 627 case OPTION_RELAX:
628 sparc_relax = 1;
629 break;
630
631 case OPTION_NO_RELAX:
632 sparc_relax = 0;
633 break;
634
252b5132
RH		 635 default:
636 return 0;
637 }
638
639 return 1;
640}
641
642void
5a49b8ac 643md_show_usage (FILE *stream)
252b5132
RH		 644{
645 const struct sparc_arch *arch;
c2158c24 646 int column;
252b5132
RH		 647
648 /* We don't get a chance to initialize anything before we're called,
649 so handle that now. */
650 if (! default_init_p)
651 init_default_arch ();
652
e0c6ed95 653 fprintf (stream, _("SPARC options:\n"));
c2158c24 654 column = 0;
252b5132
RH		 655 for (arch = &sparc_arch_table[0]; arch->name; arch++)
656 {
c2158c24
JJ		 657 if (!arch->user_option_p)
658 continue;
252b5132
RH		 659 if (arch != &sparc_arch_table[0])
660 fprintf (stream, " | ");
07726851 661 if (column + strlen (arch->name) > 70)
c2158c24
JJ		 662 {
663 column = 0;
664 fputc ('\n', stream);
665 }
07726851 666 column += 5 + 2 + strlen (arch->name);
c2158c24 667 fprintf (stream, "-A%s", arch->name);
252b5132 668 }
c2158c24
JJ		 669 for (arch = &sparc_arch_table[0]; arch->name; arch++)
670 {
671 if (!arch->user_option_p)
672 continue;
673 fprintf (stream, " | ");
07726851 674 if (column + strlen (arch->name) > 65)
c2158c24
JJ		 675 {
676 column = 0;
677 fputc ('\n', stream);
678 }
07726851 679 column += 5 + 7 + strlen (arch->name);
c2158c24
JJ		 680 fprintf (stream, "-xarch=%s", arch->name);
681 }
682 fprintf (stream, _("\n\
252b5132
RH		 683 specify variant of SPARC architecture\n\
684-bump warn when assembler switches architectures\n\
685-sparc ignored\n\
6faf3d66
JJ		 686--enforce-aligned-data force .long, etc., to be aligned correctly\n\
687-relax relax jumps and branches (default)\n\
688-no-relax avoid changing any jumps and branches\n"));
252b5132
RH		 689#ifdef OBJ_AOUT
690 fprintf (stream, _("\
691-k generate PIC\n"));
692#endif
693#ifdef OBJ_ELF
694 fprintf (stream, _("\
695-32 create 32 bit object file\n\
696-64 create 64 bit object file\n"));
697 fprintf (stream, _("\
698 [default is %d]\n"), default_arch_size);
699 fprintf (stream, _("\
700-TSO use Total Store Ordering\n\
701-PSO use Partial Store Ordering\n\
702-RMO use Relaxed Memory Ordering\n"));
703 fprintf (stream, _("\
704 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
705 fprintf (stream, _("\
706-KPIC generate PIC\n\
707-V print assembler version number\n\
a25fe906
ILT		 708-undeclared-regs ignore application global register usage without\n\
709 appropriate .register directive (default)\n\
710-no-undeclared-regs force error on application global register usage\n\
711 without appropriate .register directive\n\
252b5132
RH		 712-q ignored\n\
713-Qy, -Qn ignored\n\
714-s ignored\n"));
715#endif
716#ifdef SPARC_BIENDIAN
717 fprintf (stream, _("\
718-EL generate code for a little endian machine\n\
719-EB generate code for a big endian machine\n\
720--little-endian-data generate code for a machine having big endian\n\
c20f4f8c 721 instructions and little endian data.\n"));
252b5132
RH		 722#endif
723}
724\f
e0c6ed95 725/* Native operand size opcode translation. */
cf9a1301
RH		 726struct
727 {
728 char *name;
729 char *name32;
730 char *name64;
731 } native_op_table[] =
732{
733 {"ldn", "ld", "ldx"},
734 {"ldna", "lda", "ldxa"},
735 {"stn", "st", "stx"},
736 {"stna", "sta", "stxa"},
737 {"slln", "sll", "sllx"},
738 {"srln", "srl", "srlx"},
739 {"sran", "sra", "srax"},
740 {"casn", "cas", "casx"},
741 {"casna", "casa", "casxa"},
742 {"clrn", "clr", "clrx"},
743 {NULL, NULL, NULL},
744};
745\f
10156f83 746/* sparc64 privileged and hyperprivileged registers. */
252b5132
RH		 747
748struct priv_reg_entry
ab3e48dc
KH		 749{
750 char *name;
751 int regnum;
752};
252b5132
RH		 753
754struct priv_reg_entry priv_reg_table[] =
755{
756 {"tpc", 0},
757 {"tnpc", 1},
758 {"tstate", 2},
759 {"tt", 3},
760 {"tick", 4},
761 {"tba", 5},
762 {"pstate", 6},
763 {"tl", 7},
764 {"pil", 8},
765 {"cwp", 9},
766 {"cansave", 10},
767 {"canrestore", 11},
768 {"cleanwin", 12},
769 {"otherwin", 13},
770 {"wstate", 14},
771 {"fq", 15},
10156f83 772 {"gl", 16},
252b5132 773 {"ver", 31},
e0c6ed95 774 {"", -1}, /* End marker. */
252b5132
RH		 775};
776
10156f83
DM		 777struct priv_reg_entry hpriv_reg_table[] =
778{
779 {"hpstate", 0},
780 {"htstate", 1},
781 {"hintp", 3},
782 {"htba", 5},
783 {"hver", 6},
784 {"hstick_cmpr", 31},
785 {"", -1}, /* End marker. */
786};
787
1a6b486f
DM		 788/* v9a specific asrs. This table is ordered by initial
789 letter, in reverse. */
252b5132
RH		 790
791struct priv_reg_entry v9a_asr_table[] =
792{
793 {"tick_cmpr", 23},
19f7b010
JJ		 794 {"sys_tick_cmpr", 25},
795 {"sys_tick", 24},
1a6b486f
DM		 796 {"stick_cmpr", 25},
797 {"stick", 24},
f04d18b7
DM		 798 {"softint_clear", 21},
799 {"softint_set", 20},
2b661f3d 800 {"softint", 22},
252b5132
RH		 801 {"set_softint", 20},
802 {"pic", 17},
803 {"pcr", 16},
804 {"gsr", 19},
805 {"dcr", 18},
ea783ef3 806 {"cps", 28},
252b5132 807 {"clear_softint", 21},
e0c6ed95 808 {"", -1}, /* End marker. */
252b5132
RH		 809};
810
811static int
5a49b8ac 812cmp_reg_entry (const void *parg, const void *qarg)
252b5132
RH		 813{
814 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
815 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
816
817 return strcmp (q->name, p->name);
818}
819\f
820/* This function is called once, at assembler startup time. It should
e0c6ed95
AM		 821 set up all the tables, etc. that the MD part of the assembler will
822 need. */
252b5132
RH		 823
824void
5a49b8ac 825md_begin (void)
252b5132
RH		 826{
827 register const char *retval = NULL;
828 int lose = 0;
829 register unsigned int i = 0;
830
831 /* We don't get a chance to initialize anything before md_parse_option
832 is called, and it may not be called, so handle default initialization
833 now if not already done. */
834 if (! default_init_p)
835 init_default_arch ();
836
364b6d8b 837 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
252b5132
RH		 838 op_hash = hash_new ();
839
840 while (i < (unsigned int) sparc_num_opcodes)
841 {
842 const char *name = sparc_opcodes[i].name;
5a49b8ac 843 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
252b5132
RH		 844 if (retval != NULL)
845 {
cf9a1301
RH		 846 as_bad (_("Internal error: can't hash `%s': %s\n"),
847 sparc_opcodes[i].name, retval);
252b5132
RH		 848 lose = 1;
849 }
850 do
851 {
852 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
853 {
cf9a1301
RH		 854 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
855 sparc_opcodes[i].name, sparc_opcodes[i].args);
252b5132
RH		 856 lose = 1;
857 }
858 ++i;
859 }
860 while (i < (unsigned int) sparc_num_opcodes
861 && !strcmp (sparc_opcodes[i].name, name));
862 }
863
cf9a1301
RH		 864 for (i = 0; native_op_table[i].name; i++)
865 {
866 const struct sparc_opcode *insn;
3d4ae3c0
NC		 867 char *name = ((sparc_arch_size == 32)
868 ? native_op_table[i].name32
869 : native_op_table[i].name64);
e0c6ed95 870 insn = (struct sparc_opcode *) hash_find (op_hash, name);
cf9a1301 871 if (insn == NULL)
e0c6ed95
AM		 872 {
873 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
874 name, native_op_table[i].name);
875 lose = 1;
876 }
cf9a1301
RH		 877 else
878 {
5a49b8ac
AM		 879 retval = hash_insert (op_hash, native_op_table[i].name,
880 (void *) insn);
cf9a1301
RH		 881 if (retval != NULL)
882 {
883 as_bad (_("Internal error: can't hash `%s': %s\n"),
884 sparc_opcodes[i].name, retval);
885 lose = 1;
886 }
887 }
888 }
889
252b5132
RH		 890 if (lose)
891 as_fatal (_("Broken assembler. No assembly attempted."));
892
252b5132
RH		 893 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
894 sizeof (priv_reg_table[0]), cmp_reg_entry);
895
896 /* If -bump, record the architecture level at which we start issuing
897 warnings. The behaviour is different depending upon whether an
898 architecture was explicitly specified. If it wasn't, we issue warnings
899 for all upwards bumps. If it was, we don't start issuing warnings until
900 we need to bump beyond the requested architecture or when we bump between
901 conflicting architectures. */
902
903 if (warn_on_bump
904 && architecture_requested)
905 {
906 /* `max_architecture' records the requested architecture.
907 Issue warnings if we go above it. */
908 warn_after_architecture = max_architecture;
909
910 /* Find the highest architecture level that doesn't conflict with
911 the requested one. */
912 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
913 max_architecture > warn_after_architecture;
914 --max_architecture)
915 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
916 warn_after_architecture))
917 break;
918 }
919}
920
921/* Called after all assembly has been done. */
922
923void
5a49b8ac 924sparc_md_end (void)
252b5132 925{
19f7b010
JJ		 926 unsigned long mach = bfd_mach_sparc;
927
252b5132 928 if (sparc_arch_size == 64)
19f7b010
JJ		 929 switch (current_architecture)
930 {
931 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
932 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
933 default: mach = bfd_mach_sparc_v9; break;
934 }
252b5132 935 else
19f7b010
JJ		 936 switch (current_architecture)
937 {
938 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
939 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
940 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
941 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
942 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
943 be but for now it is (since that's the way it's always been
944 treated). */
945 default: break;
946 }
947 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
9e8c70f9
DM		 948
949#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
950 if (hwcap_seen)
ec668d69 951 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
9e8c70f9 952#endif
252b5132
RH		 953}
954\f
955/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
956
5a49b8ac
AM		 957static inline int
958in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
252b5132
RH		 959{
960 if (max <= 0)
961 abort ();
962 /* Sign-extend the value from the architecture word size, so that
963 0xffffffff is always considered -1 on sparc32. */
964 if (sparc_arch_size == 32)
965 {
e0c6ed95 966 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
6c1b24e4 967 val = ((val & U0xffffffff) ^ sign) - sign;
252b5132
RH		 968 }
969 if (val > max)
970 return 0;
971 if (val < ~max)
972 return 0;
973 return 1;
974}
975
976/* Return non-zero if VAL is in the range 0 to MAX. */
977
5a49b8ac
AM		 978static inline int
979in_unsigned_range (bfd_vma val, bfd_vma max)
252b5132
RH		 980{
981 if (val > max)
982 return 0;
983 return 1;
984}
985
986/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
987 (e.g. -15 to +31). */
988
5a49b8ac
AM		 989static inline int
990in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
252b5132
RH		 991{
992 if (max <= 0)
993 abort ();
994 if (val > max)
995 return 0;
996 if (val < ~(max >> 1))
997 return 0;
998 return 1;
999}
1000
1001static int
5a49b8ac 1002sparc_ffs (unsigned int mask)
252b5132
RH		 1003{
1004 int i;
1005
1006 if (mask == 0)
1007 return -1;
1008
1009 for (i = 0; (mask & 1) == 0; ++i)
1010 mask >>= 1;
1011 return i;
1012}
1013
1014/* Implement big shift right. */
1015static bfd_vma
5a49b8ac 1016BSR (bfd_vma val, int amount)
252b5132
RH		 1017{
1018 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1019 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1020 return val >> amount;
1021}
1022\f
1023/* For communication between sparc_ip and get_expression. */
1024static char *expr_end;
1025
252b5132
RH		 1026/* Values for `special_case'.
1027 Instructions that require wierd handling because they're longer than
1028 4 bytes. */
1029#define SPECIAL_CASE_NONE 0
1030#define SPECIAL_CASE_SET 1
1031#define SPECIAL_CASE_SETSW 2
1032#define SPECIAL_CASE_SETX 3
1033/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1034#define SPECIAL_CASE_FDIV 4
1035
1036/* Bit masks of various insns. */
1037#define NOP_INSN 0x01000000
1038#define OR_INSN 0x80100000
63fab58c 1039#define XOR_INSN 0x80180000
252b5132
RH		 1040#define FMOVS_INSN 0x81A00020
1041#define SETHI_INSN 0x01000000
1042#define SLLX_INSN 0x81281000
1043#define SRA_INSN 0x81380000
1044
1045/* The last instruction to be assembled. */
1046static const struct sparc_opcode *last_insn;
1047/* The assembled opcode of `last_insn'. */
1048static unsigned long last_opcode;
1049\f
a22b281c 1050/* Handle the set and setuw synthetic instructions. */
e0c6ed95 1051
a22b281c 1052static void
5a49b8ac 1053synthetize_setuw (const struct sparc_opcode *insn)
a22b281c
RH		 1054{
1055 int need_hi22_p = 0;
1056 int rd = (the_insn.opcode & RD (~0)) >> 25;
1057
1058 if (the_insn.exp.X_op == O_constant)
1059 {
1060 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1061 {
e0c6ed95 1062 if (sizeof (offsetT) > 4
a22b281c 1063 && (the_insn.exp.X_add_number < 0
6c1b24e4 1064 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1065 as_warn (_("set: number not in 0..4294967295 range"));
1066 }
1067 else
1068 {
e0c6ed95 1069 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1070 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1071 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c 1072 as_warn (_("set: number not in -2147483648..4294967295 range"));
e0c6ed95 1073 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
a22b281c
RH		 1074 }
1075 }
1076
1077 /* See if operand is absolute and small; skip sethi if so. */
1078 if (the_insn.exp.X_op != O_constant
1079 || the_insn.exp.X_add_number >= (1 << 12)
1080 || the_insn.exp.X_add_number < -(1 << 12))
1081 {
1082 the_insn.opcode = (SETHI_INSN | RD (rd)
1083 | ((the_insn.exp.X_add_number >> 10)
ab3e48dc
KH		 1084 & (the_insn.exp.X_op == O_constant
1085 ? 0x3fffff : 0)));
a22b281c 1086 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1087 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
a22b281c
RH		 1088 output_insn (insn, &the_insn);
1089 need_hi22_p = 1;
1090 }
1091
1092 /* See if operand has no low-order bits; skip OR if so. */
1093 if (the_insn.exp.X_op != O_constant
1094 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1095 || ! need_hi22_p)
1096 {
1097 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1098 | RD (rd) | IMMED
1099 | (the_insn.exp.X_add_number
ab3e48dc
KH		 1100 & (the_insn.exp.X_op != O_constant
1101 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
a22b281c 1102 the_insn.reloc = (the_insn.exp.X_op != O_constant
ab3e48dc 1103 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
a22b281c
RH		 1104 output_insn (insn, &the_insn);
1105 }
1106}
e0c6ed95 1107
a22b281c 1108/* Handle the setsw synthetic instruction. */
e0c6ed95 1109
a22b281c 1110static void
5a49b8ac 1111synthetize_setsw (const struct sparc_opcode *insn)
a22b281c
RH		 1112{
1113 int low32, rd, opc;
1114
1115 rd = (the_insn.opcode & RD (~0)) >> 25;
1116
1117 if (the_insn.exp.X_op != O_constant)
1118 {
1119 synthetize_setuw (insn);
1120
1121 /* Need to sign extend it. */
1122 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1123 the_insn.reloc = BFD_RELOC_NONE;
1124 output_insn (insn, &the_insn);
1125 return;
1126 }
1127
e0c6ed95 1128 if (sizeof (offsetT) > 4
6c1b24e4
AO		 1129 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1130 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
a22b281c
RH		 1131 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1132
e0c6ed95
AM		 1133 low32 = the_insn.exp.X_add_number;
1134
a22b281c
RH		 1135 if (low32 >= 0)
1136 {
1137 synthetize_setuw (insn);
1138 return;
1139 }
1140
1141 opc = OR_INSN;
e0c6ed95 1142
a22b281c
RH		 1143 the_insn.reloc = BFD_RELOC_NONE;
1144 /* See if operand is absolute and small; skip sethi if so. */
1145 if (low32 < -(1 << 12))
1146 {
1147 the_insn.opcode = (SETHI_INSN | RD (rd)
1148 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1149 output_insn (insn, &the_insn);
1150 low32 = 0x1c00 | (low32 & 0x3ff);
1151 opc = RS1 (rd) | XOR_INSN;
1152 }
1153
1154 the_insn.opcode = (opc | RD (rd) | IMMED
1155 | (low32 & 0x1fff));
1156 output_insn (insn, &the_insn);
1157}
1158
1159/* Handle the setsw synthetic instruction. */
e0c6ed95 1160
a22b281c 1161static void
5a49b8ac 1162synthetize_setx (const struct sparc_opcode *insn)
a22b281c
RH		 1163{
1164 int upper32, lower32;
1165 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1166 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1167 int upper_dstreg;
1168 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1169 int need_xor10_p = 0;
e0c6ed95 1170
6c1b24e4 1171#define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
a22b281c
RH		 1172 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1173 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1174#undef SIGNEXT32
1175
1176 upper_dstreg = tmpreg;
1177 /* The tmp reg should not be the dst reg. */
1178 if (tmpreg == dstreg)
1179 as_warn (_("setx: temporary register same as destination register"));
1180
1181 /* ??? Obviously there are other optimizations we can do
1182 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1183 doing some of these. Later. If you do change things, try to
1184 change all of this to be table driven as well. */
1185 /* What to output depends on the number if it's constant.
1186 Compute that first, then output what we've decided upon. */
1187 if (the_insn.exp.X_op != O_constant)
1188 {
1189 if (sparc_arch_size == 32)
1190 {
1191 /* When arch size is 32, we want setx to be equivalent
1192 to setuw for anything but constants. */
1193 the_insn.exp.X_add_number &= 0xffffffff;
1194 synthetize_setuw (insn);
1195 return;
1196 }
1197 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
ab3e48dc
KH		 1198 lower32 = 0;
1199 upper32 = 0;
a22b281c
RH		 1200 }
1201 else
1202 {
1203 /* Reset X_add_number, we've extracted it as upper32/lower32.
1204 Otherwise fixup_segment will complain about not being able to
1205 write an 8 byte number in a 4 byte field. */
1206 the_insn.exp.X_add_number = 0;
e0c6ed95 1207
a22b281c
RH		 1208 /* Only need hh22 if `or' insn can't handle constant. */
1209 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1210 need_hh22_p = 1;
e0c6ed95 1211
a22b281c
RH		 1212 /* Does bottom part (after sethi) have bits? */
1213 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1214 /* No hh22, but does upper32 still have bits we can't set
1215 from lower32? */
1216 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1217 need_hm10_p = 1;
e0c6ed95 1218
a22b281c
RH		 1219 /* If the lower half is all zero, we build the upper half directly
1220 into the dst reg. */
1221 if (lower32 != 0
1222 /* Need lower half if number is zero or 0xffffffff00000000. */
1223 || (! need_hh22_p && ! need_hm10_p))
1224 {
1225 /* No need for sethi if `or' insn can handle constant. */
1226 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1227 /* Note that we can't use a negative constant in the `or'
1228 insn unless the upper 32 bits are all ones. */
1229 || (lower32 < 0 && upper32 != -1)
1230 || (lower32 >= 0 && upper32 == -1))
1231 need_hi22_p = 1;
e0c6ed95 1232
a22b281c
RH		 1233 if (need_hi22_p && upper32 == -1)
1234 need_xor10_p = 1;
1235
1236 /* Does bottom part (after sethi) have bits? */
1237 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1238 /* No sethi. */
1239 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1240 /* Need `or' if we didn't set anything else. */
1241 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1242 need_lo10_p = 1;
1243 }
1244 else
1245 /* Output directly to dst reg if lower 32 bits are all zero. */
1246 upper_dstreg = dstreg;
1247 }
e0c6ed95 1248
a22b281c
RH		 1249 if (!upper_dstreg && dstreg)
1250 as_warn (_("setx: illegal temporary register g0"));
1251
1252 if (need_hh22_p)
1253 {
1254 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1255 | ((upper32 >> 10) & 0x3fffff));
1256 the_insn.reloc = (the_insn.exp.X_op != O_constant
1257 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1258 output_insn (insn, &the_insn);
1259 }
e0c6ed95 1260
a22b281c
RH		 1261 if (need_hi22_p)
1262 {
1263 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1264 | (((need_xor10_p ? ~lower32 : lower32)
ab3e48dc 1265 >> 10) & 0x3fffff));
a22b281c
RH		 1266 the_insn.reloc = (the_insn.exp.X_op != O_constant
1267 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1268 output_insn (insn, &the_insn);
1269 }
1270
1271 if (need_hm10_p)
1272 {
1273 the_insn.opcode = (OR_INSN
1274 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1275 | RD (upper_dstreg)
1276 | IMMED
1277 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1278 the_insn.reloc = (the_insn.exp.X_op != O_constant
1279 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1280 output_insn (insn, &the_insn);
1281 }
e0c6ed95 1282
a22b281c
RH		 1283 if (need_lo10_p)
1284 {
1285 /* FIXME: One nice optimization to do here is to OR the low part
1286 with the highpart if hi22 isn't needed and the low part is
1287 positive. */
1288 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1289 | RD (dstreg)
1290 | IMMED
1291 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1292 the_insn.reloc = (the_insn.exp.X_op != O_constant
1293 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1294 output_insn (insn, &the_insn);
1295 }
e0c6ed95 1296
a22b281c
RH		 1297 /* If we needed to build the upper part, shift it into place. */
1298 if (need_hh22_p || need_hm10_p)
1299 {
1300 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1301 | IMMED | 32);
1302 the_insn.reloc = BFD_RELOC_NONE;
1303 output_insn (insn, &the_insn);
1304 }
e0c6ed95 1305
a22b281c
RH		 1306 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1307 if (need_xor10_p)
1308 {
1309 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1310 | 0x1c00 | (lower32 & 0x3ff));
1311 the_insn.reloc = BFD_RELOC_NONE;
1312 output_insn (insn, &the_insn);
1313 }
1314
1315 /* If we needed to build both upper and lower parts, OR them together. */
1316 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1317 {
1318 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1319 | RD (dstreg));
1320 the_insn.reloc = BFD_RELOC_NONE;
1321 output_insn (insn, &the_insn);
1322 }
1323}
1324\f
252b5132
RH		 1325/* Main entry point to assemble one instruction. */
1326
1327void
5a49b8ac 1328md_assemble (char *str)
252b5132
RH		 1329{
1330 const struct sparc_opcode *insn;
a22b281c 1331 int special_case;
252b5132
RH		 1332
1333 know (str);
a22b281c 1334 special_case = sparc_ip (str, &insn);
b0825cc2
DM		 1335 if (insn == NULL)
1336 return;
252b5132
RH		 1337
1338 /* We warn about attempts to put a floating point branch in a delay slot,
1339 unless the delay slot has been annulled. */
b0825cc2 1340 if (last_insn != NULL
252b5132
RH		 1341 && (insn->flags & F_FBR) != 0
1342 && (last_insn->flags & F_DELAYED) != 0
1343 /* ??? This test isn't completely accurate. We assume anything with
1344 F_{UNBR,CONDBR,FBR} set is annullable. */
1345 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1346 || (last_opcode & ANNUL) == 0))
1347 as_warn (_("FP branch in delay slot"));
1348
1349 /* SPARC before v9 requires a nop instruction between a floating
1350 point instruction and a floating point branch. We insert one
1351 automatically, with a warning. */
1352 if (max_architecture < SPARC_OPCODE_ARCH_V9
252b5132
RH		 1353 && last_insn != NULL
1354 && (insn->flags & F_FBR) != 0
1355 && (last_insn->flags & F_FLOAT) != 0)
1356 {
1357 struct sparc_it nop_insn;
1358
1359 nop_insn.opcode = NOP_INSN;
1360 nop_insn.reloc = BFD_RELOC_NONE;
1361 output_insn (insn, &nop_insn);
1362 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1363 }
1364
a22b281c
RH		 1365 switch (special_case)
1366 {
1367 case SPECIAL_CASE_NONE:
e0c6ed95 1368 /* Normal insn. */
a22b281c
RH		 1369 output_insn (insn, &the_insn);
1370 break;
252b5132 1371
a22b281c
RH		 1372 case SPECIAL_CASE_SETSW:
1373 synthetize_setsw (insn);
1374 break;
e0c6ed95 1375
a22b281c
RH		 1376 case SPECIAL_CASE_SET:
1377 synthetize_setuw (insn);
1378 break;
252b5132 1379
a22b281c
RH		 1380 case SPECIAL_CASE_SETX:
1381 synthetize_setx (insn);
1382 break;
e0c6ed95 1383
a22b281c
RH		 1384 case SPECIAL_CASE_FDIV:
1385 {
1386 int rd = (the_insn.opcode >> 25) & 0x1f;
e0c6ed95 1387
a22b281c 1388 output_insn (insn, &the_insn);
e0c6ed95 1389
a22b281c
RH		 1390 /* According to information leaked from Sun, the "fdiv" instructions
1391 on early SPARC machines would produce incorrect results sometimes.
1392 The workaround is to add an fmovs of the destination register to
1393 itself just after the instruction. This was true on machines
e0c6ed95 1394 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
9c2799c2 1395 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
a22b281c
RH		 1396 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1397 output_insn (insn, &the_insn);
1398 return;
1399 }
e0c6ed95 1400
a22b281c
RH		 1401 default:
1402 as_fatal (_("failed special case insn sanity check"));
252b5132
RH		 1403 }
1404}
1405
4bafe00e
DM		 1406static const char *
1407get_hwcap_name (int mask)
1408{
ec668d69 1409 if (mask & HWCAP_MUL32)
4bafe00e 1410 return "mul32";
ec668d69 1411 if (mask & HWCAP_DIV32)
4bafe00e 1412 return "div32";
ec668d69 1413 if (mask & HWCAP_FSMULD)
4bafe00e 1414 return "fsmuld";
ec668d69 1415 if (mask & HWCAP_V8PLUS)
4bafe00e 1416 return "v8plus";
ec668d69 1417 if (mask & HWCAP_POPC)
4bafe00e 1418 return "popc";
ec668d69 1419 if (mask & HWCAP_VIS)
4bafe00e 1420 return "vis";
ec668d69 1421 if (mask & HWCAP_VIS2)
4bafe00e 1422 return "vis2";
ec668d69 1423 if (mask & HWCAP_ASI_BLK_INIT)
4bafe00e 1424 return "ASIBlkInit";
ec668d69 1425 if (mask & HWCAP_FMAF)
4bafe00e 1426 return "fmaf";
ec668d69 1427 if (mask & HWCAP_VIS3)
4bafe00e 1428 return "vis3";
ec668d69 1429 if (mask & HWCAP_HPC)
4bafe00e 1430 return "hpc";
ec668d69 1431 if (mask & HWCAP_RANDOM)
4bafe00e 1432 return "random";
ec668d69 1433 if (mask & HWCAP_TRANS)
4bafe00e 1434 return "trans";
ec668d69 1435 if (mask & HWCAP_FJFMAU)
4bafe00e 1436 return "fjfmau";
ec668d69 1437 if (mask & HWCAP_IMA)
4bafe00e 1438 return "ima";
ec668d69 1439 if (mask & HWCAP_ASI_CACHE_SPARING)
4bafe00e 1440 return "cspare";
ec668d69
DM		 1441 if (mask & HWCAP_AES)
1442 return "aes";
1443 if (mask & HWCAP_DES)
1444 return "des";
1445 if (mask & HWCAP_KASUMI)
1446 return "kasumi";
1447 if (mask & HWCAP_CAMELLIA)
1448 return "camellia";
1449 if (mask & HWCAP_MD5)
1450 return "md5";
1451 if (mask & HWCAP_SHA1)
1452 return "sha1";
1453 if (mask & HWCAP_SHA256)
1454 return "sha256";
1455 if (mask & HWCAP_SHA512)
1456 return "sha512";
1457 if (mask & HWCAP_MPMUL)
1458 return "mpmul";
1459 if (mask & HWCAP_MONT)
1460 return "mont";
1461 if (mask & HWCAP_PAUSE)
1462 return "pause";
1463 if (mask & HWCAP_CBCOND)
1464 return "cbcond";
1465 if (mask & HWCAP_CRC32C)
1466 return "crc32c";
4bafe00e
DM		 1467 return "UNKNOWN";
1468}
1469
252b5132
RH		 1470/* Subroutine of md_assemble to do the actual parsing. */
1471
a22b281c 1472static int
5a49b8ac 1473sparc_ip (char *str, const struct sparc_opcode **pinsn)
252b5132
RH		 1474{
1475 char *error_message = "";
1476 char *s;
1477 const char *args;
1478 char c;
1479 const struct sparc_opcode *insn;
1480 char *argsStart;
1481 unsigned long opcode;
1482 unsigned int mask = 0;
1483 int match = 0;
1484 int comma = 0;
1485 int v9_arg_p;
a22b281c 1486 int special_case = SPECIAL_CASE_NONE;
252b5132
RH		 1487
1488 s = str;
3882b010 1489 if (ISLOWER (*s))
252b5132
RH		 1490 {
1491 do
1492 ++s;
6cda1326 1493 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
252b5132
RH		 1494 }
1495
1496 switch (*s)
1497 {
1498 case '\0':
1499 break;
1500
1501 case ',':
1502 comma = 1;
e0c6ed95 1503 /* Fall through. */
252b5132
RH		 1504
1505 case ' ':
1506 *s++ = '\0';
1507 break;
1508
1509 default:
b0825cc2
DM		 1510 as_bad (_("Unknown opcode: `%s'"), str);
1511 *pinsn = NULL;
1512 return special_case;
252b5132
RH		 1513 }
1514 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1515 *pinsn = insn;
1516 if (insn == NULL)
1517 {
1518 as_bad (_("Unknown opcode: `%s'"), str);
a22b281c 1519 return special_case;
252b5132
RH		 1520 }
1521 if (comma)
1522 {
1523 *--s = ',';
1524 }
1525
1526 argsStart = s;
1527 for (;;)
1528 {
1529 opcode = insn->match;
1530 memset (&the_insn, '\0', sizeof (the_insn));
1531 the_insn.reloc = BFD_RELOC_NONE;
1532 v9_arg_p = 0;
1533
e0c6ed95
AM		 1534 /* Build the opcode, checking as we go to make sure that the
1535 operands match. */
252b5132
RH		 1536 for (args = insn->args;; ++args)
1537 {
1538 switch (*args)
1539 {
1540 case 'K':
1541 {
1542 int kmask = 0;
1543
1544 /* Parse a series of masks. */
1545 if (*s == '#')
1546 {
1547 while (*s == '#')
1548 {
91d6fa6a 1549 int jmask;
252b5132
RH		 1550
1551 if (! parse_keyword_arg (sparc_encode_membar, &s,
91d6fa6a 1552 &jmask))
252b5132
RH		 1553 {
1554 error_message = _(": invalid membar mask name");
1555 goto error;
1556 }
91d6fa6a 1557 kmask |= jmask;
47926f60
KH		 1558 while (*s == ' ')
1559 ++s;
252b5132
RH		 1560 if (*s == '|' || *s == '+')
1561 ++s;
47926f60
KH		 1562 while (*s == ' ')
1563 ++s;
252b5132
RH		 1564 }
1565 }
1566 else
1567 {
1568 if (! parse_const_expr_arg (&s, &kmask))
1569 {
1570 error_message = _(": invalid membar mask expression");
1571 goto error;
1572 }
1573 if (kmask < 0 || kmask > 127)
1574 {
1575 error_message = _(": invalid membar mask number");
1576 goto error;
1577 }
1578 }
1579
1580 opcode |= MEMBAR (kmask);
1581 continue;
1582 }
1583
19f7b010
JJ		 1584 case '3':
1585 {
1586 int smask = 0;
1587
1588 if (! parse_const_expr_arg (&s, &smask))
1589 {
1590 error_message = _(": invalid siam mode expression");
1591 goto error;
1592 }
1593 if (smask < 0 || smask > 7)
1594 {
1595 error_message = _(": invalid siam mode number");
1596 goto error;
1597 }
1598 opcode |= smask;
1599 continue;
1600 }
1601
252b5132
RH		 1602 case '*':
1603 {
1604 int fcn = 0;
1605
1606 /* Parse a prefetch function. */
1607 if (*s == '#')
1608 {
1609 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1610 {
1611 error_message = _(": invalid prefetch function name");
1612 goto error;
1613 }
1614 }
1615 else
1616 {
1617 if (! parse_const_expr_arg (&s, &fcn))
1618 {
1619 error_message = _(": invalid prefetch function expression");
1620 goto error;
1621 }
1622 if (fcn < 0 || fcn > 31)
1623 {
1624 error_message = _(": invalid prefetch function number");
1625 goto error;
1626 }
1627 }
1628 opcode |= RD (fcn);
1629 continue;
1630 }
1631
1632 case '!':
1633 case '?':
1634 /* Parse a sparc64 privileged register. */
1635 if (*s == '%')
1636 {
1637 struct priv_reg_entry *p = priv_reg_table;
e0c6ed95 1638 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1639
1640 s += 1;
1641 while (p->name[0] > s[0])
1642 p++;
1643 while (p->name[0] == s[0])
1644 {
1645 len = strlen (p->name);
1646 if (strncmp (p->name, s, len) == 0)
1647 break;
1648 p++;
1649 }
1650 if (p->name[0] != s[0])
1651 {
1652 error_message = _(": unrecognizable privileged register");
1653 goto error;
1654 }
1655 if (*args == '?')
1656 opcode |= (p->regnum << 14);
1657 else
1658 opcode |= (p->regnum << 25);
1659 s += len;
1660 continue;
1661 }
1662 else
1663 {
1664 error_message = _(": unrecognizable privileged register");
1665 goto error;
1666 }
1667
10156f83
DM		 1668 case '$':
1669 case '%':
1670 /* Parse a sparc64 hyperprivileged register. */
1671 if (*s == '%')
1672 {
1673 struct priv_reg_entry *p = hpriv_reg_table;
1674 unsigned int len = 9999999; /* Init to make gcc happy. */
1675
1676 s += 1;
1677 while (p->name[0] > s[0])
1678 p++;
1679 while (p->name[0] == s[0])
1680 {
1681 len = strlen (p->name);
1682 if (strncmp (p->name, s, len) == 0)
1683 break;
1684 p++;
1685 }
1686 if (p->name[0] != s[0])
1687 {
1688 error_message = _(": unrecognizable hyperprivileged register");
1689 goto error;
1690 }
1691 if (*args == '$')
1692 opcode |= (p->regnum << 14);
1693 else
1694 opcode |= (p->regnum << 25);
1695 s += len;
1696 continue;
1697 }
1698 else
1699 {
1700 error_message = _(": unrecognizable hyperprivileged register");
1701 goto error;
1702 }
1703
252b5132
RH		 1704 case '_':
1705 case '/':
19f7b010 1706 /* Parse a v9a/v9b ancillary state register. */
252b5132
RH		 1707 if (*s == '%')
1708 {
1709 struct priv_reg_entry *p = v9a_asr_table;
e0c6ed95 1710 unsigned int len = 9999999; /* Init to make gcc happy. */
252b5132
RH		 1711
1712 s += 1;
1713 while (p->name[0] > s[0])
1714 p++;
1715 while (p->name[0] == s[0])
1716 {
1717 len = strlen (p->name);
1718 if (strncmp (p->name, s, len) == 0)
1719 break;
1720 p++;
1721 }
1722 if (p->name[0] != s[0])
1723 {
19f7b010 1724 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1725 goto error;
1726 }
1727 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1728 {
1729 error_message = _(": rd on write only ancillary state register");
1730 goto error;
e0c6ed95 1731 }
19f7b010
JJ		 1732 if (p->regnum >= 24
1733 && (insn->architecture
1734 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1735 {
1736 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1737 error_message = _(": unrecognizable v9a ancillary state register");
1738 goto error;
1739 }
252b5132
RH		 1740 if (*args == '/')
1741 opcode |= (p->regnum << 14);
1742 else
1743 opcode |= (p->regnum << 25);
1744 s += len;
1745 continue;
1746 }
1747 else
1748 {
19f7b010 1749 error_message = _(": unrecognizable v9a or v9b ancillary state register");
252b5132
RH		 1750 goto error;
1751 }
1752
1753 case 'M':
1754 case 'm':
1755 if (strncmp (s, "%asr", 4) == 0)
1756 {
1757 s += 4;
1758
3882b010 1759 if (ISDIGIT (*s))
252b5132
RH		 1760 {
1761 long num = 0;
1762
3882b010 1763 while (ISDIGIT (*s))
252b5132
RH		 1764 {
1765 num = num * 10 + *s - '0';
1766 ++s;
1767 }
1768
1769 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1770 {
1771 if (num < 16 || 31 < num)
1772 {
1773 error_message = _(": asr number must be between 16 and 31");
1774 goto error;
1775 }
1776 }
1777 else
1778 {
1779 if (num < 0 || 31 < num)
1780 {
1781 error_message = _(": asr number must be between 0 and 31");
1782 goto error;
1783 }
1784 }
1785
1786 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1787 continue;
1788 }
1789 else
1790 {
1791 error_message = _(": expecting %asrN");
1792 goto error;
1793 }
e0c6ed95 1794 } /* if %asr */
252b5132
RH		 1795 break;
1796
1797 case 'I':
1798 the_insn.reloc = BFD_RELOC_SPARC_11;
1799 goto immediate;
1800
1801 case 'j':
1802 the_insn.reloc = BFD_RELOC_SPARC_10;
1803 goto immediate;
1804
6cda1326
DM		 1805 case ')':
1806 if (*s == ' ')
1807 s++;
1808 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
1809 || ISDIGIT (*s))
1810 {
1811 long num = 0;
1812
1813 if (s[0] == '0' && s[1] == 'x')
1814 {
1815 s += 2;
1816 while (ISXDIGIT (*s))
1817 {
1818 num <<= 4;
1819 num |= hex_value (*s);
1820 ++s;
1821 }
1822 }
1823 else
1824 {
1825 while (ISDIGIT (*s))
1826 {
1827 num = num * 10 + *s - '0';
1828 ++s;
1829 }
1830 }
1831 if (num < 0 || num > 31)
1832 {
1833 error_message = _(": crypto immediate must be between 0 and 31");
1834 goto error;
1835 }
1836
1837 opcode |= RS3 (num);
1838 continue;
1839 }
1840 else
1841 {
1842 error_message = _(": expecting crypto immediate");
1843 goto error;
1844 }
1845
252b5132
RH		 1846 case 'X':
1847 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1848 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1849 the_insn.reloc = BFD_RELOC_SPARC_5;
1850 else
1851 the_insn.reloc = BFD_RELOC_SPARC13;
1852 /* These fields are unsigned, but for upward compatibility,
1853 allow negative values as well. */
1854 goto immediate;
1855
1856 case 'Y':
1857 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1858 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1859 the_insn.reloc = BFD_RELOC_SPARC_6;
1860 else
1861 the_insn.reloc = BFD_RELOC_SPARC13;
1862 /* These fields are unsigned, but for upward compatibility,
1863 allow negative values as well. */
1864 goto immediate;
1865
1866 case 'k':
1867 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1868 the_insn.pcrel = 1;
1869 goto immediate;
1870
2615994e
DM		 1871 case '=':
1872 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1873 the_insn.pcrel = 1;
1874 goto immediate;
1875
252b5132
RH		 1876 case 'G':
1877 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1878 the_insn.pcrel = 1;
1879 goto immediate;
1880
1881 case 'N':
1882 if (*s == 'p' && s[1] == 'n')
1883 {
1884 s += 2;
1885 continue;
1886 }
1887 break;
1888
1889 case 'T':
1890 if (*s == 'p' && s[1] == 't')
1891 {
1892 s += 2;
1893 continue;
1894 }
1895 break;
1896
1897 case 'z':
1898 if (*s == ' ')
1899 {
1900 ++s;
1901 }
1902 if (strncmp (s, "%icc", 4) == 0)
1903 {
1904 s += 4;
1905 continue;
1906 }
1907 break;
1908
1909 case 'Z':
1910 if (*s == ' ')
1911 {
1912 ++s;
1913 }
1914 if (strncmp (s, "%xcc", 4) == 0)
1915 {
1916 s += 4;
1917 continue;
1918 }
1919 break;
1920
1921 case '6':
1922 if (*s == ' ')
1923 {
1924 ++s;
1925 }
1926 if (strncmp (s, "%fcc0", 5) == 0)
1927 {
1928 s += 5;
1929 continue;
1930 }
1931 break;
1932
1933 case '7':
1934 if (*s == ' ')
1935 {
1936 ++s;
1937 }
1938 if (strncmp (s, "%fcc1", 5) == 0)
1939 {
1940 s += 5;
1941 continue;
1942 }
1943 break;
1944
1945 case '8':
1946 if (*s == ' ')
1947 {
1948 ++s;
1949 }
1950 if (strncmp (s, "%fcc2", 5) == 0)
1951 {
1952 s += 5;
1953 continue;
1954 }
1955 break;
1956
1957 case '9':
1958 if (*s == ' ')
1959 {
1960 ++s;
1961 }
1962 if (strncmp (s, "%fcc3", 5) == 0)
1963 {
1964 s += 5;
1965 continue;
1966 }
1967 break;
1968
1969 case 'P':
1970 if (strncmp (s, "%pc", 3) == 0)
1971 {
1972 s += 3;
1973 continue;
1974 }
1975 break;
1976
1977 case 'W':
1978 if (strncmp (s, "%tick", 5) == 0)
1979 {
1980 s += 5;
1981 continue;
1982 }
1983 break;
1984
e0c6ed95 1985 case '\0': /* End of args. */
b9734f35 1986 if (s[0] == ',' && s[1] == '%')
252b5132 1987 {
739f7f82 1988 static const struct ops
dfeb0666 1989 {
b9734f35
JJ		 1990 /* The name as it appears in assembler. */
1991 char *name;
1992 /* strlen (name), precomputed for speed */
1993 int len;
1994 /* The reloc this pseudo-op translates to. */
1995 int reloc;
739f7f82
DM		 1996 /* 1 if tls call. */
1997 int tls_call;
dfeb0666 1998 }
739f7f82 1999 ops[] =
dfeb0666 2000 {
b9734f35
JJ		 2001 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
2002 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
2003 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
2004 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
2005 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
2006 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
2007 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
dfeb0666 2008 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
739f7f82 2009 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
dfeb0666 2010 { NULL, 0, 0, 0 }
b9734f35 2011 };
739f7f82 2012 const struct ops *o;
b9734f35
JJ		 2013 char *s1;
2014 int npar = 0;
2015
739f7f82 2016 for (o = ops; o->name; o++)
b9734f35
JJ		 2017 if (strncmp (s + 2, o->name, o->len) == 0)
2018 break;
2019 if (o->name == NULL)
2020 break;
2021
2022 if (s[o->len + 2] != '(')
2023 {
2024 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2025 return special_case;
2026 }
2027
739f7f82 2028 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
b9734f35
JJ		 2029 {
2030 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2031 o->name);
2032 return special_case;
2033 }
2034
739f7f82 2035 if (o->tls_call
b9734f35
JJ		 2036 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2037 || the_insn.exp.X_add_number != 0
2038 || the_insn.exp.X_add_symbol
2039 != symbol_find_or_make ("__tls_get_addr")))
2040 {
2041 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2042 o->name);
2043 return special_case;
2044 }
2045
2046 the_insn.reloc = o->reloc;
2047 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2048 s += o->len + 3;
2049
2050 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2051 if (*s1 == '(')
2052 npar++;
2053 else if (*s1 == ')')
2054 {
2055 if (!npar)
2056 break;
2057 npar--;
2058 }
2059
2060 if (*s1 != ')')
2061 {
2062 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2063 return special_case;
2064 }
2065
2066 *s1 = '\0';
2067 (void) get_expression (s);
2068 *s1 = ')';
2069 s = s1 + 1;
252b5132 2070 }
b9734f35
JJ		 2071 if (*s == '\0')
2072 match = 1;
252b5132
RH		 2073 break;
2074
2075 case '+':
2076 if (*s == '+')
2077 {
2078 ++s;
2079 continue;
2080 }
2081 if (*s == '-')
2082 {
2083 continue;
2084 }
2085 break;
2086
e0c6ed95 2087 case '[': /* These must match exactly. */
252b5132
RH		 2088 case ']':
2089 case ',':
2090 case ' ':
2091 if (*s++ == *args)
2092 continue;
2093 break;
2094
e0c6ed95 2095 case '#': /* Must be at least one digit. */
3882b010 2096 if (ISDIGIT (*s++))
252b5132 2097 {
3882b010 2098 while (ISDIGIT (*s))
252b5132
RH		 2099 {
2100 ++s;
2101 }
2102 continue;
2103 }
2104 break;
2105
e0c6ed95 2106 case 'C': /* Coprocessor state register. */
252b5132
RH		 2107 if (strncmp (s, "%csr", 4) == 0)
2108 {
2109 s += 4;
2110 continue;
2111 }
2112 break;
2113
e0c6ed95 2114 case 'b': /* Next operand is a coprocessor register. */
252b5132
RH		 2115 case 'c':
2116 case 'D':
3882b010 2117 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
252b5132
RH		 2118 {
2119 mask = *s++;
3882b010 2120 if (ISDIGIT (*s))
252b5132
RH		 2121 {
2122 mask = 10 * (mask - '0') + (*s++ - '0');
2123 if (mask >= 32)
2124 {
2125 break;
2126 }
2127 }
2128 else
2129 {
2130 mask -= '0';
2131 }
2132 switch (*args)
2133 {
2134
2135 case 'b':
2136 opcode |= mask << 14;
2137 continue;
2138
2139 case 'c':
2140 opcode |= mask;
2141 continue;
2142
2143 case 'D':
2144 opcode |= mask << 25;
2145 continue;
2146 }
2147 }
2148 break;
2149
2150 case 'r': /* next operand must be a register */
2151 case 'O':
2152 case '1':
2153 case '2':
2154 case 'd':
2155 if (*s++ == '%')
2156 {
2157 switch (c = *s++)
2158 {
2159
2160 case 'f': /* frame pointer */
2161 if (*s++ == 'p')
2162 {
2163 mask = 0x1e;
2164 break;
2165 }
2166 goto error;
2167
2168 case 'g': /* global register */
a22b281c
RH		 2169 c = *s++;
2170 if (isoctal (c))
252b5132
RH		 2171 {
2172 mask = c - '0';
2173 break;
2174 }
2175 goto error;
2176
2177 case 'i': /* in register */
a22b281c
RH		 2178 c = *s++;
2179 if (isoctal (c))
252b5132
RH		 2180 {
2181 mask = c - '0' + 24;
2182 break;
2183 }
2184 goto error;
2185
2186 case 'l': /* local register */
a22b281c
RH		 2187 c = *s++;
2188 if (isoctal (c))
252b5132
RH		 2189 {
2190 mask = (c - '0' + 16);
2191 break;
2192 }
2193 goto error;
2194
2195 case 'o': /* out register */
a22b281c
RH		 2196 c = *s++;
2197 if (isoctal (c))
252b5132
RH		 2198 {
2199 mask = (c - '0' + 8);
2200 break;
2201 }
2202 goto error;
2203
2204 case 's': /* stack pointer */
2205 if (*s++ == 'p')
2206 {
2207 mask = 0xe;
2208 break;
2209 }
2210 goto error;
2211
2212 case 'r': /* any register */
3882b010 2213 if (!ISDIGIT ((c = *s++)))
252b5132
RH		 2214 {
2215 goto error;
2216 }
2217 /* FALLTHROUGH */
2218 case '0':
2219 case '1':
2220 case '2':
2221 case '3':
2222 case '4':
2223 case '5':
2224 case '6':
2225 case '7':
2226 case '8':
2227 case '9':
3882b010 2228 if (ISDIGIT (*s))
252b5132
RH		 2229 {
2230 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2231 {
2232 goto error;
2233 }
2234 }
2235 else
2236 {
2237 c -= '0';
2238 }
2239 mask = c;
2240 break;
2241
2242 default:
2243 goto error;
2244 }
2245
6d8809aa 2246 if ((mask & ~1) == 2 && sparc_arch_size == 64
e0c6ed95 2247 && no_undeclared_regs && ! globals[mask])
79bd78be 2248 as_bad (_("detected global register use not covered by .register pseudo-op"));
6d8809aa 2249
252b5132
RH		 2250 /* Got the register, now figure out where
2251 it goes in the opcode. */
2252 switch (*args)
2253 {
2254 case '1':
2255 opcode |= mask << 14;
2256 continue;
2257
2258 case '2':
2259 opcode |= mask;
2260 continue;
2261
2262 case 'd':
2263 opcode |= mask << 25;
2264 continue;
2265
2266 case 'r':
2267 opcode |= (mask << 25) | (mask << 14);
2268 continue;
2269
2270 case 'O':
2271 opcode |= (mask << 25) | (mask << 0);
2272 continue;
2273 }
2274 }
2275 break;
2276
2277 case 'e': /* next operand is a floating point register */
2278 case 'v':
2279 case 'V':
2280
2281 case 'f':
2282 case 'B':
2283 case 'R':
2284
ea783ef3
DM		 2285 case '4':
2286 case '5':
2287
252b5132
RH		 2288 case 'g':
2289 case 'H':
2290 case 'J':
2291 {
2292 char format;
2293
2294 if (*s++ == '%'
2295 && ((format = *s) == 'f')
3882b010 2296 && ISDIGIT (*++s))
252b5132 2297 {
3882b010 2298 for (mask = 0; ISDIGIT (*s); ++s)
252b5132
RH		 2299 {
2300 mask = 10 * mask + (*s - '0');
2301 } /* read the number */
2302
2303 if ((*args == 'v'
2304 || *args == 'B'
ea783ef3 2305 || *args == '5'
252b5132
RH		 2306 || *args == 'H')
2307 && (mask & 1))
2308 {
2309 break;
2310 } /* register must be even numbered */
2311
2312 if ((*args == 'V'
2313 || *args == 'R'
2314 || *args == 'J')
2315 && (mask & 3))
2316 {
2317 break;
2318 } /* register must be multiple of 4 */
2319
2320 if (mask >= 64)
2321 {
2322 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2323 error_message = _(": There are only 64 f registers; [0-63]");
2324 else
2325 error_message = _(": There are only 32 f registers; [0-31]");
2326 goto error;
2327 } /* on error */
2328 else if (mask >= 32)
2329 {
2330 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2331 {
26664553
JJ		 2332 if (*args == 'e' || *args == 'f' || *args == 'g')
2333 {
2334 error_message
2335 = _(": There are only 32 single precision f registers; [0-31]");
2336 goto error;
2337 }
252b5132
RH		 2338 v9_arg_p = 1;
2339 mask -= 31; /* wrap high bit */
2340 }
2341 else
2342 {
2343 error_message = _(": There are only 32 f registers; [0-31]");
2344 goto error;
2345 }
2346 }
2347 }
2348 else
2349 {
2350 break;
ab3e48dc 2351 } /* if not an 'f' register. */
252b5132
RH		 2352
2353 switch (*args)
2354 {
2355 case 'v':
2356 case 'V':
2357 case 'e':
2358 opcode |= RS1 (mask);
2359 continue;
2360
252b5132
RH		 2361 case 'f':
2362 case 'B':
2363 case 'R':
2364 opcode |= RS2 (mask);
2365 continue;
2366
ea783ef3
DM		 2367 case '4':
2368 case '5':
2369 opcode |= RS3 (mask);
2370 continue;
2371
252b5132
RH		 2372 case 'g':
2373 case 'H':
2374 case 'J':
2375 opcode |= RD (mask);
2376 continue;
ab3e48dc 2377 } /* Pack it in. */
252b5132
RH		 2378
2379 know (0);
2380 break;
ab3e48dc 2381 } /* float arg */
252b5132
RH		 2382
2383 case 'F':
2384 if (strncmp (s, "%fsr", 4) == 0)
2385 {
2386 s += 4;
2387 continue;
2388 }
2389 break;
2390
ea783ef3
DM		 2391 case '(':
2392 if (strncmp (s, "%efsr", 5) == 0)
2393 {
2394 s += 5;
2395 continue;
2396 }
2397 break;
2398
ab3e48dc
KH		 2399 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2400 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
252b5132
RH		 2401 goto immediate;
2402
ab3e48dc 2403 case 'l': /* 22 bit PC relative immediate */
252b5132
RH		 2404 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2405 the_insn.pcrel = 1;
2406 goto immediate;
2407
ab3e48dc 2408 case 'L': /* 30 bit immediate */
252b5132
RH		 2409 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2410 the_insn.pcrel = 1;
2411 goto immediate;
2412
63fab58c 2413 case 'h':
ab3e48dc 2414 case 'n': /* 22 bit immediate */
252b5132
RH		 2415 the_insn.reloc = BFD_RELOC_SPARC22;
2416 goto immediate;
2417
ab3e48dc 2418 case 'i': /* 13 bit immediate */
252b5132
RH		 2419 the_insn.reloc = BFD_RELOC_SPARC13;
2420
2421 /* fallthrough */
2422
2423 immediate:
2424 if (*s == ' ')
2425 s++;
2426
cf9a1301
RH		 2427 {
2428 char *s1;
2429 char *op_arg = NULL;
30eb9c17 2430 static expressionS op_exp;
cf9a1301
RH		 2431 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2432
2433 /* Check for %hi, etc. */
2434 if (*s == '%')
2435 {
2436 static const struct ops {
2437 /* The name as it appears in assembler. */
2438 char *name;
2439 /* strlen (name), precomputed for speed */
2440 int len;
2441 /* The reloc this pseudo-op translates to. */
2442 int reloc;
2443 /* Non-zero if for v9 only. */
2444 int v9_p;
2445 /* Non-zero if can be used in pc-relative contexts. */
2446 int pcrel_p;/*FIXME:wip*/
2447 } ops[] = {
2448 /* hix/lox must appear before hi/lo so %hix won't be
2449 mistaken for %hi. */
2450 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2451 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2452 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2453 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
14865d76
DM		 2454 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2455 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
cf9a1301
RH		 2456 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2457 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2458 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2615994e
DM		 2459 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2460 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
cf9a1301
RH		 2461 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2462 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2463 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2464 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2465 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
b9734f35
JJ		 2466 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2467 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2468 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2469 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2470 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2471 0 },
2472 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2473 0 },
2474 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2475 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2476 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2477 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
739f7f82
DM		 2478 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2479 0, 0 },
2480 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2481 0, 0 },
c2158c24 2482 { NULL, 0, 0, 0, 0 }
cf9a1301
RH		 2483 };
2484 const struct ops *o;
e0c6ed95 2485
cf9a1301
RH		 2486 for (o = ops; o->name; o++)
2487 if (strncmp (s + 1, o->name, o->len) == 0)
2488 break;
2489 if (o->name == NULL)
252b5132 2490 break;
e0c6ed95 2491
cf9a1301
RH		 2492 if (s[o->len + 1] != '(')
2493 {
2494 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
a22b281c 2495 return special_case;
cf9a1301 2496 }
252b5132 2497
cf9a1301
RH		 2498 op_arg = o->name;
2499 the_insn.reloc = o->reloc;
2500 s += o->len + 2;
2501 v9_arg_p = o->v9_p;
2502 }
2503
2504 /* Note that if the get_expression() fails, we will still
2505 have created U entries in the symbol table for the
2506 'symbols' in the input string. Try not to create U
2507 symbols for registers, etc. */
252b5132 2508
252b5132
RH		 2509 /* This stuff checks to see if the expression ends in
2510 +%reg. If it does, it removes the register from
2511 the expression, and re-sets 's' to point to the
2512 right place. */
2513
cf9a1301
RH		 2514 if (op_arg)
2515 {
2516 int npar = 0;
2517
2518 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2519 if (*s1 == '(')
2520 npar++;
2521 else if (*s1 == ')')
2522 {
2523 if (!npar)
2524 break;
2525 npar--;
2526 }
2527
2528 if (*s1 != ')')
2529 {
2530 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
a22b281c 2531 return special_case;
cf9a1301 2532 }
e0c6ed95 2533
cf9a1301
RH		 2534 *s1 = '\0';
2535 (void) get_expression (s);
2536 *s1 = ')';
2537 s = s1 + 1;
2538 if (*s == ',' || *s == ']' || !*s)
2539 continue;
2540 if (*s != '+' && *s != '-')
2541 {
2542 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
a22b281c 2543 return special_case;
cf9a1301
RH		 2544 }
2545 *s1 = '0';
2546 s = s1;
2547 op_exp = the_insn.exp;
e0c6ed95 2548 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
cf9a1301 2549 }
252b5132 2550
e0c6ed95
AM		 2551 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2552 ;
252b5132 2553
3882b010 2554 if (s1 != s && ISDIGIT (s1[-1]))
252b5132
RH		 2555 {
2556 if (s1[-2] == '%' && s1[-3] == '+')
cf9a1301 2557 s1 -= 3;
f124dd4f 2558 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
cf9a1301 2559 s1 -= 4;
f124dd4f
DM		 2560 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2561 s1 -= 5;
cf9a1301
RH		 2562 else
2563 s1 = NULL;
2564 if (s1)
252b5132 2565 {
252b5132 2566 *s1 = '\0';
1eb7027c
RH		 2567 if (op_arg && s1 == s + 1)
2568 the_insn.exp.X_op = O_absent;
2569 else
2570 (void) get_expression (s);
252b5132 2571 *s1 = '+';
cf9a1301
RH		 2572 if (op_arg)
2573 *s = ')';
252b5132 2574 s = s1;
252b5132 2575 }
cf9a1301
RH		 2576 }
2577 else
2578 s1 = NULL;
2579
2580 if (!s1)
2581 {
2582 (void) get_expression (s);
2583 if (op_arg)
2584 *s = ')';
2585 s = expr_end;
2586 }
2587
2588 if (op_arg)
2589 {
2590 the_insn.exp2 = the_insn.exp;
2591 the_insn.exp = op_exp;
2592 if (the_insn.exp2.X_op == O_absent)
2593 the_insn.exp2.X_op = O_illegal;
2594 else if (the_insn.exp.X_op == O_absent)
252b5132 2595 {
cf9a1301
RH		 2596 the_insn.exp = the_insn.exp2;
2597 the_insn.exp2.X_op = O_illegal;
2598 }
2599 else if (the_insn.exp.X_op == O_constant)
2600 {
2601 valueT val = the_insn.exp.X_add_number;
2602 switch (the_insn.reloc)
2603 {
1b50c718
ILT		 2604 default:
2605 break;
2606
cf9a1301
RH		 2607 case BFD_RELOC_SPARC_HH22:
2608 val = BSR (val, 32);
e0c6ed95 2609 /* Fall through. */
cf9a1301
RH		 2610
2611 case BFD_RELOC_SPARC_LM22:
2612 case BFD_RELOC_HI22:
2613 val = (val >> 10) & 0x3fffff;
2614 break;
2615
2616 case BFD_RELOC_SPARC_HM10:
2617 val = BSR (val, 32);
e0c6ed95 2618 /* Fall through. */
cf9a1301
RH		 2619
2620 case BFD_RELOC_LO10:
2621 val &= 0x3ff;
2622 break;
2623
2615994e
DM		 2624 case BFD_RELOC_SPARC_H34:
2625 val >>= 12;
2626 val &= 0x3fffff;
2627 break;
2628
cf9a1301
RH		 2629 case BFD_RELOC_SPARC_H44:
2630 val >>= 22;
2631 val &= 0x3fffff;
2632 break;
2633
2634 case BFD_RELOC_SPARC_M44:
2635 val >>= 12;
2636 val &= 0x3ff;
2637 break;
2638
2639 case BFD_RELOC_SPARC_L44:
2640 val &= 0xfff;
2641 break;
2642
2643 case BFD_RELOC_SPARC_HIX22:
ab3e48dc 2644 val = ~val;
cf9a1301
RH		 2645 val = (val >> 10) & 0x3fffff;
2646 break;
2647
2648 case BFD_RELOC_SPARC_LOX10:
2649 val = (val & 0x3ff) | 0x1c00;
2650 break;
2651 }
2652 the_insn.exp = the_insn.exp2;
2653 the_insn.exp.X_add_number += val;
2654 the_insn.exp2.X_op = O_illegal;
2655 the_insn.reloc = old_reloc;
2656 }
2657 else if (the_insn.exp2.X_op != O_constant)
2658 {
2659 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
a22b281c 2660 return special_case;
cf9a1301
RH		 2661 }
2662 else
2663 {
dabe3bbc 2664 if (old_reloc != BFD_RELOC_SPARC13
cf9a1301
RH		 2665 || the_insn.reloc != BFD_RELOC_LO10
2666 || sparc_arch_size != 64
2667 || sparc_pic_code)
2668 {
2669 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
a22b281c 2670 return special_case;
cf9a1301
RH		 2671 }
2672 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
252b5132
RH		 2673 }
2674 }
2675 }
252b5132
RH		 2676 /* Check for constants that don't require emitting a reloc. */
2677 if (the_insn.exp.X_op == O_constant
2678 && the_insn.exp.X_add_symbol == 0
2679 && the_insn.exp.X_op_symbol == 0)
2680 {
2681 /* For pc-relative call instructions, we reject
2682 constants to get better code. */
2683 if (the_insn.pcrel
2684 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2685 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2686 {
2687 error_message = _(": PC-relative operand can't be a constant");
2688 goto error;
2689 }
2690
b9734f35
JJ		 2691 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2692 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2693 {
2694 error_message = _(": TLS operand can't be a constant");
2695 goto error;
2696 }
2697
55cf6793 2698 /* Constants that won't fit are checked in md_apply_fix
252b5132
RH		 2699 and bfd_install_relocation.
2700 ??? It would be preferable to install the constants
2701 into the insn here and save having to create a fixS
2702 for each one. There already exists code to handle
55cf6793 2703 all the various cases (e.g. in md_apply_fix and
252b5132
RH		 2704 bfd_install_relocation) so duplicating all that code
2705 here isn't right. */
698544e1
DM		 2706
2707 /* This is a special case to handle cbcond instructions
2708 properly, which can need two relocations. The first
2709 one is for the 5-bit immediate field and the latter
2710 is going to be for the WDISP10 branch part. We
2711 handle the R_SPARC_5 immediate directly here so that
2712 we don't need to add support for multiple relocations
2713 in one instruction just yet. */
2714 if (the_insn.reloc == BFD_RELOC_SPARC_5)
2715 {
2716 valueT val = the_insn.exp.X_add_number;
2717
2718 if (! in_bitfield_range (val, 0x1f))
2719 {
2720 error_message = _(": Immediate value in cbcond is out of range.");
2721 goto error;
2722 }
2723 opcode |= val & 0x1f;
2724 the_insn.reloc = BFD_RELOC_NONE;
2725 }
252b5132
RH		 2726 }
2727
2728 continue;
2729
2730 case 'a':
2731 if (*s++ == 'a')
2732 {
2733 opcode |= ANNUL;
2734 continue;
2735 }
2736 break;
2737
2738 case 'A':
2739 {
2740 int asi = 0;
2741
2742 /* Parse an asi. */
2743 if (*s == '#')
2744 {
2745 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2746 {
2747 error_message = _(": invalid ASI name");
2748 goto error;
2749 }
2750 }
2751 else
2752 {
2753 if (! parse_const_expr_arg (&s, &asi))
2754 {
2755 error_message = _(": invalid ASI expression");
2756 goto error;
2757 }
2758 if (asi < 0 || asi > 255)
2759 {
2760 error_message = _(": invalid ASI number");
2761 goto error;
2762 }
2763 }
2764 opcode |= ASI (asi);
2765 continue;
e0c6ed95 2766 } /* Alternate space. */
252b5132
RH		 2767
2768 case 'p':
2769 if (strncmp (s, "%psr", 4) == 0)
2770 {
2771 s += 4;
2772 continue;
2773 }
2774 break;
2775
e0c6ed95 2776 case 'q': /* Floating point queue. */
252b5132
RH		 2777 if (strncmp (s, "%fq", 3) == 0)
2778 {
2779 s += 3;
2780 continue;
2781 }
2782 break;
2783
e0c6ed95 2784 case 'Q': /* Coprocessor queue. */
252b5132
RH		 2785 if (strncmp (s, "%cq", 3) == 0)
2786 {
2787 s += 3;
2788 continue;
2789 }
2790 break;
2791
2792 case 'S':
2793 if (strcmp (str, "set") == 0
2794 || strcmp (str, "setuw") == 0)
2795 {
2796 special_case = SPECIAL_CASE_SET;
2797 continue;
2798 }
2799 else if (strcmp (str, "setsw") == 0)
2800 {
2801 special_case = SPECIAL_CASE_SETSW;
2802 continue;
2803 }
2804 else if (strcmp (str, "setx") == 0)
2805 {
2806 special_case = SPECIAL_CASE_SETX;
2807 continue;
2808 }
2809 else if (strncmp (str, "fdiv", 4) == 0)
2810 {
2811 special_case = SPECIAL_CASE_FDIV;
2812 continue;
2813 }
2814 break;
2815
2816 case 'o':
2817 if (strncmp (s, "%asi", 4) != 0)
2818 break;
2819 s += 4;
2820 continue;
2821
2822 case 's':
2823 if (strncmp (s, "%fprs", 5) != 0)
2824 break;
2825 s += 5;
2826 continue;
2827
2828 case 'E':
2829 if (strncmp (s, "%ccr", 4) != 0)
2830 break;
2831 s += 4;
2832 continue;
2833
2834 case 't':
2835 if (strncmp (s, "%tbr", 4) != 0)
2836 break;
2837 s += 4;
2838 continue;
2839
2840 case 'w':
2841 if (strncmp (s, "%wim", 4) != 0)
2842 break;
2843 s += 4;
2844 continue;
2845
2846 case 'x':
2847 {
2848 char *push = input_line_pointer;
2849 expressionS e;
2850
2851 input_line_pointer = s;
2852 expression (&e);
2853 if (e.X_op == O_constant)
2854 {
2855 int n = e.X_add_number;
2856 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2857 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2858 else
2859 opcode |= e.X_add_number << 5;
2860 }
2861 else
2862 as_bad (_("non-immediate OPF operand, ignored"));
2863 s = input_line_pointer;
2864 input_line_pointer = push;
2865 continue;
2866 }
2867
2868 case 'y':
2869 if (strncmp (s, "%y", 2) != 0)
2870 break;
2871 s += 2;
2872 continue;
2873
2874 case 'u':
2875 case 'U':
2876 {
2877 /* Parse a sparclet cpreg. */
2878 int cpreg;
2879 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2880 {
2881 error_message = _(": invalid cpreg name");
2882 goto error;
2883 }
2884 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2885 continue;
2886 }
2887
2888 default:
2889 as_fatal (_("failed sanity check."));
e0c6ed95 2890 } /* switch on arg code. */
252b5132
RH		 2891
2892 /* Break out of for() loop. */
2893 break;
e0c6ed95 2894 } /* For each arg that we expect. */
252b5132
RH		 2895
2896 error:
2897 if (match == 0)
2898 {
e0c6ed95 2899 /* Args don't match. */
252b5132
RH		 2900 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2901 && (insn->name == insn[1].name
2902 || !strcmp (insn->name, insn[1].name)))
2903 {
2904 ++insn;
2905 s = argsStart;
2906 continue;
2907 }
2908 else
2909 {
2910 as_bad (_("Illegal operands%s"), error_message);
a22b281c 2911 return special_case;
252b5132
RH		 2912 }
2913 }
2914 else
2915 {
e0c6ed95 2916 /* We have a match. Now see if the architecture is OK. */
252b5132 2917 int needed_arch_mask = insn->architecture;
ec668d69 2918 int hwcaps = insn->hwcaps;
252b5132 2919
4bafe00e 2920#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
9e8c70f9
DM		 2921 if (hwcaps)
2922 hwcap_seen |= hwcaps;
2923#endif
252b5132
RH		 2924 if (v9_arg_p)
2925 {
19f7b010
JJ		 2926 needed_arch_mask &=
2927 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2928 if (! needed_arch_mask)
2929 needed_arch_mask =
2930 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
252b5132
RH		 2931 }
2932
e0c6ed95
AM		 2933 if (needed_arch_mask
2934 & SPARC_OPCODE_SUPPORTED (current_architecture))
2935 /* OK. */
2936 ;
252b5132 2937 /* Can we bump up the architecture? */
e0c6ed95
AM		 2938 else if (needed_arch_mask
2939 & SPARC_OPCODE_SUPPORTED (max_architecture))
252b5132
RH		 2940 {
2941 enum sparc_opcode_arch_val needed_architecture =
2942 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2943 & needed_arch_mask);
2944
9c2799c2 2945 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
252b5132
RH		 2946 if (warn_on_bump
2947 && needed_architecture > warn_after_architecture)
2948 {
2949 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2950 sparc_opcode_archs[current_architecture].name,
2951 sparc_opcode_archs[needed_architecture].name,
2952 str);
2953 warn_after_architecture = needed_architecture;
2954 }
2955 current_architecture = needed_architecture;
2956 }
2957 /* Conflict. */
2958 /* ??? This seems to be a bit fragile. What if the next entry in
2959 the opcode table is the one we want and it is supported?
2960 It is possible to arrange the table today so that this can't
2961 happen but what about tomorrow? */
2962 else
2963 {
e0c6ed95 2964 int arch, printed_one_p = 0;
252b5132
RH		 2965 char *p;
2966 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2967
2968 /* Create a list of the architectures that support the insn. */
e0c6ed95 2969 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
252b5132
RH		 2970 p = required_archs;
2971 arch = sparc_ffs (needed_arch_mask);
2972 while ((1 << arch) <= needed_arch_mask)
2973 {
2974 if ((1 << arch) & needed_arch_mask)
2975 {
2976 if (printed_one_p)
2977 *p++ = '|';
2978 strcpy (p, sparc_opcode_archs[arch].name);
2979 p += strlen (p);
2980 printed_one_p = 1;
2981 }
2982 ++arch;
2983 }
2984
2985 as_bad (_("Architecture mismatch on \"%s\"."), str);
2986 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2987 required_archs,
2988 sparc_opcode_archs[max_architecture].name);
a22b281c 2989 return special_case;
252b5132 2990 }
4bafe00e
DM		 2991
2992 /* Make sure the the hwcaps used by the instruction are
2993 currently enabled. */
2994 if (hwcaps & ~hwcap_allowed)
2995 {
2996 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
2997
2998 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
2999 hwcap_name, str);
3000 return special_case;
3001 }
e0c6ed95 3002 } /* If no match. */
252b5132
RH		 3003
3004 break;
e0c6ed95 3005 } /* Forever looking for a match. */
252b5132
RH		 3006
3007 the_insn.opcode = opcode;
a22b281c 3008 return special_case;
252b5132
RH		 3009}
3010
3011/* Parse an argument that can be expressed as a keyword.
3012 (eg: #StoreStore or %ccfr).
3013 The result is a boolean indicating success.
3014 If successful, INPUT_POINTER is updated. */
3015
3016static int
5a49b8ac
AM		 3017parse_keyword_arg (int (*lookup_fn) (const char *),
3018 char **input_pointerP,
3019 int *valueP)
252b5132
RH		 3020{
3021 int value;
3022 char c, *p, *q;
3023
3024 p = *input_pointerP;
3025 for (q = p + (*p == '#' || *p == '%');
3882b010 3026 ISALNUM (*q) || *q == '_';
252b5132
RH		 3027 ++q)
3028 continue;
3029 c = *q;
3030 *q = 0;
3031 value = (*lookup_fn) (p);
3032 *q = c;
3033 if (value == -1)
3034 return 0;
3035 *valueP = value;
3036 *input_pointerP = q;
3037 return 1;
3038}
3039
3040/* Parse an argument that is a constant expression.
3041 The result is a boolean indicating success. */
3042
3043static int
5a49b8ac 3044parse_const_expr_arg (char **input_pointerP, int *valueP)
252b5132
RH		 3045{
3046 char *save = input_line_pointer;
3047 expressionS exp;
3048
3049 input_line_pointer = *input_pointerP;
3050 /* The next expression may be something other than a constant
3051 (say if we're not processing the right variant of the insn).
3052 Don't call expression unless we're sure it will succeed as it will
3053 signal an error (which we want to defer until later). */
3054 /* FIXME: It might be better to define md_operand and have it recognize
3055 things like %asi, etc. but continuing that route through to the end
3056 is a lot of work. */
3057 if (*input_line_pointer == '%')
3058 {
3059 input_line_pointer = save;
3060 return 0;
3061 }
3062 expression (&exp);
3063 *input_pointerP = input_line_pointer;
3064 input_line_pointer = save;
3065 if (exp.X_op != O_constant)
3066 return 0;
3067 *valueP = exp.X_add_number;
3068 return 1;
3069}
3070
3071/* Subroutine of sparc_ip to parse an expression. */
3072
3073static int
5a49b8ac 3074get_expression (char *str)
252b5132
RH		 3075{
3076 char *save_in;
3077 segT seg;
3078
3079 save_in = input_line_pointer;
3080 input_line_pointer = str;
3081 seg = expression (&the_insn.exp);
3082 if (seg != absolute_section
3083 && seg != text_section
3084 && seg != data_section
3085 && seg != bss_section
3086 && seg != undefined_section)
3087 {
3088 the_insn.error = _("bad segment");
3089 expr_end = input_line_pointer;
3090 input_line_pointer = save_in;
3091 return 1;
3092 }
3093 expr_end = input_line_pointer;
3094 input_line_pointer = save_in;
3095 return 0;
3096}
3097
3098/* Subroutine of md_assemble to output one insn. */
3099
3100static void
91d6fa6a 3101output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
252b5132
RH		 3102{
3103 char *toP = frag_more (4);
3104
e0c6ed95 3105 /* Put out the opcode. */
252b5132 3106 if (INSN_BIG_ENDIAN)
91d6fa6a 3107 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
252b5132 3108 else
91d6fa6a 3109 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
252b5132 3110
e0c6ed95 3111 /* Put out the symbol-dependent stuff. */
91d6fa6a 3112 if (theinsn->reloc != BFD_RELOC_NONE)
252b5132 3113 {
e0c6ed95
AM		 3114 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3115 (toP - frag_now->fr_literal), /* Where. */
3116 4, /* Size. */
91d6fa6a
NC		 3117 &theinsn->exp,
3118 theinsn->pcrel,
3119 theinsn->reloc);
252b5132 3120 /* Turn off overflow checking in fixup_segment. We'll do our
55cf6793 3121 own overflow checking in md_apply_fix. This is necessary because
252b5132
RH		 3122 the insn size is 4 and fixup_segment will signal an overflow for
3123 large 8 byte quantities. */
3124 fixP->fx_no_overflow = 1;
91d6fa6a
NC		 3125 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3126 fixP->tc_fix_data = theinsn->exp2.X_add_number;
252b5132
RH		 3127 }
3128
3129 last_insn = insn;
91d6fa6a 3130 last_opcode = theinsn->opcode;
732d96b6
JJ		 3131
3132#ifdef OBJ_ELF
3133 dwarf2_emit_insn (4);
3134#endif
252b5132
RH		 3135}
3136\f
252b5132 3137char *
499ac353 3138md_atof (int type, char *litP, int *sizeP)
252b5132 3139{
499ac353 3140 return ieee_md_atof (type, litP, sizeP, target_big_endian);
252b5132
RH		 3141}
3142
3143/* Write a value out to the object file, using the appropriate
3144 endianness. */
3145
3146void
5a49b8ac 3147md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 3148{
3149 if (target_big_endian)
3150 number_to_chars_bigendian (buf, val, n);
3151 else if (target_little_endian_data
3152 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
e0c6ed95
AM		 3153 /* Output debug words, which are not in allocated sections, as big
3154 endian. */
252b5132
RH		 3155 number_to_chars_bigendian (buf, val, n);
3156 else if (target_little_endian_data || ! target_big_endian)
3157 number_to_chars_littleendian (buf, val, n);
3158}
3159\f
3160/* Apply a fixS to the frags, now that we know the value it ought to
81d4177b 3161 hold. */
252b5132 3162
94f592af 3163void
5a49b8ac 3164md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
252b5132
RH		 3165{
3166 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
94f592af 3167 offsetT val = * (offsetT *) valP;
252b5132
RH		 3168 long insn;
3169
9c2799c2 3170 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
252b5132 3171
e0c6ed95 3172 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 3173
3174#ifdef OBJ_ELF
a161fe53 3175 /* SPARC ELF relocations don't use an addend in the data field. */
252b5132 3176 if (fixP->fx_addsy != NULL)
7c1d0959
L		 3177 {
3178 switch (fixP->fx_r_type)
3179 {
3180 case BFD_RELOC_SPARC_TLS_GD_HI22:
3181 case BFD_RELOC_SPARC_TLS_GD_LO10:
3182 case BFD_RELOC_SPARC_TLS_GD_ADD:
3183 case BFD_RELOC_SPARC_TLS_GD_CALL:
3184 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3185 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3186 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3187 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3188 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3189 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3190 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3191 case BFD_RELOC_SPARC_TLS_IE_HI22:
3192 case BFD_RELOC_SPARC_TLS_IE_LO10:
3193 case BFD_RELOC_SPARC_TLS_IE_LD:
3194 case BFD_RELOC_SPARC_TLS_IE_LDX:
3195 case BFD_RELOC_SPARC_TLS_IE_ADD:
3196 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3197 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3198 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3199 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3200 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3201 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3202 case BFD_RELOC_SPARC_TLS_TPOFF32:
3203 case BFD_RELOC_SPARC_TLS_TPOFF64:
3204 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3205
3206 default:
3207 break;
3208 }
3209
3210 return;
3211 }
252b5132
RH		 3212#endif
3213
3214 /* This is a hack. There should be a better way to
3215 handle this. Probably in terms of howto fields, once
3216 we can look at these fixups in terms of howtos. */
3217 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3218 val += fixP->fx_where + fixP->fx_frag->fr_address;
3219
3220#ifdef OBJ_AOUT
3221 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3222 generate a reloc, then we just want to let the reloc addend set
3223 the value. We do not want to also stuff the addend into the
3224 object file. Including the addend in the object file works when
3225 doing a static link, because the linker will ignore the object
3226 file contents. However, the dynamic linker does not ignore the
3227 object file contents. */
3228 if (fixP->fx_addsy != NULL
3229 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3230 val = 0;
3231
3232 /* When generating PIC code, we do not want an addend for a reloc
3233 against a local symbol. We adjust fx_addnumber to cancel out the
3234 value already included in val, and to also cancel out the
3235 adjustment which bfd_install_relocation will create. */
3236 if (sparc_pic_code
3237 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3238 && fixP->fx_addsy != NULL
3239 && ! S_IS_COMMON (fixP->fx_addsy)
49309057 3240 && symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3241 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3242
3243 /* When generating PIC code, we need to fiddle to get
3244 bfd_install_relocation to do the right thing for a PC relative
3245 reloc against a local symbol which we are going to keep. */
3246 if (sparc_pic_code
3247 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3248 && fixP->fx_addsy != NULL
3249 && (S_IS_EXTERNAL (fixP->fx_addsy)
3250 || S_IS_WEAK (fixP->fx_addsy))
3251 && S_IS_DEFINED (fixP->fx_addsy)
3252 && ! S_IS_COMMON (fixP->fx_addsy))
3253 {
3254 val = 0;
3255 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3256 }
3257#endif
3258
3259 /* If this is a data relocation, just output VAL. */
3260
a7bbf4e9
DM		 3261 if (fixP->fx_r_type == BFD_RELOC_8)
3262 {
3263 md_number_to_chars (buf, val, 1);
3264 }
3265 else if (fixP->fx_r_type == BFD_RELOC_16
3266 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
252b5132
RH		 3267 {
3268 md_number_to_chars (buf, val, 2);
3269 }
3270 else if (fixP->fx_r_type == BFD_RELOC_32
0f2712ed 3271 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
252b5132
RH		 3272 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3273 {
3274 md_number_to_chars (buf, val, 4);
3275 }
0f2712ed
NC		 3276 else if (fixP->fx_r_type == BFD_RELOC_64
3277 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
252b5132
RH		 3278 {
3279 md_number_to_chars (buf, val, 8);
3280 }
e0c6ed95 3281 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH		 3282 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3283 {
3284 fixP->fx_done = 0;
94f592af 3285 return;
252b5132
RH		 3286 }
3287 else
3288 {
3289 /* It's a relocation against an instruction. */
3290
3291 if (INSN_BIG_ENDIAN)
3292 insn = bfd_getb32 ((unsigned char *) buf);
3293 else
3294 insn = bfd_getl32 ((unsigned char *) buf);
e0c6ed95 3295
252b5132
RH		 3296 switch (fixP->fx_r_type)
3297 {
3298 case BFD_RELOC_32_PCREL_S2:
3299 val = val >> 2;
3300 /* FIXME: This increment-by-one deserves a comment of why it's
3301 being done! */
3302 if (! sparc_pic_code
3303 || fixP->fx_addsy == NULL
49309057 3304 || symbol_section_p (fixP->fx_addsy))
252b5132 3305 ++val;
6faf3d66 3306
252b5132 3307 insn |= val & 0x3fffffff;
6faf3d66 3308
e0c6ed95 3309 /* See if we have a delay slot. */
6faf3d66
JJ		 3310 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3311 {
3312#define G0 0
3313#define O7 15
3314#define XCC (2 << 20)
3315#define COND(x) (((x)&0xf)<<25)
3316#define CONDA COND(0x8)
3317#define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3318#define INSN_BA (F2(0,2) | CONDA)
3319#define INSN_OR F3(2, 0x2, 0)
3320#define INSN_NOP F2(0,4)
3321
3322 long delay;
3323
3324 /* If the instruction is a call with either:
3325 restore
3326 arithmetic instruction with rd == %o7
3327 where rs1 != %o7 and rs2 if it is register != %o7
3328 then we can optimize if the call destination is near
3329 by changing the call into a branch always. */
3330 if (INSN_BIG_ENDIAN)
3331 delay = bfd_getb32 ((unsigned char *) buf + 4);
3332 else
3333 delay = bfd_getl32 ((unsigned char *) buf + 4);
e0c6ed95 3334 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
6faf3d66 3335 break;
e0c6ed95
AM		 3336 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3337 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3338 || ((delay & RD (~0)) != RD (O7))))
6faf3d66 3339 break;
e0c6ed95
AM		 3340 if ((delay & RS1 (~0)) == RS1 (O7)
3341 || ((delay & F3I (~0)) == 0
3342 && (delay & RS2 (~0)) == RS2 (O7)))
6faf3d66
JJ		 3343 break;
3344 /* Ensure the branch will fit into simm22. */
3345 if ((val & 0x3fe00000)
3346 && (val & 0x3fe00000) != 0x3fe00000)
3347 break;
3348 /* Check if the arch is v9 and branch will fit
3349 into simm19. */
3350 if (((val & 0x3c0000) == 0
3351 || (val & 0x3c0000) == 0x3c0000)
3352 && (sparc_arch_size == 64
3353 || current_architecture >= SPARC_OPCODE_ARCH_V9))
e0c6ed95 3354 /* ba,pt %xcc */
6faf3d66
JJ		 3355 insn = INSN_BPA | (val & 0x7ffff);
3356 else
e0c6ed95 3357 /* ba */
6faf3d66
JJ		 3358 insn = INSN_BA | (val & 0x3fffff);
3359 if (fixP->fx_where >= 4
e0c6ed95
AM		 3360 && ((delay & (0xffffffff ^ RS1 (~0)))
3361 == (INSN_OR | RD (O7) | RS2 (G0))))
6faf3d66
JJ		 3362 {
3363 long setter;
3364 int reg;
3365
3366 if (INSN_BIG_ENDIAN)
3367 setter = bfd_getb32 ((unsigned char *) buf - 4);
3368 else
3369 setter = bfd_getl32 ((unsigned char *) buf - 4);
e0c6ed95 3370 if ((setter & (0xffffffff ^ RD (~0)))
ab3e48dc 3371 != (INSN_OR | RS1 (O7) | RS2 (G0)))
6faf3d66
JJ		 3372 break;
3373 /* The sequence was
3374 or %o7, %g0, %rN
3375 call foo
3376 or %rN, %g0, %o7
3377
3378 If call foo was replaced with ba, replace
3379 or %rN, %g0, %o7 with nop. */
e0c6ed95
AM		 3380 reg = (delay & RS1 (~0)) >> 14;
3381 if (reg != ((setter & RD (~0)) >> 25)
6faf3d66
JJ		 3382 || reg == G0 || reg == O7)
3383 break;
3384
3385 if (INSN_BIG_ENDIAN)
3386 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3387 else
3388 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3389 }
3390 }
252b5132
RH		 3391 break;
3392
3393 case BFD_RELOC_SPARC_11:
3394 if (! in_signed_range (val, 0x7ff))
3395 as_bad_where (fixP->fx_file, fixP->fx_line,
3396 _("relocation overflow"));
3397 insn |= val & 0x7ff;
3398 break;
3399
3400 case BFD_RELOC_SPARC_10:
3401 if (! in_signed_range (val, 0x3ff))
3402 as_bad_where (fixP->fx_file, fixP->fx_line,
3403 _("relocation overflow"));
3404 insn |= val & 0x3ff;
3405 break;
3406
3407 case BFD_RELOC_SPARC_7:
3408 if (! in_bitfield_range (val, 0x7f))
3409 as_bad_where (fixP->fx_file, fixP->fx_line,
3410 _("relocation overflow"));
3411 insn |= val & 0x7f;
3412 break;
3413
3414 case BFD_RELOC_SPARC_6:
3415 if (! in_bitfield_range (val, 0x3f))
3416 as_bad_where (fixP->fx_file, fixP->fx_line,
3417 _("relocation overflow"));
3418 insn |= val & 0x3f;
3419 break;
3420
3421 case BFD_RELOC_SPARC_5:
3422 if (! in_bitfield_range (val, 0x1f))
3423 as_bad_where (fixP->fx_file, fixP->fx_line,
3424 _("relocation overflow"));
3425 insn |= val & 0x1f;
3426 break;
3427
2615994e
DM		 3428 case BFD_RELOC_SPARC_WDISP10:
3429 if ((val & 3)
3430 || val >= 0x007fc
3431 || val <= -(offsetT) 0x808)
3432 as_bad_where (fixP->fx_file, fixP->fx_line,
3433 _("relocation overflow"));
3434 /* FIXME: The +1 deserves a comment. */
3435 val = (val >> 2) + 1;
3436 insn |= ((val & 0x300) << 11)
3437 | ((val & 0xff) << 5);
3438 break;
3439
252b5132 3440 case BFD_RELOC_SPARC_WDISP16:
c699f087
JJ		 3441 if ((val & 3)
3442 || val >= 0x1fffc
3443 || val <= -(offsetT) 0x20008)
252b5132
RH		 3444 as_bad_where (fixP->fx_file, fixP->fx_line,
3445 _("relocation overflow"));
3446 /* FIXME: The +1 deserves a comment. */
3447 val = (val >> 2) + 1;
3448 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3449 break;
3450
3451 case BFD_RELOC_SPARC_WDISP19:
c699f087
JJ		 3452 if ((val & 3)
3453 || val >= 0xffffc
3454 || val <= -(offsetT) 0x100008)
252b5132
RH		 3455 as_bad_where (fixP->fx_file, fixP->fx_line,
3456 _("relocation overflow"));
3457 /* FIXME: The +1 deserves a comment. */
3458 val = (val >> 2) + 1;
3459 insn |= val & 0x7ffff;
3460 break;
3461
3462 case BFD_RELOC_SPARC_HH22:
3463 val = BSR (val, 32);
e0c6ed95 3464 /* Fall through. */
252b5132
RH		 3465
3466 case BFD_RELOC_SPARC_LM22:
3467 case BFD_RELOC_HI22:
3468 if (!fixP->fx_addsy)
94f592af 3469 insn |= (val >> 10) & 0x3fffff;
252b5132 3470 else
94f592af
NC		 3471 /* FIXME: Need comment explaining why we do this. */
3472 insn &= ~0xffff;
252b5132
RH		 3473 break;
3474
3475 case BFD_RELOC_SPARC22:
3476 if (val & ~0x003fffff)
3477 as_bad_where (fixP->fx_file, fixP->fx_line,
3478 _("relocation overflow"));
3479 insn |= (val & 0x3fffff);
3480 break;
3481
3482 case BFD_RELOC_SPARC_HM10:
3483 val = BSR (val, 32);
e0c6ed95 3484 /* Fall through. */
252b5132
RH		 3485
3486 case BFD_RELOC_LO10:
3487 if (!fixP->fx_addsy)
94f592af 3488 insn |= val & 0x3ff;
252b5132 3489 else
94f592af
NC		 3490 /* FIXME: Need comment explaining why we do this. */
3491 insn &= ~0xff;
252b5132
RH		 3492 break;
3493
dabe3bbc
RH		 3494 case BFD_RELOC_SPARC_OLO10:
3495 val &= 0x3ff;
3496 val += fixP->tc_fix_data;
e0c6ed95 3497 /* Fall through. */
dabe3bbc 3498
252b5132
RH		 3499 case BFD_RELOC_SPARC13:
3500 if (! in_signed_range (val, 0x1fff))
3501 as_bad_where (fixP->fx_file, fixP->fx_line,
3502 _("relocation overflow"));
3503 insn |= val & 0x1fff;
3504 break;
3505
3506 case BFD_RELOC_SPARC_WDISP22:
3507 val = (val >> 2) + 1;
e0c6ed95 3508 /* Fall through. */
252b5132
RH		 3509 case BFD_RELOC_SPARC_BASE22:
3510 insn |= val & 0x3fffff;
3511 break;
3512
2615994e
DM		 3513 case BFD_RELOC_SPARC_H34:
3514 if (!fixP->fx_addsy)
3515 {
3516 bfd_vma tval = val;
3517 tval >>= 12;
3518 insn |= tval & 0x3fffff;
3519 }
3520 break;
3521
252b5132
RH		 3522 case BFD_RELOC_SPARC_H44:
3523 if (!fixP->fx_addsy)
3524 {
3525 bfd_vma tval = val;
3526 tval >>= 22;
3527 insn |= tval & 0x3fffff;
3528 }
3529 break;
3530
3531 case BFD_RELOC_SPARC_M44:
3532 if (!fixP->fx_addsy)
3533 insn |= (val >> 12) & 0x3ff;
3534 break;
3535
3536 case BFD_RELOC_SPARC_L44:
3537 if (!fixP->fx_addsy)
3538 insn |= val & 0xfff;
3539 break;
3540
3541 case BFD_RELOC_SPARC_HIX22:
3542 if (!fixP->fx_addsy)
3543 {
ab3e48dc 3544 val ^= ~(offsetT) 0;
252b5132
RH		 3545 insn |= (val >> 10) & 0x3fffff;
3546 }
3547 break;
3548
3549 case BFD_RELOC_SPARC_LOX10:
3550 if (!fixP->fx_addsy)
3551 insn |= 0x1c00 | (val & 0x3ff);
3552 break;
3553
3554 case BFD_RELOC_NONE:
3555 default:
3556 as_bad_where (fixP->fx_file, fixP->fx_line,
3557 _("bad or unhandled relocation type: 0x%02x"),
3558 fixP->fx_r_type);
3559 break;
3560 }
3561
3562 if (INSN_BIG_ENDIAN)
3563 bfd_putb32 (insn, (unsigned char *) buf);
3564 else
3565 bfd_putl32 (insn, (unsigned char *) buf);
3566 }
3567
3568 /* Are we finished with this relocation now? */
3569 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3570 fixP->fx_done = 1;
252b5132
RH		 3571}
3572
3573/* Translate internal representation of relocation info to BFD target
3574 format. */
e0c6ed95 3575
dabe3bbc 3576arelent **
5a49b8ac 3577tc_gen_reloc (asection *section, fixS *fixp)
252b5132 3578{
dabe3bbc 3579 static arelent *relocs[3];
252b5132
RH		 3580 arelent *reloc;
3581 bfd_reloc_code_real_type code;
3582
dabe3bbc
RH		 3583 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3584 relocs[1] = NULL;
252b5132 3585
49309057
ILT		 3586 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3587 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 3588 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3589
3590 switch (fixp->fx_r_type)
3591 {
3592 case BFD_RELOC_16:
3593 case BFD_RELOC_32:
3594 case BFD_RELOC_HI22:
3595 case BFD_RELOC_LO10:
3596 case BFD_RELOC_32_PCREL_S2:
3597 case BFD_RELOC_SPARC13:
63fab58c 3598 case BFD_RELOC_SPARC22:
1a6b486f
DM		 3599 case BFD_RELOC_SPARC_PC22:
3600 case BFD_RELOC_SPARC_PC10:
252b5132 3601 case BFD_RELOC_SPARC_BASE13:
2615994e 3602 case BFD_RELOC_SPARC_WDISP10:
252b5132
RH		 3603 case BFD_RELOC_SPARC_WDISP16:
3604 case BFD_RELOC_SPARC_WDISP19:
3605 case BFD_RELOC_SPARC_WDISP22:
3606 case BFD_RELOC_64:
3607 case BFD_RELOC_SPARC_5:
3608 case BFD_RELOC_SPARC_6:
3609 case BFD_RELOC_SPARC_7:
3610 case BFD_RELOC_SPARC_10:
3611 case BFD_RELOC_SPARC_11:
3612 case BFD_RELOC_SPARC_HH22:
3613 case BFD_RELOC_SPARC_HM10:
3614 case BFD_RELOC_SPARC_LM22:
3615 case BFD_RELOC_SPARC_PC_HH22:
3616 case BFD_RELOC_SPARC_PC_HM10:
3617 case BFD_RELOC_SPARC_PC_LM22:
2615994e 3618 case BFD_RELOC_SPARC_H34:
252b5132
RH		 3619 case BFD_RELOC_SPARC_H44:
3620 case BFD_RELOC_SPARC_M44:
3621 case BFD_RELOC_SPARC_L44:
3622 case BFD_RELOC_SPARC_HIX22:
3623 case BFD_RELOC_SPARC_LOX10:
3624 case BFD_RELOC_SPARC_REV32:
dabe3bbc 3625 case BFD_RELOC_SPARC_OLO10:
0f2712ed
NC		 3626 case BFD_RELOC_SPARC_UA16:
3627 case BFD_RELOC_SPARC_UA32:
3628 case BFD_RELOC_SPARC_UA64:
bd5e6e7e
JJ		 3629 case BFD_RELOC_8_PCREL:
3630 case BFD_RELOC_16_PCREL:
3631 case BFD_RELOC_32_PCREL:
3632 case BFD_RELOC_64_PCREL:
3633 case BFD_RELOC_SPARC_PLT32:
3634 case BFD_RELOC_SPARC_PLT64:
252b5132
RH		 3635 case BFD_RELOC_VTABLE_ENTRY:
3636 case BFD_RELOC_VTABLE_INHERIT:
b9734f35
JJ		 3637 case BFD_RELOC_SPARC_TLS_GD_HI22:
3638 case BFD_RELOC_SPARC_TLS_GD_LO10:
3639 case BFD_RELOC_SPARC_TLS_GD_ADD:
3640 case BFD_RELOC_SPARC_TLS_GD_CALL:
3641 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3642 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3643 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3644 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3645 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3646 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3647 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3648 case BFD_RELOC_SPARC_TLS_IE_HI22:
3649 case BFD_RELOC_SPARC_TLS_IE_LO10:
3650 case BFD_RELOC_SPARC_TLS_IE_LD:
3651 case BFD_RELOC_SPARC_TLS_IE_LDX:
3652 case BFD_RELOC_SPARC_TLS_IE_ADD:
3653 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3654 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3655 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3656 case BFD_RELOC_SPARC_TLS_DTPOFF64:
739f7f82
DM		 3657 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3658 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3659 case BFD_RELOC_SPARC_GOTDATA_OP:
252b5132
RH		 3660 code = fixp->fx_r_type;
3661 break;
3662 default:
3663 abort ();
3664 return NULL;
3665 }
3666
3667#if defined (OBJ_ELF) || defined (OBJ_AOUT)
3668 /* If we are generating PIC code, we need to generate a different
3669 set of relocs. */
3670
3671#ifdef OBJ_ELF
3672#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3673#else
3674#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
910600e9
RS		 3675#endif
3676#ifdef TE_VXWORKS
3677#define GOTT_BASE "__GOTT_BASE__"
3678#define GOTT_INDEX "__GOTT_INDEX__"
252b5132
RH		 3679#endif
3680
153b546a
ILT		 3681 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3682
252b5132
RH		 3683 if (sparc_pic_code)
3684 {
3685 switch (code)
3686 {
3687 case BFD_RELOC_32_PCREL_S2:
ae6063d4 3688 if (generic_force_reloc (fixp))
252b5132
RH		 3689 code = BFD_RELOC_SPARC_WPLT30;
3690 break;
3691 case BFD_RELOC_HI22:
910600e9
RS		 3692 code = BFD_RELOC_SPARC_GOT22;
3693 if (fixp->fx_addsy != NULL)
3694 {
3695 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3696 code = BFD_RELOC_SPARC_PC22;
3697#ifdef TE_VXWORKS
3698 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3699 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3700 code = BFD_RELOC_HI22; /* Unchanged. */
3701#endif
3702 }
252b5132
RH		 3703 break;
3704 case BFD_RELOC_LO10:
910600e9
RS		 3705 code = BFD_RELOC_SPARC_GOT10;
3706 if (fixp->fx_addsy != NULL)
3707 {
3708 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3709 code = BFD_RELOC_SPARC_PC10;
3710#ifdef TE_VXWORKS
3711 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3712 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3713 code = BFD_RELOC_LO10; /* Unchanged. */
3714#endif
3715 }
252b5132
RH		 3716 break;
3717 case BFD_RELOC_SPARC13:
3718 code = BFD_RELOC_SPARC_GOT13;
3719 break;
3720 default:
3721 break;
3722 }
3723 }
e0c6ed95 3724#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
252b5132 3725
062cf837
EB		 3726 /* Nothing is aligned in DWARF debugging sections. */
3727 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3728 switch (code)
3729 {
3730 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3731 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3732 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3733 default: break;
3734 }
3735
dabe3bbc
RH		 3736 if (code == BFD_RELOC_SPARC_OLO10)
3737 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3738 else
3739 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
252b5132
RH		 3740 if (reloc->howto == 0)
3741 {
3742 as_bad_where (fixp->fx_file, fixp->fx_line,
3743 _("internal error: can't export reloc type %d (`%s')"),
3744 fixp->fx_r_type, bfd_get_reloc_code_name (code));
dabe3bbc
RH		 3745 xfree (reloc);
3746 relocs[0] = NULL;
3747 return relocs;
252b5132
RH		 3748 }
3749
3750 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3751#ifdef OBJ_AOUT
3752
3753 if (reloc->howto->pc_relative == 0
3754 || code == BFD_RELOC_SPARC_PC10
3755 || code == BFD_RELOC_SPARC_PC22)
3756 reloc->addend = fixp->fx_addnumber;
3757 else if (sparc_pic_code
3758 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3759 && fixp->fx_addsy != NULL
3760 && (S_IS_EXTERNAL (fixp->fx_addsy)
3761 || S_IS_WEAK (fixp->fx_addsy))
3762 && S_IS_DEFINED (fixp->fx_addsy)
3763 && ! S_IS_COMMON (fixp->fx_addsy))
3764 reloc->addend = fixp->fx_addnumber;
3765 else
3766 reloc->addend = fixp->fx_offset - reloc->address;
3767
e0c6ed95 3768#else /* elf or coff */
252b5132 3769
bd5e6e7e
JJ		 3770 if (code != BFD_RELOC_32_PCREL_S2
3771 && code != BFD_RELOC_SPARC_WDISP22
3772 && code != BFD_RELOC_SPARC_WDISP16
3773 && code != BFD_RELOC_SPARC_WDISP19
2615994e 3774 && code != BFD_RELOC_SPARC_WDISP10
b9734f35
JJ		 3775 && code != BFD_RELOC_SPARC_WPLT30
3776 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3777 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
252b5132 3778 reloc->addend = fixp->fx_addnumber;
49309057 3779 else if (symbol_section_p (fixp->fx_addsy))
252b5132
RH		 3780 reloc->addend = (section->vma
3781 + fixp->fx_addnumber
3782 + md_pcrel_from (fixp));
3783 else
3784 reloc->addend = fixp->fx_offset;
3785#endif
3786
dabe3bbc
RH		 3787 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3788 on the same location. */
3789 if (code == BFD_RELOC_SPARC_OLO10)
3790 {
3791 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3792 relocs[2] = NULL;
3793
3794 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
ab3e48dc
KH		 3795 *reloc->sym_ptr_ptr
3796 = symbol_get_bfdsym (section_symbol (absolute_section));
dabe3bbc
RH		 3797 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3798 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3799 reloc->addend = fixp->tc_fix_data;
3800 }
3801
3802 return relocs;
252b5132
RH		 3803}
3804\f
e0c6ed95 3805/* We have no need to default values of symbols. */
252b5132 3806
252b5132 3807symbolS *
5a49b8ac 3808md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 3809{
3810 return 0;
e0c6ed95
AM		 3811}
3812
3813/* Round up a section size to the appropriate boundary. */
252b5132 3814
252b5132 3815valueT
5a49b8ac 3816md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 3817{
3818#ifndef OBJ_ELF
3819 /* This is not right for ELF; a.out wants it, and COFF will force
3820 the alignment anyways. */
3821 valueT align = ((valueT) 1
3822 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3823 valueT newsize;
e0c6ed95
AM		 3824
3825 /* Turn alignment value into a mask. */
252b5132
RH		 3826 align--;
3827 newsize = (size + align) & ~align;
3828 return newsize;
3829#else
3830 return size;
3831#endif
3832}
3833
3834/* Exactly what point is a PC-relative offset relative TO?
3835 On the sparc, they're relative to the address of the offset, plus
3836 its size. This gets us to the following instruction.
e0c6ed95
AM		 3837 (??? Is this right? FIXME-SOON) */
3838long
5a49b8ac 3839md_pcrel_from (fixS *fixP)
252b5132
RH		 3840{
3841 long ret;
3842
3843 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3844 if (! sparc_pic_code
3845 || fixP->fx_addsy == NULL
49309057 3846 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3847 ret += fixP->fx_size;
3848 return ret;
3849}
3850\f
3851/* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3852 of two. */
3853
3854static int
5a49b8ac 3855mylog2 (int value)
252b5132
RH		 3856{
3857 int shift;
3858
3859 if (value <= 0)
3860 return -1;
3861
3862 for (shift = 0; (value & 1) == 0; value >>= 1)
3863 ++shift;
3864
3865 return (value == 1) ? shift : -1;
3866}
3867
e0c6ed95 3868/* Sort of like s_lcomm. */
252b5132
RH		 3869
3870#ifndef OBJ_ELF
3871static int max_alignment = 15;
3872#endif
3873
3874static void
5a49b8ac 3875s_reserve (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 3876{
3877 char *name;
3878 char *p;
3879 char c;
3880 int align;
3881 int size;
3882 int temp;
3883 symbolS *symbolP;
3884
3885 name = input_line_pointer;
3886 c = get_symbol_end ();
3887 p = input_line_pointer;
3888 *p = c;
3889 SKIP_WHITESPACE ();
3890
3891 if (*input_line_pointer != ',')
3892 {
3893 as_bad (_("Expected comma after name"));
3894 ignore_rest_of_line ();
3895 return;
3896 }
3897
3898 ++input_line_pointer;
3899
3900 if ((size = get_absolute_expression ()) < 0)
3901 {
3902 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3903 ignore_rest_of_line ();
3904 return;
e0c6ed95 3905 } /* Bad length. */
252b5132
RH		 3906
3907 *p = 0;
3908 symbolP = symbol_find_or_make (name);
3909 *p = c;
3910
3911 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3912 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3913 {
3914 as_bad (_("bad .reserve segment -- expected BSS segment"));
3915 return;
3916 }
3917
3918 if (input_line_pointer[2] == '.')
3919 input_line_pointer += 7;
3920 else
3921 input_line_pointer += 6;
3922 SKIP_WHITESPACE ();
3923
3924 if (*input_line_pointer == ',')
3925 {
3926 ++input_line_pointer;
3927
3928 SKIP_WHITESPACE ();
3929 if (*input_line_pointer == '\n')
3930 {
3931 as_bad (_("missing alignment"));
3932 ignore_rest_of_line ();
3933 return;
3934 }
3935
3936 align = (int) get_absolute_expression ();
3937
3938#ifndef OBJ_ELF
3939 if (align > max_alignment)
3940 {
3941 align = max_alignment;
3942 as_warn (_("alignment too large; assuming %d"), align);
3943 }
3944#endif
3945
3946 if (align < 0)
3947 {
3948 as_bad (_("negative alignment"));
3949 ignore_rest_of_line ();
3950 return;
3951 }
3952
3953 if (align != 0)
3954 {
f17c130b 3955 temp = mylog2 (align);
252b5132
RH		 3956 if (temp < 0)
3957 {
3958 as_bad (_("alignment not a power of 2"));
3959 ignore_rest_of_line ();
3960 return;
3961 }
3962
3963 align = temp;
3964 }
3965
3966 record_alignment (bss_section, align);
3967 }
3968 else
3969 align = 0;
3970
3971 if (!S_IS_DEFINED (symbolP)
3972#ifdef OBJ_AOUT
3973 && S_GET_OTHER (symbolP) == 0
3974 && S_GET_DESC (symbolP) == 0
3975#endif
3976 )
3977 {
3978 if (! need_pass_2)
3979 {
3980 char *pfrag;
3981 segT current_seg = now_seg;
3982 subsegT current_subseg = now_subseg;
3983
e0c6ed95
AM		 3984 /* Switch to bss. */
3985 subseg_set (bss_section, 1);
252b5132
RH		 3986
3987 if (align)
e0c6ed95
AM		 3988 /* Do alignment. */
3989 frag_align (align, 0, 0);
252b5132 3990
e0c6ed95 3991 /* Detach from old frag. */
ab3e48dc 3992 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057 3993 symbol_get_frag (symbolP)->fr_symbol = NULL;
252b5132 3994
49309057 3995 symbol_set_frag (symbolP, frag_now);
e0c6ed95
AM		 3996 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3997 (offsetT) size, (char *) 0);
252b5132
RH		 3998 *pfrag = 0;
3999
4000 S_SET_SEGMENT (symbolP, bss_section);
4001
4002 subseg_set (current_seg, current_subseg);
4003
4004#ifdef OBJ_ELF
4005 S_SET_SIZE (symbolP, size);
4006#endif
4007 }
4008 }
4009 else
4010 {
20203fb9 4011 as_warn (_("Ignoring attempt to re-define symbol %s"),
ab3e48dc 4012 S_GET_NAME (symbolP));
20203fb9 4013 }
252b5132
RH		 4014
4015 demand_empty_rest_of_line ();
4016}
4017
4018static void
5a49b8ac 4019s_common (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4020{
4021 char *name;
4022 char c;
4023 char *p;
685736be 4024 offsetT temp, size;
252b5132
RH		 4025 symbolS *symbolP;
4026
4027 name = input_line_pointer;
4028 c = get_symbol_end ();
e0c6ed95 4029 /* Just after name is now '\0'. */
252b5132
RH		 4030 p = input_line_pointer;
4031 *p = c;
4032 SKIP_WHITESPACE ();
4033 if (*input_line_pointer != ',')
4034 {
4035 as_bad (_("Expected comma after symbol-name"));
4036 ignore_rest_of_line ();
4037 return;
4038 }
e0c6ed95
AM		 4039
4040 /* Skip ','. */
4041 input_line_pointer++;
4042
252b5132
RH		 4043 if ((temp = get_absolute_expression ()) < 0)
4044 {
685736be
NC		 4045 as_bad (_(".COMMon length (%lu) out of range ignored"),
4046 (unsigned long) temp);
252b5132
RH		 4047 ignore_rest_of_line ();
4048 return;
4049 }
4050 size = temp;
4051 *p = 0;
4052 symbolP = symbol_find_or_make (name);
4053 *p = c;
4054 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4055 {
4056 as_bad (_("Ignoring attempt to re-define symbol"));
4057 ignore_rest_of_line ();
4058 return;
4059 }
4060 if (S_GET_VALUE (symbolP) != 0)
4061 {
4062 if (S_GET_VALUE (symbolP) != (valueT) size)
4063 {
364b6d8b
JJ		 4064 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4065 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
252b5132
RH		 4066 }
4067 }
4068 else
4069 {
4070#ifndef OBJ_ELF
4071 S_SET_VALUE (symbolP, (valueT) size);
4072 S_SET_EXTERNAL (symbolP);
4073#endif
4074 }
7dcc9865 4075 know (symbol_get_frag (symbolP) == &zero_address_frag);
252b5132
RH		 4076 if (*input_line_pointer != ',')
4077 {
4078 as_bad (_("Expected comma after common length"));
4079 ignore_rest_of_line ();
4080 return;
4081 }
4082 input_line_pointer++;
4083 SKIP_WHITESPACE ();
4084 if (*input_line_pointer != '"')
4085 {
4086 temp = get_absolute_expression ();
4087
4088#ifndef OBJ_ELF
4089 if (temp > max_alignment)
4090 {
4091 temp = max_alignment;
f17c130b 4092 as_warn (_("alignment too large; assuming %ld"), (long) temp);
252b5132
RH		 4093 }
4094#endif
4095
4096 if (temp < 0)
4097 {
4098 as_bad (_("negative alignment"));
4099 ignore_rest_of_line ();
4100 return;
4101 }
4102
4103#ifdef OBJ_ELF
49309057 4104 if (symbol_get_obj (symbolP)->local)
252b5132
RH		 4105 {
4106 segT old_sec;
4107 int old_subsec;
252b5132
RH		 4108 int align;
4109
4110 old_sec = now_seg;
4111 old_subsec = now_subseg;
4112
4113 if (temp == 0)
4114 align = 0;
4115 else
f17c130b 4116 align = mylog2 (temp);
252b5132
RH		 4117
4118 if (align < 0)
4119 {
4120 as_bad (_("alignment not a power of 2"));
4121 ignore_rest_of_line ();
4122 return;
4123 }
4124
4125 record_alignment (bss_section, align);
4126 subseg_set (bss_section, 0);
4127 if (align)
4128 frag_align (align, 0, 0);
4129 if (S_GET_SEGMENT (symbolP) == bss_section)
49309057
ILT		 4130 symbol_get_frag (symbolP)->fr_symbol = 0;
4131 symbol_set_frag (symbolP, frag_now);
252b5132
RH		 4132 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4133 (offsetT) size, (char *) 0);
4134 *p = 0;
4135 S_SET_SEGMENT (symbolP, bss_section);
4136 S_CLEAR_EXTERNAL (symbolP);
4137 S_SET_SIZE (symbolP, size);
4138 subseg_set (old_sec, old_subsec);
4139 }
4140 else
e0c6ed95 4141#endif /* OBJ_ELF */
252b5132
RH		 4142 {
4143 allocate_common:
4144 S_SET_VALUE (symbolP, (valueT) size);
4145#ifdef OBJ_ELF
4146 S_SET_ALIGN (symbolP, temp);
4147 S_SET_SIZE (symbolP, size);
4148#endif
4149 S_SET_EXTERNAL (symbolP);
4150 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4151 }
4152 }
4153 else
4154 {
4155 input_line_pointer++;
4156 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4157 if (*input_line_pointer == '.')
4158 input_line_pointer++;
4159 /* @@ Some say data, some say bss. */
4160 if (strncmp (input_line_pointer, "bss\"", 4)
4161 && strncmp (input_line_pointer, "data\"", 5))
4162 {
4163 while (*--input_line_pointer != '"')
4164 ;
4165 input_line_pointer--;
4166 goto bad_common_segment;
4167 }
4168 while (*input_line_pointer++ != '"')
4169 ;
4170 goto allocate_common;
4171 }
4172
49309057 4173 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
252b5132
RH		 4174
4175 demand_empty_rest_of_line ();
4176 return;
4177
4178 {
4179 bad_common_segment:
4180 p = input_line_pointer;
4181 while (*p && *p != '\n')
4182 p++;
4183 c = *p;
4184 *p = '\0';
4185 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4186 *p = c;
4187 input_line_pointer = p;
4188 ignore_rest_of_line ();
4189 return;
4190 }
4191}
4192
67c1ffbe 4193/* Handle the .empty pseudo-op. This suppresses the warnings about
252b5132
RH		 4194 invalid delay slot usage. */
4195
4196static void
5a49b8ac 4197s_empty (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4198{
4199 /* The easy way to implement is to just forget about the last
4200 instruction. */
4201 last_insn = NULL;
4202}
4203
4204static void
5a49b8ac 4205s_seg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4206{
4207
4208 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4209 {
4210 input_line_pointer += 6;
4211 s_text (0);
4212 return;
4213 }
4214 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4215 {
4216 input_line_pointer += 6;
4217 s_data (0);
4218 return;
4219 }
4220 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4221 {
4222 input_line_pointer += 7;
4223 s_data1 ();
4224 return;
4225 }
4226 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4227 {
4228 input_line_pointer += 5;
4229 /* We only support 2 segments -- text and data -- for now, so
4230 things in the "bss segment" will have to go into data for now.
e0c6ed95
AM		 4231 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4232 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
252b5132
RH		 4233 return;
4234 }
4235 as_bad (_("Unknown segment type"));
4236 demand_empty_rest_of_line ();
4237}
4238
4239static void
5a49b8ac 4240s_data1 (void)
252b5132
RH		 4241{
4242 subseg_set (data_section, 1);
4243 demand_empty_rest_of_line ();
4244}
4245
4246static void
5a49b8ac 4247s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 4248{
4249 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4250 {
4251 ++input_line_pointer;
4252 }
4253 ++input_line_pointer;
4254}
4255
4256/* This static variable is set by s_uacons to tell sparc_cons_align
67c1ffbe 4257 that the expression does not need to be aligned. */
252b5132
RH		 4258
4259static int sparc_no_align_cons = 0;
4260
bd5e6e7e
JJ		 4261/* This static variable is set by sparc_cons to emit requested types
4262 of relocations in cons_fix_new_sparc. */
4263
4264static const char *sparc_cons_special_reloc;
4265
252b5132
RH		 4266/* This handles the unaligned space allocation pseudo-ops, such as
4267 .uaword. .uaword is just like .word, but the value does not need
4268 to be aligned. */
4269
4270static void
5a49b8ac 4271s_uacons (int bytes)
252b5132
RH		 4272{
4273 /* Tell sparc_cons_align not to align this value. */
4274 sparc_no_align_cons = 1;
4275 cons (bytes);
4ffadb11 4276 sparc_no_align_cons = 0;
252b5132
RH		 4277}
4278
cf9a1301
RH		 4279/* This handles the native word allocation pseudo-op .nword.
4280 For sparc_arch_size 32 it is equivalent to .word, for
4281 sparc_arch_size 64 it is equivalent to .xword. */
4282
4283static void
5a49b8ac 4284s_ncons (int bytes ATTRIBUTE_UNUSED)
cf9a1301
RH		 4285{
4286 cons (sparc_arch_size == 32 ? 4 : 8);
4287}
4288
6d8809aa
RH		 4289#ifdef OBJ_ELF
4290/* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4291 global register.
4292 The syntax is:
e0c6ed95 4293
6d8809aa 4294 .register %g[2367],{#scratch|symbolname|#ignore}
e0c6ed95 4295*/
6d8809aa
RH		 4296
4297static void
5a49b8ac 4298s_register (int ignore ATTRIBUTE_UNUSED)
6d8809aa
RH		 4299{
4300 char c;
4301 int reg;
4302 int flags;
4303 const char *regname;
4304
4305 if (input_line_pointer[0] != '%'
4306 || input_line_pointer[1] != 'g'
4307 || ((input_line_pointer[2] & ~1) != '2'
4308 && (input_line_pointer[2] & ~1) != '6')
4309 || input_line_pointer[3] != ',')
4310 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4311 reg = input_line_pointer[2] - '0';
4312 input_line_pointer += 4;
4313
4314 if (*input_line_pointer == '#')
4315 {
4316 ++input_line_pointer;
4317 regname = input_line_pointer;
4318 c = get_symbol_end ();
4319 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4320 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
ab3e48dc 4321 if (regname[0] == 'i')
6d8809aa
RH		 4322 regname = NULL;
4323 else
4324 regname = "";
4325 }
4326 else
4327 {
4328 regname = input_line_pointer;
4329 c = get_symbol_end ();
4330 }
4331 if (sparc_arch_size == 64)
4332 {
e0c6ed95 4333 if (globals[reg])
6d8809aa 4334 {
e0c6ed95
AM		 4335 if ((regname && globals[reg] != (symbolS *) 1
4336 && strcmp (S_GET_NAME (globals[reg]), regname))
4337 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
6d8809aa
RH		 4338 as_bad (_("redefinition of global register"));
4339 }
4340 else
4341 {
4342 if (regname == NULL)
e0c6ed95 4343 globals[reg] = (symbolS *) 1;
6d8809aa
RH		 4344 else
4345 {
4346 if (*regname)
4347 {
4348 if (symbol_find (regname))
4349 as_bad (_("Register symbol %s already defined."),
4350 regname);
4351 }
e0c6ed95
AM		 4352 globals[reg] = symbol_make (regname);
4353 flags = symbol_get_bfdsym (globals[reg])->flags;
6d8809aa
RH		 4354 if (! *regname)
4355 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4356 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4357 flags |= BSF_GLOBAL;
e0c6ed95
AM		 4358 symbol_get_bfdsym (globals[reg])->flags = flags;
4359 S_SET_VALUE (globals[reg], (valueT) reg);
4360 S_SET_ALIGN (globals[reg], reg);
4361 S_SET_SIZE (globals[reg], 0);
6d8809aa
RH		 4362 /* Although we actually want undefined_section here,
4363 we have to use absolute_section, because otherwise
4364 generic as code will make it a COM section.
4365 We fix this up in sparc_adjust_symtab. */
e0c6ed95
AM		 4366 S_SET_SEGMENT (globals[reg], absolute_section);
4367 S_SET_OTHER (globals[reg], 0);
4368 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4369 ->internal_elf_sym.st_info =
4370 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
e0c6ed95 4371 elf_symbol (symbol_get_bfdsym (globals[reg]))
6d8809aa
RH		 4372 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4373 }
4374 }
4375 }
4376
4377 *input_line_pointer = c;
4378
4379 demand_empty_rest_of_line ();
4380}
4381
4382/* Adjust the symbol table. We set undefined sections for STT_REGISTER
4383 symbols which need it. */
e0c6ed95 4384
6d8809aa 4385void
5a49b8ac 4386sparc_adjust_symtab (void)
6d8809aa
RH		 4387{
4388 symbolS *sym;
e0c6ed95 4389
6d8809aa
RH		 4390 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4391 {
4392 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4393 ->internal_elf_sym.st_info) != STT_REGISTER)
4394 continue;
4395
4396 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4397 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4398 continue;
4399
4400 S_SET_SEGMENT (sym, undefined_section);
4401 }
4402}
4403#endif
4404
252b5132
RH		 4405/* If the --enforce-aligned-data option is used, we require .word,
4406 et. al., to be aligned correctly. We do it by setting up an
4407 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4408 no unexpected alignment was introduced.
4409
4410 The SunOS and Solaris native assemblers enforce aligned data by
4411 default. We don't want to do that, because gcc can deliberately
4412 generate misaligned data if the packed attribute is used. Instead,
4413 we permit misaligned data by default, and permit the user to set an
4414 option to check for it. */
4415
4416void
5a49b8ac 4417sparc_cons_align (int nbytes)
252b5132
RH		 4418{
4419 int nalign;
252b5132
RH		 4420
4421 /* Only do this if we are enforcing aligned data. */
4422 if (! enforce_aligned_data)
4423 return;
4424
0f2712ed 4425 /* Don't align if this is an unaligned pseudo-op. */
252b5132 4426 if (sparc_no_align_cons)
0f2712ed 4427 return;
252b5132 4428
f17c130b 4429 nalign = mylog2 (nbytes);
252b5132
RH		 4430 if (nalign == 0)
4431 return;
4432
9c2799c2 4433 gas_assert (nalign > 0);
252b5132
RH		 4434
4435 if (now_seg == absolute_section)
4436 {
4437 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4438 as_bad (_("misaligned data"));
4439 return;
4440 }
4441
87975d2a
AM		 4442 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4443 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
252b5132
RH		 4444
4445 record_alignment (now_seg, nalign);
4446}
4447
0a9ef439 4448/* This is called from HANDLE_ALIGN in tc-sparc.h. */
252b5132
RH		 4449
4450void
5a49b8ac 4451sparc_handle_align (fragS *fragp)
252b5132 4452{
0a9ef439
RH		 4453 int count, fix;
4454 char *p;
4455
4456 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
bfb32b52 4457
0a9ef439 4458 switch (fragp->fr_type)
252b5132 4459 {
0a9ef439
RH		 4460 case rs_align_test:
4461 if (count != 0)
4462 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4463 break;
e0c6ed95 4464
0a9ef439
RH		 4465 case rs_align_code:
4466 p = fragp->fr_literal + fragp->fr_fix;
4467 fix = 0;
e0c6ed95 4468
0a9ef439
RH		 4469 if (count & 3)
4470 {
4471 fix = count & 3;
4472 memset (p, 0, fix);
4473 p += fix;
4474 count -= fix;
4475 }
e0c6ed95 4476
0a9ef439
RH		 4477 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4478 {
4479 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4480 if (INSN_BIG_ENDIAN)
4481 number_to_chars_bigendian (p, wval, 4);
4482 else
4483 number_to_chars_littleendian (p, wval, 4);
4484 p += 4;
4485 count -= 4;
4486 fix += 4;
e0c6ed95 4487 }
0a9ef439
RH		 4488
4489 if (INSN_BIG_ENDIAN)
4490 number_to_chars_bigendian (p, 0x01000000, 4);
4491 else
4492 number_to_chars_littleendian (p, 0x01000000, 4);
4493
4494 fragp->fr_fix += fix;
4495 fragp->fr_var = 4;
4496 break;
4497
4498 default:
4499 break;
252b5132
RH		 4500 }
4501}
4502
4503#ifdef OBJ_ELF
4504/* Some special processing for a Sparc ELF file. */
4505
4506void
5a49b8ac 4507sparc_elf_final_processing (void)
252b5132
RH		 4508{
4509 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4510 sort of BFD interface for this. */
4511 if (sparc_arch_size == 64)
4512 {
4513 switch (sparc_memory_model)
4514 {
4515 case MM_RMO:
4516 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4517 break;
4518 case MM_PSO:
4519 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4520 break;
4521 default:
4522 break;
4523 }
4524 }
4525 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4526 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4527 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4528 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
19f7b010
JJ		 4529 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4530 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
252b5132 4531}
bd5e6e7e
JJ		 4532
4533void
5a49b8ac 4534sparc_cons (expressionS *exp, int size)
bd5e6e7e
JJ		 4535{
4536 char *save;
4537
4538 SKIP_WHITESPACE ();
4539 sparc_cons_special_reloc = NULL;
4540 save = input_line_pointer;
4541 if (input_line_pointer[0] == '%'
4542 && input_line_pointer[1] == 'r'
4543 && input_line_pointer[2] == '_')
4544 {
4545 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4546 {
4547 input_line_pointer += 7;
4548 sparc_cons_special_reloc = "disp";
4549 }
4550 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4551 {
4552 if (size != 4 && size != 8)
4553 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4554 else
4555 {
4556 input_line_pointer += 6;
4557 sparc_cons_special_reloc = "plt";
4558 }
4559 }
b9734f35
JJ		 4560 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4561 {
4562 if (size != 4 && size != 8)
4563 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4564 else
4565 {
4566 input_line_pointer += 13;
4567 sparc_cons_special_reloc = "tls_dtpoff";
4568 }
4569 }
bd5e6e7e
JJ		 4570 if (sparc_cons_special_reloc)
4571 {
4572 int bad = 0;
4573
4574 switch (size)
4575 {
4576 case 1:
4577 if (*input_line_pointer != '8')
4578 bad = 1;
4579 input_line_pointer--;
4580 break;
4581 case 2:
4582 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4583 bad = 1;
4584 break;
4585 case 4:
4586 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4587 bad = 1;
4588 break;
4589 case 8:
4590 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4591 bad = 1;
4592 break;
4593 default:
4594 bad = 1;
4595 break;
4596 }
4597
4598 if (bad)
4599 {
4600 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4601 sparc_cons_special_reloc, size * 8, size);
4602 }
4603 else
4604 {
4605 input_line_pointer += 2;
4606 if (*input_line_pointer != '(')
4607 {
4608 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4609 sparc_cons_special_reloc, size * 8);
4610 bad = 1;
4611 }
4612 }
4613
4614 if (bad)
4615 {
4616 input_line_pointer = save;
4617 sparc_cons_special_reloc = NULL;
4618 }
4619 else
4620 {
4621 int c;
4622 char *end = ++input_line_pointer;
4623 int npar = 0;
4624
4625 while (! is_end_of_line[(c = *end)])
4626 {
4627 if (c == '(')
4628 npar++;
4629 else if (c == ')')
4630 {
4631 if (!npar)
4632 break;
4633 npar--;
4634 }
4635 end++;
4636 }
4637
4638 if (c != ')')
4639 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4640 sparc_cons_special_reloc, size * 8);
4641 else
4642 {
4643 *end = '\0';
4644 expression (exp);
4645 *end = c;
4646 if (input_line_pointer != end)
4647 {
4648 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4649 sparc_cons_special_reloc, size * 8);
4650 }
4651 else
4652 {
4653 input_line_pointer++;
4654 SKIP_WHITESPACE ();
4655 c = *input_line_pointer;
4656 if (! is_end_of_line[c] && c != ',')
4657 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4658 sparc_cons_special_reloc, size * 8);
4659 }
4660 }
4661 }
4662 }
4663 }
4664 if (sparc_cons_special_reloc == NULL)
4665 expression (exp);
4666}
4667
252b5132
RH		 4668#endif
4669
4670/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4671 reloc for a cons. We could use the definition there, except that
4672 we want to handle little endian relocs specially. */
4673
4674void
5a49b8ac
AM		 4675cons_fix_new_sparc (fragS *frag,
4676 int where,
4677 unsigned int nbytes,
4678 expressionS *exp)
252b5132
RH		 4679{
4680 bfd_reloc_code_real_type r;
4681
4682 r = (nbytes == 1 ? BFD_RELOC_8 :
4683 (nbytes == 2 ? BFD_RELOC_16 :
4684 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4685
0f2712ed
NC		 4686 if (target_little_endian_data
4687 && nbytes == 4
e0c6ed95 4688 && now_seg->flags & SEC_ALLOC)
252b5132 4689 r = BFD_RELOC_SPARC_REV32;
0f2712ed 4690
bd5e6e7e
JJ		 4691 if (sparc_cons_special_reloc)
4692 {
4693 if (*sparc_cons_special_reloc == 'd')
4694 switch (nbytes)
4695 {
4696 case 1: r = BFD_RELOC_8_PCREL; break;
4697 case 2: r = BFD_RELOC_16_PCREL; break;
4698 case 4: r = BFD_RELOC_32_PCREL; break;
4699 case 8: r = BFD_RELOC_64_PCREL; break;
4700 default: abort ();
4701 }
b9734f35 4702 else if (*sparc_cons_special_reloc == 'p')
bd5e6e7e
JJ		 4703 switch (nbytes)
4704 {
4705 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4706 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4707 }
b9734f35
JJ		 4708 else
4709 switch (nbytes)
4710 {
4711 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4712 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4713 }
bd5e6e7e
JJ		 4714 }
4715 else if (sparc_no_align_cons)
0f2712ed
NC		 4716 {
4717 switch (nbytes)
4718 {
4719 case 2: r = BFD_RELOC_SPARC_UA16; break;
4720 case 4: r = BFD_RELOC_SPARC_UA32; break;
4721 case 8: r = BFD_RELOC_SPARC_UA64; break;
4722 default: abort ();
4723 }
4ffadb11 4724 }
0f2712ed 4725
252b5132 4726 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
364b6d8b
JJ		 4727 sparc_cons_special_reloc = NULL;
4728}
4729
4730void
5a49b8ac 4731sparc_cfi_frame_initial_instructions (void)
364b6d8b
JJ		 4732{
4733 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4734}
4735
4736int
1df69f4f 4737sparc_regname_to_dw2regnum (char *regname)
364b6d8b
JJ		 4738{
4739 char *p, *q;
4740
4741 if (!regname[0])
4742 return -1;
4743
4744 q = "goli";
4745 p = strchr (q, regname[0]);
4746 if (p)
4747 {
4748 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4749 return -1;
4750 return (p - q) * 8 + regname[1] - '0';
4751 }
4752 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4753 return 14;
4754 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4755 return 30;
4756 if (regname[0] == 'f' || regname[0] == 'r')
4757 {
4758 unsigned int regnum;
4759
4760 regnum = strtoul (regname + 1, &q, 10);
4761 if (p == q || *q)
4762 return -1;
4763 if (regnum >= ((regname[0] == 'f'
4764 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4765 ? 64 : 32))
4766 return -1;
4767 if (regname[0] == 'f')
4768 {
4769 regnum += 32;
4770 if (regnum >= 64 && (regnum & 1))
4771 return -1;
4772 }
4773 return regnum;
4774 }
4775 return -1;
4776}
4777
4778void
4779sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4780{
4781 sparc_cons_special_reloc = "disp";
4782 sparc_no_align_cons = 1;
4783 emit_expr (exp, nbytes);
4784 sparc_no_align_cons = 0;
4785 sparc_cons_special_reloc = NULL;
252b5132 4786}
Empty description
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