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* cgen-mem.h (DECLARE_SETT): Fix return type.
[binutils.git] / sim / erc32 / erc32.c
CommitLineData
b7b31114
SG		 1/*
2 * This file is part of SIS.
3 *
4 * SIS, SPARC instruction simulator V1.8 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 675
19 * Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23/* The control space devices */
24
25#include <sys/types.h>
26#include <stdio.h>
27#include <sys/ioctl.h>
28#include <sys/fcntl.h>
29#include <sys/file.h>
30#include "sis.h"
31#include "end.h"
32
33extern int32 sis_verbose;
34extern int mecrev0;
35extern char uart_dev1[], uart_dev2[];
36
37#define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
38#define MOK 0
39
40/* MEC register addresses */
41
42#define MEC_UARTA 0x0E0
43#define MEC_UARTB 0x0E4
44#define MEC_UART_CTRL 0x0E8
45#define MEC_TIMER_CTRL 0x098
46#define MEC_RTC_COUNTER 0x080
47#define MEC_RTC_RELOAD 0x080
48#define MEC_RTC_SCALER 0x084
49#define MEC_GPT_COUNTER 0x088
50#define MEC_GPT_RELOAD 0x088
51#define MEC_GPT_SCALER 0x08C
52#define MEC_DBG 0x0C0
53#define MEC_BRK 0x0C4
54#define MEC_WPR 0x0C8
55#define MEC_SFSR 0x0A0
56#define MEC_FFAR 0x0A4
57#define MEC_IPR 0x048
58#define MEC_IMR 0x04C
59#define MEC_ICR 0x050
60#define MEC_IFR 0x054
61#define MEC_MCR 0x000
62#define MEC_MEMCFG 0x010
63#define MEC_WCR 0x018
64#define MEC_MAR0 0x020
65#define MEC_MAR1 0x024
66#define MEC_SFR 0x004
67#define MEC_WDOG 0x060
68#define MEC_TRAPD 0x064
69#define MEC_PWDR 0x008
70#define SIM_LOAD 0x0F0
71
72/* Memory exception causes */
73#define PROT_EXC 0x3
74#define UIMP_ACC 0x4
75#define MEC_ACC 0x6
76#define WATCH_EXC 0xa
77#define BREAK_EXC 0xb
78
79/* Size of UART buffers (bytes) */
80#define UARTBUF 1024
81
82/* Number of simulator ticks between flushing the UARTS. */
83/* For good performance, keep above 1000 */
84#define UART_FLUSH_TIME 3000
85
86/* MEC timer control register bits */
87#define TCR_GACR 1
88#define TCR_GACL 2
89#define TCR_GASE 4
90#define TCR_GASL 8
91#define TCR_TCRCR 0x100
92#define TCR_TCRCL 0x200
93#define TCR_TCRSE 0x400
94#define TCR_TCRSL 0x800
95
96/* New uart defines */
97#define UART_TX_TIME 1000
98#define UART_RX_TIME 1000
99#define UARTA_DR 0x1
100#define UARTA_SRE 0x2
101#define UARTA_HRE 0x4
102#define UARTA_OR 0x40
103#define UARTA_CLR 0x80
104#define UARTB_DR 0x10000
105#define UARTB_SRE 0x20000
106#define UARTB_HRE 0x40000
107#define UARTB_OR 0x400000
108#define UARTB_CLR 0x800000
109
110#define UART_DR 0x100
111#define UART_TSE 0x200
112#define UART_THE 0x400
113
114/* MEC registers */
115
116static char fname[256];
117static uint32 find = 0;
118static char simfn[] = "simload";
119static uint32 brk_point = 0;
120static uint32 watch_point = 0;
121static uint32 mec_dbg = 0;
122static uint32 mec_sfsr = 0x078;
123static uint32 mec_ffar = 0;
124static uint32 mec_ipr = 0;
125static uint32 mec_imr = 0x3fff;
126static uint32 mec_icr = 0;
127static uint32 mec_ifr = 0;
128static uint32 mec_mcr; /* MEC control register */
129static uint32 mec_memcfg; /* Memory control register */
130static uint32 mec_wcr; /* MEC waitstate register */
131static uint32 mec_mar0; /* MEC access registers (2) */
132static uint32 mec_mar1; /* MEC access registers (2) */
133static uint32 mec_regs[64];
134static uint32 posted_irq;
135static uint32 mec_ersr = 0; /* MEC error and status register */
136static uint32 mec_emr = 0x60; /* MEC error mask register */
137static uint32 mec_tcr = 0; /* MEC test comtrol register */
138
139static uint32 rtc_counter = 0xffffffff;
140static uint32 rtc_reload = 0xffffffff;
141static uint32 rtc_scaler = 0xff;
142static uint32 rtc_enabled = 0;
143static uint32 rtc_cr = 0;
144static uint32 rtc_se = 0;
145static uint32 rtc_cont = 0;
146
147static uint32 gpt_counter = 0xffffffff;
148static uint32 gpt_reload = 0xffffffff;
149static uint32 gpt_scaler = 0xffff;
150static uint32 gpt_enabled = 0;
151static uint32 gpt_cr = 0;
152static uint32 gpt_se = 0;
153static uint32 gpt_cont = 0;
154
155static uint32 wdog_scaler;
156static uint32 wdog_counter;
157static uint32 wdog_rst_delay;
158static uint32 wdog_rston;
159
160#ifdef MECREV0
161static uint32 gpt_irqon = 1;
162static uint32 rtc_irqon = 1;
163#endif
164
165enum wdog_type {
166 init, disabled, enabled, stopped
167};
168
169static enum wdog_type wdog_status;
170
171/* Memory support variables */
172
173static uint32 mem_ramr_ws; /* RAM read waitstates */
174static uint32 mem_ramw_ws; /* RAM write waitstates */
175static uint32 mem_romr_ws; /* ROM read waitstates */
176static uint32 mem_romw_ws; /* ROM write waitstates */
177static uint32 mem_ramsz; /* RAM size */
178static uint32 mem_romsz; /* RAM size */
179static uint32 mem_banksz; /* RAM bank size */
180static uint32 mem_accprot; /* RAM write protection enabled */
181
182/* UART support variables */
183
184static unsigned char Adata, Bdata;
185static int32 fd1, fd2; /* file descriptor for input file */
186static int32 Ucontrol; /* UART status register */
187static unsigned char aq[UARTBUF], bq[UARTBUF];
188static int32 res;
189static int32 anum, aind = 0;
190static int32 bnum, bind = 0;
191static char wbufa[UARTBUF], wbufb[UARTBUF];
192static unsigned wnuma;
193static unsigned wnumb;
194static FILE *f1 = NULL, *f2 = NULL;
195
196static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
197static uint32 uart_stat_reg;
198static uint32 uarta_data, uartb_data;
199
200void uarta_tx();
201void uartb_tx();
202uint32 read_uart();
203void write_uart();
204uint32 rtc_counter_read();
205void rtc_scaler_set();
206void rtc_reload_set();
207uint32 gpt_counter_read();
208void gpt_scaler_set();
209void gpt_reload_set();
210void timer_ctrl();
211void port_init();
212void uart_irq_start();
213void mec_reset();
214void wdog_start();
215
216
217/* One-time init */
218
219void
220init_sim()
221{
222 port_init();
223}
224
225/* Power-on reset init */
226
227void
228reset()
229{
230 mec_reset();
231 uart_irq_start();
232 wdog_start();
233}
234
235/* IU error mode manager */
236
237int
238error_mode(pc)
239 uint32 pc;
240{
241
242 if ((mec_emr & 0x1) == 0) {
243 if (mec_mcr & 0x20) {
244 sys_reset();
245 mec_ersr = 0x8000;
246 printf("Error manager reset - IU in error mode at 0x%08x\n", pc);
247 }
248 }
249}
250
251/* Check memory settings */
252
253void
254decode_memcfg()
255{
256 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
257 mem_banksz = ((mec_memcfg >> 10) & 7) + 18 - 6;
258 mem_romsz = (4 * 1024) << ((mec_memcfg >> 18) & 7);
259 if (sis_verbose)
260 printf("RAM size: %d K, ROM size: %d K, protection bank size: %d K\n",
261 mem_ramsz >> 10, mem_romsz >> 10, 1 << mem_banksz);
262}
263
264void
265decode_wcr()
266{
267 mem_ramr_ws = mec_wcr & 3;
268 mem_ramw_ws = (mec_wcr >> 2) & 3;
269 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
270 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
271 if (sis_verbose)
272 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
273 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
274}
275
276void
277decode_mcr()
278{
279 mem_accprot = (mec_mcr >> 3) & 1;
280 if (sis_verbose && mem_accprot)
281 printf("Memory access protection enabled\n");
282 if (sis_verbose && (mec_mcr & 2))
283 printf("Software reset enabled\n");
284 if (sis_verbose && (mec_mcr & 1))
285 printf("Power-down mode enabled\n");
286}
287
288/* Flush ports when simulator stops */
289
290void
291sim_stop()
292{
293#ifdef FAST_UART
294 flush_uart();
295#endif
296}
297
298void
299close_port()
300{
301 if (f1)
302 fclose(f1);
303 if (f2)
304 fclose(f2);
305}
306
307void
308exit_sim()
309{
310 close_port();
311}
312
313void
314mec_reset()
315{
316
317 find = 0;
318 brk_point = 0;
319 watch_point = 0;
320 mec_dbg = 0;
321 mec_sfsr = 0x078;
322 mec_ffar = 0;
323 mec_ipr = 0;
324 mec_imr = 0x3fff;
325 mec_icr = 0;
326 mec_ifr = 0;
327 mec_memcfg = 0x10000;
328 mec_mcr = 0x01b50014;
329 mec_wcr = -1;
330 mec_mar0 = -1;
331 mec_mar1 = -1;
332 mec_ersr = 0; /* MEC error and status register */
333 mec_emr = 0x60; /* MEC error mask register */
334 mec_tcr = 0; /* MEC test comtrol register */
335
336 decode_memcfg();
337 decode_wcr();
338 decode_mcr();
339
340 posted_irq = 0;
341 wnuma = wnumb = 0;
342 anum = aind = bnum = bind = 0;
343
344 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
345 uarta_data = uartb_data = UART_THE | UART_TSE;
346
347 rtc_counter = 0xffffffff;
348 rtc_reload = 0xffffffff;
349 rtc_scaler = 0xff;
350 rtc_enabled = 0;
351 rtc_cr = 0;
352 rtc_se = 0;
353 rtc_cont = 0;
354
355 gpt_counter = 0xffffffff;
356 gpt_reload = 0xffffffff;
357 gpt_scaler = 0xffff;
358 gpt_enabled = 0;
359 gpt_cr = 0;
360 gpt_se = 0;
361 gpt_cont = 0;
362
363 wdog_scaler = 255;
364 wdog_rst_delay = 255;
365 wdog_counter = 0xffff;
366 wdog_rston = 0;
367 wdog_status = init;
368
369#ifdef MECREV0
370 gpt_irqon = 1;
371 rtc_irqon = 1;
372#endif
373
374}
375
376
377
378int32
379mec_intack(level)
380 int32 level;
381{
382 int irq_test;
383
384 if (sis_verbose)
385 printf("interrupt %d acknowledged\n",level);
386 irq_test = mec_tcr & 0x80000;
387 if ((irq_test) && (mec_ifr & (1 << level)))
388 mec_ifr &= ~(1 << level);
389 else
390 mec_ipr &= ~(1 << level);
391 posted_irq &= ~(1 << level);
392#ifdef MECREV0
393 if (mecrev0) {
394 if (uart_stat_reg & 1)
395 mec_ipr |= (1 << 4);
396 if (uart_stat_reg & 0x100)
397 mec_ipr |= (1 << 5);
398 }
399#endif
400}
401
402int32
403chk_irq()
404{
405 int32 i;
406 uint32 itmp;
407
408 itmp = ((mec_ipr | mec_ifr) & ~mec_imr) & 0x0fffe;
409 if (itmp != 0) {
410 for (i = 15; i > 0; i--) {
411 if (((itmp >> i) & 1) != 0) {
412 if ((posted_irq & (1 << i)) == 0) {
413 if (sis_verbose)
414 printf("interrupt %d generated\n",i);
415 set_int(i, mec_intack, i);
416 posted_irq |= (1 << i);
417 }
418 }
419 }
420 }
421}
422
423void
424mec_irq(level)
425 int32 level;
426{
427 mec_ipr |= (1 << level);
428 chk_irq();
429}
430
431void
432set_sfsr(fault, addr, asi, read)
433 uint32 fault;
434 uint32 addr;
435 uint32 asi;
436 uint32 read;
437{
438 mec_ffar = addr;
439 mec_sfsr = (fault << 3) | (!read << 15);
440 switch (asi) {
441 case 8:
442 mec_sfsr |= 0x2002;
443 break;
444 case 9:
445 mec_sfsr |= 0x3002;
446 break;
447 case 0xa:
448 mec_sfsr |= 0x0004;
449 break;
450 case 0xb:
451 mec_sfsr |= 0x1004;
452 break;
453 }
454}
455
456int32
457chk_brk(addr, asi)
458 uint32 addr;
459{
460 if ((mec_dbg & 0x80000) && (addr == brk_point) &&
461 ((asi == 9) || (asi == 8))) {
462 mec_dbg |= 0x00800000;
463 if (mec_dbg & 0x00200000) {
464 set_sfsr(BREAK_EXC, addr, asi, 1);
465 return (1);
466 }
467 }
468 return (0);
469}
470
471int32
472chk_watch(addr, read, asi)
473 uint32 addr;
474 uint32 read;
475{
476 uint32 hit;
477
478 if ((mec_dbg & 0x40000) && (asi != 9) && (asi != 8) &&
479 (((mec_dbg & 0x10000) && (read == 0)) || ((mec_dbg & 0x20000) && read))) {
480 if (((addr ^ watch_point) &
481 (0xffff0000 | (mec_dbg & 0x0ffff))) == 0) {
482 mec_dbg |= 0x00400000;
483 if (mec_dbg & 0x100000) {
484 set_sfsr(WATCH_EXC, addr, asi, read);
485 return (1);
486 }
487 }
488 }
489 return (0);
490}
491
492int32
493mec_read(addr, asi, data)
494 uint32 addr;
495 uint32 asi;
496 uint32 *data;
497{
498
499 switch (addr & 0x0ff) {
500
501 case MEC_SFR:
502 case MEC_WDOG:
503 return (1);
504 break;
505 case MEC_DBG:
506 *data = mec_dbg;
507 break;
508 case MEC_UARTA:
509 case MEC_UARTB:
510 if (asi != 0xb)
511 return (1);
512 *data = read_uart(addr);
513 break;
514
515 case MEC_UART_CTRL:
516
517 *data = read_uart(addr);
518 break;
519
520 case MEC_RTC_COUNTER:
521 *data = rtc_counter_read();
522 break;
523
524 case MEC_GPT_COUNTER:
525 *data = gpt_counter_read();
526 break;
527
528 case MEC_SFSR:
529 *data = mec_sfsr;
530 break;
531
532 case MEC_FFAR:
533 *data = mec_ffar;
534 break;
535
536 case MEC_IPR:
537 *data = mec_ipr;
538 break;
539
540 case MEC_IMR:
541 *data = mec_imr;
542 break;
543
544 case MEC_IFR:
545 *data = mec_ifr;
546 break;
547
548 case SIM_LOAD:
549 fname[find] = 0;
550 if (find == 0)
551 strcpy(fname, "simload");
552 *data = bfd_load(fname);
553 find = 0;
554 break;
555
556 case MEC_MCR:
557 *data = mec_mcr;
558 break;
559
560 case MEC_MEMCFG:
561 *data = mec_memcfg;
562 break;
563
564 case MEC_WCR:
565 *data = mec_wcr;
566 break;
567
568 case MEC_MAR0:
569 *data = mec_mar0;
570 break;
571
572 case MEC_MAR1:
573 *data = mec_mar1;
574 break;
575
576 case MEC_PWDR:
577 return (1);
578 break;
579
580 default:
581 if (sis_verbose)
582 printf("Warning, read from unimplemented MEC register %x\n\r", addr);
583 *data = mec_regs[((addr & 0x0ff) >> 2)];
584 break;
585 }
586 return (MOK);
587}
588
589int
590mec_write(addr, data)
591 uint32 addr;
592 uint32 data;
593{
594
595 switch (addr & 0x0ff) {
596
597 case MEC_SFR:
598 if (mec_mcr & 0x2) {
599 sys_reset();
600 mec_ersr = 0x4000;
601 printf(" Software reset issued\n");
602 }
603 break;
604
605 case MEC_BRK:
606 brk_point = data;
607 break;
608
609 case MEC_DBG:
610 mec_dbg = data;
611 break;
612
613 case MEC_WPR:
614 watch_point = data;
615 break;
616
617 case MEC_UARTA:
618 case MEC_UARTB:
619 case MEC_UART_CTRL:
620 write_uart(addr, data);
621 break;
622
623 case MEC_GPT_RELOAD:
624 gpt_reload_set(data);
625 break;
626
627 case MEC_GPT_SCALER:
628 gpt_scaler_set(data);
629 break;
630
631 case MEC_TIMER_CTRL:
632 timer_ctrl(data);
633 break;
634
635 case MEC_RTC_RELOAD:
636 rtc_reload_set(data);
637 break;
638
639 case MEC_RTC_SCALER:
640 rtc_scaler_set(data);
641 break;
642
643 case MEC_SFSR:
644 mec_sfsr = 0;
645 break;
646
647 case MEC_IMR:
648 mec_imr = data & 0x7ffe;
649 chk_irq();
650 break;
651
652 case MEC_ICR:
653 mec_icr &= ~data & 0x0fffe;
654 break;
655
656 case MEC_IFR:
657 mec_ifr = data & 0xfffe;
658 chk_irq();
659 break;
660 case SIM_LOAD:
661 fname[find++] = (char) data;
662 break;
663
664 case MEC_MCR:
665 mec_mcr = data;
666 decode_mcr();
667 break;
668
669 case MEC_MEMCFG:
670 mec_memcfg = data & ~0xC0e08000;
671 decode_memcfg();
672 break;
673
674 case MEC_WCR:
675 mec_wcr = data;
676 decode_wcr();
677 break;
678
679 case MEC_MAR0:
680 mec_mar0 = data;
681 break;
682
683 case MEC_MAR1:
684 mec_mar1 = data;
685 break;
686
687 case MEC_WDOG:
688 wdog_scaler = (data >> 16) & 0x0ff;
689 wdog_counter = data & 0x0ffff;
690 wdog_rst_delay = data >> 24;
691 wdog_rston = 0;
692 if (wdog_status == stopped)
693 wdog_start();
694 wdog_status = enabled;
695 break;
696
697 case MEC_TRAPD:
698 if (wdog_status == init) {
699 wdog_status = disabled;
700 if (sis_verbose)
701 printf("Watchdog disabled\n");
702 }
703 break;
704
705 case MEC_PWDR:
706 if (mec_mcr & 1)
707 wait_for_irq();
708 break;
709
710 default:
711 if (sis_verbose)
712 printf("Warning, write to unimplemented MEC register %x\n\r",
713 addr);
714 mec_regs[((addr & 0x0ffc) >> 2)] = data;
715 break;
716 }
717 return (MOK);
718}
719
720
721/* MEC UARTS */
722
723
724void
725port_init()
726{
727
728 int32 pty_remote = 1;
729
730
731
732 if ((fd1 = open(uart_dev1, O_RDWR | O_NDELAY | O_NONBLOCK)) < 0) {
733 printf("Warning, couldn't open output device %s\n", uart_dev1);
734 } else {
735 printf("serial port A on %s\n", uart_dev1);
736 f1 = fdopen(fd1, "r+");
737 setbuf(f1, NULL);
738 }
739 if ((fd2 = open(uart_dev2, O_RDWR | O_NDELAY | O_NONBLOCK)) < 0) {
740 printf("Warning, couldn't open output device %s\n", uart_dev2);
741 } else {
742 printf("serial port B on %s\n", uart_dev2);
743 f2 = fdopen(fd2, "r+");
744 setbuf(f2, NULL);
745 }
746
747 wnuma = wnumb = 0;
748}
749
750uint32
751read_uart(addr)
752 uint32 addr;
753{
754
755 unsigned tmp;
756
757 switch (addr & 0xff) {
758
759 case 0xE0: /* UART 1 */
760#ifdef FAST_UART
761 if (aind < anum) {
762 if ((aind + 1) < anum)
763 mec_irq(4);
764 return (0x700 | (uint32) aq[aind++]);
765 } else {
766 if (f1)
767 anum = fread(aq, 1, UARTBUF, f1);
768 else
769 anum = 0;
770 if (anum > 0) {
771 aind = 0;
772 if ((aind + 1) < anum)
773 mec_irq(4);
774 return (0x700 | (uint32) aq[aind++]);
775 } else {
776 return (0x600 | (uint32) aq[aind]);
777 }
778
779 }
780#else
781 tmp = uarta_data;
782 uarta_data &= ~UART_DR;
783 uart_stat_reg &= ~UARTA_DR;
784 return tmp;
785#endif
786 break;
787
788 case 0xE4: /* UART 2 */
789#ifdef FAST_UART
790 if (bind < bnum) {
791 if ((bind + 1) < bnum)
792 mec_irq(5);
793 return (0x700 | (uint32) bq[bind++]);
794 } else {
795 if (f2)
796 bnum = fread(bq, 1, UARTBUF, f2);
797 else
798 bnum = 0;
799 if (bnum > 0) {
800 bind = 0;
801 if ((bind + 1) < bnum)
802 mec_irq(5);
803 return (0x700 | (uint32) bq[bind++]);
804 } else {
805 return (0x600 | (uint32) bq[bind]);
806 }
807
808 }
809#else
810 tmp = uartb_data;
811 uartb_data &= ~UART_DR;
812 uart_stat_reg &= ~UARTB_DR;
813 return tmp;
814#endif
815 break;
816
817 case 0xE8: /* UART status register */
818#ifdef FAST_UART
819 Ucontrol = 0;
820 if (aind < anum) {
821 Ucontrol |= 0x00000001;
822 } else {
823 if (f1)
824 anum = fread(aq, 1, UARTBUF, f1);
825 else
826 anum = 0;
827 if (anum > 0) {
828 Ucontrol |= 0x00000001;
829 aind = 0;
830 mec_irq(4);
831 }
832 }
833 if (bind < bnum) {
834 Ucontrol |= 0x00010000;
835 } else {
836 if (f2)
837 bnum = fread(bq, 1, UARTBUF, f2);
838 else
839 bnum = 0;
840 if (bnum > 0) {
841 Ucontrol |= 0x00010000;
842 bind = 0;
843 mec_irq(5);
844 }
845 }
846
847 Ucontrol |= 0x00060006;
848 return (Ucontrol);
849#else
850 return (uart_stat_reg);
851#endif
852 break;
853 default:
854 if (sis_verbose)
855 printf("Read from unimplemented MEC register (%x)\n", addr);
856
857 }
858 return (0);
859}
860
861void
862write_uart(addr, data)
863 uint32 addr;
864 uint32 data;
865{
866
867 int32 wnum = 0;
868 unsigned char c;
869
870 c = (unsigned char) data;
871 switch (addr & 0xff) {
872
873 case 0xE0: /* UART A */
874#ifdef FAST_UART
875 if (wnuma < UARTBUF)
876 wbufa[wnuma++] = c;
877 else {
878 while (wnuma)
879 if (f1)
880 wnuma -= fwrite(wbufa, 1, wnuma, f1);
881 else
882 wnuma--;
883 wbufa[wnuma++] = c;
884 }
885 mec_irq(4);
886#else
887 if (uart_stat_reg & UARTA_SRE) {
888 uarta_sreg = c;
889 uart_stat_reg &= ~UARTA_SRE;
890 event(uarta_tx, 0, UART_TX_TIME);
891 } else {
892 uarta_hreg = c;
893 uart_stat_reg &= ~UARTA_HRE;
894 }
895#endif
896 break;
897
898 case 0xE4: /* UART B */
899#ifdef FAST_UART
900 if (wnumb < UARTBUF)
901 wbufb[wnumb++] = c;
902 else {
903 while (wnumb)
904 if (f2)
905 wnumb -= fwrite(wbufb, 1, wnumb, f2);
906 else
907 wnumb--;
908 wbufb[wnumb++] = c;
909 }
910 mec_irq(5);
911#else
912 if (uart_stat_reg & UARTB_SRE) {
913 uartb_sreg = c;
914 uart_stat_reg &= ~UARTB_SRE;
915 event(uartb_tx, 0, UART_TX_TIME);
916 } else {
917 uartb_hreg = c;
918 uart_stat_reg &= ~UARTB_HRE;
919 }
920#endif
921 break;
922 case 0xE8: /* UART status register */
923#ifndef FAST_UART
924 if (data & UARTA_CLR) {
925 uart_stat_reg &= 0xFFFF0000;
926 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
927 }
928 if (data & UARTB_CLR) {
929 uart_stat_reg &= 0x0000FFFF;
930 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
931 }
932#endif
933 break;
934 default:
935 if (sis_verbose)
936 printf("Write to unimplemented MEC register (%x)\n", addr);
937
938 }
939}
940
941flush_uart()
942{
943 while (wnuma)
944 if (f1)
945 wnuma -= fwrite(wbufa, 1, wnuma, f1);
946 else
947 wnuma = 0;
948 while (wnumb)
949 if (f2)
950 wnumb -= fwrite(wbufb, 1, wnumb, f2);
951 else
952 wnumb = 0;
953}
954
955
956
957void
958uarta_tx()
959{
960
961 while ((f1 ? fwrite(&uarta_sreg, 1, 1, f1) : 1) != 1);
962 if (uart_stat_reg & UARTA_HRE) {
963 uart_stat_reg |= UARTA_SRE;
964 } else {
965 uarta_sreg = uarta_hreg;
966 uart_stat_reg |= UARTA_HRE;
967 event(uarta_tx, 0, UART_TX_TIME);
968 }
969 mec_irq(4);
970}
971
972void
973uartb_tx()
974{
975 while (fwrite(&uartb_sreg, 1, 1, f2) != 1);
976 if (uart_stat_reg & UARTB_HRE) {
977 uart_stat_reg |= UARTB_SRE;
978 } else {
979 uartb_sreg = uartb_hreg;
980 uart_stat_reg |= UARTB_HRE;
981 event(uartb_tx, 0, UART_TX_TIME);
982 }
983 mec_irq(5);
984}
985
986void
987uart_rx(arg)
988 caddr_t arg;
989{
990 int32 rsize;
991 char rxd;
992
993 rsize = fread(&rxd, 1, 1, f1);
994 if (rsize) {
995 uarta_data = UART_DR | rxd;
996 if (uart_stat_reg & UARTA_HRE)
997 uarta_data |= UART_THE;
998 if (uart_stat_reg & UARTA_SRE)
999 uarta_data |= UART_TSE;
1000 if (uart_stat_reg & UARTA_DR) {
1001 uart_stat_reg |= UARTA_OR;
1002 mec_irq(7); /* UART error interrupt */
1003 }
1004 uart_stat_reg |= UARTA_DR;
1005 mec_irq(4);
1006 }
1007 rsize = fread(&rxd, 1, 1, f2);
1008 if (rsize) {
1009 uartb_data = UART_DR | rxd;
1010 if (uart_stat_reg & UARTB_HRE)
1011 uartb_data |= UART_THE;
1012 if (uart_stat_reg & UARTB_SRE)
1013 uartb_data |= UART_TSE;
1014 if (uart_stat_reg & UARTB_DR) {
1015 uart_stat_reg |= UARTB_OR;
1016 mec_irq(7); /* UART error interrupt */
1017 }
1018 uart_stat_reg |= UARTB_DR;
1019 mec_irq(5);
1020 }
1021 event(uart_rx, 0, UART_RX_TIME);
1022}
1023
1024void
1025uart_intr(arg)
1026 caddr_t arg;
1027{
1028 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1029 flush_uart(); /* Flush UART ports */
1030 event(uart_intr, 0, UART_FLUSH_TIME);
1031}
1032
1033
1034void
1035uart_irq_start()
1036{
1037#ifdef FAST_UART
1038 event(uart_intr, 0, UART_FLUSH_TIME);
1039#else
1040 event(uart_rx, 0, UART_RX_TIME);
1041#endif
1042}
1043
1044/* Watch-dog */
1045
1046void
1047wdog_intr(arg)
1048 caddr_t arg;
1049{
1050 if (wdog_status == disabled) {
1051 wdog_status = stopped;
1052 } else {
1053
1054 if (wdog_counter) {
1055 wdog_counter--;
1056 event(wdog_intr, 0, wdog_scaler + 1);
1057 } else {
1058 if (wdog_rston) {
1059 printf("Watchdog reset!\n");
1060 sys_reset();
1061 mec_ersr = 0xC000;
1062 } else {
1063 mec_irq(15);
1064 wdog_rston = 1;
1065 wdog_counter = wdog_rst_delay;
1066 event(wdog_intr, 0, wdog_scaler + 1);
1067 }
1068 }
1069 }
1070}
1071
1072void
1073wdog_start()
1074{
1075 event(wdog_intr, 0, wdog_scaler + 1);
1076 if (sis_verbose)
1077 printf("Watchdog started, scaler = %d, counter = %d\n",
1078 wdog_scaler, wdog_counter);
1079}
1080
1081
1082/* MEC timers */
1083
1084
1085void
1086rtc_intr(arg)
1087 caddr_t arg;
1088{
1089 if (rtc_counter == 0) {
1090#ifdef MECREV0
1091 if (mecrev0) {
1092 if (rtc_cr) {
1093 rtc_counter = rtc_reload;
1094 mec_irq(13);
1095 } else {
1096 rtc_cont = 0;
1097 if (rtc_irqon) {
1098 mec_irq(13);
1099 rtc_irqon = 0;
1100 } else {
1101 if (sis_verbose)
1102 printf("RTC interrupt lost (MEC rev.0)\n");
1103 }
1104 }
1105 } else {
1106 mec_irq(13);
1107 if (rtc_cr)
1108 rtc_counter = rtc_reload;
1109 else
1110 rtc_cont = 0;
1111 }
1112
1113#else
1114
1115 mec_irq(13);
1116 if (rtc_cr)
1117 rtc_counter = rtc_reload;
1118 else
1119 rtc_cont = 0;
1120#endif
1121
1122 } else
1123 rtc_counter -= 1;
1124 if (rtc_se && rtc_cont) {
1125 event(rtc_intr, 0, rtc_scaler + 1);
1126 rtc_enabled = 1;
1127 } else {
1128 if (sis_verbose)
1129 printf("RTC stopped\n\r");
1130 rtc_enabled = 0;
1131 }
1132}
1133
1134void
1135rtc_start()
1136{
1137 if (sis_verbose)
1138 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1139 event(rtc_intr, 0, rtc_scaler + 1);
1140 rtc_enabled = 1;
1141}
1142
1143uint32
1144rtc_counter_read()
1145{
1146 return (rtc_counter);
1147}
1148
1149void
1150rtc_scaler_set(val)
1151 uint32 val;
1152{
1153 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1154}
1155
1156void
1157rtc_reload_set(val)
1158 uint32 val;
1159{
1160 rtc_reload = val;
1161}
1162
1163void
1164gpt_intr(arg)
1165 caddr_t arg;
1166{
1167 if (gpt_counter == 0) {
1168#ifdef MECREV0
1169 if (mecrev0) {
1170 if (gpt_cr) {
1171 gpt_counter = gpt_reload;
1172 mec_irq(12);
1173 } else {
1174 gpt_cont = 0;
1175 if (gpt_irqon) {
1176 mec_irq(12);
1177 gpt_irqon = 0;
1178 } else {
1179 if (sis_verbose)
1180 printf("GPT interrupt lost (MEC rev.0)\n");
1181 }
1182 }
1183 } else {
1184 mec_irq(12);
1185 if (gpt_cr)
1186 gpt_counter = gpt_reload;
1187 else
1188 gpt_cont = 0;
1189 }
1190
1191#else
1192 mec_irq(12);
1193 if (gpt_cr)
1194 gpt_counter = gpt_reload;
1195 else
1196 gpt_cont = 0;
1197#endif
1198 } else
1199 gpt_counter -= 1;
1200 if (gpt_se && gpt_cont) {
1201 event(gpt_intr, 0, gpt_scaler + 1);
1202 gpt_enabled = 1;
1203 } else {
1204 if (sis_verbose)
1205 printf("GPT stopped\n\r");
1206 gpt_enabled = 0;
1207 }
1208}
1209
1210void
1211gpt_start()
1212{
1213 if (sis_verbose)
1214 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1215 event(gpt_intr, 0, gpt_scaler + 1);
1216 gpt_enabled = 1;
1217}
1218
1219uint32
1220gpt_counter_read()
1221{
1222 return (gpt_counter);
1223}
1224
1225void
1226gpt_scaler_set(val)
1227 uint32 val;
1228{
1229 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1230}
1231
1232void
1233gpt_reload_set(val)
1234 uint32 val;
1235{
1236 gpt_reload = val;
1237}
1238
1239void
1240timer_ctrl(val)
1241 uint32 val;
1242{
1243
1244#ifdef MECREV0
1245 if ((mecrev0) && (val & 0x500))
1246 rtc_irqon = 1;
1247#endif
1248
1249 rtc_cr = ((val & TCR_TCRCR) != 0);
1250 if (val & TCR_TCRCL) {
1251 rtc_counter = rtc_reload;
1252 rtc_cont = 1;
1253 }
1254 if (val & TCR_TCRSL) {
1255 rtc_cont = 1;
1256 }
1257 rtc_se = ((val & TCR_TCRSE) != 0);
1258 if (rtc_cont && rtc_se && (rtc_enabled == 0))
1259 rtc_start();
1260
1261#ifdef MECREV0
1262 if ((mecrev0) && (val & 0x5))
1263 gpt_irqon = 1;
1264#endif
1265
1266 gpt_cr = (val & TCR_GACR);
1267 if (val & TCR_GACL) {
1268 gpt_counter = gpt_reload;
1269 gpt_cont = 1;
1270 }
1271 if (val & TCR_GACL) {
1272 gpt_cont = 1;
1273 }
1274 gpt_se = (val & TCR_GASE) >> 2;
1275 if (gpt_cont && gpt_se && (gpt_enabled == 0))
1276 gpt_start();
1277}
1278
1279
1280/* Memory emulation */
1281
1282/* ROM size 512 Kbyte */
1283#define ROM_SZ 0x080000
1284
1285/* RAM size 4 Mbyte */
1286#define RAM_START 0x02000000
1287#define RAM_END 0x02400000
1288#define RAM_MASK 0x003fffff
1289
1290/* MEC registers */
1291#define MEC_START 0x01f80000
1292#define MEC_END 0x01f80100
1293
1294/* Memory exception waitstates */
1295#define MEM_EX_WS 1
1296
1297/* ERC32 always adds one waitstate during ldd/std */
1298#define LDD_WS 1
1299#define STD_WS 1
1300
1301extern int32 sis_verbose;
1302
1303static uint32 romb[ROM_SZ / 4];
1304static uint32 ramb[(RAM_END - RAM_START) / 4];
1305
1306int
1307memory_read(asi, addr, data, ws)
1308 int32 asi;
1309 uint32 addr;
1310 uint32 *data;
1311 int32 *ws;
1312{
1313 int32 mexc;
1314 uint32 *mem;
1315
1316#ifdef MECBRK
1317
1318 if (mec_dbg & 0x80000) {
1319 if (chk_brk(addr, asi)) {
1320 *ws = MEM_EX_WS;
1321 return (1);
1322 }
1323 }
1324 if (mec_dbg & 0x40000) {
1325 if (chk_watch(addr, 1, asi)) {
1326 *ws = MEM_EX_WS;
1327 return (1);
1328 }
1329 }
1330#endif
1331
1332 if (addr < mem_romsz) {
1333 *data = romb[addr >> 2];
1334 *ws = mem_romr_ws;
1335 return (0);
1336 } else if ((addr >= RAM_START) && (addr < (RAM_START + mem_ramsz))) {
1337 *data = ramb[(addr & RAM_MASK) >> 2];
1338 *ws = mem_ramr_ws;
1339 return (0);
1340 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1341 mexc = mec_read(addr, asi, data);
1342 if (mexc) {
1343 set_sfsr(MEC_ACC, addr, asi, 1);
1344 *ws = MEM_EX_WS;
1345 } else {
1346 *ws = 0;
1347 }
1348 return (mexc);
1349 }
1350 printf("Memory exception at %x (illegal address)\n", addr);
1351 set_sfsr(UIMP_ACC, addr, asi, 1);
1352 *ws = MEM_EX_WS;
1353 return (1);
1354}
1355
1356int
1357memory_write(asi, addr, data, sz, ws)
1358 int32 asi;
1359 uint32 addr;
1360 uint32 *data;
1361 int32 sz;
1362 int32 *ws;
1363{
1364 uint32 byte_addr;
1365 uint32 byte_mask;
1366 uint32 waddr;
1367 uint32 bank;
1368 int32 mexc;
1369
1370#ifdef MECBRK
1371 if (mec_dbg & 0x40000) {
1372 if (chk_watch(addr, 0, asi)) {
1373 *ws = MEM_EX_WS;
1374 return (1);
1375 }
1376 }
1377#endif
1378
1379 if ((addr >= RAM_START) && (addr < (RAM_START + mem_ramsz))) {
1380 if (mem_accprot) {
1381 bank = (addr & RAM_MASK) >> mem_banksz;
1382 if (bank < 32
1383 ? !((1 << bank) & mec_mar0)
1384 : !((1 << (bank - 32) & mec_mar1))) {
1385 printf("Memory access protection error at %x\n", addr);
1386 set_sfsr(PROT_EXC, addr, asi, 0);
1387 *ws = MEM_EX_WS;
1388 return (1);
1389 }
1390 }
1391 *ws = mem_ramw_ws;
1392 waddr = (addr & RAM_MASK) >> 2;
1393 switch (sz) {
1394 case 0:
1395 byte_addr = addr & 3;
1396 byte_mask = 0x0ff << (24 - (8 * byte_addr));
1397 ramb[waddr] = (ramb[waddr] & ~byte_mask)
1398 | ((*data & 0x0ff) << (24 - (8 * byte_addr)));
1399 break;
1400 case 1:
1401 byte_addr = (addr & 2) >> 1;
1402 byte_mask = 0x0ffff << (16 - (16 * byte_addr));
1403 ramb[waddr] = (ramb[waddr] & ~byte_mask)
1404 | ((*data & 0x0ffff) << (16 - (16 * byte_addr)));
1405 break;
1406 case 2:
1407 ramb[waddr] = *data;
1408 break;
1409 case 3:
1410 ramb[waddr] = data[0];
1411 ramb[waddr + 1] = data[1];
1412 *ws += mem_ramw_ws + STD_WS;
1413 break;
1414 }
1415 return (0);
1416 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1417 if ((sz != 2) || (asi != 0xb)) {
1418 set_sfsr(MEC_ACC, addr, asi, 0);
1419 *ws = MEM_EX_WS;
1420 return (1);
1421 }
1422 mexc = mec_write(addr, *data);
1423 if (mexc) {
1424 set_sfsr(MEC_ACC, addr, asi, 0);
1425 *ws = MEM_EX_WS;
1426 } else {
1427 *ws = 0;
1428 }
1429 return (mexc);
1430
1431 }
1432 *ws = MEM_EX_WS;
1433 set_sfsr(UIMP_ACC, addr, asi, 0);
1434 return (1);
1435}
1436
1437unsigned char *
1438get_mem_ptr(addr, size)
1439 uint32 addr;
1440 uint32 size;
1441{
1442 char *bram, *brom;
1443
1444 brom = (char *) romb;
1445 bram = (char *) ramb;
1446 if ((addr + size) < ROM_SZ) {
1447 return (&brom[addr]);
1448 } else if ((addr >= RAM_START) && ((addr + size) < RAM_END)) {
1449 return (&bram[(addr & RAM_MASK)]);
1450 }
1451 return ((char *) -1);
1452}
1453
1454int
1455sis_memory_write(addr, data, length)
1456 uint32 addr;
1457 char *data;
1458 uint32 length;
1459{
1460 char *mem;
1461 uint32 i;
1462
1463 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1464 return (0);
1465#ifdef HOST_LITTLE_ENDIAN
1466 for (i = 0; i < length; i++) {
1467 mem[i ^ 0x3] = data[i];
1468 }
1469#else
1470 memcpy(mem, data, length);
1471#endif
1472 return (length);
1473}
1474
1475int
1476sis_memory_read(addr, data, length)
1477 uint32 addr;
1478 char *data;
1479 uint32 length;
1480{
1481 char *mem;
1482 int i;
1483
1484 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1485 return (0);
1486
1487#ifdef HOST_LITTLE_ENDIAN
1488 for (i = 0; i < length; i++) {
1489 data[i] = mem[i ^ 0x3];
1490 }
1491#else
1492 memcpy(data, mem, length);
1493#endif
1494 return (length);
1495}
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