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* m32r-asm.c: Regenerate.
[binutils.git] / opcodes / m32r-opc.c
CommitLineData
ab0bd049
DE		 1/* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
9c03036a 3
fbc8134d 4THIS FILE IS USED TO GENERATE m32r-opc.c.
7c26196f 5
ab0bd049 6Copyright (C) 1998 Free Software Foundation, Inc.
9c03036a 7
ab0bd049 8This file is part of the GNU Binutils and GDB, the GNU debugger.
9c03036a
DE		 9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2, or (at your option)
13any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
ab0bd049 20You should have received a copy of the GNU General Public License
fbc8134d
DE		 21along with this program; if not, write to the Free Software Foundation, Inc.,
2259 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
9c03036a 23
23cf992f 24#include "sysdep.h"
9c03036a
DE		 25#include <stdio.h>
26#include "ansidecl.h"
27#include "libiberty.h"
28#include "bfd.h"
ab0bd049 29#include "symcat.h"
9c03036a 30#include "m32r-opc.h"
fbc8134d 31#include "opintl.h"
9c03036a 32
c2009f4a
DE		 33/* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
35
36static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37static unsigned int asm_hash_insn PARAMS ((const char *));
38static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
39static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
40
52a53d1f
DE		 41/* Cover function to read and properly byteswap an insn value. */
42
43CGEN_INSN_INT
44cgen_get_insn_value (od, buf, length)
45 CGEN_OPCODE_DESC od;
46 unsigned char *buf;
47 int length;
48{
49 CGEN_INSN_INT value;
50
51 switch (length)
52 {
53 case 8:
54 value = *buf;
55 break;
56 case 16:
57 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
58 value = bfd_getb16 (buf);
59 else
60 value = bfd_getl16 (buf);
61 break;
62 case 32:
63 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
64 value = bfd_getb32 (buf);
65 else
66 value = bfd_getl32 (buf);
67 break;
68 default:
69 abort ();
70 }
71
72 return value;
73}
74
75/* Cover function to store an insn value properly byteswapped. */
76
77void
78cgen_put_insn_value (od, buf, length, value)
79 CGEN_OPCODE_DESC od;
80 unsigned char *buf;
81 int length;
82 CGEN_INSN_INT value;
83{
84 switch (length)
85 {
86 case 8:
87 buf[0] = value;
88 break;
89 case 16:
90 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
91 bfd_putb16 (value, buf);
92 else
93 bfd_putl16 (value, buf);
94 break;
95 case 32:
96 if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
97 bfd_putb32 (value, buf);
98 else
99 bfd_putl32 (value, buf);
100 break;
101 default:
102 abort ();
103 }
104}
105
ab0bd049 106/* Look up instruction INSN_VALUE and extract its fields.
1294c286 107 INSN, if non-null, is the insn table entry.
ab0bd049
DE		 108 Otherwise INSN_VALUE is examined to compute it.
109 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
52a53d1f 110 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
1294c286 111 If INSN != NULL, LENGTH must be valid.
390bd87d 112 ALIAS_P is non-zero if alias insns are to be included in the search.
1294c286 113
ab0bd049
DE		 114 The result a pointer to the insn table entry, or NULL if the instruction
115 wasn't recognized. */
116
117const CGEN_INSN *
c2009f4a
DE		 118m32r_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
119 CGEN_OPCODE_DESC od;
ab0bd049 120 const CGEN_INSN *insn;
52a53d1f 121 CGEN_INSN_BYTES insn_value;
ab0bd049
DE		 122 int length;
123 CGEN_FIELDS *fields;
1294c286 124 int alias_p;
ab0bd049 125{
52a53d1f
DE		 126 unsigned char buf[16];
127 unsigned char *bufp;
128 unsigned int base_insn;
129#if CGEN_INT_INSN_P
130 CGEN_EXTRACT_INFO *info = NULL;
131#else
132 CGEN_EXTRACT_INFO ex_info;
133 CGEN_EXTRACT_INFO *info = &ex_info;
134#endif
135
136#if ! CGEN_INT_INSN_P
137 ex_info.dis_info = NULL;
138 ex_info.bytes = insn_value;
139 ex_info.valid = -1;
140#endif
ab0bd049
DE		 141
142 if (!insn)
143 {
144 const CGEN_INSN_LIST *insn_list;
145
52a53d1f
DE		 146#if CGEN_INT_INSN_P
147 cgen_put_insn_value (od, buf, length, insn_value);
148 bufp = buf;
149 base_insn = insn_value; /*???*/
ab0bd049 150#else
52a53d1f
DE		 151 base_insn = cgen_get_insn_value (od, buf, length);
152 bufp = insn_value;
ab0bd049
DE		 153#endif
154
155 /* The instructions are stored in hash lists.
156 Pick the first one and keep trying until we find the right one. */
157
52a53d1f 158 insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
ab0bd049
DE		 159 while (insn_list != NULL)
160 {
161 insn = insn_list->insn;
162
390bd87d
DE		 163 if (alias_p
164 || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
ab0bd049 165 {
390bd87d
DE		 166 /* Basic bit mask must be correct. */
167 /* ??? May wish to allow target to defer this check until the
168 extract handler. */
169 if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
170 {
fbc8134d 171 /* ??? 0 is passed for `pc' */
52a53d1f 172 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
fbc8134d
DE		 173 insn_value, fields,
174 (bfd_vma) 0);
1294c286
DE		 175 if (elength > 0)
176 {
177 /* sanity check */
178 if (length != 0 && length != elength)
179 abort ();
180 return insn;
181 }
390bd87d 182 }
ab0bd049
DE		 183 }
184
185 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
186 }
187 }
188 else
189 {
390bd87d
DE		 190 /* Sanity check: can't pass an alias insn if ! alias_p. */
191 if (! alias_p
192 && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
193 abort ();
1294c286
DE		 194 /* Sanity check: length must be correct. */
195 if (length != CGEN_INSN_BITSIZE (insn))
196 abort ();
390bd87d 197
fbc8134d 198 /* ??? 0 is passed for `pc' */
52a53d1f 199 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
fbc8134d 200 (bfd_vma) 0);
1294c286
DE		 201 /* Sanity check: must succeed.
202 Could relax this later if it ever proves useful. */
203 if (length == 0)
204 abort ();
205 return insn;
ab0bd049
DE		 206 }
207
208 return NULL;
209}
210
1294c286 211/* Fill in the operand instances used by INSN whose operands are FIELDS.
b02643b5 212 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
1294c286 213 in. */
ab0bd049 214
1294c286 215void
c2009f4a
DE		 216m32r_cgen_get_insn_operands (od, insn, fields, indices)
217 CGEN_OPCODE_DESC od;
1294c286
DE		 218 const CGEN_INSN * insn;
219 const CGEN_FIELDS * fields;
ab0bd049
DE		 220 int *indices;
221{
ab0bd049
DE		 222 const CGEN_OPERAND_INSTANCE *opinst;
223 int i;
224
ab0bd049 225 for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
b2f18612
DE		 226 opinst != NULL
227 && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
ab0bd049
DE		 228 ++i, ++opinst)
229 {
230 const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
231 if (op == NULL)
232 indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
233 else
0cc2fbf3
DE		 234 indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
235 fields);
ab0bd049 236 }
1294c286 237}
ab0bd049 238
1294c286
DE		 239/* Cover function to m32r_cgen_get_insn_operands when either INSN or FIELDS
240 isn't known.
241 The INSN, INSN_VALUE, and LENGTH arguments are passed to
242 m32r_cgen_lookup_insn unchanged.
243
244 The result is the insn table entry or NULL if the instruction wasn't
245 recognized. */
246
247const CGEN_INSN *
c2009f4a
DE		 248m32r_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
249 CGEN_OPCODE_DESC od;
1294c286 250 const CGEN_INSN *insn;
52a53d1f 251 CGEN_INSN_BYTES insn_value;
1294c286
DE		 252 int length;
253 int *indices;
254{
255 CGEN_FIELDS fields;
256
257 /* Pass non-zero for ALIAS_P only if INSN != NULL.
258 If INSN == NULL, we want a real insn. */
c2009f4a 259 insn = m32r_cgen_lookup_insn (od, insn, insn_value, length, &fields,
1294c286
DE		 260 insn != NULL);
261 if (! insn)
262 return NULL;
263
c2009f4a 264 m32r_cgen_get_insn_operands (od, insn, &fields, indices);
ab0bd049
DE		 265 return insn;
266}
23cf992f
NC		 267/* Attributes. */
268
7c26196f 269static const CGEN_ATTR_ENTRY MACH_attr[] =
5d07b6cf 270{
52a53d1f 271 { "base", MACH_BASE },
5d07b6cf 272 { "m32r", MACH_M32R },
7c26196f
DE		 273/* start-sanitize-m32rx */
274 { "m32rx", MACH_M32RX },
275/* end-sanitize-m32rx */
276 { "max", MACH_MAX },
277 { 0, 0 }
278};
279
280/* start-sanitize-m32rx */
281static const CGEN_ATTR_ENTRY PIPE_attr[] =
282{
283 { "NONE", PIPE_NONE },
284 { "O", PIPE_O },
285 { "S", PIPE_S },
286 { "OS", PIPE_OS },
23cf992f
NC		 287 { 0, 0 }
288};
289
7c26196f 290/* end-sanitize-m32rx */
52a53d1f
DE		 291const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
292{
293 { "MACH", & MACH_attr[0] },
294 { "CACHE-ADDR", NULL },
295 { "FUN-ACCESS", NULL },
296 { "PC", NULL },
297 { "PROFILE", NULL },
298 { "SIGN-OPT", NULL },
299 { "UNSIGNED", NULL },
300 { 0, 0 }
301};
302
7c26196f 303const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
5d07b6cf
DE		 304{
305 { "ABS-ADDR", NULL },
23cf992f 306 { "FAKE", NULL },
a6cefe4f 307 { "HASH-PREFIX", NULL },
23cf992f 308 { "NEGATIVE", NULL },
23cf992f
NC		 309 { "PCREL-ADDR", NULL },
310 { "RELAX", NULL },
311 { "RELOC", NULL },
312 { "SIGN-OPT", NULL },
313 { "UNSIGNED", NULL },
314 { 0, 0 }
315};
316
7c26196f 317const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
5d07b6cf 318{
7c26196f
DE		 319 { "MACH", & MACH_attr[0] },
320/* start-sanitize-m32rx */
321 { "PIPE", & PIPE_attr[0] },
322/* end-sanitize-m32rx */
5d07b6cf 323 { "ALIAS", NULL },
23cf992f
NC		 324 { "COND-CTI", NULL },
325 { "FILL-SLOT", NULL },
1294c286 326 { "NO-DIS", NULL },
23cf992f 327 { "RELAX", NULL },
23cf992f 328 { "RELAXABLE", NULL },
52a53d1f 329 { "SKIP-CTI", NULL },
fbc8134d 330 { "SPECIAL", NULL },
23cf992f 331 { "UNCOND-CTI", NULL },
52a53d1f 332 { "VIRTUAL", NULL },
23cf992f 333 { 0, 0 }
9c03036a
DE		 334};
335
853713a7 336CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
5d07b6cf
DE		 337{
338 { "fp", 13 },
9c03036a
DE		 339 { "lr", 14 },
340 { "sp", 15 },
341 { "r0", 0 },
342 { "r1", 1 },
343 { "r2", 2 },
344 { "r3", 3 },
345 { "r4", 4 },
346 { "r5", 5 },
347 { "r6", 6 },
348 { "r7", 7 },
349 { "r8", 8 },
350 { "r9", 9 },
351 { "r10", 10 },
352 { "r11", 11 },
353 { "r12", 12 },
354 { "r13", 13 },
355 { "r14", 14 },
356 { "r15", 15 }
357};
358
853713a7 359CGEN_KEYWORD m32r_cgen_opval_h_gr =
5d07b6cf
DE		 360{
361 & m32r_cgen_opval_h_gr_entries[0],
9c03036a
DE		 362 19
363};
364
853713a7 365CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
5d07b6cf
DE		 366{
367 { "psw", 0 },
9c03036a
DE		 368 { "cbr", 1 },
369 { "spi", 2 },
370 { "spu", 3 },
371 { "bpc", 6 },
52a53d1f
DE		 372 { "bbpsw", 8 },
373 { "bbpc", 14 },
9c03036a
DE		 374 { "cr0", 0 },
375 { "cr1", 1 },
376 { "cr2", 2 },
377 { "cr3", 3 },
378 { "cr4", 4 },
379 { "cr5", 5 },
b2ddf0c4
NC		 380 { "cr6", 6 },
381 { "cr7", 7 },
382 { "cr8", 8 },
383 { "cr9", 9 },
384 { "cr10", 10 },
385 { "cr11", 11 },
386 { "cr12", 12 },
387 { "cr13", 13 },
388 { "cr14", 14 },
389 { "cr15", 15 }
9c03036a
DE		 390};
391
853713a7 392CGEN_KEYWORD m32r_cgen_opval_h_cr =
5d07b6cf
DE		 393{
394 & m32r_cgen_opval_h_cr_entries[0],
52a53d1f 395 23
9c03036a
DE		 396};
397
7c26196f
DE		 398/* start-sanitize-m32rx */
399CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
400{
401 { "a0", 0 },
402 { "a1", 1 }
403};
23cf992f 404
7c26196f 405CGEN_KEYWORD m32r_cgen_opval_h_accums =
5d07b6cf 406{
7c26196f
DE		 407 & m32r_cgen_opval_h_accums_entries[0],
408 2
9c03036a
DE		 409};
410
7c26196f
DE		 411/* end-sanitize-m32rx */
412
ab0bd049
DE		 413/* The hardware table. */
414
415#define HW_ENT(n) m32r_cgen_hw_entries[n]
416static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
7c26196f 417{
52a53d1f
DE		 418 { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
419 { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
420 { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
421 { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
422 { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
423 { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
424 { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_SIGN_OPT)|(1<<CGEN_HW_UNSIGNED), { (1<<MACH_BASE) } } },
425 { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
426 { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
427 { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
428 { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
429 { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
7c26196f 430/* start-sanitize-m32rx */
52a53d1f 431 { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_M32RX) } } },
7c26196f 432/* end-sanitize-m32rx */
52a53d1f
DE		 433 { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
434 { HW_H_PSW, & HW_ENT (HW_H_PSW + 1), "h-psw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
435 { HW_H_BPSW, & HW_ENT (HW_H_BPSW + 1), "h-bpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
436 { HW_H_BBPSW, & HW_ENT (HW_H_BBPSW + 1), "h-bbpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
437 { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
7c26196f
DE		 438 { 0 }
439};
9c03036a 440
ab0bd049
DE		 441/* The operand table. */
442
8d157f96
DE		 443#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
444#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
0bf55db8 445
7c26196f 446const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
9c03036a 447{
23cf992f 448/* pc: program counter */
ab0bd049 449 { "pc", & HW_ENT (HW_H_PC), 0, 0,
fbc8134d 450 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
9c03036a 451/* sr: source register */
ab0bd049
DE		 452 { "sr", & HW_ENT (HW_H_GR), 12, 4,
453 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 454/* dr: destination register */
ab0bd049
DE		 455 { "dr", & HW_ENT (HW_H_GR), 4, 4,
456 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 457/* src1: source register 1 */
ab0bd049
DE		 458 { "src1", & HW_ENT (HW_H_GR), 4, 4,
459 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 460/* src2: source register 2 */
ab0bd049
DE		 461 { "src2", & HW_ENT (HW_H_GR), 12, 4,
462 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 463/* scr: source control register */
ab0bd049
DE		 464 { "scr", & HW_ENT (HW_H_CR), 12, 4,
465 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 466/* dcr: destination control register */
ab0bd049
DE		 467 { "dcr", & HW_ENT (HW_H_CR), 4, 4,
468 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 469/* simm8: 8 bit signed immediate */
ab0bd049 470 { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
a6cefe4f 471 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 472/* simm16: 16 bit signed immediate */
ab0bd049 473 { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
a6cefe4f 474 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
9c03036a 475/* uimm4: 4 bit trap number */
ab0bd049 476 { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
a6cefe4f 477 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 478/* uimm5: 5 bit shift count */
ab0bd049 479 { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
a6cefe4f 480 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 481/* uimm16: 16 bit unsigned immediate */
ab0bd049 482 { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
a6cefe4f 483 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 484/* start-sanitize-m32rx */
485/* imm1: 1 bit immediate */
486 { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
a6cefe4f 487 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
ab0bd049
DE		 488/* end-sanitize-m32rx */
489/* start-sanitize-m32rx */
490/* accd: accumulator destination register */
491 { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
492 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
493/* end-sanitize-m32rx */
7c26196f 494/* start-sanitize-m32rx */
ab0bd049
DE		 495/* accs: accumulator source register */
496 { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
497 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f
DE		 498/* end-sanitize-m32rx */
499/* start-sanitize-m32rx */
500/* acc: accumulator reg (d) */
ab0bd049
DE		 501 { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
502 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
7c26196f 503/* end-sanitize-m32rx */
a6cefe4f
DE		 504/* hash: # prefix */
505 { "hash", & HW_ENT (HW_H_SINT), 0, 0,
506 { 0, 0, { 0 } } },
9c03036a 507/* hi16: high 16 bit immediate, sign optional */
ab0bd049
DE		 508 { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
509 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 510/* slo16: 16 bit signed immediate, for low() */
ab0bd049
DE		 511 { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
512 { 0, 0, { 0 } } },
9c03036a 513/* ulo16: 16 bit unsigned immediate, for low() */
ab0bd049
DE		 514 { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
515 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 516/* uimm24: 24 bit address */
ab0bd049 517 { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
a6cefe4f 518 { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
9c03036a 519/* disp8: 8 bit displacement */
ab0bd049
DE		 520 { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
521 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 522/* disp16: 16 bit displacement */
ab0bd049
DE		 523 { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
524 { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
9c03036a 525/* disp24: 24 bit displacement */
ab0bd049
DE		 526 { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
527 { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
23cf992f 528/* condbit: condition bit */
ab0bd049
DE		 529 { "condbit", & HW_ENT (HW_H_COND), 0, 0,
530 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f 531/* accum: accumulator */
ab0bd049
DE		 532 { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
533 { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
23cf992f
NC		 534};
535
ab0bd049
DE		 536/* Operand references. */
537
7caa7497
DE		 538#define INPUT CGEN_OPERAND_INSTANCE_INPUT
539#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
540
1294c286 541static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
52a53d1f
DE		 542 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
543 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
544 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 545 { 0 }
546};
547
1294c286 548static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
52a53d1f
DE		 549 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
550 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
551 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 552 { 0 }
553};
554
1294c286 555static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
52a53d1f
DE		 556 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
557 { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
558 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 559 { 0 }
560};
561
1294c286 562static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
52a53d1f
DE		 563 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
564 { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
565 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 566 { 0 }
567};
568
1294c286 569static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
52a53d1f
DE		 570 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
571 { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
572 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 573 { 0 }
574};
575
1294c286 576static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
52a53d1f
DE		 577 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
578 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
579 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
580 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
390bd87d
DE		 581 { 0 }
582};
583
1294c286 584static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
52a53d1f
DE		 585 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
586 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
587 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
588 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
ab0bd049
DE		 589 { 0 }
590};
591
1294c286 592static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
52a53d1f
DE		 593 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
594 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
595 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
596 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
597 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
ab0bd049
DE		 598 { 0 }
599};
600
1294c286 601static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
52a53d1f
DE		 602 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
603 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
604 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 605 { 0 }
606};
607
1294c286 608static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
52a53d1f
DE		 609 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
610 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
611 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 612 { 0 }
613};
614
1294c286 615static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
52a53d1f
DE		 616 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
617 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
618 { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
619 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 620 { 0 }
621};
622
1294c286 623static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
52a53d1f
DE		 624 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
625 { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
626 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 627 { 0 }
628};
629
1294c286 630static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
52a53d1f
DE		 631 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
632 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
633 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
634 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 635 { 0 }
636};
637
1294c286 638static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
52a53d1f
DE		 639 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
640 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
641 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
642 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 643 { 0 }
644};
645
b2ddf0c4 646/* start-sanitize-m32rx */
1294c286 647static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
52a53d1f
DE		 648 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
649 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
650 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
651 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
652 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 653 { 0 }
654};
655
b2ddf0c4
NC		 656/* end-sanitize-m32rx */
657/* start-sanitize-m32rx */
1294c286 658static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
52a53d1f
DE		 659 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
660 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
661 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
662 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
663 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 664 { 0 }
665};
666
b2ddf0c4 667/* end-sanitize-m32rx */
1294c286 668static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
52a53d1f
DE		 669 { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
670 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 671 { 0 }
672};
673
1294c286 674static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
52a53d1f
DE		 675 { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
676 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 677 { 0 }
678};
679
1294c286 680static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
52a53d1f
DE		 681 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
682 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
683 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
ab0bd049
DE		 684 { 0 }
685};
686
1294c286 687static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
52a53d1f
DE		 688 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
689 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
690 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
ab0bd049
DE		 691 { 0 }
692};
693
b2ddf0c4 694/* start-sanitize-m32rx */
1294c286 695static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
52a53d1f
DE		 696 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
697 { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
ab0bd049
DE		 698 { 0 }
699};
700
b2ddf0c4 701/* end-sanitize-m32rx */
1294c286 702static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
52a53d1f
DE		 703 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
704 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
705 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 706 { 0 }
707};
708
b2ddf0c4 709/* start-sanitize-m32rx */
1294c286 710static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
52a53d1f
DE		 711 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
712 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
713 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 714 { 0 }
715};
716
b2ddf0c4 717/* end-sanitize-m32rx */
1294c286 718static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
52a53d1f
DE		 719 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
720 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
721 { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
722 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 723 { 0 }
724};
725
1294c286 726static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
52a53d1f
DE		 727 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
728 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
ab0bd049
DE		 729 { 0 }
730};
731
1294c286 732static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
52a53d1f
DE		 733 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
734 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
735 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 736 { 0 }
737};
738
1294c286 739static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
52a53d1f
DE		 740 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
741 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
742 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
743 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 744 { 0 }
745};
746
1294c286 747static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
52a53d1f
DE		 748 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
749 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
750 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 751 { 0 }
752};
753
1294c286 754static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
52a53d1f
DE		 755 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
756 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
757 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
758 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 759 { 0 }
760};
761
1294c286 762static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
52a53d1f
DE		 763 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
764 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
765 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 766 { 0 }
767};
768
1294c286 769static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
52a53d1f
DE		 770 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
771 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
772 { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
773 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 774 { 0 }
775};
776
1294c286 777static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
52a53d1f
DE		 778 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
779 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
780 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
781 { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
390bd87d
DE		 782 { 0 }
783};
784
1294c286 785static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
52a53d1f
DE		 786 { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
787 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 788 { 0 }
789};
790
1294c286 791static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
52a53d1f
DE		 792 { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
793 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 794 { 0 }
795};
796
1294c286 797static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
52a53d1f
DE		 798 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
799 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 800 { 0 }
801};
802
1294c286 803static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
52a53d1f
DE		 804 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
805 { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
806 { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
807 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
390bd87d
DE		 808 { 0 }
809};
810
1294c286 811static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
52a53d1f
DE		 812 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
813 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
814 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
815 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 816 { 0 }
817};
818
b2ddf0c4 819/* start-sanitize-m32rx */
1294c286 820static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
52a53d1f
DE		 821 { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
822 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
823 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
824 { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 825 { 0 }
826};
827
b2ddf0c4 828/* end-sanitize-m32rx */
1294c286 829static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
52a53d1f
DE		 830 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
831 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
832 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
390bd87d
DE		 833 { 0 }
834};
835
b2ddf0c4 836/* start-sanitize-m32rx */
1294c286 837static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
52a53d1f
DE		 838 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
839 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
840 { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
ab0bd049
DE		 841 { 0 }
842};
843
b2ddf0c4 844/* end-sanitize-m32rx */
1294c286 845static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
52a53d1f
DE		 846 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
847 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 848 { 0 }
849};
850
1294c286 851static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
52a53d1f
DE		 852 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
853 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 854 { 0 }
855};
856
b2ddf0c4 857/* start-sanitize-m32rx */
1294c286 858static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
52a53d1f
DE		 859 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
860 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 861 { 0 }
862};
863
b2ddf0c4 864/* end-sanitize-m32rx */
1294c286 865static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
52a53d1f
DE		 866 { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
867 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 868 { 0 }
869};
870
1294c286 871static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
52a53d1f
DE		 872 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
873 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
874 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 875 { 0 }
876};
877
b2ddf0c4 878/* start-sanitize-m32rx */
1294c286 879static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
52a53d1f
DE		 880 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
881 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
882 { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
ab0bd049
DE		 883 { 0 }
884};
885
b2ddf0c4 886/* end-sanitize-m32rx */
1294c286 887static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
52a53d1f
DE		 888 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
889 { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
ab0bd049
DE		 890 { 0 }
891};
892
1294c286 893static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
52a53d1f
DE		 894 { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
895 { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 896 { 0 }
897};
898
b2ddf0c4 899/* start-sanitize-m32rx */
1294c286 900static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
52a53d1f
DE		 901 { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
902 { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
903 { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
ab0bd049
DE		 904 { 0 }
905};
906
b2ddf0c4 907/* end-sanitize-m32rx */
1294c286 908static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
52a53d1f
DE		 909 { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
910 { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
911 { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
912 { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
913 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
914 { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
915 { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
916 { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
ab0bd049
DE		 917 { 0 }
918};
919
1294c286 920static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
52a53d1f
DE		 921 { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
922 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 923 { 0 }
924};
925
1294c286 926static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
52a53d1f
DE		 927 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
928 { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
929 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
390bd87d
DE		 930 { 0 }
931};
932
1294c286 933static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
52a53d1f
DE		 934 { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
935 { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
936 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 937 { 0 }
938};
939
1294c286 940static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
52a53d1f
DE		 941 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
942 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
943 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
390bd87d
DE		 944 { 0 }
945};
946
1294c286 947static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
52a53d1f
DE		 948 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
949 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
950 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
951 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 952 { 0 }
953};
954
1294c286 955static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
52a53d1f
DE		 956 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
957 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
958 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
390bd87d
DE		 959 { 0 }
960};
961
1294c286 962static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
52a53d1f
DE		 963 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
964 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
965 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
966 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
390bd87d
DE		 967 { 0 }
968};
969
1294c286 970static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
52a53d1f
DE		 971 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
972 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
973 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
390bd87d
DE		 974 { 0 }
975};
976
1294c286 977static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
52a53d1f
DE		 978 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
979 { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
980 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
981 { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
390bd87d
DE		 982 { 0 }
983};
984
1294c286 985static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
52a53d1f
DE		 986 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
987 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
988 { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
989 { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
390bd87d
DE		 990 { 0 }
991};
992
1294c286 993static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
52a53d1f
DE		 994 { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
995 { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
996 { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
997 { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
998 { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
999 { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
1000 { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
1001 { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
1002 { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
1003 { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
1004 { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
ab0bd049
DE		 1005 { 0 }
1006};
1007
1294c286 1008static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
52a53d1f
DE		 1009 { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
1010 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
1011 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
1012 { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
1013 { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
390bd87d
DE		 1014 { 0 }
1015};
1016
b2ddf0c4 1017/* start-sanitize-m32rx */
1294c286 1018static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
52a53d1f
DE		 1019 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
1020 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 1021 { 0 }
1022};
1023
b2ddf0c4
NC		 1024/* end-sanitize-m32rx */
1025/* start-sanitize-m32rx */
1294c286 1026static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
52a53d1f
DE		 1027 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
1028 { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
1029 { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
ab0bd049
DE		 1030 { 0 }
1031};
1032
b2ddf0c4
NC		 1033/* end-sanitize-m32rx */
1034/* start-sanitize-m32rx */
1294c286 1035static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
52a53d1f
DE		 1036 { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
1037 { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
1038 { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
ab0bd049
DE		 1039 { 0 }
1040};
1041
b2ddf0c4
NC		 1042/* end-sanitize-m32rx */
1043/* start-sanitize-m32rx */
1294c286 1044static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
52a53d1f
DE		 1045 { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
1046 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
1047 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
1048 { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
ab0bd049
DE		 1049 { 0 }
1050};
1051
b2ddf0c4
NC		 1052/* end-sanitize-m32rx */
1053/* start-sanitize-m32rx */
1294c286 1054static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
52a53d1f
DE		 1055 { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
1056 { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
1057 { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
390bd87d
DE		 1058 { 0 }
1059};
1060
b2ddf0c4
NC		 1061/* end-sanitize-m32rx */
1062/* start-sanitize-m32rx */
1294c286 1063static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
52a53d1f 1064 { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
ab0bd049
DE		 1065 { 0 }
1066};
1067
b2ddf0c4 1068/* end-sanitize-m32rx */
7caa7497
DE		 1069#undef INPUT
1070#undef OUTPUT
1071
0bf55db8 1072#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
8d157f96
DE		 1073#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1074#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
23cf992f 1075
1294c286
DE		 1076/* The instruction table.
1077 This is currently non-static because the simulator accesses it
1078 directly. */
ab0bd049 1079
7c26196f 1080const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
5d07b6cf 1081{
1294c286 1082 /* Special null first entry.
52a53d1f
DE		 1083 A `num' value of zero is thus invalid.
1084 Also, the special `invalid' insn resides here. */
23cf992f 1085 { { 0 }, 0 },
9c03036a
DE		 1086/* add $dr,$sr */
1087 {
23cf992f 1088 { 1, 1, 1, 1 },
1294c286 1089 M32R_INSN_ADD, "add", "add",
2e6dfccc 1090 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1091 { 16, 16, 0xf0f0 }, 0xa0,
1294c286 1092 (PTR) & fmt_add_ops[0],
52a53d1f 1093 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a 1094 },
a6cefe4f 1095/* add3 $dr,$sr,$hash$slo16 */
9c03036a 1096 {
23cf992f 1097 { 1, 1, 1, 1 },
1294c286 1098 M32R_INSN_ADD3, "add3", "add3",
2e6dfccc 1099 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
0bf55db8 1100 { 32, 32, 0xf0f00000 }, 0x80a00000,
1294c286 1101 (PTR) & fmt_add3_ops[0],
52a53d1f 1102 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
7c26196f 1103 },
9c03036a
DE		 1104/* and $dr,$sr */
1105 {
23cf992f 1106 { 1, 1, 1, 1 },
1294c286 1107 M32R_INSN_AND, "and", "and",
2e6dfccc 1108 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1109 { 16, 16, 0xf0f0 }, 0xc0,
1294c286 1110 (PTR) & fmt_add_ops[0],
52a53d1f 1111 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1112 },
9c03036a
DE		 1113/* and3 $dr,$sr,$uimm16 */
1114 {
23cf992f 1115 { 1, 1, 1, 1 },
1294c286 1116 M32R_INSN_AND3, "and3", "and3",
2e6dfccc 1117 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
0bf55db8 1118 { 32, 32, 0xf0f00000 }, 0x80c00000,
1294c286 1119 (PTR) & fmt_and3_ops[0],
52a53d1f 1120 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1121 },
1122/* or $dr,$sr */
1123 {
23cf992f 1124 { 1, 1, 1, 1 },
1294c286 1125 M32R_INSN_OR, "or", "or",
2e6dfccc 1126 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1127 { 16, 16, 0xf0f0 }, 0xe0,
1294c286 1128 (PTR) & fmt_add_ops[0],
52a53d1f 1129 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1130 },
a6cefe4f 1131/* or3 $dr,$sr,$hash$ulo16 */
7c26196f
DE		 1132 {
1133 { 1, 1, 1, 1 },
1294c286 1134 M32R_INSN_OR3, "or3", "or3",
2e6dfccc 1135 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
0bf55db8 1136 { 32, 32, 0xf0f00000 }, 0x80e00000,
1294c286 1137 (PTR) & fmt_or3_ops[0],
52a53d1f 1138 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1139 },
9c03036a
DE		 1140/* xor $dr,$sr */
1141 {
23cf992f 1142 { 1, 1, 1, 1 },
1294c286 1143 M32R_INSN_XOR, "xor", "xor",
2e6dfccc 1144 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1145 { 16, 16, 0xf0f0 }, 0xd0,
1294c286 1146 (PTR) & fmt_add_ops[0],
52a53d1f 1147 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1148 },
9c03036a
DE		 1149/* xor3 $dr,$sr,$uimm16 */
1150 {
23cf992f 1151 { 1, 1, 1, 1 },
1294c286 1152 M32R_INSN_XOR3, "xor3", "xor3",
2e6dfccc 1153 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
0bf55db8 1154 { 32, 32, 0xf0f00000 }, 0x80d00000,
1294c286 1155 (PTR) & fmt_and3_ops[0],
52a53d1f 1156 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1157 },
1158/* addi $dr,$simm8 */
1159 {
23cf992f 1160 { 1, 1, 1, 1 },
1294c286 1161 M32R_INSN_ADDI, "addi", "addi",
2e6dfccc 1162 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
0bf55db8 1163 { 16, 16, 0xf000 }, 0x4000,
1294c286 1164 (PTR) & fmt_addi_ops[0],
52a53d1f 1165 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 1166 },
1167/* addv $dr,$sr */
1168 {
23cf992f 1169 { 1, 1, 1, 1 },
1294c286 1170 M32R_INSN_ADDV, "addv", "addv",
2e6dfccc 1171 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1172 { 16, 16, 0xf0f0 }, 0x80,
1294c286 1173 (PTR) & fmt_addv_ops[0],
52a53d1f 1174 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1175 },
9c03036a
DE		 1176/* addv3 $dr,$sr,$simm16 */
1177 {
23cf992f 1178 { 1, 1, 1, 1 },
1294c286 1179 M32R_INSN_ADDV3, "addv3", "addv3",
2e6dfccc 1180 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 1181 { 32, 32, 0xf0f00000 }, 0x80800000,
1294c286 1182 (PTR) & fmt_addv3_ops[0],
52a53d1f 1183 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1184 },
1185/* addx $dr,$sr */
1186 {
23cf992f 1187 { 1, 1, 1, 1 },
1294c286 1188 M32R_INSN_ADDX, "addx", "addx",
2e6dfccc 1189 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1190 { 16, 16, 0xf0f0 }, 0x90,
1294c286 1191 (PTR) & fmt_addx_ops[0],
52a53d1f 1192 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a 1193 },
9c03036a
DE		 1194/* bc.s $disp8 */
1195 {
23cf992f 1196 { 1, 1, 1, 1 },
1294c286 1197 M32R_INSN_BC8, "bc8", "bc.s",
2e6dfccc 1198 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1199 { 16, 16, 0xff00 }, 0x7c00,
1294c286 1200 (PTR) & fmt_bc8_ops[0],
52a53d1f 1201 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1202 },
1203/* bc.l $disp24 */
1204 {
23cf992f 1205 { 1, 1, 1, 1 },
1294c286 1206 M32R_INSN_BC24, "bc24", "bc.l",
2e6dfccc 1207 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1208 { 32, 32, 0xff000000 }, 0xfc000000,
1294c286 1209 (PTR) & fmt_bc24_ops[0],
52a53d1f 1210 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1211 },
1212/* beq $src1,$src2,$disp16 */
1213 {
23cf992f 1214 { 1, 1, 1, 1 },
1294c286 1215 M32R_INSN_BEQ, "beq", "beq",
2e6dfccc 1216 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1217 { 32, 32, 0xf0f00000 }, 0xb0000000,
1294c286 1218 (PTR) & fmt_beq_ops[0],
52a53d1f 1219 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1220 },
1221/* beqz $src2,$disp16 */
1222 {
23cf992f 1223 { 1, 1, 1, 1 },
1294c286 1224 M32R_INSN_BEQZ, "beqz", "beqz",
2e6dfccc 1225 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1226 { 32, 32, 0xfff00000 }, 0xb0800000,
1294c286 1227 (PTR) & fmt_beqz_ops[0],
52a53d1f 1228 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1229 },
1230/* bgez $src2,$disp16 */
1231 {
23cf992f 1232 { 1, 1, 1, 1 },
1294c286 1233 M32R_INSN_BGEZ, "bgez", "bgez",
2e6dfccc 1234 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1235 { 32, 32, 0xfff00000 }, 0xb0b00000,
1294c286 1236 (PTR) & fmt_beqz_ops[0],
52a53d1f 1237 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1238 },
1239/* bgtz $src2,$disp16 */
1240 {
23cf992f 1241 { 1, 1, 1, 1 },
1294c286 1242 M32R_INSN_BGTZ, "bgtz", "bgtz",
2e6dfccc 1243 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1244 { 32, 32, 0xfff00000 }, 0xb0d00000,
1294c286 1245 (PTR) & fmt_beqz_ops[0],
52a53d1f 1246 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1247 },
1248/* blez $src2,$disp16 */
1249 {
23cf992f 1250 { 1, 1, 1, 1 },
1294c286 1251 M32R_INSN_BLEZ, "blez", "blez",
2e6dfccc 1252 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1253 { 32, 32, 0xfff00000 }, 0xb0c00000,
1294c286 1254 (PTR) & fmt_beqz_ops[0],
52a53d1f 1255 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1256 },
1257/* bltz $src2,$disp16 */
1258 {
23cf992f 1259 { 1, 1, 1, 1 },
1294c286 1260 M32R_INSN_BLTZ, "bltz", "bltz",
2e6dfccc 1261 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1262 { 32, 32, 0xfff00000 }, 0xb0a00000,
1294c286 1263 (PTR) & fmt_beqz_ops[0],
52a53d1f 1264 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1265 },
1266/* bnez $src2,$disp16 */
1267 {
23cf992f 1268 { 1, 1, 1, 1 },
1294c286 1269 M32R_INSN_BNEZ, "bnez", "bnez",
2e6dfccc 1270 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1271 { 32, 32, 0xfff00000 }, 0xb0900000,
1294c286 1272 (PTR) & fmt_beqz_ops[0],
52a53d1f 1273 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1274 },
9c03036a
DE		 1275/* bl.s $disp8 */
1276 {
23cf992f 1277 { 1, 1, 1, 1 },
1294c286 1278 M32R_INSN_BL8, "bl8", "bl.s",
2e6dfccc 1279 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1280 { 16, 16, 0xff00 }, 0x7e00,
1294c286 1281 (PTR) & fmt_bl8_ops[0],
52a53d1f 1282 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1283 },
1284/* bl.l $disp24 */
1285 {
23cf992f 1286 { 1, 1, 1, 1 },
1294c286 1287 M32R_INSN_BL24, "bl24", "bl.l",
2e6dfccc 1288 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1289 { 32, 32, 0xff000000 }, 0xfe000000,
1294c286 1290 (PTR) & fmt_bl24_ops[0],
52a53d1f 1291 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
7c26196f 1292 },
7c26196f
DE		 1293/* start-sanitize-m32rx */
1294/* bcl.s $disp8 */
1295 {
1296 { 1, 1, 1, 1 },
1294c286 1297 M32R_INSN_BCL8, "bcl8", "bcl.s",
2e6dfccc 1298 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1299 { 16, 16, 0xff00 }, 0x7800,
1294c286 1300 (PTR) & fmt_bcl8_ops[0],
52a53d1f 1301 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1302 },
1303/* end-sanitize-m32rx */
1304/* start-sanitize-m32rx */
1305/* bcl.l $disp24 */
1306 {
1307 { 1, 1, 1, 1 },
1294c286 1308 M32R_INSN_BCL24, "bcl24", "bcl.l",
2e6dfccc 1309 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1310 { 32, 32, 0xff000000 }, 0xf8000000,
1294c286
DE		 1311 (PTR) & fmt_bcl24_ops[0],
1312 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
9c03036a 1313 },
7c26196f 1314/* end-sanitize-m32rx */
9c03036a
DE		 1315/* bnc.s $disp8 */
1316 {
23cf992f 1317 { 1, 1, 1, 1 },
1294c286 1318 M32R_INSN_BNC8, "bnc8", "bnc.s",
2e6dfccc 1319 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1320 { 16, 16, 0xff00 }, 0x7d00,
1294c286 1321 (PTR) & fmt_bc8_ops[0],
52a53d1f 1322 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1323 },
1324/* bnc.l $disp24 */
1325 {
23cf992f 1326 { 1, 1, 1, 1 },
1294c286 1327 M32R_INSN_BNC24, "bnc24", "bnc.l",
2e6dfccc 1328 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1329 { 32, 32, 0xff000000 }, 0xfd000000,
1294c286 1330 (PTR) & fmt_bc24_ops[0],
52a53d1f 1331 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1332 },
1333/* bne $src1,$src2,$disp16 */
1334 {
23cf992f 1335 { 1, 1, 1, 1 },
1294c286 1336 M32R_INSN_BNE, "bne", "bne",
2e6dfccc 1337 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
0bf55db8 1338 { 32, 32, 0xf0f00000 }, 0xb0100000,
1294c286 1339 (PTR) & fmt_beq_ops[0],
52a53d1f 1340 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1341 },
9c03036a
DE		 1342/* bra.s $disp8 */
1343 {
23cf992f 1344 { 1, 1, 1, 1 },
1294c286 1345 M32R_INSN_BRA8, "bra8", "bra.s",
2e6dfccc 1346 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1347 { 16, 16, 0xff00 }, 0x7f00,
1294c286 1348 (PTR) & fmt_bra8_ops[0],
52a53d1f 1349 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1350 },
1351/* bra.l $disp24 */
1352 {
23cf992f 1353 { 1, 1, 1, 1 },
1294c286 1354 M32R_INSN_BRA24, "bra24", "bra.l",
2e6dfccc 1355 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1356 { 32, 32, 0xff000000 }, 0xff000000,
1294c286 1357 (PTR) & fmt_bra24_ops[0],
52a53d1f 1358 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
7c26196f
DE		 1359 },
1360/* start-sanitize-m32rx */
7c26196f
DE		 1361/* bncl.s $disp8 */
1362 {
1363 { 1, 1, 1, 1 },
1294c286 1364 M32R_INSN_BNCL8, "bncl8", "bncl.s",
2e6dfccc 1365 { { MNEM, ' ', OP (DISP8), 0 } },
0bf55db8 1366 { 16, 16, 0xff00 }, 0x7900,
1294c286 1367 (PTR) & fmt_bcl8_ops[0],
52a53d1f 1368 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1369 },
1370/* end-sanitize-m32rx */
1371/* start-sanitize-m32rx */
1372/* bncl.l $disp24 */
1373 {
1374 { 1, 1, 1, 1 },
1294c286 1375 M32R_INSN_BNCL24, "bncl24", "bncl.l",
2e6dfccc 1376 { { MNEM, ' ', OP (DISP24), 0 } },
0bf55db8 1377 { 32, 32, 0xff000000 }, 0xf9000000,
1294c286
DE		 1378 (PTR) & fmt_bcl24_ops[0],
1379 { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 1380 },
1381/* end-sanitize-m32rx */
9c03036a
DE		 1382/* cmp $src1,$src2 */
1383 {
23cf992f 1384 { 1, 1, 1, 1 },
1294c286 1385 M32R_INSN_CMP, "cmp", "cmp",
2e6dfccc 1386 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1387 { 16, 16, 0xf0f0 }, 0x40,
1294c286 1388 (PTR) & fmt_cmp_ops[0],
52a53d1f 1389 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1390 },
9c03036a
DE		 1391/* cmpi $src2,$simm16 */
1392 {
23cf992f 1393 { 1, 1, 1, 1 },
1294c286 1394 M32R_INSN_CMPI, "cmpi", "cmpi",
2e6dfccc 1395 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
0bf55db8 1396 { 32, 32, 0xfff00000 }, 0x80400000,
1294c286 1397 (PTR) & fmt_cmpi_ops[0],
52a53d1f 1398 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1399 },
1400/* cmpu $src1,$src2 */
1401 {
23cf992f 1402 { 1, 1, 1, 1 },
1294c286 1403 M32R_INSN_CMPU, "cmpu", "cmpu",
2e6dfccc 1404 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1405 { 16, 16, 0xf0f0 }, 0x50,
1294c286 1406 (PTR) & fmt_cmp_ops[0],
52a53d1f 1407 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 1408 },
1294c286 1409/* cmpui $src2,$simm16 */
23cf992f
NC		 1410 {
1411 { 1, 1, 1, 1 },
1294c286 1412 M32R_INSN_CMPUI, "cmpui", "cmpui",
2e6dfccc 1413 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
0bf55db8 1414 { 32, 32, 0xfff00000 }, 0x80500000,
1294c286 1415 (PTR) & fmt_cmpi_ops[0],
52a53d1f 1416 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
7c26196f
DE		 1417 },
1418/* start-sanitize-m32rx */
1419/* cmpeq $src1,$src2 */
1420 {
1421 { 1, 1, 1, 1 },
1294c286 1422 M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
2e6dfccc 1423 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1424 { 16, 16, 0xf0f0 }, 0x60,
1294c286 1425 (PTR) & fmt_cmp_ops[0],
8d157f96 1426 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 1427 },
1428/* end-sanitize-m32rx */
1429/* start-sanitize-m32rx */
1430/* cmpz $src2 */
1431 {
1432 { 1, 1, 1, 1 },
1294c286 1433 M32R_INSN_CMPZ, "cmpz", "cmpz",
2e6dfccc 1434 { { MNEM, ' ', OP (SRC2), 0 } },
0bf55db8 1435 { 16, 16, 0xfff0 }, 0x70,
1294c286 1436 (PTR) & fmt_cmpz_ops[0],
8d157f96 1437 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
9c03036a 1438 },
7c26196f 1439/* end-sanitize-m32rx */
9c03036a
DE		 1440/* div $dr,$sr */
1441 {
23cf992f 1442 { 1, 1, 1, 1 },
1294c286 1443 M32R_INSN_DIV, "div", "div",
2e6dfccc 1444 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1445 { 32, 32, 0xf0f0ffff }, 0x90000000,
1294c286 1446 (PTR) & fmt_div_ops[0],
52a53d1f 1447 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1448 },
1449/* divu $dr,$sr */
1450 {
23cf992f 1451 { 1, 1, 1, 1 },
1294c286 1452 M32R_INSN_DIVU, "divu", "divu",
2e6dfccc 1453 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1454 { 32, 32, 0xf0f0ffff }, 0x90100000,
1294c286 1455 (PTR) & fmt_div_ops[0],
52a53d1f 1456 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1457 },
1458/* rem $dr,$sr */
1459 {
23cf992f 1460 { 1, 1, 1, 1 },
1294c286 1461 M32R_INSN_REM, "rem", "rem",
2e6dfccc 1462 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1463 { 32, 32, 0xf0f0ffff }, 0x90200000,
1294c286 1464 (PTR) & fmt_div_ops[0],
52a53d1f 1465 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1466 },
1467/* remu $dr,$sr */
1468 {
23cf992f 1469 { 1, 1, 1, 1 },
1294c286 1470 M32R_INSN_REMU, "remu", "remu",
2e6dfccc 1471 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1472 { 32, 32, 0xf0f0ffff }, 0x90300000,
1294c286 1473 (PTR) & fmt_div_ops[0],
52a53d1f 1474 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
ab0bd049
DE		 1475 },
1476/* start-sanitize-m32rx */
1477/* divh $dr,$sr */
1478 {
1479 { 1, 1, 1, 1 },
1294c286 1480 M32R_INSN_DIVH, "divh", "divh",
2e6dfccc 1481 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1482 { 32, 32, 0xf0f0ffff }, 0x90000010,
1294c286 1483 (PTR) & fmt_div_ops[0],
8d157f96 1484 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f 1485 },
ab0bd049 1486/* end-sanitize-m32rx */
7c26196f
DE		 1487/* start-sanitize-m32rx */
1488/* jc $sr */
1489 {
1490 { 1, 1, 1, 1 },
1294c286 1491 M32R_INSN_JC, "jc", "jc",
2e6dfccc 1492 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1493 { 16, 16, 0xfff0 }, 0x1cc0,
1294c286 1494 (PTR) & fmt_jc_ops[0],
fbc8134d 1495 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 1496 },
1497/* end-sanitize-m32rx */
1498/* start-sanitize-m32rx */
1499/* jnc $sr */
1500 {
1501 { 1, 1, 1, 1 },
1294c286 1502 M32R_INSN_JNC, "jnc", "jnc",
2e6dfccc 1503 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1504 { 16, 16, 0xfff0 }, 0x1dc0,
1294c286 1505 (PTR) & fmt_jc_ops[0],
fbc8134d 1506 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
9c03036a 1507 },
7c26196f 1508/* end-sanitize-m32rx */
9c03036a
DE		 1509/* jl $sr */
1510 {
23cf992f 1511 { 1, 1, 1, 1 },
1294c286 1512 M32R_INSN_JL, "jl", "jl",
2e6dfccc 1513 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1514 { 16, 16, 0xfff0 }, 0x1ec0,
1294c286 1515 (PTR) & fmt_jl_ops[0],
52a53d1f 1516 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1517 },
1518/* jmp $sr */
1519 {
23cf992f 1520 { 1, 1, 1, 1 },
1294c286 1521 M32R_INSN_JMP, "jmp", "jmp",
2e6dfccc 1522 { { MNEM, ' ', OP (SR), 0 } },
0bf55db8 1523 { 16, 16, 0xfff0 }, 0x1fc0,
1294c286 1524 (PTR) & fmt_jmp_ops[0],
52a53d1f 1525 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1526 },
1527/* ld $dr,@$sr */
1528 {
23cf992f 1529 { 1, 1, 1, 1 },
1294c286 1530 M32R_INSN_LD, "ld", "ld",
2e6dfccc 1531 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1532 { 16, 16, 0xf0f0 }, 0x20c0,
1294c286 1533 (PTR) & fmt_ld_ops[0],
52a53d1f 1534 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1535 },
9c03036a
DE		 1536/* ld $dr,@($slo16,$sr) */
1537 {
23cf992f 1538 { 1, 1, 1, 1 },
1294c286 1539 M32R_INSN_LD_D, "ld-d", "ld",
2e6dfccc 1540 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1541 { 32, 32, 0xf0f00000 }, 0xa0c00000,
1294c286 1542 (PTR) & fmt_ld_d_ops[0],
52a53d1f 1543 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1544 },
9c03036a
DE		 1545/* ldb $dr,@$sr */
1546 {
23cf992f 1547 { 1, 1, 1, 1 },
1294c286 1548 M32R_INSN_LDB, "ldb", "ldb",
2e6dfccc 1549 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1550 { 16, 16, 0xf0f0 }, 0x2080,
1294c286 1551 (PTR) & fmt_ldb_ops[0],
52a53d1f 1552 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1553 },
9c03036a
DE		 1554/* ldb $dr,@($slo16,$sr) */
1555 {
23cf992f 1556 { 1, 1, 1, 1 },
1294c286 1557 M32R_INSN_LDB_D, "ldb-d", "ldb",
2e6dfccc 1558 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1559 { 32, 32, 0xf0f00000 }, 0xa0800000,
1294c286 1560 (PTR) & fmt_ldb_d_ops[0],
52a53d1f 1561 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1562 },
9c03036a
DE		 1563/* ldh $dr,@$sr */
1564 {
23cf992f 1565 { 1, 1, 1, 1 },
1294c286 1566 M32R_INSN_LDH, "ldh", "ldh",
2e6dfccc 1567 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1568 { 16, 16, 0xf0f0 }, 0x20a0,
1294c286 1569 (PTR) & fmt_ldh_ops[0],
52a53d1f 1570 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1571 },
9c03036a
DE		 1572/* ldh $dr,@($slo16,$sr) */
1573 {
23cf992f 1574 { 1, 1, 1, 1 },
1294c286 1575 M32R_INSN_LDH_D, "ldh-d", "ldh",
2e6dfccc 1576 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1577 { 32, 32, 0xf0f00000 }, 0xa0a00000,
1294c286 1578 (PTR) & fmt_ldh_d_ops[0],
52a53d1f 1579 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1580 },
9c03036a
DE		 1581/* ldub $dr,@$sr */
1582 {
23cf992f 1583 { 1, 1, 1, 1 },
1294c286 1584 M32R_INSN_LDUB, "ldub", "ldub",
2e6dfccc 1585 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1586 { 16, 16, 0xf0f0 }, 0x2090,
1294c286 1587 (PTR) & fmt_ldb_ops[0],
52a53d1f 1588 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1589 },
9c03036a
DE		 1590/* ldub $dr,@($slo16,$sr) */
1591 {
23cf992f 1592 { 1, 1, 1, 1 },
1294c286 1593 M32R_INSN_LDUB_D, "ldub-d", "ldub",
2e6dfccc 1594 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1595 { 32, 32, 0xf0f00000 }, 0xa0900000,
1294c286 1596 (PTR) & fmt_ldb_d_ops[0],
52a53d1f 1597 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1598 },
9c03036a
DE		 1599/* lduh $dr,@$sr */
1600 {
23cf992f 1601 { 1, 1, 1, 1 },
1294c286 1602 M32R_INSN_LDUH, "lduh", "lduh",
2e6dfccc 1603 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1604 { 16, 16, 0xf0f0 }, 0x20b0,
1294c286 1605 (PTR) & fmt_ldh_ops[0],
52a53d1f 1606 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 1607 },
9c03036a
DE		 1608/* lduh $dr,@($slo16,$sr) */
1609 {
23cf992f 1610 { 1, 1, 1, 1 },
1294c286 1611 M32R_INSN_LDUH_D, "lduh-d", "lduh",
2e6dfccc 1612 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
0bf55db8 1613 { 32, 32, 0xf0f00000 }, 0xa0b00000,
1294c286 1614 (PTR) & fmt_ldh_d_ops[0],
52a53d1f 1615 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1616 },
9c03036a
DE		 1617/* ld $dr,@$sr+ */
1618 {
23cf992f 1619 { 1, 1, 1, 1 },
1294c286 1620 M32R_INSN_LD_PLUS, "ld-plus", "ld",
2e6dfccc 1621 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
0bf55db8 1622 { 16, 16, 0xf0f0 }, 0x20e0,
1294c286 1623 (PTR) & fmt_ld_plus_ops[0],
52a53d1f 1624 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 1625 },
9c03036a
DE		 1626/* ld24 $dr,$uimm24 */
1627 {
23cf992f 1628 { 1, 1, 1, 1 },
1294c286 1629 M32R_INSN_LD24, "ld24", "ld24",
2e6dfccc 1630 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
0bf55db8 1631 { 32, 32, 0xf0000000 }, 0xe0000000,
1294c286 1632 (PTR) & fmt_ld24_ops[0],
52a53d1f 1633 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 1634 },
9c03036a
DE		 1635/* ldi8 $dr,$simm8 */
1636 {
23cf992f 1637 { 1, 1, 1, 1 },
1294c286 1638 M32R_INSN_LDI8, "ldi8", "ldi8",
2e6dfccc 1639 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
0bf55db8 1640 { 16, 16, 0xf000 }, 0x6000,
1294c286 1641 (PTR) & fmt_ldi8_ops[0],
52a53d1f 1642 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a 1643 },
a6cefe4f 1644/* ldi16 $dr,$hash$slo16 */
9c03036a 1645 {
23cf992f 1646 { 1, 1, 1, 1 },
1294c286 1647 M32R_INSN_LDI16, "ldi16", "ldi16",
2e6dfccc 1648 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
0bf55db8 1649 { 32, 32, 0xf0ff0000 }, 0x90f00000,
1294c286 1650 (PTR) & fmt_ldi16_ops[0],
52a53d1f 1651 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 1652 },
1653/* lock $dr,@$sr */
1654 {
23cf992f 1655 { 1, 1, 1, 1 },
1294c286 1656 M32R_INSN_LOCK, "lock", "lock",
2e6dfccc 1657 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
0bf55db8 1658 { 16, 16, 0xf0f0 }, 0x20d0,
1294c286 1659 (PTR) & fmt_lock_ops[0],
52a53d1f 1660 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1661 },
1662/* machi $src1,$src2 */
1663 {
23cf992f 1664 { 1, 1, 1, 1 },
1294c286 1665 M32R_INSN_MACHI, "machi", "machi",
2e6dfccc 1666 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1667 { 16, 16, 0xf0f0 }, 0x3040,
1294c286 1668 (PTR) & fmt_machi_ops[0],
8d157f96 1669 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1670 },
1671/* start-sanitize-m32rx */
1672/* machi $src1,$src2,$acc */
1673 {
1674 { 1, 1, 1, 1 },
1294c286 1675 M32R_INSN_MACHI_A, "machi-a", "machi",
2e6dfccc 1676 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1677 { 16, 16, 0xf070 }, 0x3040,
1294c286 1678 (PTR) & fmt_machi_a_ops[0],
8d157f96 1679 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1680 },
7c26196f 1681/* end-sanitize-m32rx */
9c03036a
DE		 1682/* maclo $src1,$src2 */
1683 {
23cf992f 1684 { 1, 1, 1, 1 },
1294c286 1685 M32R_INSN_MACLO, "maclo", "maclo",
2e6dfccc 1686 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1687 { 16, 16, 0xf0f0 }, 0x3050,
1294c286 1688 (PTR) & fmt_machi_ops[0],
8d157f96 1689 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1690 },
7c26196f
DE		 1691/* start-sanitize-m32rx */
1692/* maclo $src1,$src2,$acc */
1693 {
1694 { 1, 1, 1, 1 },
1294c286 1695 M32R_INSN_MACLO_A, "maclo-a", "maclo",
2e6dfccc 1696 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1697 { 16, 16, 0xf070 }, 0x3050,
1294c286 1698 (PTR) & fmt_machi_a_ops[0],
8d157f96 1699 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1700 },
1701/* end-sanitize-m32rx */
9c03036a
DE		 1702/* macwhi $src1,$src2 */
1703 {
23cf992f 1704 { 1, 1, 1, 1 },
1294c286 1705 M32R_INSN_MACWHI, "macwhi", "macwhi",
2e6dfccc 1706 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1707 { 16, 16, 0xf0f0 }, 0x3060,
1294c286 1708 (PTR) & fmt_machi_ops[0],
8d157f96 1709 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1710 },
c2009f4a
DE		 1711/* start-sanitize-m32rx */
1712/* macwhi $src1,$src2,$acc */
1713 {
1714 { 1, 1, 1, 1 },
1715 M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
1716 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1717 { 16, 16, 0xf070 }, 0x3060,
c2009f4a
DE		 1718 (PTR) & fmt_machi_a_ops[0],
1719 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1720 },
1721/* end-sanitize-m32rx */
9c03036a
DE		 1722/* macwlo $src1,$src2 */
1723 {
23cf992f 1724 { 1, 1, 1, 1 },
1294c286 1725 M32R_INSN_MACWLO, "macwlo", "macwlo",
2e6dfccc 1726 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1727 { 16, 16, 0xf0f0 }, 0x3070,
1294c286 1728 (PTR) & fmt_machi_ops[0],
8d157f96 1729 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1730 },
c2009f4a
DE		 1731/* start-sanitize-m32rx */
1732/* macwlo $src1,$src2,$acc */
1733 {
1734 { 1, 1, 1, 1 },
1735 M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
1736 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1737 { 16, 16, 0xf070 }, 0x3070,
c2009f4a
DE		 1738 (PTR) & fmt_machi_a_ops[0],
1739 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1740 },
1741/* end-sanitize-m32rx */
9c03036a
DE		 1742/* mul $dr,$sr */
1743 {
23cf992f 1744 { 1, 1, 1, 1 },
1294c286 1745 M32R_INSN_MUL, "mul", "mul",
2e6dfccc 1746 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1747 { 16, 16, 0xf0f0 }, 0x1060,
1294c286 1748 (PTR) & fmt_add_ops[0],
52a53d1f 1749 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } }
9c03036a
DE		 1750 },
1751/* mulhi $src1,$src2 */
1752 {
23cf992f 1753 { 1, 1, 1, 1 },
1294c286 1754 M32R_INSN_MULHI, "mulhi", "mulhi",
2e6dfccc 1755 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1756 { 16, 16, 0xf0f0 }, 0x3000,
1294c286 1757 (PTR) & fmt_mulhi_ops[0],
8d157f96 1758 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1759 },
1760/* start-sanitize-m32rx */
1761/* mulhi $src1,$src2,$acc */
1762 {
1763 { 1, 1, 1, 1 },
1294c286 1764 M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
2e6dfccc 1765 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1766 { 16, 16, 0xf070 }, 0x3000,
1294c286 1767 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1768 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1769 },
7c26196f 1770/* end-sanitize-m32rx */
9c03036a
DE		 1771/* mullo $src1,$src2 */
1772 {
23cf992f 1773 { 1, 1, 1, 1 },
1294c286 1774 M32R_INSN_MULLO, "mullo", "mullo",
2e6dfccc 1775 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1776 { 16, 16, 0xf0f0 }, 0x3010,
1294c286 1777 (PTR) & fmt_mulhi_ops[0],
8d157f96 1778 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1779 },
7c26196f
DE		 1780/* start-sanitize-m32rx */
1781/* mullo $src1,$src2,$acc */
1782 {
1783 { 1, 1, 1, 1 },
1294c286 1784 M32R_INSN_MULLO_A, "mullo-a", "mullo",
2e6dfccc 1785 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
0bf55db8 1786 { 16, 16, 0xf070 }, 0x3010,
1294c286 1787 (PTR) & fmt_mulhi_a_ops[0],
8d157f96 1788 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1789 },
1790/* end-sanitize-m32rx */
9c03036a
DE		 1791/* mulwhi $src1,$src2 */
1792 {
23cf992f 1793 { 1, 1, 1, 1 },
1294c286 1794 M32R_INSN_MULWHI, "mulwhi", "mulwhi",
2e6dfccc 1795 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1796 { 16, 16, 0xf0f0 }, 0x3020,
1294c286 1797 (PTR) & fmt_mulhi_ops[0],
8d157f96 1798 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1799 },
c2009f4a
DE		 1800/* start-sanitize-m32rx */
1801/* mulwhi $src1,$src2,$acc */
1802 {
1803 { 1, 1, 1, 1 },
1804 M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
1805 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1806 { 16, 16, 0xf070 }, 0x3020,
c2009f4a
DE		 1807 (PTR) & fmt_mulhi_a_ops[0],
1808 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1809 },
1810/* end-sanitize-m32rx */
9c03036a
DE		 1811/* mulwlo $src1,$src2 */
1812 {
23cf992f 1813 { 1, 1, 1, 1 },
1294c286 1814 M32R_INSN_MULWLO, "mulwlo", "mulwlo",
2e6dfccc 1815 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 1816 { 16, 16, 0xf0f0 }, 0x3030,
1294c286 1817 (PTR) & fmt_mulhi_ops[0],
8d157f96 1818 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1819 },
c2009f4a
DE		 1820/* start-sanitize-m32rx */
1821/* mulwlo $src1,$src2,$acc */
1822 {
1823 { 1, 1, 1, 1 },
1824 M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
1825 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
1826 { 16, 16, 0xf070 }, 0x3030,
c2009f4a
DE		 1827 (PTR) & fmt_mulhi_a_ops[0],
1828 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
1829 },
1830/* end-sanitize-m32rx */
9c03036a
DE		 1831/* mv $dr,$sr */
1832 {
23cf992f 1833 { 1, 1, 1, 1 },
1294c286 1834 M32R_INSN_MV, "mv", "mv",
2e6dfccc 1835 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1836 { 16, 16, 0xf0f0 }, 0x1080,
1294c286 1837 (PTR) & fmt_mv_ops[0],
52a53d1f 1838 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 1839 },
1840/* mvfachi $dr */
1841 {
23cf992f 1842 { 1, 1, 1, 1 },
1294c286 1843 M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
2e6dfccc 1844 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1845 { 16, 16, 0xf0ff }, 0x50f0,
1294c286 1846 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1847 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1848 },
1849/* start-sanitize-m32rx */
1850/* mvfachi $dr,$accs */
1851 {
1852 { 1, 1, 1, 1 },
1294c286 1853 M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
2e6dfccc 1854 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1855 { 16, 16, 0xf0f3 }, 0x50f0,
1294c286 1856 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1857 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1858 },
7c26196f 1859/* end-sanitize-m32rx */
9c03036a
DE		 1860/* mvfaclo $dr */
1861 {
23cf992f 1862 { 1, 1, 1, 1 },
1294c286 1863 M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
2e6dfccc 1864 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1865 { 16, 16, 0xf0ff }, 0x50f1,
1294c286 1866 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1867 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1868 },
7c26196f
DE		 1869/* start-sanitize-m32rx */
1870/* mvfaclo $dr,$accs */
1871 {
1872 { 1, 1, 1, 1 },
1294c286 1873 M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
2e6dfccc 1874 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1875 { 16, 16, 0xf0f3 }, 0x50f1,
1294c286 1876 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1877 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1878 },
1879/* end-sanitize-m32rx */
9c03036a
DE		 1880/* mvfacmi $dr */
1881 {
23cf992f 1882 { 1, 1, 1, 1 },
1294c286 1883 M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
2e6dfccc 1884 { { MNEM, ' ', OP (DR), 0 } },
0bf55db8 1885 { 16, 16, 0xf0ff }, 0x50f2,
1294c286 1886 (PTR) & fmt_mvfachi_ops[0],
8d157f96 1887 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1888 },
1889/* start-sanitize-m32rx */
1890/* mvfacmi $dr,$accs */
1891 {
1892 { 1, 1, 1, 1 },
1294c286 1893 M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
2e6dfccc 1894 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
0bf55db8 1895 { 16, 16, 0xf0f3 }, 0x50f2,
1294c286 1896 (PTR) & fmt_mvfachi_a_ops[0],
8d157f96 1897 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1898 },
7c26196f 1899/* end-sanitize-m32rx */
9c03036a
DE		 1900/* mvfc $dr,$scr */
1901 {
23cf992f 1902 { 1, 1, 1, 1 },
1294c286 1903 M32R_INSN_MVFC, "mvfc", "mvfc",
2e6dfccc 1904 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
0bf55db8 1905 { 16, 16, 0xf0f0 }, 0x1090,
1294c286 1906 (PTR) & fmt_mvfc_ops[0],
52a53d1f 1907 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1908 },
1909/* mvtachi $src1 */
1910 {
23cf992f 1911 { 1, 1, 1, 1 },
1294c286 1912 M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
2e6dfccc 1913 { { MNEM, ' ', OP (SRC1), 0 } },
0bf55db8 1914 { 16, 16, 0xf0ff }, 0x5070,
1294c286 1915 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1916 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
9c03036a 1917 },
7c26196f
DE		 1918/* start-sanitize-m32rx */
1919/* mvtachi $src1,$accs */
1920 {
1921 { 1, 1, 1, 1 },
1294c286 1922 M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
2e6dfccc 1923 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
0bf55db8 1924 { 16, 16, 0xf0f3 }, 0x5070,
1294c286 1925 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1926 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 1927 },
1928/* end-sanitize-m32rx */
9c03036a
DE		 1929/* mvtaclo $src1 */
1930 {
23cf992f 1931 { 1, 1, 1, 1 },
1294c286 1932 M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
2e6dfccc 1933 { { MNEM, ' ', OP (SRC1), 0 } },
0bf55db8 1934 { 16, 16, 0xf0ff }, 0x5071,
1294c286 1935 (PTR) & fmt_mvtachi_ops[0],
8d157f96 1936 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1937 },
1938/* start-sanitize-m32rx */
1939/* mvtaclo $src1,$accs */
1940 {
1941 { 1, 1, 1, 1 },
1294c286 1942 M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
2e6dfccc 1943 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
0bf55db8 1944 { 16, 16, 0xf0f3 }, 0x5071,
1294c286 1945 (PTR) & fmt_mvtachi_a_ops[0],
8d157f96 1946 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 1947 },
7c26196f 1948/* end-sanitize-m32rx */
9c03036a
DE		 1949/* mvtc $sr,$dcr */
1950 {
23cf992f 1951 { 1, 1, 1, 1 },
1294c286 1952 M32R_INSN_MVTC, "mvtc", "mvtc",
2e6dfccc 1953 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
0bf55db8 1954 { 16, 16, 0xf0f0 }, 0x10a0,
1294c286 1955 (PTR) & fmt_mvtc_ops[0],
52a53d1f 1956 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 1957 },
1958/* neg $dr,$sr */
1959 {
23cf992f 1960 { 1, 1, 1, 1 },
1294c286 1961 M32R_INSN_NEG, "neg", "neg",
2e6dfccc 1962 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1963 { 16, 16, 0xf0f0 }, 0x30,
1294c286 1964 (PTR) & fmt_mv_ops[0],
52a53d1f 1965 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 1966 },
1967/* nop */
1968 {
23cf992f 1969 { 1, 1, 1, 1 },
1294c286 1970 M32R_INSN_NOP, "nop", "nop",
2e6dfccc 1971 { { MNEM, 0 } },
0bf55db8 1972 { 16, 16, 0xffff }, 0x7000,
1294c286 1973 (PTR) 0,
52a53d1f 1974 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 1975 },
1976/* not $dr,$sr */
1977 {
23cf992f 1978 { 1, 1, 1, 1 },
1294c286 1979 M32R_INSN_NOT, "not", "not",
2e6dfccc 1980 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 1981 { 16, 16, 0xf0f0 }, 0xb0,
1294c286 1982 (PTR) & fmt_mv_ops[0],
52a53d1f 1983 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 1984 },
1985/* rac */
1986 {
23cf992f 1987 { 1, 1, 1, 1 },
1294c286 1988 M32R_INSN_RAC, "rac", "rac",
2e6dfccc 1989 { { MNEM, 0 } },
0bf55db8 1990 { 16, 16, 0xffff }, 0x5090,
1294c286 1991 (PTR) & fmt_rac_ops[0],
8d157f96 1992 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
7c26196f
DE		 1993 },
1994/* start-sanitize-m32rx */
a6cefe4f 1995/* rac $accd,$accs,$imm1 */
ab0bd049
DE		 1996 {
1997 { 1, 1, 1, 1 },
1294c286 1998 M32R_INSN_RAC_DSI, "rac-dsi", "rac",
2e6dfccc 1999 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
0bf55db8 2000 { 16, 16, 0xf3f2 }, 0x5090,
1294c286 2001 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 2002 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2003 },
7c26196f 2004/* end-sanitize-m32rx */
9c03036a
DE		 2005/* rach */
2006 {
23cf992f 2007 { 1, 1, 1, 1 },
1294c286 2008 M32R_INSN_RACH, "rach", "rach",
2e6dfccc 2009 { { MNEM, 0 } },
0bf55db8 2010 { 16, 16, 0xffff }, 0x5080,
1294c286 2011 (PTR) & fmt_rac_ops[0],
8d157f96 2012 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
ab0bd049
DE		 2013 },
2014/* start-sanitize-m32rx */
a6cefe4f 2015/* rach $accd,$accs,$imm1 */
7c26196f
DE		 2016 {
2017 { 1, 1, 1, 1 },
1294c286 2018 M32R_INSN_RACH_DSI, "rach-dsi", "rach",
2e6dfccc 2019 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
0bf55db8 2020 { 16, 16, 0xf3f2 }, 0x5080,
1294c286 2021 (PTR) & fmt_rac_dsi_ops[0],
8d157f96 2022 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2023 },
7c26196f 2024/* end-sanitize-m32rx */
9c03036a
DE		 2025/* rte */
2026 {
23cf992f 2027 { 1, 1, 1, 1 },
1294c286 2028 M32R_INSN_RTE, "rte", "rte",
2e6dfccc 2029 { { MNEM, 0 } },
0bf55db8 2030 { 16, 16, 0xffff }, 0x10d6,
1294c286 2031 (PTR) & fmt_rte_ops[0],
52a53d1f 2032 { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
7c26196f 2033 },
a6cefe4f 2034/* seth $dr,$hash$hi16 */
7c26196f
DE		 2035 {
2036 { 1, 1, 1, 1 },
1294c286 2037 M32R_INSN_SETH, "seth", "seth",
2e6dfccc 2038 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
0bf55db8 2039 { 32, 32, 0xf0ff0000 }, 0xd0c00000,
1294c286 2040 (PTR) & fmt_seth_ops[0],
52a53d1f 2041 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2042 },
9c03036a
DE		 2043/* sll $dr,$sr */
2044 {
23cf992f 2045 { 1, 1, 1, 1 },
1294c286 2046 M32R_INSN_SLL, "sll", "sll",
2e6dfccc 2047 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2048 { 16, 16, 0xf0f0 }, 0x1040,
1294c286 2049 (PTR) & fmt_add_ops[0],
52a53d1f 2050 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 2051 },
9c03036a
DE		 2052/* sll3 $dr,$sr,$simm16 */
2053 {
23cf992f 2054 { 1, 1, 1, 1 },
1294c286 2055 M32R_INSN_SLL3, "sll3", "sll3",
2e6dfccc 2056 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 2057 { 32, 32, 0xf0f00000 }, 0x90c00000,
1294c286 2058 (PTR) & fmt_sll3_ops[0],
52a53d1f 2059 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 2060 },
2061/* slli $dr,$uimm5 */
2062 {
23cf992f 2063 { 1, 1, 1, 1 },
1294c286 2064 M32R_INSN_SLLI, "slli", "slli",
2e6dfccc 2065 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 2066 { 16, 16, 0xf0e0 }, 0x5040,
1294c286 2067 (PTR) & fmt_slli_ops[0],
52a53d1f 2068 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2069 },
2070/* sra $dr,$sr */
2071 {
23cf992f 2072 { 1, 1, 1, 1 },
1294c286 2073 M32R_INSN_SRA, "sra", "sra",
2e6dfccc 2074 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2075 { 16, 16, 0xf0f0 }, 0x1020,
1294c286 2076 (PTR) & fmt_add_ops[0],
52a53d1f 2077 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 2078 },
9c03036a
DE		 2079/* sra3 $dr,$sr,$simm16 */
2080 {
23cf992f 2081 { 1, 1, 1, 1 },
1294c286 2082 M32R_INSN_SRA3, "sra3", "sra3",
2e6dfccc 2083 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 2084 { 32, 32, 0xf0f00000 }, 0x90a00000,
1294c286 2085 (PTR) & fmt_sll3_ops[0],
52a53d1f 2086 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 2087 },
2088/* srai $dr,$uimm5 */
2089 {
23cf992f 2090 { 1, 1, 1, 1 },
1294c286 2091 M32R_INSN_SRAI, "srai", "srai",
2e6dfccc 2092 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 2093 { 16, 16, 0xf0e0 }, 0x5020,
1294c286 2094 (PTR) & fmt_slli_ops[0],
52a53d1f 2095 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2096 },
2097/* srl $dr,$sr */
2098 {
23cf992f 2099 { 1, 1, 1, 1 },
1294c286 2100 M32R_INSN_SRL, "srl", "srl",
2e6dfccc 2101 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2102 { 16, 16, 0xf0f0 }, 0x1000,
1294c286 2103 (PTR) & fmt_add_ops[0],
52a53d1f 2104 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
7c26196f 2105 },
9c03036a
DE		 2106/* srl3 $dr,$sr,$simm16 */
2107 {
23cf992f 2108 { 1, 1, 1, 1 },
1294c286 2109 M32R_INSN_SRL3, "srl3", "srl3",
2e6dfccc 2110 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
0bf55db8 2111 { 32, 32, 0xf0f00000 }, 0x90800000,
1294c286 2112 (PTR) & fmt_sll3_ops[0],
52a53d1f 2113 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a
DE		 2114 },
2115/* srli $dr,$uimm5 */
2116 {
23cf992f 2117 { 1, 1, 1, 1 },
1294c286 2118 M32R_INSN_SRLI, "srli", "srli",
2e6dfccc 2119 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
0bf55db8 2120 { 16, 16, 0xf0e0 }, 0x5000,
1294c286 2121 (PTR) & fmt_slli_ops[0],
52a53d1f 2122 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2123 },
2124/* st $src1,@$src2 */
2125 {
23cf992f 2126 { 1, 1, 1, 1 },
1294c286 2127 M32R_INSN_ST, "st", "st",
2e6dfccc 2128 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2129 { 16, 16, 0xf0f0 }, 0x2040,
1294c286 2130 (PTR) & fmt_st_ops[0],
52a53d1f 2131 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2132 },
9c03036a
DE		 2133/* st $src1,@($slo16,$src2) */
2134 {
23cf992f 2135 { 1, 1, 1, 1 },
1294c286 2136 M32R_INSN_ST_D, "st-d", "st",
2e6dfccc 2137 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2138 { 32, 32, 0xf0f00000 }, 0xa0400000,
1294c286 2139 (PTR) & fmt_st_d_ops[0],
52a53d1f 2140 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2141 },
9c03036a
DE		 2142/* stb $src1,@$src2 */
2143 {
23cf992f 2144 { 1, 1, 1, 1 },
1294c286 2145 M32R_INSN_STB, "stb", "stb",
2e6dfccc 2146 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2147 { 16, 16, 0xf0f0 }, 0x2000,
1294c286 2148 (PTR) & fmt_stb_ops[0],
52a53d1f 2149 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2150 },
1294c286 2151/* stb $src1,@($slo16,$src2) */
9c03036a 2152 {
23cf992f 2153 { 1, 1, 1, 1 },
1294c286 2154 M32R_INSN_STB_D, "stb-d", "stb",
2e6dfccc 2155 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2156 { 32, 32, 0xf0f00000 }, 0xa0000000,
1294c286 2157 (PTR) & fmt_stb_d_ops[0],
52a53d1f 2158 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2159 },
9c03036a
DE		 2160/* sth $src1,@$src2 */
2161 {
23cf992f 2162 { 1, 1, 1, 1 },
1294c286 2163 M32R_INSN_STH, "sth", "sth",
2e6dfccc 2164 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2165 { 16, 16, 0xf0f0 }, 0x2020,
1294c286 2166 (PTR) & fmt_sth_ops[0],
52a53d1f 2167 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2168 },
9c03036a
DE		 2169/* sth $src1,@($slo16,$src2) */
2170 {
23cf992f 2171 { 1, 1, 1, 1 },
1294c286 2172 M32R_INSN_STH_D, "sth-d", "sth",
2e6dfccc 2173 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
0bf55db8 2174 { 32, 32, 0xf0f00000 }, 0xa0200000,
1294c286 2175 (PTR) & fmt_sth_d_ops[0],
52a53d1f 2176 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
9c03036a 2177 },
9c03036a
DE		 2178/* st $src1,@+$src2 */
2179 {
23cf992f 2180 { 1, 1, 1, 1 },
1294c286 2181 M32R_INSN_ST_PLUS, "st-plus", "st",
2e6dfccc 2182 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
0bf55db8 2183 { 16, 16, 0xf0f0 }, 0x2060,
1294c286 2184 (PTR) & fmt_st_plus_ops[0],
52a53d1f 2185 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2186 },
2187/* st $src1,@-$src2 */
2188 {
23cf992f 2189 { 1, 1, 1, 1 },
1294c286 2190 M32R_INSN_ST_MINUS, "st-minus", "st",
2e6dfccc 2191 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
0bf55db8 2192 { 16, 16, 0xf0f0 }, 0x2070,
1294c286 2193 (PTR) & fmt_st_plus_ops[0],
52a53d1f 2194 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a
DE		 2195 },
2196/* sub $dr,$sr */
2197 {
23cf992f 2198 { 1, 1, 1, 1 },
1294c286 2199 M32R_INSN_SUB, "sub", "sub",
2e6dfccc 2200 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2201 { 16, 16, 0xf0f0 }, 0x20,
1294c286 2202 (PTR) & fmt_add_ops[0],
52a53d1f 2203 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2204 },
2205/* subv $dr,$sr */
2206 {
23cf992f 2207 { 1, 1, 1, 1 },
1294c286 2208 M32R_INSN_SUBV, "subv", "subv",
2e6dfccc 2209 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2210 { 16, 16, 0xf0f0 }, 0x0,
1294c286 2211 (PTR) & fmt_addv_ops[0],
52a53d1f 2212 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
9c03036a
DE		 2213 },
2214/* subx $dr,$sr */
2215 {
23cf992f 2216 { 1, 1, 1, 1 },
1294c286 2217 M32R_INSN_SUBX, "subx", "subx",
2e6dfccc 2218 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
0bf55db8 2219 { 16, 16, 0xf0f0 }, 0x10,
1294c286 2220 (PTR) & fmt_addx_ops[0],
52a53d1f 2221 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
7c26196f 2222 },
a6cefe4f 2223/* trap $uimm4 */
7c26196f
DE		 2224 {
2225 { 1, 1, 1, 1 },
1294c286 2226 M32R_INSN_TRAP, "trap", "trap",
2e6dfccc 2227 { { MNEM, ' ', OP (UIMM4), 0 } },
0bf55db8 2228 { 16, 16, 0xfff0 }, 0x10f0,
1294c286 2229 (PTR) & fmt_trap_ops[0],
52a53d1f 2230 { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
9c03036a 2231 },
9c03036a
DE		 2232/* unlock $src1,@$src2 */
2233 {
23cf992f 2234 { 1, 1, 1, 1 },
1294c286 2235 M32R_INSN_UNLOCK, "unlock", "unlock",
2e6dfccc 2236 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
0bf55db8 2237 { 16, 16, 0xf0f0 }, 0x2050,
1294c286 2238 (PTR) & fmt_unlock_ops[0],
52a53d1f 2239 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
9c03036a 2240 },
7c26196f 2241/* start-sanitize-m32rx */
b02643b5 2242/* satb $dr,$sr */
7c26196f
DE		 2243 {
2244 { 1, 1, 1, 1 },
1294c286 2245 M32R_INSN_SATB, "satb", "satb",
2e6dfccc 2246 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
d8ca5fae 2247 { 32, 32, 0xf0f0ffff }, 0x80600300,
1294c286 2248 (PTR) & fmt_satb_ops[0],
8d157f96 2249 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2250 },
2251/* end-sanitize-m32rx */
2252/* start-sanitize-m32rx */
b02643b5 2253/* sath $dr,$sr */
7c26196f
DE		 2254 {
2255 { 1, 1, 1, 1 },
1294c286 2256 M32R_INSN_SATH, "sath", "sath",
2e6dfccc 2257 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
b2ddf0c4 2258 { 32, 32, 0xf0f0ffff }, 0x80600200,
1294c286 2259 (PTR) & fmt_satb_ops[0],
8d157f96 2260 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2261 },
2262/* end-sanitize-m32rx */
2263/* start-sanitize-m32rx */
b02643b5 2264/* sat $dr,$sr */
7c26196f
DE		 2265 {
2266 { 1, 1, 1, 1 },
1294c286 2267 M32R_INSN_SAT, "sat", "sat",
2e6dfccc 2268 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
d8ca5fae 2269 { 32, 32, 0xf0f0ffff }, 0x80600000,
1294c286 2270 (PTR) & fmt_sat_ops[0],
fbc8134d 2271 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
7c26196f
DE		 2272 },
2273/* end-sanitize-m32rx */
2274/* start-sanitize-m32rx */
2275/* pcmpbz $src2 */
2276 {
2277 { 1, 1, 1, 1 },
1294c286 2278 M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
2e6dfccc 2279 { { MNEM, ' ', OP (SRC2), 0 } },
0bf55db8 2280 { 16, 16, 0xfff0 }, 0x370,
1294c286 2281 (PTR) & fmt_cmpz_ops[0],
c2009f4a 2282 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
7c26196f
DE		 2283 },
2284/* end-sanitize-m32rx */
2285/* start-sanitize-m32rx */
2286/* sadd */
2287 {
2288 { 1, 1, 1, 1 },
1294c286 2289 M32R_INSN_SADD, "sadd", "sadd",
2e6dfccc 2290 { { MNEM, 0 } },
0bf55db8 2291 { 16, 16, 0xffff }, 0x50e4,
1294c286 2292 (PTR) & fmt_sadd_ops[0],
8d157f96 2293 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
9c03036a 2294 },
7c26196f
DE		 2295/* end-sanitize-m32rx */
2296/* start-sanitize-m32rx */
2297/* macwu1 $src1,$src2 */
2298 {
2299 { 1, 1, 1, 1 },
1294c286 2300 M32R_INSN_MACWU1, "macwu1", "macwu1",
2e6dfccc 2301 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2302 { 16, 16, 0xf0f0 }, 0x50b0,
1294c286 2303 (PTR) & fmt_macwu1_ops[0],
8d157f96 2304 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2305 },
2306/* end-sanitize-m32rx */
2307/* start-sanitize-m32rx */
2308/* msblo $src1,$src2 */
2309 {
2310 { 1, 1, 1, 1 },
1294c286 2311 M32R_INSN_MSBLO, "msblo", "msblo",
2e6dfccc 2312 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2313 { 16, 16, 0xf0f0 }, 0x50d0,
1294c286 2314 (PTR) & fmt_machi_ops[0],
8d157f96 2315 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2316 },
2317/* end-sanitize-m32rx */
2318/* start-sanitize-m32rx */
2319/* mulwu1 $src1,$src2 */
2320 {
2321 { 1, 1, 1, 1 },
1294c286 2322 M32R_INSN_MULWU1, "mulwu1", "mulwu1",
2e6dfccc 2323 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2324 { 16, 16, 0xf0f0 }, 0x50a0,
1294c286 2325 (PTR) & fmt_mulwu1_ops[0],
8d157f96 2326 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2327 },
2328/* end-sanitize-m32rx */
2329/* start-sanitize-m32rx */
ab0bd049 2330/* maclh1 $src1,$src2 */
7c26196f
DE		 2331 {
2332 { 1, 1, 1, 1 },
1294c286 2333 M32R_INSN_MACLH1, "maclh1", "maclh1",
2e6dfccc 2334 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
0bf55db8 2335 { 16, 16, 0xf0f0 }, 0x50c0,
1294c286 2336 (PTR) & fmt_macwu1_ops[0],
8d157f96 2337 { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
7c26196f
DE		 2338 },
2339/* end-sanitize-m32rx */
2340/* start-sanitize-m32rx */
2341/* sc */
2342 {
2343 { 1, 1, 1, 1 },
1294c286 2344 M32R_INSN_SC, "sc", "sc",
2e6dfccc 2345 { { MNEM, 0 } },
0bf55db8 2346 { 16, 16, 0xffff }, 0x7401,
1294c286 2347 (PTR) & fmt_sc_ops[0],
52a53d1f 2348 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2349 },
2350/* end-sanitize-m32rx */
2351/* start-sanitize-m32rx */
2352/* snc */
2353 {
2354 { 1, 1, 1, 1 },
1294c286 2355 M32R_INSN_SNC, "snc", "snc",
2e6dfccc 2356 { { MNEM, 0 } },
0bf55db8 2357 { 16, 16, 0xffff }, 0x7501,
1294c286 2358 (PTR) & fmt_sc_ops[0],
52a53d1f 2359 { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
7c26196f
DE		 2360 },
2361/* end-sanitize-m32rx */
9c03036a
DE		 2362};
2363
23cf992f 2364#undef A
0bf55db8
DE		 2365#undef MNEM
2366#undef OP
23cf992f 2367
c2009f4a 2368static const CGEN_INSN_TABLE insn_table =
853713a7 2369{
9c03036a 2370 & m32r_cgen_insn_table_entries[0],
23cf992f 2371 sizeof (CGEN_INSN),
7c26196f 2372 MAX_INSNS,
1294c286
DE		 2373 NULL
2374};
2375
2376/* Each non-simple macro entry points to an array of expansion possibilities. */
2377
2378#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
2379#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
2380#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2381
2382/* The macro instruction table. */
2383
2384static const CGEN_INSN macro_insn_table_entries[] =
2385{
2386/* bc $disp8 */
2387 {
2388 { 1, 1, 1, 1 },
2389 -1, "bc8r", "bc",
2e6dfccc 2390 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2391 { 16, 16, 0xff00 }, 0x7c00,
2392 (PTR) 0,
52a53d1f 2393 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2394 },
2395/* bc $disp24 */
2396 {
2397 { 1, 1, 1, 1 },
2398 -1, "bc24r", "bc",
2e6dfccc 2399 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2400 { 32, 32, 0xff000000 }, 0xfc000000,
2401 (PTR) 0,
52a53d1f 2402 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2403 },
2404/* bl $disp8 */
2405 {
2406 { 1, 1, 1, 1 },
2407 -1, "bl8r", "bl",
2e6dfccc 2408 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2409 { 16, 16, 0xff00 }, 0x7e00,
2410 (PTR) 0,
52a53d1f 2411 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2412 },
2413/* bl $disp24 */
2414 {
2415 { 1, 1, 1, 1 },
2416 -1, "bl24r", "bl",
2e6dfccc 2417 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2418 { 32, 32, 0xff000000 }, 0xfe000000,
2419 (PTR) 0,
52a53d1f 2420 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2421 },
2422/* bcl $disp8 */
2423 {
2424 { 1, 1, 1, 1 },
2425 -1, "bcl8r", "bcl",
2e6dfccc 2426 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2427 { 16, 16, 0xff00 }, 0x7800,
2428 (PTR) 0,
52a53d1f 2429 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1294c286
DE		 2430 },
2431/* bcl $disp24 */
2432 {
2433 { 1, 1, 1, 1 },
2434 -1, "bcl24r", "bcl",
2e6dfccc 2435 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2436 { 32, 32, 0xff000000 }, 0xf8000000,
2437 (PTR) 0,
2438 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2439 },
2440/* bnc $disp8 */
2441 {
2442 { 1, 1, 1, 1 },
2443 -1, "bnc8r", "bnc",
2e6dfccc 2444 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2445 { 16, 16, 0xff00 }, 0x7d00,
2446 (PTR) 0,
52a53d1f 2447 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2448 },
2449/* bnc $disp24 */
2450 {
2451 { 1, 1, 1, 1 },
2452 -1, "bnc24r", "bnc",
2e6dfccc 2453 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2454 { 32, 32, 0xff000000 }, 0xfd000000,
2455 (PTR) 0,
52a53d1f 2456 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2457 },
2458/* bra $disp8 */
2459 {
2460 { 1, 1, 1, 1 },
2461 -1, "bra8r", "bra",
2e6dfccc 2462 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2463 { 16, 16, 0xff00 }, 0x7f00,
2464 (PTR) 0,
52a53d1f 2465 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2466 },
2467/* bra $disp24 */
2468 {
2469 { 1, 1, 1, 1 },
2470 -1, "bra24r", "bra",
2e6dfccc 2471 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2472 { 32, 32, 0xff000000 }, 0xff000000,
2473 (PTR) 0,
52a53d1f 2474 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2475 },
2476/* bncl $disp8 */
2477 {
2478 { 1, 1, 1, 1 },
2479 -1, "bncl8r", "bncl",
2e6dfccc 2480 { { MNEM, ' ', OP (DISP8), 0 } },
1294c286
DE		 2481 { 16, 16, 0xff00 }, 0x7900,
2482 (PTR) 0,
52a53d1f 2483 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1294c286
DE		 2484 },
2485/* bncl $disp24 */
2486 {
2487 { 1, 1, 1, 1 },
2488 -1, "bncl24r", "bncl",
2e6dfccc 2489 { { MNEM, ' ', OP (DISP24), 0 } },
1294c286
DE		 2490 { 32, 32, 0xff000000 }, 0xf9000000,
2491 (PTR) 0,
2492 { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
2493 },
2494/* ld $dr,@($sr) */
2495 {
2496 { 1, 1, 1, 1 },
2497 -1, "ld-2", "ld",
2e6dfccc 2498 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2499 { 16, 16, 0xf0f0 }, 0x20c0,
2500 (PTR) 0,
52a53d1f 2501 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2502 },
2503/* ld $dr,@($sr,$slo16) */
2504 {
2505 { 1, 1, 1, 1 },
2506 -1, "ld-d2", "ld",
2e6dfccc 2507 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2508 { 32, 32, 0xf0f00000 }, 0xa0c00000,
2509 (PTR) 0,
52a53d1f 2510 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2511 },
2512/* ldb $dr,@($sr) */
2513 {
2514 { 1, 1, 1, 1 },
2515 -1, "ldb-2", "ldb",
2e6dfccc 2516 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2517 { 16, 16, 0xf0f0 }, 0x2080,
2518 (PTR) 0,
52a53d1f 2519 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2520 },
2521/* ldb $dr,@($sr,$slo16) */
2522 {
2523 { 1, 1, 1, 1 },
2524 -1, "ldb-d2", "ldb",
2e6dfccc 2525 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2526 { 32, 32, 0xf0f00000 }, 0xa0800000,
2527 (PTR) 0,
52a53d1f 2528 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2529 },
2530/* ldh $dr,@($sr) */
2531 {
2532 { 1, 1, 1, 1 },
2533 -1, "ldh-2", "ldh",
2e6dfccc 2534 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2535 { 16, 16, 0xf0f0 }, 0x20a0,
2536 (PTR) 0,
52a53d1f 2537 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2538 },
2539/* ldh $dr,@($sr,$slo16) */
2540 {
2541 { 1, 1, 1, 1 },
2542 -1, "ldh-d2", "ldh",
2e6dfccc 2543 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2544 { 32, 32, 0xf0f00000 }, 0xa0a00000,
2545 (PTR) 0,
52a53d1f 2546 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2547 },
2548/* ldub $dr,@($sr) */
2549 {
2550 { 1, 1, 1, 1 },
2551 -1, "ldub-2", "ldub",
2e6dfccc 2552 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2553 { 16, 16, 0xf0f0 }, 0x2090,
2554 (PTR) 0,
52a53d1f 2555 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2556 },
2557/* ldub $dr,@($sr,$slo16) */
2558 {
2559 { 1, 1, 1, 1 },
2560 -1, "ldub-d2", "ldub",
2e6dfccc 2561 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2562 { 32, 32, 0xf0f00000 }, 0xa0900000,
2563 (PTR) 0,
52a53d1f 2564 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2565 },
2566/* lduh $dr,@($sr) */
2567 {
2568 { 1, 1, 1, 1 },
2569 -1, "lduh-2", "lduh",
2e6dfccc 2570 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1294c286
DE		 2571 { 16, 16, 0xf0f0 }, 0x20b0,
2572 (PTR) 0,
52a53d1f 2573 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2574 },
2575/* lduh $dr,@($sr,$slo16) */
2576 {
2577 { 1, 1, 1, 1 },
2578 -1, "lduh-d2", "lduh",
2e6dfccc 2579 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2580 { 32, 32, 0xf0f00000 }, 0xa0b00000,
2581 (PTR) 0,
52a53d1f 2582 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2583 },
2584/* pop $dr */
2585 {
2586 { 1, 1, 1, 1 },
2587 -1, "pop", "pop",
2e6dfccc 2588 { { MNEM, ' ', OP (DR), 0 } },
1294c286
DE		 2589 { 16, 16, 0xf0ff }, 0x20ef,
2590 (PTR) 0,
52a53d1f 2591 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2592 },
2593/* ldi $dr,$simm8 */
2594 {
2595 { 1, 1, 1, 1 },
2596 -1, "ldi8a", "ldi",
2e6dfccc 2597 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1294c286
DE		 2598 { 16, 16, 0xf000 }, 0x6000,
2599 (PTR) 0,
52a53d1f 2600 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
1294c286
DE		 2601 },
2602/* ldi $dr,$hash$slo16 */
2603 {
2604 { 1, 1, 1, 1 },
2605 -1, "ldi16a", "ldi",
2e6dfccc 2606 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1294c286
DE		 2607 { 32, 32, 0xf0ff0000 }, 0x90f00000,
2608 (PTR) 0,
52a53d1f 2609 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2610 },
2611/* rac $accd */
2612 {
2613 { 1, 1, 1, 1 },
2614 -1, "rac-d", "rac",
2e6dfccc 2615 { { MNEM, ' ', OP (ACCD), 0 } },
1294c286
DE		 2616 { 16, 16, 0xf3ff }, 0x5090,
2617 (PTR) 0,
2618 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2619 },
2620/* rac $accd,$accs */
2621 {
2622 { 1, 1, 1, 1 },
2623 -1, "rac-ds", "rac",
2e6dfccc 2624 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1294c286
DE		 2625 { 16, 16, 0xf3f3 }, 0x5090,
2626 (PTR) 0,
2627 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2628 },
2629/* rach $accd */
2630 {
2631 { 1, 1, 1, 1 },
2632 -1, "rach-d", "rach",
2e6dfccc 2633 { { MNEM, ' ', OP (ACCD), 0 } },
1294c286
DE		 2634 { 16, 16, 0xf3ff }, 0x5080,
2635 (PTR) 0,
2636 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2637 },
2638/* rach $accd,$accs */
2639 {
2640 { 1, 1, 1, 1 },
2641 -1, "rach-ds", "rach",
2e6dfccc 2642 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1294c286
DE		 2643 { 16, 16, 0xf3f3 }, 0x5080,
2644 (PTR) 0,
2645 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
2646 },
2647/* st $src1,@($src2) */
2648 {
2649 { 1, 1, 1, 1 },
2650 -1, "st-2", "st",
2e6dfccc 2651 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286
DE		 2652 { 16, 16, 0xf0f0 }, 0x2040,
2653 (PTR) 0,
52a53d1f 2654 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2655 },
2656/* st $src1,@($src2,$slo16) */
2657 {
2658 { 1, 1, 1, 1 },
2659 -1, "st-d2", "st",
2e6dfccc 2660 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2661 { 32, 32, 0xf0f00000 }, 0xa0400000,
2662 (PTR) 0,
52a53d1f 2663 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2664 },
2665/* stb $src1,@($src2) */
2666 {
2667 { 1, 1, 1, 1 },
2668 -1, "stb-2", "stb",
2e6dfccc 2669 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286
DE		 2670 { 16, 16, 0xf0f0 }, 0x2000,
2671 (PTR) 0,
52a53d1f 2672 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2673 },
2674/* stb $src1,@($src2,$slo16) */
2675 {
2676 { 1, 1, 1, 1 },
2677 -1, "stb-d2", "stb",
2e6dfccc 2678 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2679 { 32, 32, 0xf0f00000 }, 0xa0000000,
2680 (PTR) 0,
52a53d1f 2681 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2682 },
2683/* sth $src1,@($src2) */
2684 {
2685 { 1, 1, 1, 1 },
2686 -1, "sth-2", "sth",
2e6dfccc 2687 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1294c286
DE		 2688 { 16, 16, 0xf0f0 }, 0x2020,
2689 (PTR) 0,
52a53d1f 2690 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1294c286
DE		 2691 },
2692/* sth $src1,@($src2,$slo16) */
2693 {
2694 { 1, 1, 1, 1 },
2695 -1, "sth-d2", "sth",
2e6dfccc 2696 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1294c286
DE		 2697 { 32, 32, 0xf0f00000 }, 0xa0200000,
2698 (PTR) 0,
52a53d1f 2699 { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2700 },
2701/* push $src1 */
2702 {
2703 { 1, 1, 1, 1 },
2704 -1, "push", "push",
2e6dfccc 2705 { { MNEM, ' ', OP (SRC1), 0 } },
1294c286
DE		 2706 { 16, 16, 0xf0ff }, 0x207f,
2707 (PTR) 0,
52a53d1f 2708 { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1294c286
DE		 2709 },
2710};
2711
2712#undef A
2713#undef MNEM
2714#undef OP
2715
c2009f4a 2716static const CGEN_INSN_TABLE macro_insn_table =
1294c286
DE		 2717{
2718 & macro_insn_table_entries[0],
2719 sizeof (CGEN_INSN),
2720 (sizeof (macro_insn_table_entries) /
2721 sizeof (macro_insn_table_entries[0])),
2722 NULL
9c03036a
DE		 2723};
2724
c2009f4a
DE		 2725static void
2726init_tables ()
2727{
2728}
1294c286
DE		 2729
2730/* Return non-zero if INSN is to be added to the hash table.
2731 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
2732
2733static int
2734asm_hash_insn_p (insn)
2735 const CGEN_INSN * insn;
2736{
2737 return CGEN_ASM_HASH_P (insn);
2738}
2739
2740static int
2741dis_hash_insn_p (insn)
2742 const CGEN_INSN * insn;
2743{
2744 /* If building the hash table and the NO-DIS attribute is present,
2745 ignore. */
2746 if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
2747 return 0;
2748 return CGEN_DIS_HASH_P (insn);
2749}
2750
2751/* The result is the hash value of the insn.
2752 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
9c03036a 2753
1294c286
DE		 2754static unsigned int
2755asm_hash_insn (mnem)
2756 const char * mnem;
9c03036a 2757{
1294c286 2758 return CGEN_ASM_HASH (mnem);
9c03036a
DE		 2759}
2760
52a53d1f
DE		 2761/* BUF is a pointer to the insn's bytes in target order.
2762 VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
2763 host order. */
2764
1294c286
DE		 2765static unsigned int
2766dis_hash_insn (buf, value)
5d07b6cf 2767 const char * buf;
9c03036a
DE		 2768 unsigned long value;
2769{
2770 return CGEN_DIS_HASH (buf, value);
2771}
2772
c2009f4a
DE		 2773/* Initialize an opcode table and return a descriptor.
2774 It's much like opening a file, and must be the first function called. */
2775
2776CGEN_OPCODE_DESC
2777m32r_cgen_opcode_open (mach, endian)
2778 int mach;
2779 enum cgen_endian endian;
5d07b6cf 2780{
c2009f4a
DE		 2781 CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
2782 static int init_p;
2783
2784 if (! init_p)
2785 {
2786 init_tables ();
2787 init_p = 1;
2788 }
2789
2790 memset (table, 0, sizeof (*table));
2791
2792 CGEN_OPCODE_MACH (table) = mach;
2793 CGEN_OPCODE_ENDIAN (table) = endian;
52a53d1f
DE		 2794 /* FIXME: for the sparc case we can determine insn-endianness statically.
2795 The worry here is where both data and insn endian can be independently
2796 chosen, in which case this function will need another argument.
2797 Actually, will want to allow for more arguments in the future anyway. */
2798 CGEN_OPCODE_INSN_ENDIAN (table) = endian;
c2009f4a
DE		 2799
2800 CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
2801
2802 CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
2803
2804 * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
2805
2806 * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
2807
2808 CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
2809 CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
2810 CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
2811
2812 CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
2813 CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
2814 CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
2815
2816 return (CGEN_OPCODE_DESC) table;
2817}
2818
2819/* Close an opcode table. */
9c03036a
DE		 2820
2821void
c2009f4a
DE		 2822m32r_cgen_opcode_close (desc)
2823 CGEN_OPCODE_DESC desc;
9c03036a 2824{
c2009f4a 2825 free (desc);
9c03036a
DE		 2826}
2827
fbc8134d
DE		 2828/* Getting values from cgen_fields is handled by a collection of functions.
2829 They are distinguished by the type of the VALUE argument they return.
2830 TODO: floating point, inlining support, remove cases where result type
2831 not appropriate. */
9c03036a 2832
fbc8134d
DE		 2833int
2834m32r_cgen_get_int_operand (opindex, fields)
9c03036a 2835 int opindex;
fbc8134d 2836 const CGEN_FIELDS * fields;
9c03036a 2837{
fbc8134d
DE		 2838 int value;
2839
9c03036a
DE		 2840 switch (opindex)
2841 {
23cf992f 2842 case M32R_OPERAND_SR :
fbc8134d 2843 value = fields->f_r2;
9c03036a 2844 break;
23cf992f 2845 case M32R_OPERAND_DR :
fbc8134d 2846 value = fields->f_r1;
9c03036a 2847 break;
23cf992f 2848 case M32R_OPERAND_SRC1 :
fbc8134d 2849 value = fields->f_r1;
9c03036a 2850 break;
23cf992f 2851 case M32R_OPERAND_SRC2 :
fbc8134d 2852 value = fields->f_r2;
9c03036a 2853 break;
23cf992f 2854 case M32R_OPERAND_SCR :
fbc8134d 2855 value = fields->f_r2;
9c03036a 2856 break;
23cf992f 2857 case M32R_OPERAND_DCR :
fbc8134d 2858 value = fields->f_r1;
9c03036a 2859 break;
23cf992f 2860 case M32R_OPERAND_SIMM8 :
fbc8134d 2861 value = fields->f_simm8;
9c03036a 2862 break;
23cf992f 2863 case M32R_OPERAND_SIMM16 :
fbc8134d 2864 value = fields->f_simm16;
9c03036a 2865 break;
23cf992f 2866 case M32R_OPERAND_UIMM4 :
fbc8134d 2867 value = fields->f_uimm4;
9c03036a 2868 break;
23cf992f 2869 case M32R_OPERAND_UIMM5 :
fbc8134d 2870 value = fields->f_uimm5;
9c03036a 2871 break;
23cf992f 2872 case M32R_OPERAND_UIMM16 :
fbc8134d 2873 value = fields->f_uimm16;
23cf992f 2874 break;
ab0bd049
DE		 2875/* start-sanitize-m32rx */
2876 case M32R_OPERAND_IMM1 :
fbc8134d 2877 value = fields->f_imm1;
ab0bd049
DE		 2878 break;
2879/* end-sanitize-m32rx */
2880/* start-sanitize-m32rx */
2881 case M32R_OPERAND_ACCD :
fbc8134d 2882 value = fields->f_accd;
ab0bd049
DE		 2883 break;
2884/* end-sanitize-m32rx */
7c26196f
DE		 2885/* start-sanitize-m32rx */
2886 case M32R_OPERAND_ACCS :
fbc8134d 2887 value = fields->f_accs;
7c26196f
DE		 2888 break;
2889/* end-sanitize-m32rx */
2890/* start-sanitize-m32rx */
2891 case M32R_OPERAND_ACC :
fbc8134d 2892 value = fields->f_acc;
7c26196f
DE		 2893 break;
2894/* end-sanitize-m32rx */
a6cefe4f 2895 case M32R_OPERAND_HASH :
fbc8134d 2896 value = fields->f_nil;
a6cefe4f 2897 break;
23cf992f 2898 case M32R_OPERAND_HI16 :
fbc8134d 2899 value = fields->f_hi16;
9c03036a 2900 break;
23cf992f 2901 case M32R_OPERAND_SLO16 :
fbc8134d 2902 value = fields->f_simm16;
9c03036a 2903 break;
23cf992f 2904 case M32R_OPERAND_ULO16 :
fbc8134d 2905 value = fields->f_uimm16;
9c03036a 2906 break;
23cf992f 2907 case M32R_OPERAND_UIMM24 :
fbc8134d 2908 value = fields->f_uimm24;
9c03036a 2909 break;
23cf992f 2910 case M32R_OPERAND_DISP8 :
fbc8134d 2911 value = fields->f_disp8;
9c03036a 2912 break;
23cf992f 2913 case M32R_OPERAND_DISP16 :
fbc8134d 2914 value = fields->f_disp16;
9c03036a 2915 break;
23cf992f 2916 case M32R_OPERAND_DISP24 :
fbc8134d 2917 value = fields->f_disp24;
9c03036a
DE		 2918 break;
2919
2920 default :
fbc8134d
DE		 2921 /* xgettext:c-format */
2922 fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
9c03036a
DE		 2923 opindex);
2924 abort ();
2925 }
9c03036a 2926
fbc8134d
DE		 2927 return value;
2928}
9c03036a 2929
fbc8134d
DE		 2930bfd_vma
2931m32r_cgen_get_vma_operand (opindex, fields)
5d07b6cf 2932 int opindex;
853713a7 2933 const CGEN_FIELDS * fields;
9c03036a 2934{
fbc8134d 2935 bfd_vma value;
9c03036a
DE		 2936
2937 switch (opindex)
2938 {
23cf992f 2939 case M32R_OPERAND_SR :
9c03036a
DE		 2940 value = fields->f_r2;
2941 break;
23cf992f 2942 case M32R_OPERAND_DR :
9c03036a
DE		 2943 value = fields->f_r1;
2944 break;
23cf992f 2945 case M32R_OPERAND_SRC1 :
9c03036a
DE		 2946 value = fields->f_r1;
2947 break;
23cf992f 2948 case M32R_OPERAND_SRC2 :
9c03036a
DE		 2949 value = fields->f_r2;
2950 break;
23cf992f 2951 case M32R_OPERAND_SCR :
9c03036a
DE		 2952 value = fields->f_r2;
2953 break;
23cf992f 2954 case M32R_OPERAND_DCR :
9c03036a
DE		 2955 value = fields->f_r1;
2956 break;
23cf992f 2957 case M32R_OPERAND_SIMM8 :
9c03036a
DE		 2958 value = fields->f_simm8;
2959 break;
23cf992f 2960 case M32R_OPERAND_SIMM16 :
9c03036a
DE		 2961 value = fields->f_simm16;
2962 break;
23cf992f 2963 case M32R_OPERAND_UIMM4 :
9c03036a
DE		 2964 value = fields->f_uimm4;
2965 break;
23cf992f 2966 case M32R_OPERAND_UIMM5 :
9c03036a
DE		 2967 value = fields->f_uimm5;
2968 break;
23cf992f 2969 case M32R_OPERAND_UIMM16 :
9c03036a
DE		 2970 value = fields->f_uimm16;
2971 break;
ab0bd049
DE		 2972/* start-sanitize-m32rx */
2973 case M32R_OPERAND_IMM1 :
2974 value = fields->f_imm1;
2975 break;
2976/* end-sanitize-m32rx */
2977/* start-sanitize-m32rx */
2978 case M32R_OPERAND_ACCD :
2979 value = fields->f_accd;
2980 break;
2981/* end-sanitize-m32rx */
7c26196f
DE		 2982/* start-sanitize-m32rx */
2983 case M32R_OPERAND_ACCS :
2984 value = fields->f_accs;
2985 break;
2986/* end-sanitize-m32rx */
2987/* start-sanitize-m32rx */
2988 case M32R_OPERAND_ACC :
2989 value = fields->f_acc;
2990 break;
2991/* end-sanitize-m32rx */
a6cefe4f
DE		 2992 case M32R_OPERAND_HASH :
2993 value = fields->f_nil;
2994 break;
23cf992f 2995 case M32R_OPERAND_HI16 :
9c03036a
DE		 2996 value = fields->f_hi16;
2997 break;
23cf992f 2998 case M32R_OPERAND_SLO16 :
9c03036a
DE		 2999 value = fields->f_simm16;
3000 break;
23cf992f 3001 case M32R_OPERAND_ULO16 :
9c03036a
DE		 3002 value = fields->f_uimm16;
3003 break;
23cf992f 3004 case M32R_OPERAND_UIMM24 :
9c03036a
DE		 3005 value = fields->f_uimm24;
3006 break;
23cf992f 3007 case M32R_OPERAND_DISP8 :
9c03036a
DE		 3008 value = fields->f_disp8;
3009 break;
23cf992f 3010 case M32R_OPERAND_DISP16 :
9c03036a
DE		 3011 value = fields->f_disp16;
3012 break;
23cf992f 3013 case M32R_OPERAND_DISP24 :
9c03036a
DE		 3014 value = fields->f_disp24;
3015 break;
3016
3017 default :
fbc8134d
DE		 3018 /* xgettext:c-format */
3019 fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
9c03036a
DE		 3020 opindex);
3021 abort ();
3022 }
3023
3024 return value;
3025}
3026
fbc8134d
DE		 3027/* Stuffing values in cgen_fields is handled by a collection of functions.
3028 They are distinguished by the type of the VALUE argument they accept.
3029 TODO: floating point, inlining support, remove cases where argument type
3030 not appropriate. */
3031
3032void
3033m32r_cgen_set_int_operand (opindex, fields, value)
3034 int opindex;
3035 CGEN_FIELDS * fields;
3036 int value;
3037{
3038 switch (opindex)
3039 {
3040 case M32R_OPERAND_SR :
3041 fields->f_r2 = value;
3042 break;
3043 case M32R_OPERAND_DR :
3044 fields->f_r1 = value;
3045 break;
3046 case M32R_OPERAND_SRC1 :
3047 fields->f_r1 = value;
3048 break;
3049 case M32R_OPERAND_SRC2 :
3050 fields->f_r2 = value;
3051 break;
3052 case M32R_OPERAND_SCR :
3053 fields->f_r2 = value;
3054 break;
3055 case M32R_OPERAND_DCR :
3056 fields->f_r1 = value;
3057 break;
3058 case M32R_OPERAND_SIMM8 :
3059 fields->f_simm8 = value;
3060 break;
3061 case M32R_OPERAND_SIMM16 :
3062 fields->f_simm16 = value;
3063 break;
3064 case M32R_OPERAND_UIMM4 :
3065 fields->f_uimm4 = value;
3066 break;
3067 case M32R_OPERAND_UIMM5 :
3068 fields->f_uimm5 = value;
3069 break;
3070 case M32R_OPERAND_UIMM16 :
3071 fields->f_uimm16 = value;
3072 break;
3073/* start-sanitize-m32rx */
3074 case M32R_OPERAND_IMM1 :
3075 fields->f_imm1 = value;
3076 break;
3077/* end-sanitize-m32rx */
3078/* start-sanitize-m32rx */
3079 case M32R_OPERAND_ACCD :
3080 fields->f_accd = value;
3081 break;
3082/* end-sanitize-m32rx */
3083/* start-sanitize-m32rx */
3084 case M32R_OPERAND_ACCS :
3085 fields->f_accs = value;
3086 break;
3087/* end-sanitize-m32rx */
3088/* start-sanitize-m32rx */
3089 case M32R_OPERAND_ACC :
3090 fields->f_acc = value;
3091 break;
3092/* end-sanitize-m32rx */
3093 case M32R_OPERAND_HASH :
3094 fields->f_nil = value;
3095 break;
3096 case M32R_OPERAND_HI16 :
3097 fields->f_hi16 = value;
3098 break;
3099 case M32R_OPERAND_SLO16 :
3100 fields->f_simm16 = value;
3101 break;
3102 case M32R_OPERAND_ULO16 :
3103 fields->f_uimm16 = value;
3104 break;
3105 case M32R_OPERAND_UIMM24 :
3106 fields->f_uimm24 = value;
3107 break;
3108 case M32R_OPERAND_DISP8 :
3109 fields->f_disp8 = value;
3110 break;
3111 case M32R_OPERAND_DISP16 :
3112 fields->f_disp16 = value;
3113 break;
3114 case M32R_OPERAND_DISP24 :
3115 fields->f_disp24 = value;
3116 break;
3117
3118 default :
3119 /* xgettext:c-format */
3120 fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3121 opindex);
3122 abort ();
3123 }
3124}
3125
3126void
3127m32r_cgen_set_vma_operand (opindex, fields, value)
3128 int opindex;
3129 CGEN_FIELDS * fields;
3130 bfd_vma value;
3131{
3132 switch (opindex)
3133 {
3134 case M32R_OPERAND_SR :
3135 fields->f_r2 = value;
3136 break;
3137 case M32R_OPERAND_DR :
3138 fields->f_r1 = value;
3139 break;
3140 case M32R_OPERAND_SRC1 :
3141 fields->f_r1 = value;
3142 break;
3143 case M32R_OPERAND_SRC2 :
3144 fields->f_r2 = value;
3145 break;
3146 case M32R_OPERAND_SCR :
3147 fields->f_r2 = value;
3148 break;
3149 case M32R_OPERAND_DCR :
3150 fields->f_r1 = value;
3151 break;
3152 case M32R_OPERAND_SIMM8 :
3153 fields->f_simm8 = value;
3154 break;
3155 case M32R_OPERAND_SIMM16 :
3156 fields->f_simm16 = value;
3157 break;
3158 case M32R_OPERAND_UIMM4 :
3159 fields->f_uimm4 = value;
3160 break;
3161 case M32R_OPERAND_UIMM5 :
3162 fields->f_uimm5 = value;
3163 break;
3164 case M32R_OPERAND_UIMM16 :
3165 fields->f_uimm16 = value;
3166 break;
3167/* start-sanitize-m32rx */
3168 case M32R_OPERAND_IMM1 :
3169 fields->f_imm1 = value;
3170 break;
3171/* end-sanitize-m32rx */
3172/* start-sanitize-m32rx */
3173 case M32R_OPERAND_ACCD :
3174 fields->f_accd = value;
3175 break;
3176/* end-sanitize-m32rx */
3177/* start-sanitize-m32rx */
3178 case M32R_OPERAND_ACCS :
3179 fields->f_accs = value;
3180 break;
3181/* end-sanitize-m32rx */
3182/* start-sanitize-m32rx */
3183 case M32R_OPERAND_ACC :
3184 fields->f_acc = value;
3185 break;
3186/* end-sanitize-m32rx */
3187 case M32R_OPERAND_HASH :
3188 fields->f_nil = value;
3189 break;
3190 case M32R_OPERAND_HI16 :
3191 fields->f_hi16 = value;
3192 break;
3193 case M32R_OPERAND_SLO16 :
3194 fields->f_simm16 = value;
3195 break;
3196 case M32R_OPERAND_ULO16 :
3197 fields->f_uimm16 = value;
3198 break;
3199 case M32R_OPERAND_UIMM24 :
3200 fields->f_uimm24 = value;
3201 break;
3202 case M32R_OPERAND_DISP8 :
3203 fields->f_disp8 = value;
3204 break;
3205 case M32R_OPERAND_DISP16 :
3206 fields->f_disp16 = value;
3207 break;
3208 case M32R_OPERAND_DISP24 :
3209 fields->f_disp24 = value;
3210 break;
3211
3212 default :
3213 /* xgettext:c-format */
3214 fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3215 opindex);
3216 abort ();
3217 }
3218}
3219
Empty description
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