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sim: constify arg to sim_do_command
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df1756f4 1/* Simulator for Atmel's AVR core.
ecd75fc8 2 Copyright (C) 2009-2014 Free Software Foundation, Inc.
df1756f4
TG		 3 Written by Tristan Gingold, AdaCore.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "config.h"
21
22#ifdef HAVE_STRING_H
23#include <string.h>
24#endif
25#include "bfd.h"
26#include "gdb/callback.h"
27#include "gdb/signals.h"
28#include "libiberty.h"
29#include "gdb/remote-sim.h"
30#include "dis-asm.h"
31#include "sim-utils.h"
32
33/* As AVR is a 8/16 bits processor, define handy types. */
34typedef unsigned short int word;
35typedef signed short int sword;
36typedef unsigned char byte;
37typedef signed char sbyte;
38
39/* Debug flag to display instructions and registers. */
40static int tracing = 0;
41static int lock_step = 0;
42static int verbose;
43
44/* The only real register. */
45static unsigned int pc;
46
47/* We update a cycle counter. */
48static unsigned int cycles = 0;
49
50/* If true, the pc needs more than 2 bytes. */
51static int avr_pc22;
52
53static struct bfd *cur_bfd;
54
55static enum sim_stop cpu_exception;
56static int cpu_signal;
57
58static SIM_OPEN_KIND sim_kind;
59static char *myname;
60static host_callback *callback;
61
62/* Max size of I space (which is always flash on avr). */
63#define MAX_AVR_FLASH (128 * 1024)
64#define PC_MASK (MAX_AVR_FLASH - 1)
65
66/* Mac size of D space. */
67#define MAX_AVR_SRAM (64 * 1024)
68#define SRAM_MASK (MAX_AVR_SRAM - 1)
69
70/* D space offset in ELF file. */
71#define SRAM_VADDR 0x800000
72
73/* Simulator specific ports. */
74#define STDIO_PORT 0x52
75#define EXIT_PORT 0x4F
76#define ABORT_PORT 0x49
77
78/* GDB defined register numbers. */
79#define AVR_SREG_REGNUM 32
80#define AVR_SP_REGNUM 33
81#define AVR_PC_REGNUM 34
82
83/* Memory mapped registers. */
84#define SREG 0x5F
85#define REG_SP 0x5D
86#define EIND 0x5C
87#define RAMPZ 0x5B
88
89#define REGX 0x1a
90#define REGY 0x1c
91#define REGZ 0x1e
92#define REGZ_LO 0x1e
93#define REGZ_HI 0x1f
94
95/* Sreg (status) bits. */
96#define SREG_I 0x80
97#define SREG_T 0x40
98#define SREG_H 0x20
99#define SREG_S 0x10
100#define SREG_V 0x08
101#define SREG_N 0x04
102#define SREG_Z 0x02
103#define SREG_C 0x01
104
105/* In order to speed up emulation we use a simple approach:
106 a code is associated with each instruction. The pre-decoding occurs
107 usually once when the instruction is first seen.
108 This works well because I&D spaces are separated.
109
110 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
111*/
112enum avr_opcode
113 {
114 /* Opcode not yet decoded. */
115 OP_unknown,
116 OP_bad,
117
118 OP_nop,
119
120 OP_rjmp,
121 OP_rcall,
122 OP_ret,
123 OP_reti,
124
125 OP_break,
126
127 OP_brbs,
128 OP_brbc,
129
130 OP_bset,
131 OP_bclr,
132
133 OP_bld,
134 OP_bst,
135
136 OP_sbrc,
137 OP_sbrs,
138
139 OP_eor,
140 OP_and,
141 OP_andi,
142 OP_or,
143 OP_ori,
144 OP_com,
145 OP_swap,
146 OP_neg,
147
148 OP_out,
149 OP_in,
150 OP_cbi,
151 OP_sbi,
152
153 OP_sbic,
154 OP_sbis,
155
156 OP_ldi,
157 OP_cpse,
158 OP_cp,
159 OP_cpi,
160 OP_cpc,
161 OP_sub,
162 OP_sbc,
163 OP_sbiw,
164 OP_adiw,
165 OP_add,
166 OP_adc,
167 OP_subi,
168 OP_sbci,
169 OP_inc,
170 OP_dec,
171 OP_lsr,
172 OP_ror,
173 OP_asr,
174
175 OP_mul,
176 OP_muls,
177 OP_mulsu,
178 OP_fmul,
179 OP_fmuls,
180 OP_fmulsu,
181
182 OP_mov,
183 OP_movw,
184
185 OP_push,
186 OP_pop,
187
188 OP_st_X,
189 OP_st_dec_X,
190 OP_st_X_inc,
191 OP_st_Y_inc,
192 OP_st_dec_Y,
193 OP_st_Z_inc,
194 OP_st_dec_Z,
195 OP_std_Y,
196 OP_std_Z,
197 OP_ldd_Y,
198 OP_ldd_Z,
199 OP_ld_Z_inc,
200 OP_ld_dec_Z,
201 OP_ld_Y_inc,
202 OP_ld_dec_Y,
203 OP_ld_X,
204 OP_ld_X_inc,
205 OP_ld_dec_X,
206
207 OP_lpm,
208 OP_lpm_Z,
209 OP_lpm_inc_Z,
210 OP_elpm,
211 OP_elpm_Z,
212 OP_elpm_inc_Z,
213
214 OP_ijmp,
215 OP_icall,
216
217 OP_eijmp,
218 OP_eicall,
219
220 /* 2 words opcodes. */
221#define OP_2words OP_jmp
222 OP_jmp,
223 OP_call,
224 OP_sts,
225 OP_lds
226 };
227
228struct avr_insn_cell
229{
230 /* The insn (16 bits). */
231 word op;
232
233 /* Pre-decoding code. */
234 enum avr_opcode code : 8;
235 /* One byte of additional information. */
236 byte r;
237};
238
239/* I&D memories. */
240static struct avr_insn_cell flash[MAX_AVR_FLASH];
241static byte sram[MAX_AVR_SRAM];
242
243void
244sim_size (int s)
245{
246}
247
248/* Sign extend a value. */
249static int sign_ext (word val, int nb_bits)
250{
251 if (val & (1 << (nb_bits - 1)))
252 return val | (-1 << nb_bits);
253 return val;
254}
255
256/* Insn field extractors. */
257
258/* Extract xxxx_xxxRx_xxxx_RRRR. */
259static inline byte get_r (word op)
260{
261 return (op & 0xf) | ((op >> 5) & 0x10);
262}
263
264/* Extract xxxx_xxxxx_xxxx_RRRR. */
265static inline byte get_r16 (word op)
266{
267 return 16 + (op & 0xf);
268}
269
270/* Extract xxxx_xxxxx_xxxx_xRRR. */
271static inline byte get_r16_23 (word op)
272{
273 return 16 + (op & 0x7);
274}
275
276/* Extract xxxx_xxxD_DDDD_xxxx. */
277static inline byte get_d (word op)
278{
279 return (op >> 4) & 0x1f;
280}
281
282/* Extract xxxx_xxxx_DDDD_xxxx. */
283static inline byte get_d16 (word op)
284{
285 return 16 + ((op >> 4) & 0x0f);
286}
287
288/* Extract xxxx_xxxx_xDDD_xxxx. */
289static inline byte get_d16_23 (word op)
290{
291 return 16 + ((op >> 4) & 0x07);
292}
293
294/* Extract xxxx_xAAx_xxxx_AAAA. */
295static inline byte get_A (word op)
296{
297 return (op & 0x0f) | ((op & 0x600) >> 5);
298}
299
300/* Extract xxxx_xxxx_AAAA_Axxx. */
301static inline byte get_biA (word op)
302{
303 return (op >> 3) & 0x1f;
304}
305
306/* Extract xxxx_KKKK_xxxx_KKKK. */
307static inline byte get_K (word op)
308{
309 return (op & 0xf) | ((op & 0xf00) >> 4);
310}
311
312/* Extract xxxx_xxKK_KKKK_Kxxx. */
313static inline int get_k (word op)
314{
315 return sign_ext ((op & 0x3f8) >> 3, 7);
316}
317
318/* Extract xxxx_xxxx_xxDD_xxxx. */
319static inline byte get_d24 (word op)
320{
321 return 24 + ((op >> 3) & 6);
322}
323
324/* Extract xxxx_xxxx_KKxx_KKKK. */
325static inline byte get_k6 (word op)
326{
327 return (op & 0xf) | ((op >> 2) & 0x30);
328}
329
330/* Extract xxQx_QQxx_xxxx_xQQQ. */
331static inline byte get_q (word op)
332{
333 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20);
334}
335
336/* Extract xxxx_xxxx_xxxx_xBBB. */
337static inline byte get_b (word op)
338{
339 return (op & 7);
340}
341
342/* AVR is little endian. */
343static inline word
344read_word (unsigned int addr)
345{
346 return sram[addr] | (sram[addr + 1] << 8);
347}
348
349static inline void
350write_word (unsigned int addr, word w)
351{
352 sram[addr] = w;
353 sram[addr + 1] = w >> 8;
354}
355
356static inline word
357read_word_post_inc (unsigned int addr)
358{
359 word v = read_word (addr);
360 write_word (addr, v + 1);
361 return v;
362}
363
364static inline word
365read_word_pre_dec (unsigned int addr)
366{
367 word v = read_word (addr) - 1;
368 write_word (addr, v);
369 return v;
370}
371
372static void
373update_flags_logic (byte res)
374{
375 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
376 if (res == 0)
377 sram[SREG] |= SREG_Z;
378 if (res & 0x80)
379 sram[SREG] |= SREG_N | SREG_S;
380}
381
382static void
383update_flags_add (byte r, byte a, byte b)
384{
385 byte carry;
386
387 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
388 if (r & 0x80)
389 sram[SREG] |= SREG_N;
390 carry = (a & b) | (a & ~r) | (b & ~r);
391 if (carry & 0x08)
392 sram[SREG] |= SREG_H;
393 if (carry & 0x80)
394 sram[SREG] |= SREG_C;
395 if (((a & b & ~r) | (~a & ~b & r)) & 0x80)
396 sram[SREG] |= SREG_V;
397 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
398 sram[SREG] |= SREG_S;
399 if (r == 0)
400 sram[SREG] |= SREG_Z;
401}
402
403static void update_flags_sub (byte r, byte a, byte b)
404{
405 byte carry;
406
407 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
408 if (r & 0x80)
409 sram[SREG] |= SREG_N;
410 carry = (~a & b) | (b & r) | (r & ~a);
411 if (carry & 0x08)
412 sram[SREG] |= SREG_H;
413 if (carry & 0x80)
414 sram[SREG] |= SREG_C;
415 if (((a & ~b & ~r) | (~a & b & r)) & 0x80)
416 sram[SREG] |= SREG_V;
417 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
418 sram[SREG] |= SREG_S;
419 /* Note: Z is not set. */
420}
421
422static enum avr_opcode
423decode (unsigned int pc)
424{
425 word op1 = flash[pc].op;
426
427 switch ((op1 >> 12) & 0x0f)
428 {
429 case 0x0:
430 switch ((op1 >> 10) & 0x3)
431 {
432 case 0x0:
433 switch ((op1 >> 8) & 0x3)
434 {
435 case 0x0:
436 if (op1 == 0)
437 return OP_nop;
438 break;
439 case 0x1:
440 return OP_movw;
441 case 0x2:
442 return OP_muls;
443 case 0x3:
444 if (op1 & 0x80)
445 {
446 if (op1 & 0x08)
447 return OP_fmulsu;
448 else
449 return OP_fmuls;
450 }
451 else
452 {
453 if (op1 & 0x08)
454 return OP_fmul;
455 else
456 return OP_mulsu;
457 }
458 }
459 break;
460 case 0x1:
461 return OP_cpc;
462 case 0x2:
463 flash[pc].r = SREG_C;
464 return OP_sbc;
465 case 0x3:
466 flash[pc].r = 0;
467 return OP_add;
468 }
469 break;
470 case 0x1:
471 switch ((op1 >> 10) & 0x3)
472 {
473 case 0x0:
474 return OP_cpse;
475 case 0x1:
476 return OP_cp;
477 case 0x2:
478 flash[pc].r = 0;
479 return OP_sub;
480 case 0x3:
481 flash[pc].r = SREG_C;
482 return OP_adc;
483 }
484 break;
485 case 0x2:
486 switch ((op1 >> 10) & 0x3)
487 {
488 case 0x0:
489 return OP_and;
490 case 0x1:
491 return OP_eor;
492 case 0x2:
493 return OP_or;
494 case 0x3:
495 return OP_mov;
496 }
497 break;
498 case 0x3:
499 return OP_cpi;
500 case 0x4:
501 return OP_sbci;
502 case 0x5:
503 return OP_subi;
504 case 0x6:
505 return OP_ori;
506 case 0x7:
507 return OP_andi;
508 case 0x8:
509 case 0xa:
510 if (op1 & 0x0200)
511 {
512 if (op1 & 0x0008)
513 {
514 flash[pc].r = get_q (op1);
515 return OP_std_Y;
516 }
517 else
518 {
519 flash[pc].r = get_q (op1);
520 return OP_std_Z;
521 }
522 }
523 else
524 {
525 if (op1 & 0x0008)
526 {
527 flash[pc].r = get_q (op1);
528 return OP_ldd_Y;
529 }
530 else
531 {
532 flash[pc].r = get_q (op1);
533 return OP_ldd_Z;
534 }
535 }
536 break;
537 case 0x9: /* 9xxx */
538 switch ((op1 >> 8) & 0xf)
539 {
540 case 0x0:
541 case 0x1:
542 switch ((op1 >> 0) & 0xf)
543 {
544 case 0x0:
545 return OP_lds;
546 case 0x1:
547 return OP_ld_Z_inc;
548 case 0x2:
549 return OP_ld_dec_Z;
550 case 0x4:
551 return OP_lpm_Z;
552 case 0x5:
553 return OP_lpm_inc_Z;
554 case 0x6:
555 return OP_elpm_Z;
556 case 0x7:
557 return OP_elpm_inc_Z;
558 case 0x9:
559 return OP_ld_Y_inc;
560 case 0xa:
561 return OP_ld_dec_Y;
562 case 0xc:
563 return OP_ld_X;
564 case 0xd:
565 return OP_ld_X_inc;
566 case 0xe:
567 return OP_ld_dec_X;
568 case 0xf:
569 return OP_pop;
570 }
571 break;
572 case 0x2:
573 case 0x3:
574 switch ((op1 >> 0) & 0xf)
575 {
576 case 0x0:
577 return OP_sts;
578 case 0x1:
579 return OP_st_Z_inc;
580 case 0x2:
581 return OP_st_dec_Z;
582 case 0x9:
583 return OP_st_Y_inc;
584 case 0xa:
585 return OP_st_dec_Y;
586 case 0xc:
587 return OP_st_X;
588 case 0xd:
589 return OP_st_X_inc;
590 case 0xe:
591 return OP_st_dec_X;
592 case 0xf:
593 return OP_push;
594 }
595 break;
596 case 0x4:
597 case 0x5:
598 switch (op1 & 0xf)
599 {
600 case 0x0:
601 return OP_com;
602 case 0x1:
603 return OP_neg;
604 case 0x2:
605 return OP_swap;
606 case 0x3:
607 return OP_inc;
608 case 0x5:
609 flash[pc].r = 0x80;
610 return OP_asr;
611 case 0x6:
612 flash[pc].r = 0;
613 return OP_lsr;
614 case 0x7:
615 return OP_ror;
616 case 0x8: /* 9[45]x8 */
617 switch ((op1 >> 4) & 0x1f)
618 {
619 case 0x00:
620 case 0x01:
621 case 0x02:
622 case 0x03:
623 case 0x04:
624 case 0x05:
625 case 0x06:
626 case 0x07:
627 return OP_bset;
628 case 0x08:
629 case 0x09:
630 case 0x0a:
631 case 0x0b:
632 case 0x0c:
633 case 0x0d:
634 case 0x0e:
635 case 0x0f:
636 return OP_bclr;
637 case 0x10:
638 return OP_ret;
639 case 0x11:
640 return OP_reti;
641 case 0x19:
642 return OP_break;
643 case 0x1c:
644 return OP_lpm;
645 case 0x1d:
646 return OP_elpm;
647 default:
648 break;
649 }
650 break;
651 case 0x9: /* 9[45]x9 */
652 switch ((op1 >> 4) & 0x1f)
653 {
654 case 0x00:
655 return OP_ijmp;
656 case 0x01:
657 return OP_eijmp;
658 case 0x10:
659 return OP_icall;
660 case 0x11:
661 return OP_eicall;
662 default:
663 break;
664 }
665 break;
666 case 0xa:
667 return OP_dec;
668 case 0xc:
669 case 0xd:
670 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
671 return OP_jmp;
672 case 0xe:
673 case 0xf:
674 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
675 return OP_call;
676 }
677 break;
678 case 0x6:
679 return OP_adiw;
680 case 0x7:
681 return OP_sbiw;
682 case 0x8:
683 return OP_cbi;
684 case 0x9:
685 return OP_sbic;
686 case 0xa:
687 return OP_sbi;
688 case 0xb:
689 return OP_sbis;
690 case 0xc:
691 case 0xd:
692 case 0xe:
693 case 0xf:
694 return OP_mul;
695 }
696 break;
697 case 0xb:
698 flash[pc].r = get_A (op1);
699 if (((op1 >> 11) & 1) == 0)
700 return OP_in;
701 else
702 return OP_out;
703 case 0xc:
704 return OP_rjmp;
705 case 0xd:
706 return OP_rcall;
707 case 0xe:
708 return OP_ldi;
709 case 0xf:
710 switch ((op1 >> 9) & 7)
711 {
712 case 0:
713 case 1:
714 flash[pc].r = 1 << (op1 & 7);
715 return OP_brbs;
716 case 2:
717 case 3:
718 flash[pc].r = 1 << (op1 & 7);
719 return OP_brbc;
720 case 4:
721 if ((op1 & 8) == 0)
722 {
723 flash[pc].r = 1 << (op1 & 7);
724 return OP_bld;
725 }
726 break;
727 case 5:
728 if ((op1 & 8) == 0)
729 {
730 flash[pc].r = 1 << (op1 & 7);
731 return OP_bst;
732 }
733 break;
734 case 6:
735 if ((op1 & 8) == 0)
736 {
737 flash[pc].r = 1 << (op1 & 7);
738 return OP_sbrc;
739 }
740 break;
741 case 7:
742 if ((op1 & 8) == 0)
743 {
744 flash[pc].r = 1 << (op1 & 7);
745 return OP_sbrs;
746 }
747 break;
748 }
749 }
750 sim_cb_eprintf (callback,
751 "Unhandled instruction at pc=0x%x, op=%04x\n", pc * 2, op1);
752 return OP_bad;
753}
754
755/* Disassemble an instruction. */
756
757static int
758disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
759 struct disassemble_info *info)
760{
761 int res;
762
763 res = sim_read (NULL, memaddr, myaddr, length);
764 if (res != length)
765 return -1;
766 return 0;
767}
768
769/* Memory error support for an opcodes disassembler. */
770
771static void
772disasm_perror_memory (int status, bfd_vma memaddr,
773 struct disassemble_info *info)
774{
775 if (status != -1)
776 /* Can't happen. */
777 info->fprintf_func (info->stream, "Unknown error %d.", status);
778 else
779 /* Actually, address between memaddr and memaddr + len was
780 out of bounds. */
781 info->fprintf_func (info->stream,
782 "Address 0x%x is out of bounds.",
783 (int) memaddr);
784}
785
786static void
787disassemble_insn (SIM_DESC sd, SIM_ADDR pc)
788{
789 struct disassemble_info disasm_info;
790 int len;
791 int i;
792
793 INIT_DISASSEMBLE_INFO (disasm_info, callback, sim_cb_eprintf);
794
795 disasm_info.arch = bfd_get_arch (cur_bfd);
796 disasm_info.mach = bfd_get_mach (cur_bfd);
797 disasm_info.endian = BFD_ENDIAN_LITTLE;
798 disasm_info.read_memory_func = disasm_read_memory;
799 disasm_info.memory_error_func = disasm_perror_memory;
800
801 len = print_insn_avr (pc << 1, &disasm_info);
802 len = len / 2;
803 for (i = 0; i < len; i++)
804 sim_cb_eprintf (callback, " %04x", flash[pc + i].op);
805}
806
807static void
808do_call (unsigned int npc)
809{
810 unsigned int sp = read_word (REG_SP);
811
812 /* Big endian! */
813 sram[sp--] = pc;
814 sram[sp--] = pc >> 8;
815 if (avr_pc22)
816 {
817 sram[sp--] = pc >> 16;
818 cycles++;
819 }
820 write_word (REG_SP, sp);
821 pc = npc & PC_MASK;
822 cycles += 3;
823}
824
825static int
826get_insn_length (unsigned int p)
827{
828 if (flash[p].code == OP_unknown)
829 flash[p].code = decode(p);
830 if (flash[p].code >= OP_2words)
831 return 2;
832 else
833 return 1;
834}
835
836static unsigned int
837get_z (void)
838{
839 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO];
840}
841
842static unsigned char
843get_lpm (unsigned int addr)
844{
845 word w;
846
847 w = flash[(addr >> 1) & PC_MASK].op;
848 if (addr & 1)
849 w >>= 8;
850 return w;
851}
852
853static void
854gen_mul (unsigned int res)
855{
856 write_word (0, res);
857 sram[SREG] &= ~(SREG_Z | SREG_C);
858 if (res == 0)
859 sram[SREG] |= SREG_Z;
860 if (res & 0x8000)
861 sram[SREG] |= SREG_C;
862 cycles++;
863}
864
865void
866sim_resume (SIM_DESC sd, int step, int signal)
867{
868 unsigned int ipc;
869
870 if (step)
871 {
872 cpu_exception = sim_stopped;
a493e3e2 873 cpu_signal = GDB_SIGNAL_TRAP;
df1756f4
TG		 874 }
875 else
876 cpu_exception = sim_running;
877
878 do
879 {
880 int code;
881 word op;
882 byte res;
883 byte r, d, vd;
884
885 again:
886 code = flash[pc].code;
887 op = flash[pc].op;
888
889
890 if ((tracing || lock_step) && code != OP_unknown)
891 {
892 if (verbose > 0) {
893 int flags;
894 int i;
895
896 sim_cb_eprintf (callback, "R00-07:");
897 for (i = 0; i < 8; i++)
898 sim_cb_eprintf (callback, " %02x", sram[i]);
899 sim_cb_eprintf (callback, " -");
900 for (i = 8; i < 16; i++)
901 sim_cb_eprintf (callback, " %02x", sram[i]);
902 sim_cb_eprintf (callback, " SP: %02x %02x",
903 sram[REG_SP + 1], sram[REG_SP]);
904 sim_cb_eprintf (callback, "\n");
905 sim_cb_eprintf (callback, "R16-31:");
906 for (i = 16; i < 24; i++)
907 sim_cb_eprintf (callback, " %02x", sram[i]);
908 sim_cb_eprintf (callback, " -");
909 for (i = 24; i < 32; i++)
910 sim_cb_eprintf (callback, " %02x", sram[i]);
911 sim_cb_eprintf (callback, " ");
912 flags = sram[SREG];
913 for (i = 0; i < 8; i++)
914 sim_cb_eprintf (callback, "%c",
915 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-');
916 sim_cb_eprintf (callback, "\n");
917 }
918
919 if (lock_step && !tracing)
920 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * pc, flash[pc].op);
921 else
922 {
923 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
924 2 * pc, flash[pc].op, code, flash[pc].r);
925 disassemble_insn (sd, pc);
926 sim_cb_eprintf (callback, "\n");
927 }
928 }
929
930 ipc = pc;
931 pc = (pc + 1) & PC_MASK;
932 cycles++;
933
934 switch (code)
935 {
936 case OP_unknown:
937 flash[ipc].code = decode(ipc);
938 pc = ipc;
939 cycles--;
940 goto again;
941 break;
942
943 case OP_nop:
944 break;
945
946 case OP_jmp:
947 /* 2 words instruction, but we don't care about the pc. */
948 pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK;
949 cycles += 2;
950 break;
951
952 case OP_eijmp:
953 pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK;
954 cycles += 2;
955 break;
956
957 case OP_ijmp:
958 pc = read_word (REGZ) & PC_MASK;
959 cycles += 1;
960 break;
961
962 case OP_call:
963 /* 2 words instruction. */
964 pc++;
965 do_call ((flash[ipc].r << 16) | flash[ipc + 1].op);
966 break;
967
968 case OP_eicall:
969 do_call ((sram[EIND] << 16) | read_word (REGZ));
970 break;
971
972 case OP_icall:
973 do_call (read_word (REGZ));
974 break;
975
976 case OP_rcall:
977 do_call (pc + sign_ext (op & 0xfff, 12));
978 break;
979
980 case OP_reti:
981 sram[SREG] |= SREG_I;
982 /* Fall through */
983 case OP_ret:
984 {
985 unsigned int sp = read_word (REG_SP);
986 if (avr_pc22)
987 {
46b51513 988 pc = sram[++sp] << 16;
df1756f4
TG		 989 cycles++;
990 }
991 else
992 pc = 0;
993 pc |= sram[++sp] << 8;
994 pc |= sram[++sp];
995 write_word (REG_SP, sp);
996 }
997 cycles += 3;
998 break;
999
1000 case OP_break:
1001 /* Stop on this address. */
1002 cpu_exception = sim_stopped;
a493e3e2 1003 cpu_signal = GDB_SIGNAL_TRAP;
df1756f4
TG		 1004 pc = ipc;
1005 break;
1006
1007 case OP_bld:
1008 d = get_d (op);
1009 r = flash[ipc].r;
1010 if (sram[SREG] & SREG_T)
1011 sram[d] |= r;
1012 else
1013 sram[d] &= ~r;
1014 break;
1015
1016 case OP_bst:
1017 if (sram[get_d (op)] & flash[ipc].r)
1018 sram[SREG] |= SREG_T;
1019 else
1020 sram[SREG] &= ~SREG_T;
1021 break;
1022
1023 case OP_sbrc:
1024 case OP_sbrs:
1025 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0))
1026 {
1027 int l = get_insn_length(pc);
1028 pc += l;
1029 cycles += l;
1030 }
1031 break;
1032
1033 case OP_push:
1034 {
1035 unsigned int sp = read_word (REG_SP);
1036 sram[sp--] = sram[get_d (op)];
1037 write_word (REG_SP, sp);
1038 }
1039 cycles++;
1040 break;
1041
1042 case OP_pop:
1043 {
1044 unsigned int sp = read_word (REG_SP);
1045 sram[get_d (op)] = sram[++sp];
1046 write_word (REG_SP, sp);
1047 }
1048 cycles++;
1049 break;
1050
1051 case OP_bclr:
1052 sram[SREG] &= ~(1 << ((op >> 4) & 0x7));
1053 break;
1054
1055 case OP_bset:
1056 sram[SREG] |= 1 << ((op >> 4) & 0x7);
1057 break;
1058
1059 case OP_rjmp:
1060 pc = (pc + sign_ext (op & 0xfff, 12)) & PC_MASK;
1061 cycles++;
1062 break;
1063
1064 case OP_eor:
1065 d = get_d (op);
1066 res = sram[d] ^ sram[get_r (op)];
1067 sram[d] = res;
1068 update_flags_logic (res);
1069 break;
1070
1071 case OP_and:
1072 d = get_d (op);
1073 res = sram[d] & sram[get_r (op)];
1074 sram[d] = res;
1075 update_flags_logic (res);
1076 break;
1077
1078 case OP_andi:
1079 d = get_d16 (op);
1080 res = sram[d] & get_K (op);
1081 sram[d] = res;
1082 update_flags_logic (res);
1083 break;
1084
1085 case OP_or:
1086 d = get_d (op);
1087 res = sram[d] | sram[get_r (op)];
1088 sram[d] = res;
1089 update_flags_logic (res);
1090 break;
1091
1092 case OP_ori:
1093 d = get_d16 (op);
1094 res = sram[d] | get_K (op);
1095 sram[d] = res;
1096 update_flags_logic (res);
1097 break;
1098
1099 case OP_com:
1100 d = get_d (op);
1101 res = ~sram[d];
1102 sram[d] = res;
1103 update_flags_logic (res);
1104 sram[SREG] |= SREG_C;
1105 break;
1106
1107 case OP_swap:
1108 d = get_d (op);
1109 vd = sram[d];
1110 sram[d] = (vd >> 4) | (vd << 4);
1111 break;
1112
1113 case OP_neg:
1114 d = get_d (op);
1115 vd = sram[d];
1116 res = -vd;
1117 sram[d] = res;
1118 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1119 if (res == 0)
1120 sram[SREG] |= SREG_Z;
1121 else
1122 sram[SREG] |= SREG_C;
1123 if (res == 0x80)
1124 sram[SREG] |= SREG_V | SREG_N;
1125 else if (res & 0x80)
1126 sram[SREG] |= SREG_N | SREG_S;
1127 if ((res | vd) & 0x08)
1128 sram[SREG] |= SREG_H;
1129 break;
1130
1131 case OP_inc:
1132 d = get_d (op);
1133 res = sram[d] + 1;
1134 sram[d] = res;
1135 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1136 if (res == 0x80)
1137 sram[SREG] |= SREG_V | SREG_N;
1138 else if (res & 0x80)
1139 sram[SREG] |= SREG_N | SREG_S;
1140 else if (res == 0)
1141 sram[SREG] |= SREG_Z;
1142 break;
1143
1144 case OP_dec:
1145 d = get_d (op);
1146 res = sram[d] - 1;
1147 sram[d] = res;
1148 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1149 if (res == 0x7f)
1150 sram[SREG] |= SREG_V | SREG_S;
1151 else if (res & 0x80)
1152 sram[SREG] |= SREG_N | SREG_S;
1153 else if (res == 0)
1154 sram[SREG] |= SREG_Z;
1155 break;
1156
1157 case OP_lsr:
1158 case OP_asr:
1159 d = get_d (op);
1160 vd = sram[d];
1161 res = (vd >> 1) | (vd & flash[ipc].r);
1162 sram[d] = res;
1163 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1164 if (vd & 1)
1165 sram[SREG] |= SREG_C | SREG_S;
1166 if (res & 0x80)
1167 sram[SREG] |= SREG_N;
1168 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1169 sram[SREG] |= SREG_V;
1170 if (res == 0)
1171 sram[SREG] |= SREG_Z;
1172 break;
1173
1174 case OP_ror:
1175 d = get_d (op);
1176 vd = sram[d];
1177 res = vd >> 1 | (sram[SREG] << 7);
1178 sram[d] = res;
1179 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1180 if (vd & 1)
1181 sram[SREG] |= SREG_C | SREG_S;
1182 if (res & 0x80)
1183 sram[SREG] |= SREG_N;
1184 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1185 sram[SREG] |= SREG_V;
1186 if (res == 0)
1187 sram[SREG] |= SREG_Z;
1188 break;
1189
1190 case OP_mul:
1191 gen_mul ((word)sram[get_r (op)] * (word)sram[get_d (op)]);
1192 break;
1193
1194 case OP_muls:
1195 gen_mul((sword)(sbyte)sram[get_r16 (op)]
1196 * (sword)(sbyte)sram[get_d16 (op)]);
1197 break;
1198
1199 case OP_mulsu:
1200 gen_mul ((sword)(word)sram[get_r16_23 (op)]
1201 * (sword)(sbyte)sram[get_d16_23 (op)]);
1202 break;
1203
1204 case OP_fmul:
1205 gen_mul(((word)sram[get_r16_23 (op)]
1206 * (word)sram[get_d16_23 (op)]) << 1);
1207 break;
1208
1209 case OP_fmuls:
1210 gen_mul(((sword)(sbyte)sram[get_r16_23 (op)]
1211 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
1212 break;
1213
1214 case OP_fmulsu:
1215 gen_mul(((sword)(word)sram[get_r16_23 (op)]
1216 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
1217 break;
1218
1219 case OP_adc:
1220 case OP_add:
1221 r = sram[get_r (op)];
1222 d = get_d (op);
1223 vd = sram[d];
1224 res = r + vd + (sram[SREG] & flash[ipc].r);
1225 sram[d] = res;
1226 update_flags_add (res, vd, r);
1227 break;
1228
1229 case OP_sub:
1230 d = get_d (op);
1231 vd = sram[d];
1232 r = sram[get_r (op)];
1233 res = vd - r;
1234 sram[d] = res;
1235 update_flags_sub (res, vd, r);
1236 if (res == 0)
1237 sram[SREG] |= SREG_Z;
1238 break;
1239
1240 case OP_sbc:
1241 {
1242 byte old = sram[SREG];
1243 d = get_d (op);
1244 vd = sram[d];
1245 r = sram[get_r (op)];
1246 res = vd - r - (old & SREG_C);
1247 sram[d] = res;
1248 update_flags_sub (res, vd, r);
1249 if (res == 0 && (old & SREG_Z))
1250 sram[SREG] |= SREG_Z;
1251 }
1252 break;
1253
1254 case OP_subi:
1255 d = get_d16 (op);
1256 vd = sram[d];
1257 r = get_K (op);
1258 res = vd - r;
1259 sram[d] = res;
1260 update_flags_sub (res, vd, r);
1261 if (res == 0)
1262 sram[SREG] |= SREG_Z;
1263 break;
1264
1265 case OP_sbci:
1266 {
1267 byte old = sram[SREG];
1268
1269 d = get_d16 (op);
1270 vd = sram[d];
1271 r = get_K (op);
1272 res = vd - r - (old & SREG_C);
1273 sram[d] = res;
1274 update_flags_sub (res, vd, r);
1275 if (res == 0 && (old & SREG_Z))
1276 sram[SREG] |= SREG_Z;
1277 }
1278 break;
1279
1280 case OP_mov:
1281 sram[get_d (op)] = sram[get_r (op)];
1282 break;
1283
1284 case OP_movw:
1285 d = (op & 0xf0) >> 3;
1286 r = (op & 0x0f) << 1;
1287 sram[d] = sram[r];
1288 sram[d + 1] = sram[r + 1];
1289 break;
1290
1291 case OP_out:
1292 d = get_A (op) + 0x20;
1293 res = sram[get_d (op)];
1294 sram[d] = res;
1295 if (d == STDIO_PORT)
1296 putchar (res);
1297 else if (d == EXIT_PORT)
1298 {
1299 cpu_exception = sim_exited;
1300 cpu_signal = 0;
1301 return;
1302 }
1303 else if (d == ABORT_PORT)
1304 {
1305 cpu_exception = sim_exited;
1306 cpu_signal = 1;
1307 return;
1308 }
1309 break;
1310
1311 case OP_in:
1312 d = get_A (op) + 0x20;
1313 sram[get_d (op)] = sram[d];
1314 break;
1315
1316 case OP_cbi:
1317 d = get_biA (op) + 0x20;
1318 sram[d] &= ~(1 << get_b(op));
1319 break;
1320
1321 case OP_sbi:
1322 d = get_biA (op) + 0x20;
1323 sram[d] |= 1 << get_b(op);
1324 break;
1325
1326 case OP_sbic:
1327 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op)))
1328 {
1329 int l = get_insn_length(pc);
1330 pc += l;
1331 cycles += l;
1332 }
1333 break;
1334
1335 case OP_sbis:
1336 if (sram[get_biA (op) + 0x20] & 1 << get_b(op))
1337 {
1338 int l = get_insn_length(pc);
1339 pc += l;
1340 cycles += l;
1341 }
1342 break;
1343
1344 case OP_ldi:
1345 res = get_K (op);
1346 d = get_d16 (op);
1347 sram[d] = res;
1348 break;
1349
1350 case OP_lds:
1351 sram[get_d (op)] = sram[flash[pc].op];
1352 pc++;
1353 cycles++;
1354 break;
1355
1356 case OP_sts:
1357 sram[flash[pc].op] = sram[get_d (op)];
1358 pc++;
1359 cycles++;
1360 break;
1361
1362 case OP_cpse:
1363 if (sram[get_r (op)] == sram[get_d (op)])
1364 {
1365 int l = get_insn_length(pc);
1366 pc += l;
1367 cycles += l;
1368 }
1369 break;
1370
1371 case OP_cp:
1372 r = sram[get_r (op)];
1373 d = sram[get_d (op)];
1374 res = d - r;
1375 update_flags_sub (res, d, r);
1376 if (res == 0)
1377 sram[SREG] |= SREG_Z;
1378 break;
1379
1380 case OP_cpi:
1381 r = get_K (op);
1382 d = sram[get_d16 (op)];
1383 res = d - r;
1384 update_flags_sub (res, d, r);
1385 if (res == 0)
1386 sram[SREG] |= SREG_Z;
1387 break;
1388
1389 case OP_cpc:
1390 {
1391 byte old = sram[SREG];
1392 d = sram[get_d (op)];
1393 r = sram[get_r (op)];
1394 res = d - r - (old & SREG_C);
1395 update_flags_sub (res, d, r);
1396 if (res == 0 && (old & SREG_Z))
1397 sram[SREG] |= SREG_Z;
1398 }
1399 break;
1400
1401 case OP_brbc:
1402 if (!(sram[SREG] & flash[ipc].r))
1403 {
1404 pc = (pc + get_k (op)) & PC_MASK;
1405 cycles++;
1406 }
1407 break;
1408
1409 case OP_brbs:
1410 if (sram[SREG] & flash[ipc].r)
1411 {
1412 pc = (pc + get_k (op)) & PC_MASK;
1413 cycles++;
1414 }
1415 break;
1416
1417 case OP_lpm:
1418 sram[0] = get_lpm (read_word (REGZ));
1419 cycles += 2;
1420 break;
1421
1422 case OP_lpm_Z:
1423 sram[get_d (op)] = get_lpm (read_word (REGZ));
1424 cycles += 2;
1425 break;
1426
1427 case OP_lpm_inc_Z:
1428 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ));
1429 cycles += 2;
1430 break;
1431
1432 case OP_elpm:
1433 sram[0] = get_lpm (get_z ());
1434 cycles += 2;
1435 break;
1436
1437 case OP_elpm_Z:
1438 sram[get_d (op)] = get_lpm (get_z ());
1439 cycles += 2;
1440 break;
1441
1442 case OP_elpm_inc_Z:
1443 {
1444 unsigned int z = get_z ();
1445
1446 sram[get_d (op)] = get_lpm (z);
1447 z++;
1448 sram[REGZ_LO] = z;
1449 sram[REGZ_HI] = z >> 8;
1450 sram[RAMPZ] = z >> 16;
1451 }
1452 cycles += 2;
1453 break;
1454
1455 case OP_ld_Z_inc:
1456 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK];
1457 cycles++;
1458 break;
1459
1460 case OP_ld_dec_Z:
1461 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK];
1462 cycles++;
1463 break;
1464
1465 case OP_ld_X_inc:
1466 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK];
1467 cycles++;
1468 break;
1469
1470 case OP_ld_dec_X:
1471 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK];
1472 cycles++;
1473 break;
1474
1475 case OP_ld_Y_inc:
1476 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK];
1477 cycles++;
1478 break;
1479
1480 case OP_ld_dec_Y:
1481 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK];
1482 cycles++;
1483 break;
1484
1485 case OP_st_X:
1486 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)];
1487 cycles++;
1488 break;
1489
1490 case OP_st_X_inc:
1491 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)];
1492 cycles++;
1493 break;
1494
1495 case OP_st_dec_X:
1496 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)];
1497 cycles++;
1498 break;
1499
1500 case OP_st_Z_inc:
1501 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)];
1502 cycles++;
1503 break;
1504
1505 case OP_st_dec_Z:
1506 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)];
1507 cycles++;
1508 break;
1509
1510 case OP_st_Y_inc:
1511 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)];
1512 cycles++;
1513 break;
1514
1515 case OP_st_dec_Y:
1516 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)];
1517 cycles++;
1518 break;
1519
1520 case OP_std_Y:
1521 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)];
1522 cycles++;
1523 break;
1524
1525 case OP_std_Z:
1526 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)];
1527 cycles++;
1528 break;
1529
1530 case OP_ldd_Z:
1531 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r];
1532 cycles++;
1533 break;
1534
1535 case OP_ldd_Y:
1536 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r];
1537 cycles++;
1538 break;
1539
1540 case OP_ld_X:
1541 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK];
1542 cycles++;
1543 break;
1544
1545 case OP_sbiw:
1546 {
1547 word wk = get_k6 (op);
1548 word wres;
1549 word wr;
1550
1551 d = get_d24 (op);
1552 wr = read_word (d);
1553 wres = wr - wk;
1554
1555 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1556 if (wres == 0)
1557 sram[SREG] |= SREG_Z;
1558 if (wres & 0x8000)
1559 sram[SREG] |= SREG_N;
1560 if (wres & ~wr & 0x8000)
1561 sram[SREG] |= SREG_C;
1562 if (~wres & wr & 0x8000)
1563 sram[SREG] |= SREG_V;
1564 if (((~wres & wr) ^ wres) & 0x8000)
1565 sram[SREG] |= SREG_S;
1566 write_word (d, wres);
1567 }
1568 cycles++;
1569 break;
1570
1571 case OP_adiw:
1572 {
1573 word wk = get_k6 (op);
1574 word wres;
1575 word wr;
1576
1577 d = get_d24 (op);
1578 wr = read_word (d);
1579 wres = wr + wk;
1580
1581 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1582 if (wres == 0)
1583 sram[SREG] |= SREG_Z;
1584 if (wres & 0x8000)
1585 sram[SREG] |= SREG_N;
1586 if (~wres & wr & 0x8000)
1587 sram[SREG] |= SREG_C;
1588 if (wres & ~wr & 0x8000)
1589 sram[SREG] |= SREG_V;
1590 if (((wres & ~wr) ^ wres) & 0x8000)
1591 sram[SREG] |= SREG_S;
1592 write_word (d, wres);
1593 }
1594 cycles++;
1595 break;
1596
1597 case OP_bad:
1598 sim_cb_eprintf (callback, "Bad instruction at pc=0x%x\n", ipc * 2);
1599 return;
1600
1601 default:
1602 sim_cb_eprintf (callback,
1603 "Unhandled instruction at pc=0x%x, code=%d\n",
1604 2 * ipc, code);
1605 return;
1606 }
1607 }
1608 while (cpu_exception == sim_running);
1609}
1610
1611
1612int
1613sim_trace (SIM_DESC sd)
1614{
1615 tracing = 1;
1616
1617 sim_resume (sd, 0, 0);
1618
1619 tracing = 0;
1620
1621 return 1;
1622}
1623
1624int
5558e7e6 1625sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
df1756f4
TG		 1626{
1627 int osize = size;
1628
1629 if (addr >= 0 && addr < SRAM_VADDR)
1630 {
8f0ac700 1631 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1632 {
8f0ac700
TG		 1633 word val = flash[addr >> 1].op;
1634
1635 if (addr & 1)
1636 val = (val & 0xff) | (buffer[0] << 8);
1637 else
1638 val = (val & 0xff00) | buffer[0];
1639
1640 flash[addr >> 1].op = val;
1641 flash[addr >> 1].code = OP_unknown;
df1756f4 1642 addr++;
8f0ac700
TG		 1643 buffer++;
1644 size--;
df1756f4
TG		 1645 }
1646 return osize - size;
1647 }
1648 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1649 {
1650 addr -= SRAM_VADDR;
1651 if (addr + size > MAX_AVR_SRAM)
1652 size = MAX_AVR_SRAM - addr;
1653 memcpy (sram + addr, buffer, size);
1654 return size;
1655 }
1656 else
1657 return 0;
1658}
1659
1660int
1661sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1662{
1663 int osize = size;
1664
1665 if (addr >= 0 && addr < SRAM_VADDR)
1666 {
8f0ac700 1667 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1668 {
8f0ac700
TG		 1669 word val = flash[addr >> 1].op;
1670
1671 if (addr & 1)
1672 val >>= 8;
1673
1674 *buffer++ = val;
df1756f4 1675 addr++;
8f0ac700 1676 size--;
df1756f4
TG		 1677 }
1678 return osize - size;
1679 }
1680 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1681 {
1682 addr -= SRAM_VADDR;
1683 if (addr + size > MAX_AVR_SRAM)
1684 size = MAX_AVR_SRAM - addr;
1685 memcpy (buffer, sram + addr, size);
1686 return size;
1687 }
1688 else
1689 {
1690 /* Avoid errors. */
1691 memset (buffer, 0, size);
1692 return size;
1693 }
1694}
1695
1696int
1697sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1698{
1699 if (rn < 32 && length == 1)
1700 {
1701 sram[rn] = *memory;
1702 return 1;
1703 }
1704 if (rn == AVR_SREG_REGNUM && length == 1)
1705 {
1706 sram[SREG] = *memory;
1707 return 1;
1708 }
1709 if (rn == AVR_SP_REGNUM && length == 2)
1710 {
1711 sram[REG_SP] = memory[0];
1712 sram[REG_SP + 1] = memory[1];
1713 return 2;
1714 }
1715 if (rn == AVR_PC_REGNUM && length == 4)
1716 {
1717 pc = (memory[0] >> 1) | (memory[1] << 7)
1718 | (memory[2] << 15) | (memory[3] << 23);
1719 pc &= PC_MASK;
1720 return 4;
1721 }
1722 return 0;
1723}
1724
1725int
1726sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1727{
1728 if (rn < 32 && length == 1)
1729 {
1730 *memory = sram[rn];
1731 return 1;
1732 }
1733 if (rn == AVR_SREG_REGNUM && length == 1)
1734 {
1735 *memory = sram[SREG];
1736 return 1;
1737 }
1738 if (rn == AVR_SP_REGNUM && length == 2)
1739 {
1740 memory[0] = sram[REG_SP];
1741 memory[1] = sram[REG_SP + 1];
1742 return 2;
1743 }
1744 if (rn == AVR_PC_REGNUM && length == 4)
1745 {
1746 memory[0] = pc << 1;
1747 memory[1] = pc >> 7;
1748 memory[2] = pc >> 15;
1749 memory[3] = pc >> 23;
1750 return 4;
1751 }
1752 return 0;
1753}
1754
1755void
1756sim_stop_reason (SIM_DESC sd, enum sim_stop * reason, int *sigrc)
1757{
1758 *reason = cpu_exception;
1759 *sigrc = cpu_signal;
1760}
1761
1762int
1763sim_stop (SIM_DESC sd)
1764{
1765 cpu_exception = sim_stopped;
a493e3e2 1766 cpu_signal = GDB_SIGNAL_INT;
244d5259 1767 return 1;
df1756f4
TG		 1768}
1769
1770void
1771sim_info (SIM_DESC sd, int verbose)
1772{
1773 callback->printf_filtered
1774 (callback, "\n\n# cycles %10u\n", cycles);
1775}
1776
1777SIM_DESC
1778sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
1779{
1780 myname = argv[0];
1781 callback = cb;
1782
1783 cur_bfd = abfd;
1784
1785 /* Fudge our descriptor for now. */
1786 return (SIM_DESC) 1;
1787}
1788
1789void
1790sim_close (SIM_DESC sd, int quitting)
1791{
1792 /* nothing to do */
1793}
1794
1795SIM_RC
b2b255bd 1796sim_load (SIM_DESC sd, const char *prog, bfd *abfd, int from_tty)
df1756f4
TG		 1797{
1798 bfd *prog_bfd;
1799
33bcfade
TG		 1800 /* Clear all the memory. */
1801 memset (sram, 0, sizeof (sram));
1802 memset (flash, 0, sizeof (flash));
1803
df1756f4
TG		 1804 prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
1805 sim_kind == SIM_OPEN_DEBUG,
1806 0, sim_write);
1807 if (prog_bfd == NULL)
1808 return SIM_RC_FAIL;
1809
1810 avr_pc22 = (bfd_get_mach (prog_bfd) >= bfd_mach_avr6);
1811
1812 if (abfd != NULL)
1813 cur_bfd = abfd;
1814
1815 return SIM_RC_OK;
1816}
1817
1818SIM_RC
1819sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
1820{
1821 /* Set the initial register set. */
1822 pc = 0;
1823
1824 return SIM_RC_OK;
1825}
1826
1827void
1828sim_kill (SIM_DESC sd)
1829{
1830 /* nothing to do */
1831}
1832
1833void
60d847df 1834sim_do_command (SIM_DESC sd, const char *cmd)
df1756f4
TG		 1835{
1836 /* Nothing there yet; it's all an error. */
1837
1838 if (cmd == NULL)
1839 return;
1840
1841 if (strcmp (cmd, "verbose") == 0)
1842 verbose = 2;
1843 else if (strcmp (cmd, "trace") == 0)
1844 tracing = 1;
1845 else
1846 sim_cb_eprintf (callback,
1847 "Error: \"%s\" is not a valid avr simulator command.\n",
1848 cmd);
1849}
1850
1851void
1852sim_set_callbacks (host_callback *ptr)
1853{
1854 callback = ptr;
1855}
af9f7da7
MF		 1856
1857char **
3cb2ab1a 1858sim_complete_command (SIM_DESC sd, const char *text, const char *word)
af9f7da7
MF		 1859{
1860 return NULL;
1861}
Empty description
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