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2003-09-14 Andrew Cagney <[email protected]>
[binutils.git] / gdb / sh-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
1e698235 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 [email protected]
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
c906108c
SS		 29#include "symtab.h"
30#include "symfile.h"
31#include "gdbtypes.h"
32#include "gdbcmd.h"
33#include "gdbcore.h"
34#include "value.h"
35#include "dis-asm.h"
73c1f219 36#include "inferior.h"
c906108c 37#include "gdb_string.h"
b4a20239 38#include "arch-utils.h"
fb409745 39#include "floatformat.h"
4e052eda 40#include "regcache.h"
d16aafd8 41#include "doublest.h"
4be87837 42#include "osabi.h"
c906108c 43
ab3b8126
JT		 44#include "sh-tdep.h"
45
d658f924 46#include "elf-bfd.h"
1a8629c7
MS		 47#include "solib-svr4.h"
48
55ff77ac 49/* sh flags */
283150cd
EZ		 50#include "elf/sh.h"
51/* registers numbers shared with the simulator */
1c922164 52#include "gdb/sim-sh.h"
283150cd 53
55ff77ac 54static void (*sh_show_regs) (void);
cc17453a 55
88e04cc1
EZ		 56#define SH_DEFAULT_NUM_REGS 59
57
cc17453a
EZ		 58/* Define other aspects of the stack frame.
59 we keep a copy of the worked out return pc lying around, since it
60 is a useful bit of info */
61
62struct frame_extra_info
63{
64 CORE_ADDR return_pc;
65 int leaf_function;
66 int f_offset;
63978407 67};
c906108c 68
fa88f677 69static const char *
cc17453a 70sh_generic_register_name (int reg_nr)
c5aa993b 71{
cc17453a 72 static char *register_names[] =
c5aa993b 73 {
cc17453a
EZ		 74 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
75 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
76 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
77 "fpul", "fpscr",
78 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
79 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
80 "ssr", "spc",
81 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
82 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
83 };
84 if (reg_nr < 0)
85 return NULL;
86 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
87 return NULL;
88 return register_names[reg_nr];
89}
90
fa88f677 91static const char *
cc17453a
EZ		 92sh_sh_register_name (int reg_nr)
93{
94 static char *register_names[] =
63978407 95 {
cc17453a
EZ		 96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
99 "", "",
100 "", "", "", "", "", "", "", "",
101 "", "", "", "", "", "", "", "",
102 "", "",
103 "", "", "", "", "", "", "", "",
104 "", "", "", "", "", "", "", "",
105 };
106 if (reg_nr < 0)
107 return NULL;
108 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
109 return NULL;
110 return register_names[reg_nr];
111}
112
fa88f677 113static const char *
cc17453a
EZ		 114sh_sh3_register_name (int reg_nr)
115{
116 static char *register_names[] =
c5aa993b 117 {
cc17453a
EZ		 118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
121 "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "ssr", "spc",
125 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
126 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
127 };
128 if (reg_nr < 0)
129 return NULL;
130 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
131 return NULL;
132 return register_names[reg_nr];
133}
134
fa88f677 135static const char *
cc17453a
EZ		 136sh_sh3e_register_name (int reg_nr)
137{
138 static char *register_names[] =
63978407 139 {
cc17453a
EZ		 140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
143 "fpul", "fpscr",
144 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
145 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
146 "ssr", "spc",
147 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
148 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
149 };
150 if (reg_nr < 0)
151 return NULL;
152 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
153 return NULL;
154 return register_names[reg_nr];
155}
156
2d188dd3
NC		 157static const char *
158sh_sh2e_register_name (int reg_nr)
159{
160 static char *register_names[] =
161 {
162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
164 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
165 "fpul", "fpscr",
166 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
167 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
168 "", "",
169 "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "",
171 };
172 if (reg_nr < 0)
173 return NULL;
174 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
175 return NULL;
176 return register_names[reg_nr];
177}
178
fa88f677 179static const char *
cc17453a
EZ		 180sh_sh_dsp_register_name (int reg_nr)
181{
182 static char *register_names[] =
c5aa993b 183 {
cc17453a
EZ		 184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
187 "", "dsr",
188 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
189 "y0", "y1", "", "", "", "", "", "mod",
190 "", "",
191 "rs", "re", "", "", "", "", "", "",
192 "", "", "", "", "", "", "", "",
193 };
194 if (reg_nr < 0)
195 return NULL;
196 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
197 return NULL;
198 return register_names[reg_nr];
199}
200
fa88f677 201static const char *
cc17453a
EZ		 202sh_sh3_dsp_register_name (int reg_nr)
203{
204 static char *register_names[] =
c5aa993b 205 {
cc17453a
EZ		 206 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
207 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
209 "", "dsr",
210 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
211 "y0", "y1", "", "", "", "", "", "mod",
212 "ssr", "spc",
213 "rs", "re", "", "", "", "", "", "",
214 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
215 "", "", "", "", "", "", "", "",
216 };
217 if (reg_nr < 0)
218 return NULL;
219 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
220 return NULL;
221 return register_names[reg_nr];
222}
223
fa88f677 224static const char *
53116e27
EZ		 225sh_sh4_register_name (int reg_nr)
226{
227 static char *register_names[] =
228 {
a38d2a54 229 /* general registers 0-15 */
53116e27
EZ		 230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 232 /* 16 - 22 */
53116e27 233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 234 /* 23, 24 */
53116e27 235 "fpul", "fpscr",
a38d2a54 236 /* floating point registers 25 - 40 */
53116e27
EZ		 237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 239 /* 41, 42 */
53116e27 240 "ssr", "spc",
a38d2a54 241 /* bank 0 43 - 50 */
53116e27 242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 243 /* bank 1 51 - 58 */
53116e27 244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 245 /* double precision (pseudo) 59 - 66 */
fe9f384f 246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 247 /* vectors (pseudo) 67 - 70 */
fe9f384f 248 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 251 };
252 if (reg_nr < 0)
253 return NULL;
254 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
255 return NULL;
256 return register_names[reg_nr];
257}
258
283150cd
EZ		 259#define NUM_PSEUDO_REGS_SH_MEDIA 80
260#define NUM_PSEUDO_REGS_SH_COMPACT 51
261
3117ed25 262static const unsigned char *
fba45db2 263sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 264{
265 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
266 static unsigned char breakpoint[] = {0xc3, 0xc3};
267
268 *lenptr = sizeof (breakpoint);
269 return breakpoint;
270}
c906108c 271
48db5a3c
CV		 272static CORE_ADDR
273sh_push_dummy_code (struct gdbarch *gdbarch,
274 CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc,
275 struct value **args, int nargs,
276 struct type *value_type,
277 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
278{
279 /* Allocate space sufficient for a breakpoint. */
280 sp = (sp - 2) & ~1;
281 /* Store the address of that breakpoint */
282 *bp_addr = sp;
283 /* sh always starts the call at the callee's entry point. */
284 *real_pc = funaddr;
285 return sp;
286}
287
c906108c 288/* Prologue looks like
c5aa993b
JM		 289 [mov.l <regs>,@-r15]...
290 [sts.l pr,@-r15]
291 [mov.l r14,@-r15]
292 [mov r15,r14]
8db62801
EZ		 293
294 Actually it can be more complicated than this. For instance, with
295 newer gcc's:
296
297 mov.l r14,@-r15
298 add #-12,r15
299 mov r15,r14
300 mov r4,r1
301 mov r5,r2
302 mov.l r6,@(4,r14)
303 mov.l r7,@(8,r14)
304 mov.b r1,@r14
305 mov r14,r1
306 mov r14,r1
307 add #2,r1
308 mov.w r2,@r1
309
c5aa993b 310 */
c906108c 311
8db62801
EZ		 312/* STS.L PR,@-r15 0100111100100010
313 r15-4-->r15, PR-->(r15) */
c906108c 314#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 315
316/* MOV.L Rm,@-r15 00101111mmmm0110
317 r15-4-->r15, Rm-->(R15) */
c906108c 318#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 319
c906108c 320#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 321
322/* MOV r15,r14 0110111011110011
323 r15-->r14 */
c906108c 324#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 325
326/* ADD #imm,r15 01111111iiiiiiii
327 r15+imm-->r15 */
c906108c 328#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 329
c906108c
SS		 330#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
331#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 332
333/* ADD r3,r15 0011111100111100
334 r15+r3-->r15 */
c906108c 335#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 336
337/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 338 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 339 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 340#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 341
8db62801 342/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 343 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 344 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
345 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
346#define IS_ARG_MOV(x) \
347(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 348 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
349 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 350
351/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
352 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
3bbfbb92 353#define IS_MOV_TO_R14(x) \
cc17453a 354 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 355
356#define FPSCR_SZ (1 << 20)
c906108c 357
c906108c
SS		 358/* Skip any prologue before the guts of a function */
359
8db62801
EZ		 360/* Skip the prologue using the debug information. If this fails we'll
361 fall back on the 'guess' method below. */
362static CORE_ADDR
fba45db2 363after_prologue (CORE_ADDR pc)
8db62801
EZ		 364{
365 struct symtab_and_line sal;
366 CORE_ADDR func_addr, func_end;
367
368 /* If we can not find the symbol in the partial symbol table, then
369 there is no hope we can determine the function's start address
370 with this code. */
371 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
372 return 0;
373
374 /* Get the line associated with FUNC_ADDR. */
375 sal = find_pc_line (func_addr, 0);
376
377 /* There are only two cases to consider. First, the end of the source line
378 is within the function bounds. In that case we return the end of the
379 source line. Second is the end of the source line extends beyond the
380 bounds of the current function. We need to use the slow code to
381 examine instructions in that case. */
382 if (sal.end < func_end)
383 return sal.end;
384 else
385 return 0;
386}
387
388/* Here we look at each instruction in the function, and try to guess
389 where the prologue ends. Unfortunately this is not always
390 accurate. */
391static CORE_ADDR
3bbfbb92 392sh_skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 393{
2bfa91ee 394 CORE_ADDR here, end;
8db62801 395 int updated_fp = 0;
2bfa91ee
EZ		 396
397 if (!start_pc)
398 return 0;
399
400 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 401 {
2bfa91ee
EZ		 402 int w = read_memory_integer (here, 2);
403 here += 2;
404 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801 405 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
3bbfbb92 406 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
2bfa91ee
EZ		 407 {
408 start_pc = here;
2bfa91ee 409 }
8db62801
EZ		 410 else if (IS_MOV_SP_FP (w))
411 {
412 start_pc = here;
413 updated_fp = 1;
414 }
415 else
416 /* Don't bail out yet, if we are before the copy of sp. */
417 if (updated_fp)
418 break;
c906108c
SS		 419 }
420
421 return start_pc;
422}
423
cc17453a 424static CORE_ADDR
fba45db2 425sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 426{
427 CORE_ADDR post_prologue_pc;
428
429 /* See if we can determine the end of the prologue via the symbol table.
430 If so, then return either PC, or the PC after the prologue, whichever
431 is greater. */
8db62801
EZ		 432 post_prologue_pc = after_prologue (pc);
433
434 /* If after_prologue returned a useful address, then use it. Else
435 fall back on the instruction skipping code. */
436 if (post_prologue_pc != 0)
437 return max (pc, post_prologue_pc);
438 else
55ff77ac 439 return sh_skip_prologue_hard_way (pc);
8db62801
EZ		 440}
441
cc17453a
EZ		 442/* Immediately after a function call, return the saved pc.
443 Can't always go through the frames for this because on some machines
444 the new frame is not set up until the new function executes
445 some instructions.
446
447 The return address is the value saved in the PR register + 4 */
448static CORE_ADDR
fba45db2 449sh_saved_pc_after_call (struct frame_info *frame)
cc17453a 450{
55ff77ac 451 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
cc17453a
EZ		 452}
453
454/* Should call_function allocate stack space for a struct return? */
455static int
fba45db2 456sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a 457{
7079c36c 458#if 0
cc17453a 459 return (TYPE_LENGTH (type) > 1);
7079c36c
CV		 460#else
461 int len = TYPE_LENGTH (type);
462 int nelem = TYPE_NFIELDS (type);
463 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
464 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
465#endif
cc17453a
EZ		 466}
467
cc17453a
EZ		 468/* Disassemble an instruction. */
469static int
fba45db2 470gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c 471{
1c509ca8
JR		 472 info->endian = TARGET_BYTE_ORDER;
473 return print_insn_sh (memaddr, info);
283150cd
EZ		 474}
475
a5afb99f
AC		 476/* Given a GDB frame, determine the address of the calling function's
477 frame. This will be used to create a new GDB frame struct, and
e9582e71
AC		 478 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
479 will be called for the new frame.
c906108c
SS		 480
481 For us, the frame address is its stack pointer value, so we look up
482 the function prologue to determine the caller's sp value, and return it. */
cc17453a 483static CORE_ADDR
fba45db2 484sh_frame_chain (struct frame_info *frame)
c906108c 485{
1e2330ba
AC		 486 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
487 get_frame_base (frame),
488 get_frame_base (frame)))
489 return get_frame_base (frame); /* dummy frame same as caller's frame */
627b3ba2
AC		 490 if (get_frame_pc (frame)
491 && !deprecated_inside_entry_file (get_frame_pc (frame)))
da50a4b7
AC		 492 return read_memory_integer (get_frame_base (frame)
493 + get_frame_extra_info (frame)->f_offset, 4);
c906108c
SS		 494 else
495 return 0;
496}
497
498/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
499 we might want to do here is to check REGNUM against the clobber mask, and
500 somehow flag it as invalid if it isn't saved on the stack somewhere. This
501 would provide a graceful failure mode when trying to get the value of
502 caller-saves registers for an inner frame. */
cc17453a 503static CORE_ADDR
fba45db2 504sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 505{
11c02a10 506 for (; fi; fi = get_next_frame (fi))
1e2330ba
AC		 507 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
508 get_frame_base (fi)))
c906108c 509 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 510 that's where the previous routine appears to have done a call from. */
1e2330ba
AC		 511 return deprecated_read_register_dummy (get_frame_pc (fi),
512 get_frame_base (fi), regnum);
c5aa993b 513 else
c906108c 514 {
f30ee0bc 515 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
50abf9e5 516 if (!get_frame_pc (fi))
2bfa91ee 517 return 0;
b2fb4676
AC		 518 if (get_frame_saved_regs (fi)[regnum] != 0)
519 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
48db5a3c 520 register_size (current_gdbarch, regnum));
c906108c
SS		 521 }
522 return read_register (regnum);
523}
524
525/* Put here the code to store, into a struct frame_saved_regs, the
526 addresses of the saved registers of frame described by FRAME_INFO.
527 This includes special registers such as pc and fp saved in special
528 ways in the stack frame. sp is even more special: the address we
529 return for it IS the sp for the next frame. */
cc17453a 530static void
fba45db2 531sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c 532{
e7d717c0 533 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
c906108c
SS		 534 int rn;
535 int have_fp = 0;
536 int depth;
537 int pc;
538 int opc;
539 int insn;
540 int r3_val = 0;
1e2330ba
AC		 541 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
542 get_frame_base (fi));
cc17453a 543
b2fb4676 544 if (get_frame_saved_regs (fi) == NULL)
cc17453a
EZ		 545 frame_saved_regs_zalloc (fi);
546 else
b2fb4676 547 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
cc17453a
EZ		 548
549 if (dummy_regs)
550 {
551 /* DANGER! This is ONLY going to work if the char buffer format of
552 the saved registers is byte-for-byte identical to the
553 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
7b5849cc 554 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
cc17453a
EZ		 555 return;
556 }
557
da50a4b7
AC		 558 get_frame_extra_info (fi)->leaf_function = 1;
559 get_frame_extra_info (fi)->f_offset = 0;
cc17453a 560
cd4bffcf 561 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 562 where[rn] = -1;
563
564 depth = 0;
565
566 /* Loop around examining the prologue insns until we find something
567 that does not appear to be part of the prologue. But give up
568 after 20 of them, since we're getting silly then. */
569
be41e9f4 570 pc = get_frame_func (fi);
cc17453a
EZ		 571 if (!pc)
572 {
50abf9e5 573 deprecated_update_frame_pc_hack (fi, 0);
cc17453a
EZ		 574 return;
575 }
576
577 for (opc = pc + (2 * 28); pc < opc; pc += 2)
578 {
579 insn = read_memory_integer (pc, 2);
580 /* See where the registers will be saved to */
581 if (IS_PUSH (insn))
582 {
583 rn = GET_PUSHED_REG (insn);
584 where[rn] = depth;
585 depth += 4;
586 }
587 else if (IS_STS (insn))
588 {
55ff77ac 589 where[PR_REGNUM] = depth;
cc17453a 590 /* If we're storing the pr then this isn't a leaf */
da50a4b7 591 get_frame_extra_info (fi)->leaf_function = 0;
cc17453a
EZ		 592 depth += 4;
593 }
594 else if (IS_MOV_R3 (insn))
595 {
596 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
597 }
598 else if (IS_SHLL_R3 (insn))
599 {
600 r3_val <<= 1;
601 }
602 else if (IS_ADD_R3SP (insn))
603 {
604 depth += -r3_val;
605 }
606 else if (IS_ADD_SP (insn))
607 {
608 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
609 }
610 else if (IS_MOV_SP_FP (insn))
611 break;
612#if 0 /* This used to just stop when it found an instruction that
613 was not considered part of the prologue. Now, we just
614 keep going looking for likely instructions. */
615 else
616 break;
617#endif
618 }
619
620 /* Now we know how deep things are, we can work out their addresses */
621
cd4bffcf 622 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
cc17453a
EZ		 623 {
624 if (where[rn] >= 0)
625 {
0ba6dca9 626 if (rn == DEPRECATED_FP_REGNUM)
cc17453a 627 have_fp = 1;
c906108c 628
1e2330ba 629 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
cc17453a
EZ		 630 }
631 else
632 {
b2fb4676 633 get_frame_saved_regs (fi)[rn] = 0;
cc17453a
EZ		 634 }
635 }
636
637 if (have_fp)
638 {
0ba6dca9 639 get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
cc17453a
EZ		 640 }
641 else
642 {
1e2330ba 643 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
cc17453a
EZ		 644 }
645
0ba6dca9 646 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
cc17453a
EZ		 647 /* Work out the return pc - either from the saved pr or the pr
648 value */
649}
650
3bbfbb92
EZ		 651/* For vectors of 4 floating point registers. */
652static int
653fv_reg_base_num (int fv_regnum)
654{
655 int fp_regnum;
656
657 fp_regnum = FP0_REGNUM +
658 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
659 return fp_regnum;
660}
661
662/* For double precision floating point registers, i.e 2 fp regs.*/
663static int
664dr_reg_base_num (int dr_regnum)
665{
666 int fp_regnum;
667
668 fp_regnum = FP0_REGNUM +
669 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
670 return fp_regnum;
671}
672
283150cd
EZ		 673static void
674sh_fp_frame_init_saved_regs (struct frame_info *fi)
675{
ddde02bd 676 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
283150cd
EZ		 677 int rn;
678 int have_fp = 0;
cc17453a
EZ		 679 int depth;
680 int pc;
681 int opc;
682 int insn;
683 int r3_val = 0;
1e2330ba 684 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
f81353e4 685 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
cc17453a 686
b2fb4676 687 if (get_frame_saved_regs (fi) == NULL)
cc17453a
EZ		 688 frame_saved_regs_zalloc (fi);
689 else
b2fb4676 690 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
cc17453a 691
c906108c
SS		 692 if (dummy_regs)
693 {
694 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 695 the saved registers is byte-for-byte identical to the
696 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
7b5849cc 697 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
c906108c
SS		 698 return;
699 }
700
da50a4b7
AC		 701 get_frame_extra_info (fi)->leaf_function = 1;
702 get_frame_extra_info (fi)->f_offset = 0;
c906108c 703
cd4bffcf 704 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 705 where[rn] = -1;
706
707 depth = 0;
708
709 /* Loop around examining the prologue insns until we find something
710 that does not appear to be part of the prologue. But give up
711 after 20 of them, since we're getting silly then. */
712
be41e9f4 713 pc = get_frame_func (fi);
2bfa91ee 714 if (!pc)
c906108c 715 {
50abf9e5 716 deprecated_update_frame_pc_hack (fi, 0);
2bfa91ee
EZ		 717 return;
718 }
719
720 for (opc = pc + (2 * 28); pc < opc; pc += 2)
721 {
722 insn = read_memory_integer (pc, 2);
c906108c
SS		 723 /* See where the registers will be saved to */
724 if (IS_PUSH (insn))
725 {
c906108c
SS		 726 rn = GET_PUSHED_REG (insn);
727 where[rn] = depth;
c906108c
SS		 728 depth += 4;
729 }
730 else if (IS_STS (insn))
731 {
55ff77ac 732 where[PR_REGNUM] = depth;
c906108c 733 /* If we're storing the pr then this isn't a leaf */
da50a4b7 734 get_frame_extra_info (fi)->leaf_function = 0;
c906108c
SS		 735 depth += 4;
736 }
737 else if (IS_MOV_R3 (insn))
738 {
739 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 740 }
741 else if (IS_SHLL_R3 (insn))
742 {
743 r3_val <<= 1;
c906108c
SS		 744 }
745 else if (IS_ADD_R3SP (insn))
746 {
747 depth += -r3_val;
c906108c
SS		 748 }
749 else if (IS_ADD_SP (insn))
750 {
c906108c 751 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 752 }
753 else if (IS_FMOV (insn))
754 {
f81353e4 755 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 756 {
757 depth += 8;
758 }
759 else
760 {
761 depth += 4;
762 }
763 }
2bfa91ee
EZ		 764 else if (IS_MOV_SP_FP (insn))
765 break;
766#if 0 /* This used to just stop when it found an instruction that
767 was not considered part of the prologue. Now, we just
768 keep going looking for likely instructions. */
c906108c
SS		 769 else
770 break;
2bfa91ee 771#endif
c906108c
SS		 772 }
773
774 /* Now we know how deep things are, we can work out their addresses */
775
cd4bffcf 776 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
c906108c
SS		 777 {
778 if (where[rn] >= 0)
779 {
0ba6dca9 780 if (rn == DEPRECATED_FP_REGNUM)
c906108c
SS		 781 have_fp = 1;
782
1e2330ba 783 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
c906108c
SS		 784 }
785 else
786 {
b2fb4676 787 get_frame_saved_regs (fi)[rn] = 0;
c906108c
SS		 788 }
789 }
790
791 if (have_fp)
792 {
b2fb4676 793 get_frame_saved_regs (fi)[SP_REGNUM] =
0ba6dca9 794 read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
c906108c
SS		 795 }
796 else
797 {
1e2330ba 798 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
c906108c
SS		 799 }
800
0ba6dca9 801 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
c906108c
SS		 802 /* Work out the return pc - either from the saved pr or the pr
803 value */
804}
805
cc17453a
EZ		 806/* Initialize the extra info saved in a FRAME */
807static void
fba45db2 808sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 809{
cc17453a 810
a00a19e9 811 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
c906108c 812
11c02a10 813 if (get_next_frame (fi))
8bedc050 814 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
c906108c 815
1e2330ba
AC		 816 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
817 get_frame_base (fi)))
c906108c 818 {
04714b91
AC		 819 /* We need to setup fi->frame here because call_function_by_hand
820 gets it wrong by assuming it's always FP. */
1e2330ba 821 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi),
8ccd593b 822 SP_REGNUM));
da50a4b7 823 get_frame_extra_info (fi)->return_pc = deprecated_read_register_dummy (get_frame_pc (fi),
1e2330ba 824 get_frame_base (fi),
135c175f 825 PC_REGNUM);
b1e29e33 826 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
da50a4b7 827 get_frame_extra_info (fi)->leaf_function = 0;
c906108c
SS		 828 return;
829 }
830 else
831 {
55ff77ac
CV		 832 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
833 get_frame_extra_info (fi)->return_pc =
834 sh_find_callers_reg (fi, PR_REGNUM);
283150cd 835 }
283150cd
EZ		 836}
837
cc17453a
EZ		 838/* Extract from an array REGBUF containing the (raw) register state
839 the address in which a function should return its structure value,
840 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 841static CORE_ADDR
48db5a3c 842sh_extract_struct_value_address (struct regcache *regcache)
cc17453a 843{
48db5a3c
CV		 844 ULONGEST addr;
845 /*FIXME: Is R0 really correct here? Not STRUCT_RETURN_REGNUM? */
846 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
847 return addr;
cc17453a
EZ		 848}
849
850static CORE_ADDR
fba45db2 851sh_frame_saved_pc (struct frame_info *frame)
cc17453a 852{
da50a4b7 853 return (get_frame_extra_info (frame)->return_pc);
cc17453a
EZ		 854}
855
c906108c
SS		 856/* Discard from the stack the innermost frame,
857 restoring all saved registers. */
cc17453a 858static void
fba45db2 859sh_pop_frame (void)
c906108c 860{
52f0bd74
AC		 861 struct frame_info *frame = get_current_frame ();
862 CORE_ADDR fp;
863 int regnum;
c906108c 864
1e2330ba
AC		 865 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
866 get_frame_base (frame),
867 get_frame_base (frame)))
c906108c
SS		 868 generic_pop_dummy_frame ();
869 else
c5aa993b 870 {
c193f6ac 871 fp = get_frame_base (frame);
f30ee0bc 872 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
c906108c 873
c5aa993b 874 /* Copy regs from where they were saved in the frame */
cd4bffcf 875 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
b2fb4676 876 if (get_frame_saved_regs (frame)[regnum])
cd4bffcf 877 write_register (regnum,
b2fb4676 878 read_memory_integer (get_frame_saved_regs (frame)[regnum], 4));
c906108c 879
da50a4b7 880 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
c5aa993b
JM		 881 write_register (SP_REGNUM, fp + 4);
882 }
c906108c
SS		 883 flush_cached_frames ();
884}
885
19f59343
MS		 886static CORE_ADDR
887sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
888{
889 return sp & ~3;
890}
891
55ff77ac 892/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 893 Setup the function arguments for calling a function in the inferior.
894
895 On the Hitachi SH architecture, there are four registers (R4 to R7)
896 which are dedicated for passing function arguments. Up to the first
897 four arguments (depending on size) may go into these registers.
898 The rest go on the stack.
899
6df2bf50
MS		 900 MVS: Except on SH variants that have floating point registers.
901 In that case, float and double arguments are passed in the same
902 manner, but using FP registers instead of GP registers.
903
c906108c
SS		 904 Arguments that are smaller than 4 bytes will still take up a whole
905 register or a whole 32-bit word on the stack, and will be
906 right-justified in the register or the stack word. This includes
907 chars, shorts, and small aggregate types.
908
909 Arguments that are larger than 4 bytes may be split between two or
910 more registers. If there are not enough registers free, an argument
911 may be passed partly in a register (or registers), and partly on the
912 stack. This includes doubles, long longs, and larger aggregates.
913 As far as I know, there is no upper limit to the size of aggregates
914 that will be passed in this way; in other words, the convention of
915 passing a pointer to a large aggregate instead of a copy is not used.
916
6df2bf50 917 MVS: The above appears to be true for the SH variants that do not
55ff77ac 918 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 919 aggregate argument onto the stack (and not place it in registers)
920 if it is larger than 16 bytes (four GP registers).
921
c906108c
SS		 922 An exceptional case exists for struct arguments (and possibly other
923 aggregates such as arrays) if the size is larger than 4 bytes but
924 not a multiple of 4 bytes. In this case the argument is never split
925 between the registers and the stack, but instead is copied in its
926 entirety onto the stack, AND also copied into as many registers as
927 there is room for. In other words, space in registers permitting,
928 two copies of the same argument are passed in. As far as I can tell,
929 only the one on the stack is used, although that may be a function
930 of the level of compiler optimization. I suspect this is a compiler
931 bug. Arguments of these odd sizes are left-justified within the
932 word (as opposed to arguments smaller than 4 bytes, which are
933 right-justified).
c5aa993b 934
c906108c
SS		 935 If the function is to return an aggregate type such as a struct, it
936 is either returned in the normal return value register R0 (if its
937 size is no greater than one byte), or else the caller must allocate
938 space into which the callee will copy the return value (if the size
939 is greater than one byte). In this case, a pointer to the return
940 value location is passed into the callee in register R2, which does
941 not displace any of the other arguments passed in via registers R4
942 to R7. */
943
cc17453a 944static CORE_ADDR
6df2bf50
MS		 945sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
946 CORE_ADDR func_addr,
947 struct regcache *regcache,
948 CORE_ADDR bp_addr, int nargs,
949 struct value **args,
950 CORE_ADDR sp, int struct_return,
951 CORE_ADDR struct_addr)
952{
953 int stack_offset, stack_alloc;
954 int argreg, flt_argreg;
955 int argnum;
956 struct type *type;
957 CORE_ADDR regval;
958 char *val;
959 char valbuf[4];
960 int len;
961 int odd_sized_struct;
962 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
963
964 /* first force sp to a 4-byte alignment */
965 sp = sh_frame_align (gdbarch, sp);
966
967 /* The "struct return pointer" pseudo-argument has its own dedicated
968 register */
969 if (struct_return)
970 regcache_cooked_write_unsigned (regcache,
971 STRUCT_RETURN_REGNUM,
972 struct_addr);
973
974 /* Now make sure there's space on the stack */
975 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
976 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
977 sp -= stack_alloc; /* make room on stack for args */
978
979 /* Now load as many as possible of the first arguments into
980 registers, and push the rest onto the stack. There are 16 bytes
981 in four registers available. Loop thru args from first to last. */
982
55ff77ac
CV		 983 argreg = ARG0_REGNUM;
984 flt_argreg = FLOAT_ARG0_REGNUM;
6df2bf50
MS		 985 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
986 {
987 type = VALUE_TYPE (args[argnum]);
988 len = TYPE_LENGTH (type);
989 memset (valbuf, 0, sizeof (valbuf));
990 if (len < 4)
991 {
992 /* value gets right-justified in the register or stack word */
993 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
994 memcpy (valbuf + (4 - len),
995 (char *) VALUE_CONTENTS (args[argnum]), len);
996 else
997 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
998 val = valbuf;
999 }
1000 else
1001 val = (char *) VALUE_CONTENTS (args[argnum]);
48db5a3c 1002
6df2bf50
MS		 1003 if (len > 4 && (len & 3) != 0)
1004 odd_sized_struct = 1; /* Such structs go entirely on stack. */
1005 else if (len > 16)
1006 odd_sized_struct = 1; /* So do aggregates bigger than 4 words. */
1007 else
1008 odd_sized_struct = 0;
1009 while (len > 0)
1010 {
1011 if ((TYPE_CODE (type) == TYPE_CODE_FLT
55ff77ac
CV		 1012 && flt_argreg > FLOAT_ARGLAST_REGNUM)
1013 || argreg > ARGLAST_REGNUM
6df2bf50
MS		 1014 || odd_sized_struct)
1015 {
1016 /* must go on the stack */
1017 write_memory (sp + stack_offset, val, 4);
1018 stack_offset += 4;
1019 }
1020 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1021 That's because some *&^%$ things get passed on the stack
1022 AND in the registers! */
1023 if (TYPE_CODE (type) == TYPE_CODE_FLT &&
55ff77ac 1024 flt_argreg > 0 && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50
MS		 1025 {
1026 /* Argument goes in a single-precision fp reg. */
1027 regval = extract_unsigned_integer (val, register_size (gdbarch,
1028 argreg));
1029 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1030 }
55ff77ac 1031 else if (argreg <= ARGLAST_REGNUM)
6df2bf50
MS		 1032 {
1033 /* there's room in a register */
1034 regval = extract_unsigned_integer (val, register_size (gdbarch,
1035 argreg));
1036 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1037 }
1038 /* Store the value 4 bytes at a time. This means that things
1039 larger than 4 bytes may go partly in registers and partly
1040 on the stack. */
1041 len -= register_size (gdbarch, argreg);
1042 val += register_size (gdbarch, argreg);
1043 }
1044 }
1045
1046 /* Store return address. */
55ff77ac 1047 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1048
1049 /* Update stack pointer. */
1050 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1051
1052 return sp;
1053}
1054
1055static CORE_ADDR
1056sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1057 CORE_ADDR func_addr,
1058 struct regcache *regcache,
1059 CORE_ADDR bp_addr,
1060 int nargs, struct value **args,
1061 CORE_ADDR sp, int struct_return,
1062 CORE_ADDR struct_addr)
c906108c
SS		 1063{
1064 int stack_offset, stack_alloc;
1065 int argreg;
1066 int argnum;
1067 struct type *type;
1068 CORE_ADDR regval;
1069 char *val;
1070 char valbuf[4];
1071 int len;
1072 int odd_sized_struct;
48db5a3c 1073 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c906108c
SS		 1074
1075 /* first force sp to a 4-byte alignment */
19f59343 1076 sp = sh_frame_align (gdbarch, sp);
c906108c
SS		 1077
1078 /* The "struct return pointer" pseudo-argument has its own dedicated
1079 register */
1080 if (struct_return)
55ff77ac
CV		 1081 regcache_cooked_write_unsigned (regcache,
1082 STRUCT_RETURN_REGNUM,
6df2bf50 1083 struct_addr);
c906108c
SS		 1084
1085 /* Now make sure there's space on the stack */
cc17453a 1086 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 1087 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
1088 sp -= stack_alloc; /* make room on stack for args */
c906108c 1089
c906108c
SS		 1090 /* Now load as many as possible of the first arguments into
1091 registers, and push the rest onto the stack. There are 16 bytes
1092 in four registers available. Loop thru args from first to last. */
1093
55ff77ac 1094 argreg = ARG0_REGNUM;
c906108c
SS		 1095 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1096 {
1097 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 1098 len = TYPE_LENGTH (type);
1099 memset (valbuf, 0, sizeof (valbuf));
c906108c 1100 if (len < 4)
cc17453a
EZ		 1101 {
1102 /* value gets right-justified in the register or stack word */
7079c36c
CV		 1103 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1104 memcpy (valbuf + (4 - len),
1105 (char *) VALUE_CONTENTS (args[argnum]), len);
1106 else
1107 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
c5aa993b
JM		 1108 val = valbuf;
1109 }
c906108c 1110 else
c5aa993b 1111 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 1112
1113 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 1114 odd_sized_struct = 1; /* such structs go entirely on stack */
1115 else
c906108c
SS		 1116 odd_sized_struct = 0;
1117 while (len > 0)
1118 {
55ff77ac 1119 if (argreg > ARGLAST_REGNUM
3bbfbb92
EZ		 1120 || odd_sized_struct)
1121 {
1122 /* must go on the stack */
c906108c
SS		 1123 write_memory (sp + stack_offset, val, 4);
1124 stack_offset += 4;
1125 }
1126 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1127 That's because some *&^%$ things get passed on the stack
1128 AND in the registers! */
55ff77ac 1129 if (argreg <= ARGLAST_REGNUM)
3bbfbb92
EZ		 1130 {
1131 /* there's room in a register */
48db5a3c
CV		 1132 regval = extract_unsigned_integer (val, register_size (gdbarch,
1133 argreg));
1134 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c
SS		 1135 }
1136 /* Store the value 4 bytes at a time. This means that things
1137 larger than 4 bytes may go partly in registers and partly
1138 on the stack. */
48db5a3c
CV		 1139 len -= register_size (gdbarch, argreg);
1140 val += register_size (gdbarch, argreg);
c906108c
SS		 1141 }
1142 }
48db5a3c
CV		 1143
1144 /* Store return address. */
55ff77ac 1145 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1146
1147 /* Update stack pointer. */
1148 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1149
c906108c
SS		 1150 return sp;
1151}
1152
cc17453a
EZ		 1153/* Find a function's return value in the appropriate registers (in
1154 regbuf), and copy it into valbuf. Extract from an array REGBUF
1155 containing the (raw) register state a function return value of type
1156 TYPE, and copy that, in virtual format, into VALBUF. */
1157static void
48db5a3c
CV		 1158sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1159 void *valbuf)
c906108c 1160{
cc17453a 1161 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1162 int return_register = R0_REGNUM;
1163 int offset;
1164
cc17453a 1165 if (len <= 4)
3116c80a 1166 {
48db5a3c
CV		 1167 ULONGEST c;
1168
1169 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1170 store_unsigned_integer (valbuf, len, c);
3116c80a 1171 }
48db5a3c 1172 else if (len == 8)
3116c80a 1173 {
48db5a3c
CV		 1174 int i, regnum = R0_REGNUM;
1175 for (i = 0; i < len; i += 4)
1176 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
3116c80a
EZ		 1177 }
1178 else
1179 error ("bad size for return value");
1180}
1181
1182static void
48db5a3c
CV		 1183sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1184 void *valbuf)
3116c80a 1185{
3116c80a 1186 if (TYPE_CODE (type) == TYPE_CODE_FLT)
3116c80a 1187 {
48db5a3c
CV		 1188 int len = TYPE_LENGTH (type);
1189 int i, regnum = FP0_REGNUM;
1190 for (i = 0; i < len; i += 4)
1191 regcache_raw_read (regcache, regnum++, (char *)valbuf + i);
3116c80a 1192 }
cc17453a 1193 else
48db5a3c 1194 sh_default_extract_return_value (type, regcache, valbuf);
cc17453a 1195}
c906108c 1196
cc17453a
EZ		 1197/* Write into appropriate registers a function return value
1198 of type TYPE, given in virtual format.
1199 If the architecture is sh4 or sh3e, store a function's return value
1200 in the R0 general register or in the FP0 floating point register,
1201 depending on the type of the return value. In all the other cases
3bbfbb92 1202 the result is stored in r0, left-justified. */
cc17453a 1203static void
48db5a3c
CV		 1204sh_default_store_return_value (struct type *type, struct regcache *regcache,
1205 const void *valbuf)
cc17453a 1206{
48db5a3c
CV		 1207 ULONGEST val;
1208 int len = TYPE_LENGTH (type);
d19b71be 1209
48db5a3c 1210 if (len <= 4)
d19b71be 1211 {
48db5a3c
CV		 1212 val = extract_unsigned_integer (valbuf, len);
1213 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1214 }
1215 else
48db5a3c
CV		 1216 {
1217 int i, regnum = R0_REGNUM;
1218 for (i = 0; i < len; i += 4)
1219 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
1220 }
cc17453a 1221}
c906108c 1222
cc17453a 1223static void
48db5a3c
CV		 1224sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1225 const void *valbuf)
cc17453a
EZ		 1226{
1227 if (TYPE_CODE (type) == TYPE_CODE_FLT)
48db5a3c
CV		 1228 {
1229 int len = TYPE_LENGTH (type);
1230 int i, regnum = FP0_REGNUM;
1231 for (i = 0; i < len; i += 4)
1232 regcache_raw_write (regcache, regnum++, (char *)valbuf + i);
1233 }
cc17453a 1234 else
48db5a3c 1235 sh_default_store_return_value (type, regcache, valbuf);
c906108c
SS		 1236}
1237
1238/* Print the registers in a form similar to the E7000 */
1239
1240static void
fba45db2 1241sh_generic_show_regs (void)
c906108c 1242{
f81353e4
EZ		 1243 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1244
cc17453a
EZ		 1245 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1246 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1247 (long) read_register (SR_REGNUM),
1248 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1249 (long) read_register (MACH_REGNUM),
1250 (long) read_register (MACL_REGNUM));
1251
1252 printf_filtered ("GBR=%08lx VBR=%08lx",
1253 (long) read_register (GBR_REGNUM),
1254 (long) read_register (VBR_REGNUM));
1255
1256 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1257 (long) read_register (0),
1258 (long) read_register (1),
1259 (long) read_register (2),
1260 (long) read_register (3),
1261 (long) read_register (4),
1262 (long) read_register (5),
1263 (long) read_register (6),
1264 (long) read_register (7));
1265 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1266 (long) read_register (8),
1267 (long) read_register (9),
1268 (long) read_register (10),
1269 (long) read_register (11),
1270 (long) read_register (12),
1271 (long) read_register (13),
1272 (long) read_register (14),
1273 (long) read_register (15));
1274}
c906108c 1275
cc17453a 1276static void
fba45db2 1277sh3_show_regs (void)
cc17453a 1278{
f81353e4
EZ		 1279 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1280
d4f3574e
SS		 1281 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1282 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1283 (long) read_register (SR_REGNUM),
1284 (long) read_register (PR_REGNUM),
d4f3574e
SS		 1285 (long) read_register (MACH_REGNUM),
1286 (long) read_register (MACL_REGNUM));
1287
1288 printf_filtered ("GBR=%08lx VBR=%08lx",
1289 (long) read_register (GBR_REGNUM),
1290 (long) read_register (VBR_REGNUM));
cc17453a 1291 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1292 (long) read_register (tdep->SSR_REGNUM),
1293 (long) read_register (tdep->SPC_REGNUM));
c906108c 1294
d4f3574e
SS		 1295 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1296 (long) read_register (0),
1297 (long) read_register (1),
1298 (long) read_register (2),
1299 (long) read_register (3),
1300 (long) read_register (4),
1301 (long) read_register (5),
1302 (long) read_register (6),
1303 (long) read_register (7));
1304 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1305 (long) read_register (8),
1306 (long) read_register (9),
1307 (long) read_register (10),
1308 (long) read_register (11),
1309 (long) read_register (12),
1310 (long) read_register (13),
1311 (long) read_register (14),
1312 (long) read_register (15));
c906108c
SS		 1313}
1314
53116e27 1315
2d188dd3
NC		 1316static void
1317sh2e_show_regs (void)
1318{
1319 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1320 paddr (read_register (PC_REGNUM)),
1321 (long) read_register (SR_REGNUM),
1322 (long) read_register (PR_REGNUM),
1323 (long) read_register (MACH_REGNUM),
1324 (long) read_register (MACL_REGNUM));
1325
1326 printf_filtered ("GBR=%08lx VBR=%08lx",
1327 (long) read_register (GBR_REGNUM),
1328 (long) read_register (VBR_REGNUM));
1329 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1330 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1331 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
1332
1333 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1334 (long) read_register (0),
1335 (long) read_register (1),
1336 (long) read_register (2),
1337 (long) read_register (3),
1338 (long) read_register (4),
1339 (long) read_register (5),
1340 (long) read_register (6),
1341 (long) read_register (7));
1342 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1343 (long) read_register (8),
1344 (long) read_register (9),
1345 (long) read_register (10),
1346 (long) read_register (11),
1347 (long) read_register (12),
1348 (long) read_register (13),
1349 (long) read_register (14),
1350 (long) read_register (15));
1351
1352 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1353 (long) read_register (FP0_REGNUM + 0),
1354 (long) read_register (FP0_REGNUM + 1),
1355 (long) read_register (FP0_REGNUM + 2),
1356 (long) read_register (FP0_REGNUM + 3),
1357 (long) read_register (FP0_REGNUM + 4),
1358 (long) read_register (FP0_REGNUM + 5),
1359 (long) read_register (FP0_REGNUM + 6),
1360 (long) read_register (FP0_REGNUM + 7));
1361 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1362 (long) read_register (FP0_REGNUM + 8),
1363 (long) read_register (FP0_REGNUM + 9),
1364 (long) read_register (FP0_REGNUM + 10),
1365 (long) read_register (FP0_REGNUM + 11),
1366 (long) read_register (FP0_REGNUM + 12),
1367 (long) read_register (FP0_REGNUM + 13),
1368 (long) read_register (FP0_REGNUM + 14),
1369 (long) read_register (FP0_REGNUM + 15));
1370}
1371
cc17453a 1372static void
fba45db2 1373sh3e_show_regs (void)
cc17453a 1374{
f81353e4
EZ		 1375 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1376
cc17453a
EZ		 1377 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1378 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1379 (long) read_register (SR_REGNUM),
1380 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1381 (long) read_register (MACH_REGNUM),
1382 (long) read_register (MACL_REGNUM));
1383
1384 printf_filtered ("GBR=%08lx VBR=%08lx",
1385 (long) read_register (GBR_REGNUM),
1386 (long) read_register (VBR_REGNUM));
1387 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1388 (long) read_register (tdep->SSR_REGNUM),
1389 (long) read_register (tdep->SPC_REGNUM));
cc17453a 1390 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 1391 (long) read_register (tdep->FPUL_REGNUM),
1392 (long) read_register (tdep->FPSCR_REGNUM));
c906108c 1393
cc17453a
EZ		 1394 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1395 (long) read_register (0),
1396 (long) read_register (1),
1397 (long) read_register (2),
1398 (long) read_register (3),
1399 (long) read_register (4),
1400 (long) read_register (5),
1401 (long) read_register (6),
1402 (long) read_register (7));
1403 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1404 (long) read_register (8),
1405 (long) read_register (9),
1406 (long) read_register (10),
1407 (long) read_register (11),
1408 (long) read_register (12),
1409 (long) read_register (13),
1410 (long) read_register (14),
1411 (long) read_register (15));
1412
1413 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1414 (long) read_register (FP0_REGNUM + 0),
1415 (long) read_register (FP0_REGNUM + 1),
1416 (long) read_register (FP0_REGNUM + 2),
1417 (long) read_register (FP0_REGNUM + 3),
1418 (long) read_register (FP0_REGNUM + 4),
1419 (long) read_register (FP0_REGNUM + 5),
1420 (long) read_register (FP0_REGNUM + 6),
1421 (long) read_register (FP0_REGNUM + 7));
1422 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1423 (long) read_register (FP0_REGNUM + 8),
1424 (long) read_register (FP0_REGNUM + 9),
1425 (long) read_register (FP0_REGNUM + 10),
1426 (long) read_register (FP0_REGNUM + 11),
1427 (long) read_register (FP0_REGNUM + 12),
1428 (long) read_register (FP0_REGNUM + 13),
1429 (long) read_register (FP0_REGNUM + 14),
1430 (long) read_register (FP0_REGNUM + 15));
1431}
1432
1433static void
fba45db2 1434sh3_dsp_show_regs (void)
c906108c 1435{
f81353e4
EZ		 1436 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1437
cc17453a
EZ		 1438 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1439 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1440 (long) read_register (SR_REGNUM),
1441 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1442 (long) read_register (MACH_REGNUM),
1443 (long) read_register (MACL_REGNUM));
c906108c 1444
cc17453a
EZ		 1445 printf_filtered ("GBR=%08lx VBR=%08lx",
1446 (long) read_register (GBR_REGNUM),
1447 (long) read_register (VBR_REGNUM));
1448
1449 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1450 (long) read_register (tdep->SSR_REGNUM),
1451 (long) read_register (tdep->SPC_REGNUM));
cc17453a
EZ		 1452
1453 printf_filtered (" DSR=%08lx",
f81353e4 1454 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 1455
1456 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1457 (long) read_register (0),
1458 (long) read_register (1),
1459 (long) read_register (2),
1460 (long) read_register (3),
1461 (long) read_register (4),
1462 (long) read_register (5),
1463 (long) read_register (6),
1464 (long) read_register (7));
1465 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1466 (long) read_register (8),
1467 (long) read_register (9),
1468 (long) read_register (10),
1469 (long) read_register (11),
1470 (long) read_register (12),
1471 (long) read_register (13),
1472 (long) read_register (14),
1473 (long) read_register (15));
1474
1475 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 1476 (long) read_register (tdep->A0G_REGNUM) & 0xff,
1477 (long) read_register (tdep->A0_REGNUM),
1478 (long) read_register (tdep->M0_REGNUM),
1479 (long) read_register (tdep->X0_REGNUM),
1480 (long) read_register (tdep->Y0_REGNUM),
1481 (long) read_register (tdep->RS_REGNUM),
1482 (long) read_register (tdep->MOD_REGNUM));
cc17453a 1483 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 1484 (long) read_register (tdep->A1G_REGNUM) & 0xff,
1485 (long) read_register (tdep->A1_REGNUM),
1486 (long) read_register (tdep->M1_REGNUM),
1487 (long) read_register (tdep->X1_REGNUM),
1488 (long) read_register (tdep->Y1_REGNUM),
1489 (long) read_register (tdep->RE_REGNUM));
c906108c
SS		 1490}
1491
cc17453a 1492static void
fba45db2 1493sh4_show_regs (void)
cc17453a 1494{
f81353e4
EZ		 1495 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1496
1497 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
cc17453a
EZ		 1498 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1499 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1500 (long) read_register (SR_REGNUM),
1501 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1502 (long) read_register (MACH_REGNUM),
1503 (long) read_register (MACL_REGNUM));
1504
1505 printf_filtered ("GBR=%08lx VBR=%08lx",
1506 (long) read_register (GBR_REGNUM),
1507 (long) read_register (VBR_REGNUM));
1508 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1509 (long) read_register (tdep->SSR_REGNUM),
1510 (long) read_register (tdep->SPC_REGNUM));
cc17453a 1511 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 1512 (long) read_register (tdep->FPUL_REGNUM),
1513 (long) read_register (tdep->FPSCR_REGNUM));
cc17453a
EZ		 1514
1515 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1516 (long) read_register (0),
1517 (long) read_register (1),
1518 (long) read_register (2),
1519 (long) read_register (3),
1520 (long) read_register (4),
1521 (long) read_register (5),
1522 (long) read_register (6),
1523 (long) read_register (7));
1524 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1525 (long) read_register (8),
1526 (long) read_register (9),
1527 (long) read_register (10),
1528 (long) read_register (11),
1529 (long) read_register (12),
1530 (long) read_register (13),
1531 (long) read_register (14),
1532 (long) read_register (15));
1533
1534 printf_filtered ((pr
1535 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1536 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1537 (long) read_register (FP0_REGNUM + 0),
1538 (long) read_register (FP0_REGNUM + 1),
1539 (long) read_register (FP0_REGNUM + 2),
1540 (long) read_register (FP0_REGNUM + 3),
1541 (long) read_register (FP0_REGNUM + 4),
1542 (long) read_register (FP0_REGNUM + 5),
1543 (long) read_register (FP0_REGNUM + 6),
1544 (long) read_register (FP0_REGNUM + 7));
1545 printf_filtered ((pr
1546 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1547 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1548 (long) read_register (FP0_REGNUM + 8),
1549 (long) read_register (FP0_REGNUM + 9),
1550 (long) read_register (FP0_REGNUM + 10),
1551 (long) read_register (FP0_REGNUM + 11),
1552 (long) read_register (FP0_REGNUM + 12),
1553 (long) read_register (FP0_REGNUM + 13),
1554 (long) read_register (FP0_REGNUM + 14),
1555 (long) read_register (FP0_REGNUM + 15));
1556}
1557
1558static void
fba45db2 1559sh_dsp_show_regs (void)
cc17453a 1560{
f81353e4
EZ		 1561 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1562
cc17453a
EZ		 1563 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1564 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1565 (long) read_register (SR_REGNUM),
1566 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1567 (long) read_register (MACH_REGNUM),
1568 (long) read_register (MACL_REGNUM));
1569
1570 printf_filtered ("GBR=%08lx VBR=%08lx",
1571 (long) read_register (GBR_REGNUM),
1572 (long) read_register (VBR_REGNUM));
1573
1574 printf_filtered (" DSR=%08lx",
f81353e4 1575 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 1576
1577 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1578 (long) read_register (0),
1579 (long) read_register (1),
1580 (long) read_register (2),
1581 (long) read_register (3),
1582 (long) read_register (4),
1583 (long) read_register (5),
1584 (long) read_register (6),
1585 (long) read_register (7));
1586 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1587 (long) read_register (8),
1588 (long) read_register (9),
1589 (long) read_register (10),
1590 (long) read_register (11),
1591 (long) read_register (12),
1592 (long) read_register (13),
1593 (long) read_register (14),
1594 (long) read_register (15));
1595
1596 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 1597 (long) read_register (tdep->A0G_REGNUM) & 0xff,
1598 (long) read_register (tdep->A0_REGNUM),
1599 (long) read_register (tdep->M0_REGNUM),
1600 (long) read_register (tdep->X0_REGNUM),
1601 (long) read_register (tdep->Y0_REGNUM),
1602 (long) read_register (tdep->RS_REGNUM),
1603 (long) read_register (tdep->MOD_REGNUM));
cc17453a 1604 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 1605 (long) read_register (tdep->A1G_REGNUM) & 0xff,
1606 (long) read_register (tdep->A1_REGNUM),
1607 (long) read_register (tdep->M1_REGNUM),
1608 (long) read_register (tdep->X1_REGNUM),
1609 (long) read_register (tdep->Y1_REGNUM),
1610 (long) read_register (tdep->RE_REGNUM));
cc17453a
EZ		 1611}
1612
a78f21af
AC		 1613static void
1614sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 1615{
1616 if (sh_show_regs)
1617 (*sh_show_regs)();
1618}
1619
cc17453a
EZ		 1620/* Return the GDB type object for the "standard" data type
1621 of data in register N. */
cc17453a 1622static struct type *
48db5a3c 1623sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 1624{
f81353e4
EZ		 1625 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1626
cc17453a 1627 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 1628 && (reg_nr <= tdep->FP_LAST_REGNUM))
1629 || (reg_nr == tdep->FPUL_REGNUM))
cc17453a 1630 return builtin_type_float;
8db62801 1631 else
cc17453a
EZ		 1632 return builtin_type_int;
1633}
1634
7f4dbe94
EZ		 1635static struct type *
1636sh_sh4_build_float_register_type (int high)
1637{
1638 struct type *temp;
1639
1640 temp = create_range_type (NULL, builtin_type_int, 0, high);
1641 return create_array_type (NULL, builtin_type_float, temp);
1642}
1643
53116e27 1644static struct type *
48db5a3c 1645sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27 1646{
48db5a3c 1647 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
f81353e4 1648
53116e27 1649 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 1650 && (reg_nr <= tdep->FP_LAST_REGNUM))
1651 || (reg_nr == tdep->FPUL_REGNUM))
53116e27 1652 return builtin_type_float;
f81353e4
EZ		 1653 else if (reg_nr >= tdep->DR0_REGNUM
1654 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 1655 return builtin_type_double;
f81353e4
EZ		 1656 else if (reg_nr >= tdep->FV0_REGNUM
1657 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1658 return sh_sh4_build_float_register_type (3);
1659 else
1660 return builtin_type_int;
1661}
1662
cc17453a 1663static struct type *
48db5a3c 1664sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ		 1665{
1666 return builtin_type_int;
1667}
1668
fb409745
EZ		 1669/* On the sh4, the DRi pseudo registers are problematic if the target
1670 is little endian. When the user writes one of those registers, for
1671 instance with 'ser var $dr0=1', we want the double to be stored
1672 like this:
1673 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1674 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1675
1676 This corresponds to little endian byte order & big endian word
1677 order. However if we let gdb write the register w/o conversion, it
1678 will write fr0 and fr1 this way:
1679 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1680 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1681 because it will consider fr0 and fr1 as a single LE stretch of memory.
1682
1683 To achieve what we want we must force gdb to store things in
1684 floatformat_ieee_double_littlebyte_bigword (which is defined in
1685 include/floatformat.h and libiberty/floatformat.c.
1686
1687 In case the target is big endian, there is no problem, the
1688 raw bytes will look like:
1689 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1690 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1691
1692 The other pseudo registers (the FVs) also don't pose a problem
1693 because they are stored as 4 individual FP elements. */
1694
7bd872fe 1695static void
fb409745
EZ		 1696sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1697 char *from, char *to)
55ff77ac
CV		 1698{
1699 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
283150cd 1700
55ff77ac
CV		 1701 if (regnum >= tdep->DR0_REGNUM
1702 && regnum <= tdep->DR_LAST_REGNUM)
283150cd
EZ		 1703 {
1704 DOUBLEST val;
1705 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
55ff77ac 1706 store_typed_floating (to, type, val);
283150cd
EZ		 1707 }
1708 else
55ff77ac 1709 error ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 1710}
1711
1712static void
1713sh_sh4_register_convert_to_raw (struct type *type, int regnum,
d8124050 1714 const void *from, void *to)
283150cd
EZ		 1715{
1716 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1717
1718 if (regnum >= tdep->DR0_REGNUM
1719 && regnum <= tdep->DR_LAST_REGNUM)
1720 {
48db5a3c 1721 DOUBLEST val = extract_typed_floating (from, type);
283150cd
EZ		 1722 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1723 }
1724 else
1725 error("sh_register_convert_to_raw called with non DR register number");
1726}
1727
a78f21af 1728static void
d8124050
AC		 1729sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1730 int reg_nr, void *buffer)
53116e27
EZ		 1731{
1732 int base_regnum, portion;
d9d9c31f 1733 char temp_buffer[MAX_REGISTER_SIZE];
d8124050 1734 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53116e27 1735
7bd872fe
EZ		 1736 if (reg_nr >= tdep->DR0_REGNUM
1737 && reg_nr <= tdep->DR_LAST_REGNUM)
1738 {
1739 base_regnum = dr_reg_base_num (reg_nr);
1740
1741 /* Build the value in the provided buffer. */
1742 /* Read the real regs for which this one is an alias. */
1743 for (portion = 0; portion < 2; portion++)
d8124050 1744 regcache_raw_read (regcache, base_regnum + portion,
0818c12a 1745 (temp_buffer
48db5a3c 1746 + register_size (gdbarch, base_regnum) * portion));
7bd872fe
EZ		 1747 /* We must pay attention to the endiannes. */
1748 sh_sh4_register_convert_to_virtual (reg_nr,
48db5a3c 1749 gdbarch_register_type (gdbarch, reg_nr),
7bd872fe
EZ		 1750 temp_buffer, buffer);
1751 }
1752 else if (reg_nr >= tdep->FV0_REGNUM
1753 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27 1754 {
7bd872fe
EZ		 1755 base_regnum = fv_reg_base_num (reg_nr);
1756
1757 /* Read the real regs for which this one is an alias. */
1758 for (portion = 0; portion < 4; portion++)
d8124050
AC		 1759 regcache_raw_read (regcache, base_regnum + portion,
1760 ((char *) buffer
48db5a3c 1761 + register_size (gdbarch, base_regnum) * portion));
53116e27
EZ		 1762 }
1763}
1764
a78f21af 1765static void
d8124050
AC		 1766sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1767 int reg_nr, const void *buffer)
53116e27
EZ		 1768{
1769 int base_regnum, portion;
d9d9c31f 1770 char temp_buffer[MAX_REGISTER_SIZE];
d8124050 1771 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
53116e27 1772
f81353e4
EZ		 1773 if (reg_nr >= tdep->DR0_REGNUM
1774 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27
EZ		 1775 {
1776 base_regnum = dr_reg_base_num (reg_nr);
1777
7bd872fe 1778 /* We must pay attention to the endiannes. */
48db5a3c 1779 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr,
7bd872fe
EZ		 1780 buffer, temp_buffer);
1781
53116e27
EZ		 1782 /* Write the real regs for which this one is an alias. */
1783 for (portion = 0; portion < 2; portion++)
d8124050 1784 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 1785 (temp_buffer
48db5a3c 1786 + register_size (gdbarch, base_regnum) * portion));
53116e27 1787 }
f81353e4
EZ		 1788 else if (reg_nr >= tdep->FV0_REGNUM
1789 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1790 {
1791 base_regnum = fv_reg_base_num (reg_nr);
1792
1793 /* Write the real regs for which this one is an alias. */
1794 for (portion = 0; portion < 4; portion++)
d8124050
AC		 1795 regcache_raw_write (regcache, base_regnum + portion,
1796 ((char *) buffer
48db5a3c 1797 + register_size (gdbarch, base_regnum) * portion));
53116e27
EZ		 1798 }
1799}
1800
3bbfbb92 1801/* Floating point vector of 4 float registers. */
53116e27 1802static void
48db5a3c
CV		 1803do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1804 int fv_regnum)
53116e27
EZ		 1805{
1806 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
48db5a3c
CV		 1807 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1808 fv_regnum - gdbarch_tdep (gdbarch)->FV0_REGNUM,
53116e27
EZ		 1809 (int) read_register (first_fp_reg_num),
1810 (int) read_register (first_fp_reg_num + 1),
1811 (int) read_register (first_fp_reg_num + 2),
1812 (int) read_register (first_fp_reg_num + 3));
1813}
1814
3bbfbb92 1815/* Double precision registers. */
53116e27 1816static void
48db5a3c
CV		 1817do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1818 int dr_regnum)
53116e27
EZ		 1819{
1820 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1821
48db5a3c
CV		 1822 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1823 dr_regnum - gdbarch_tdep (gdbarch)->DR0_REGNUM,
53116e27
EZ		 1824 (int) read_register (first_fp_reg_num),
1825 (int) read_register (first_fp_reg_num + 1));
1826}
1827
1828static void
48db5a3c
CV		 1829sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1830 int regnum)
53116e27 1831{
48db5a3c 1832 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
f81353e4 1833
53116e27 1834 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1835 internal_error (__FILE__, __LINE__,
1836 "Invalid pseudo register number %d\n", regnum);
f81353e4 1837 else if (regnum >= tdep->DR0_REGNUM
48db5a3c
CV		 1838 && regnum <= tdep->DR_LAST_REGNUM)
1839 do_dr_register_info (gdbarch, file, regnum);
f81353e4
EZ		 1840 else if (regnum >= tdep->FV0_REGNUM
1841 && regnum <= tdep->FV_LAST_REGNUM)
48db5a3c 1842 do_fv_register_info (gdbarch, file, regnum);
53116e27
EZ		 1843}
1844
53116e27 1845static void
48db5a3c 1846sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27
EZ		 1847{ /* do values for FP (float) regs */
1848 char *raw_buffer;
1849 double flt; /* double extracted from raw hex data */
1850 int inv;
1851 int j;
1852
1853 /* Allocate space for the float. */
48db5a3c 1854 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
53116e27
EZ		 1855
1856 /* Get the data in raw format. */
48db5a3c 1857 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
53116e27
EZ		 1858 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1859
1860 /* Get the register as a number */
1861 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1862
1863 /* Print the name and some spaces. */
48db5a3c
CV		 1864 fputs_filtered (REGISTER_NAME (regnum), file);
1865 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
53116e27
EZ		 1866
1867 /* Print the value. */
93d56215 1868 if (inv)
48db5a3c 1869 fprintf_filtered (file, "<invalid float>");
93d56215 1870 else
48db5a3c 1871 fprintf_filtered (file, "%-10.9g", flt);
53116e27
EZ		 1872
1873 /* Print the fp register as hex. */
48db5a3c
CV		 1874 fprintf_filtered (file, "\t(raw 0x");
1875 for (j = 0; j < register_size (gdbarch, regnum); j++)
53116e27 1876 {
d7449b42 1877 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
48db5a3c
CV		 1878 : register_size (gdbarch, regnum) - 1 - j;
1879 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
53116e27 1880 }
48db5a3c
CV		 1881 fprintf_filtered (file, ")");
1882 fprintf_filtered (file, "\n");
53116e27
EZ		 1883}
1884
1885static void
48db5a3c 1886sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27 1887{
123a958e 1888 char raw_buffer[MAX_REGISTER_SIZE];
53116e27 1889
48db5a3c
CV		 1890 fputs_filtered (REGISTER_NAME (regnum), file);
1891 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
53116e27
EZ		 1892
1893 /* Get the data in raw format. */
48db5a3c
CV		 1894 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1895 fprintf_filtered (file, "*value not available*\n");
53116e27 1896
48db5a3c
CV		 1897 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1898 file, 'x', 1, 0, Val_pretty_default);
1899 fprintf_filtered (file, "\t");
1900 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1901 file, 0, 1, 0, Val_pretty_default);
1902 fprintf_filtered (file, "\n");
53116e27
EZ		 1903}
1904
1905static void
48db5a3c 1906sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27
EZ		 1907{
1908 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1909 internal_error (__FILE__, __LINE__,
1910 "Invalid register number %d\n", regnum);
53116e27 1911
e30839fe 1912 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27 1913 {
48db5a3c
CV		 1914 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
1915 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
53116e27 1916 else
48db5a3c 1917 sh_do_register (gdbarch, file, regnum); /* All other regs */
53116e27
EZ		 1918 }
1919
1920 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
48db5a3c 1921 {
55ff77ac 1922 sh_print_pseudo_register (gdbarch, file, regnum);
48db5a3c 1923 }
53116e27
EZ		 1924}
1925
a78f21af 1926static void
48db5a3c
CV		 1927sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1928 struct frame_info *frame, int regnum, int fpregs)
53116e27
EZ		 1929{
1930 if (regnum != -1) /* do one specified register */
1931 {
1932 if (*(REGISTER_NAME (regnum)) == '\0')
1933 error ("Not a valid register for the current processor type");
1934
48db5a3c 1935 sh_print_register (gdbarch, file, regnum);
53116e27
EZ		 1936 }
1937 else
1938 /* do all (or most) registers */
1939 {
1940 regnum = 0;
1941 while (regnum < NUM_REGS)
1942 {
1943 /* If the register name is empty, it is undefined for this
1944 processor, so don't display anything. */
1945 if (REGISTER_NAME (regnum) == NULL
1946 || *(REGISTER_NAME (regnum)) == '\0')
1947 {
1948 regnum++;
1949 continue;
1950 }
1951
48db5a3c 1952 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
53116e27
EZ		 1953 {
1954 if (fpregs)
1955 {
1956 /* true for "INFO ALL-REGISTERS" command */
48db5a3c 1957 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
53116e27
EZ		 1958 regnum ++;
1959 }
1960 else
48db5a3c 1961 regnum += (gdbarch_tdep (gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1962 }
1963 else
1964 {
48db5a3c 1965 sh_do_register (gdbarch, file, regnum); /* All other regs */
53116e27
EZ		 1966 regnum++;
1967 }
1968 }
1969
1970 if (fpregs)
1971 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1972 {
55ff77ac 1973 sh_print_pseudo_register (gdbarch, file, regnum);
53116e27
EZ		 1974 regnum++;
1975 }
1976 }
1977}
1978
1a8629c7
MS		 1979#ifdef SVR4_SHARED_LIBS
1980
1981/* Fetch (and possibly build) an appropriate link_map_offsets structure
1982 for native i386 linux targets using the struct offsets defined in
1983 link.h (but without actual reference to that file).
1984
1985 This makes it possible to access i386-linux shared libraries from
1986 a gdb that was not built on an i386-linux host (for cross debugging).
1987 */
1988
1989struct link_map_offsets *
1990sh_linux_svr4_fetch_link_map_offsets (void)
1991{
1992 static struct link_map_offsets lmo;
1993 static struct link_map_offsets *lmp = 0;
1994
1995 if (lmp == 0)
1996 {
1997 lmp = &lmo;
1998
1999 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2000
2001 lmo.r_map_offset = 4;
2002 lmo.r_map_size = 4;
2003
2004 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2005
2006 lmo.l_addr_offset = 0;
2007 lmo.l_addr_size = 4;
2008
2009 lmo.l_name_offset = 4;
2010 lmo.l_name_size = 4;
2011
2012 lmo.l_next_offset = 12;
2013 lmo.l_next_size = 4;
2014
2015 lmo.l_prev_offset = 16;
2016 lmo.l_prev_size = 4;
2017 }
2018
2019 return lmp;
2020}
2021#endif /* SVR4_SHARED_LIBS */
2022
2f14585c
JR		 2023\f
2024enum
2025{
2026 DSP_DSR_REGNUM = 24,
2027 DSP_A0G_REGNUM,
2028 DSP_A0_REGNUM,
2029 DSP_A1G_REGNUM,
2030 DSP_A1_REGNUM,
2031 DSP_M0_REGNUM,
2032 DSP_M1_REGNUM,
2033 DSP_X0_REGNUM,
2034 DSP_X1_REGNUM,
2035 DSP_Y0_REGNUM,
2036 DSP_Y1_REGNUM,
2037
2038 DSP_MOD_REGNUM = 40,
2039
2040 DSP_RS_REGNUM = 43,
2041 DSP_RE_REGNUM,
2042
2043 DSP_R0_BANK_REGNUM = 51,
2044 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
2045};
2046
2047static int
2048sh_dsp_register_sim_regno (int nr)
2049{
2050 if (legacy_register_sim_regno (nr) < 0)
2051 return legacy_register_sim_regno (nr);
32f63c4b 2052 if (nr >= DSP_DSR_REGNUM && nr <= DSP_Y1_REGNUM)
2f14585c
JR		 2053 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
2054 if (nr == DSP_MOD_REGNUM)
2055 return SIM_SH_MOD_REGNUM;
2056 if (nr == DSP_RS_REGNUM)
2057 return SIM_SH_RS_REGNUM;
2058 if (nr == DSP_RE_REGNUM)
2059 return SIM_SH_RE_REGNUM;
2060 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2061 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2062 return nr;
2063}
d658f924 2064\f
cc17453a
EZ		 2065static gdbarch_init_ftype sh_gdbarch_init;
2066
2067static struct gdbarch *
fba45db2 2068sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2069{
cc17453a
EZ		 2070 struct gdbarch *gdbarch;
2071 struct gdbarch_tdep *tdep;
d658f924 2072
55ff77ac
CV		 2073 sh_show_regs = sh_generic_show_regs;
2074 switch (info.bfd_arch_info->mach)
2075 {
2076 case bfd_mach_sh2e:
2077 sh_show_regs = sh2e_show_regs;
2078 break;
2079 case bfd_mach_sh_dsp:
2080 sh_show_regs = sh_dsp_show_regs;
2081 break;
2082
2083 case bfd_mach_sh3:
2084 sh_show_regs = sh3_show_regs;
2085 break;
2086
2087 case bfd_mach_sh3e:
2088 sh_show_regs = sh3e_show_regs;
2089 break;
2090
2091 case bfd_mach_sh3_dsp:
2092 sh_show_regs = sh3_dsp_show_regs;
2093 break;
2094
2095 case bfd_mach_sh4:
2096 sh_show_regs = sh4_show_regs;
2097 break;
2098
2099 case bfd_mach_sh5:
2100 sh_show_regs = sh64_show_regs;
2101 /* SH5 is handled entirely in sh64-tdep.c */
2102 return sh64_gdbarch_init (info, arches);
2103 }
2104
4be87837
DJ		 2105 /* If there is already a candidate, use it. */
2106 arches = gdbarch_list_lookup_by_info (arches, &info);
2107 if (arches != NULL)
2108 return arches->gdbarch;
cc17453a
EZ		 2109
2110 /* None found, create a new architecture from the information
2111 provided. */
2112 tdep = XMALLOC (struct gdbarch_tdep);
2113 gdbarch = gdbarch_alloc (&info, tdep);
2114
a5afb99f
AC		 2115 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2116 ready to unwind the PC first (see frame.c:get_prev_frame()). */
2117 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
2118
cc17453a
EZ		 2119 /* Initialize the register numbers that are not common to all the
2120 variants to -1, if necessary thse will be overwritten in the case
2121 statement below. */
2122 tdep->FPUL_REGNUM = -1;
2123 tdep->FPSCR_REGNUM = -1;
2124 tdep->DSR_REGNUM = -1;
e6c42fda 2125 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 2126 tdep->A0G_REGNUM = -1;
2127 tdep->A0_REGNUM = -1;
2128 tdep->A1G_REGNUM = -1;
2129 tdep->A1_REGNUM = -1;
2130 tdep->M0_REGNUM = -1;
2131 tdep->M1_REGNUM = -1;
2132 tdep->X0_REGNUM = -1;
2133 tdep->X1_REGNUM = -1;
2134 tdep->Y0_REGNUM = -1;
2135 tdep->Y1_REGNUM = -1;
2136 tdep->MOD_REGNUM = -1;
2137 tdep->RS_REGNUM = -1;
2138 tdep->RE_REGNUM = -1;
2139 tdep->SSR_REGNUM = -1;
2140 tdep->SPC_REGNUM = -1;
53116e27 2141 tdep->DR0_REGNUM = -1;
e6c42fda 2142 tdep->DR_LAST_REGNUM = -1;
53116e27 2143 tdep->FV0_REGNUM = -1;
e6c42fda 2144 tdep->FV_LAST_REGNUM = -1;
283150cd 2145
48db5a3c
CV		 2146 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2147 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2148 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2149 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2150 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2151 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2152 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2153 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2154
88e04cc1 2155 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
a38d2a54 2156 set_gdbarch_sp_regnum (gdbarch, 15);
0ba6dca9 2157 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
a38d2a54 2158 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2159 set_gdbarch_fp0_regnum (gdbarch, -1);
2160 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2161
eaf90c5d 2162 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92 2163 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
48db5a3c 2164
2bf0cb65 2165 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2f14585c 2166 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c
CV		 2167
2168 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2169
2170 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2171 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2172 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2173 set_gdbarch_function_start_offset (gdbarch, 0);
2174
2175 set_gdbarch_frame_args_skip (gdbarch, 0);
2176 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2177 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2178
48db5a3c
CV		 2179 set_gdbarch_deprecated_frame_chain (gdbarch, sh_frame_chain);
2180 set_gdbarch_deprecated_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
2181 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
2182 set_gdbarch_deprecated_pop_frame (gdbarch, sh_pop_frame);
2183 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2184 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
19f59343 2185 set_gdbarch_frame_align (gdbarch, sh_frame_align);
cc17453a
EZ		 2186
2187 switch (info.bfd_arch_info->mach)
8db62801 2188 {
cc17453a 2189 case bfd_mach_sh:
48db5a3c
CV		 2190 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2191 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2192 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2193 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2194 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2195 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
6df2bf50 2196 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
48db5a3c
CV		 2197 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2198
f30ee0bc 2199 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
cc17453a
EZ		 2200 break;
2201 case bfd_mach_sh2:
48db5a3c
CV		 2202 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2203 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2204 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2205 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2206 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2207 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
6df2bf50 2208 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
48db5a3c
CV		 2209 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2210
f30ee0bc 2211 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
cc17453a 2212 break;
2d188dd3 2213 case bfd_mach_sh2e:
48db5a3c
CV		 2214 /* doubles on sh2e and sh3e are actually 4 byte. */
2215 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2216
2217 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2218 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2219 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2220 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2d188dd3 2221 set_gdbarch_fp0_regnum (gdbarch, 25);
48db5a3c
CV		 2222 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2223 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
6df2bf50 2224 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
48db5a3c 2225 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2d188dd3
NC		 2226 tdep->FPUL_REGNUM = 23;
2227 tdep->FPSCR_REGNUM = 24;
2228 tdep->FP_LAST_REGNUM = 40;
48db5a3c 2229
55ff77ac 2230 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
2d188dd3 2231 break;
cc17453a 2232 case bfd_mach_sh_dsp:
48db5a3c
CV		 2233 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2234 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2235 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2236 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2f14585c 2237 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
48db5a3c
CV		 2238 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2239 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
6df2bf50 2240 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
48db5a3c 2241 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
cc17453a
EZ		 2242 tdep->DSR_REGNUM = 24;
2243 tdep->A0G_REGNUM = 25;
2244 tdep->A0_REGNUM = 26;
2245 tdep->A1G_REGNUM = 27;
2246 tdep->A1_REGNUM = 28;
2247 tdep->M0_REGNUM = 29;
2248 tdep->M1_REGNUM = 30;
2249 tdep->X0_REGNUM = 31;
2250 tdep->X1_REGNUM = 32;
2251 tdep->Y0_REGNUM = 33;
2252 tdep->Y1_REGNUM = 34;
2253 tdep->MOD_REGNUM = 40;
2254 tdep->RS_REGNUM = 43;
2255 tdep->RE_REGNUM = 44;
48db5a3c
CV		 2256
2257 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
cc17453a
EZ		 2258 break;
2259 case bfd_mach_sh3:
48db5a3c
CV		 2260 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2261 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2262 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2263 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2264 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2265 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
6df2bf50 2266 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
48db5a3c 2267 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
cc17453a
EZ		 2268 tdep->SSR_REGNUM = 41;
2269 tdep->SPC_REGNUM = 42;
48db5a3c
CV		 2270
2271 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
cc17453a
EZ		 2272 break;
2273 case bfd_mach_sh3e:
48db5a3c
CV		 2274 /* doubles on sh2e and sh3e are actually 4 byte. */
2275 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2276
2277 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2278 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2279 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2280 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
cc17453a 2281 set_gdbarch_fp0_regnum (gdbarch, 25);
48db5a3c
CV		 2282 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2283 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
6df2bf50 2284 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
48db5a3c 2285 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
cc17453a
EZ		 2286 tdep->FPUL_REGNUM = 23;
2287 tdep->FPSCR_REGNUM = 24;
e6c42fda 2288 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2289 tdep->SSR_REGNUM = 41;
2290 tdep->SPC_REGNUM = 42;
48db5a3c
CV		 2291
2292 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
cc17453a
EZ		 2293 break;
2294 case bfd_mach_sh3_dsp:
48db5a3c
CV		 2295 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2296 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2297 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2298 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2299 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2300 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2301 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
6df2bf50 2302 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
48db5a3c 2303 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
cc17453a
EZ		 2304 tdep->DSR_REGNUM = 24;
2305 tdep->A0G_REGNUM = 25;
2306 tdep->A0_REGNUM = 26;
2307 tdep->A1G_REGNUM = 27;
2308 tdep->A1_REGNUM = 28;
2309 tdep->M0_REGNUM = 29;
2310 tdep->M1_REGNUM = 30;
2311 tdep->X0_REGNUM = 31;
2312 tdep->X1_REGNUM = 32;
2313 tdep->Y0_REGNUM = 33;
2314 tdep->Y1_REGNUM = 34;
2315 tdep->MOD_REGNUM = 40;
2316 tdep->RS_REGNUM = 43;
2317 tdep->RE_REGNUM = 44;
2318 tdep->SSR_REGNUM = 41;
2319 tdep->SPC_REGNUM = 42;
48db5a3c
CV		 2320
2321 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
cc17453a
EZ		 2322 break;
2323 case bfd_mach_sh4:
48db5a3c
CV		 2324 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2325 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2326 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2327 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
cc17453a 2328 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27 2329 set_gdbarch_num_pseudo_regs (gdbarch, 12);
d8124050
AC		 2330 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2331 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
48db5a3c
CV		 2332 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2333 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
6df2bf50 2334 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
48db5a3c 2335 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
cc17453a
EZ		 2336 tdep->FPUL_REGNUM = 23;
2337 tdep->FPSCR_REGNUM = 24;
e6c42fda 2338 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2339 tdep->SSR_REGNUM = 41;
2340 tdep->SPC_REGNUM = 42;
53116e27 2341 tdep->DR0_REGNUM = 59;
e6c42fda 2342 tdep->DR_LAST_REGNUM = 66;
53116e27 2343 tdep->FV0_REGNUM = 67;
e6c42fda 2344 tdep->FV_LAST_REGNUM = 70;
48db5a3c
CV		 2345
2346 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
cc17453a
EZ		 2347 break;
2348 default:
48db5a3c
CV		 2349 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2350 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
48db5a3c
CV		 2351 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2352 set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code);
2353 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2354 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2355
f30ee0bc 2356 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
cc17453a 2357 break;
8db62801 2358 }
cc17453a 2359
4be87837
DJ		 2360 /* Hook in ABI-specific overrides, if they have been registered. */
2361 gdbarch_init_osabi (info, gdbarch);
d658f924 2362
cc17453a 2363 return gdbarch;
8db62801
EZ		 2364}
2365
d658f924
JT		 2366static void
2367sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2368{
2369 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2370
2371 if (tdep == NULL)
2372 return;
2373
4be87837 2374 /* FIXME: dump the rest of gdbarch_tdep. */
d658f924
JT		 2375}
2376
a78f21af
AC		 2377extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2378
c906108c 2379void
fba45db2 2380_initialize_sh_tdep (void)
c906108c
SS		 2381{
2382 struct cmd_list_element *c;
cc17453a 2383
d658f924 2384 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
c906108c 2385
53116e27 2386 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2387}
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