[binutils.git] / gdb / ia64-linux-nat.c

/* Functions specific to running gdb native on IA-64 running
   GNU/Linux.

   Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation,
   Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "defs.h"
#include "gdb_string.h"
#include "inferior.h"
#include "target.h"
#include "gdbcore.h"
#include "regcache.h"

#include <signal.h>
#include <sys/ptrace.h>
#include "gdb_wait.h"
#ifdef HAVE_SYS_REG_H
#include <sys/reg.h>
#endif
#include <sys/user.h>

#include <asm/ptrace_offsets.h>
#include <sys/procfs.h>

/* Prototypes for supply_gregset etc. */
#include "gregset.h"

/* These must match the order of the register names.

   Some sort of lookup table is needed because the offsets associated
   with the registers are all over the board.  */

static int u_offsets[] =
  {
    /* general registers */
    -1,		/* gr0 not available; i.e, it's always zero */
    PT_R1,
    PT_R2,
    PT_R3,
    PT_R4,
    PT_R5,
    PT_R6,
    PT_R7,
    PT_R8,
    PT_R9,
    PT_R10,
    PT_R11,
    PT_R12,
    PT_R13,
    PT_R14,
    PT_R15,
    PT_R16,
    PT_R17,
    PT_R18,
    PT_R19,
    PT_R20,
    PT_R21,
    PT_R22,
    PT_R23,
    PT_R24,
    PT_R25,
    PT_R26,
    PT_R27,
    PT_R28,
    PT_R29,
    PT_R30,
    PT_R31,
    /* gr32 through gr127 not directly available via the ptrace interface */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    /* Floating point registers */
    -1, -1,	/* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
    PT_F2,
    PT_F3,
    PT_F4,
    PT_F5,
    PT_F6,
    PT_F7,
    PT_F8,
    PT_F9,
    PT_F10,
    PT_F11,
    PT_F12,
    PT_F13,
    PT_F14,
    PT_F15,
    PT_F16,
    PT_F17,
    PT_F18,
    PT_F19,
    PT_F20,
    PT_F21,
    PT_F22,
    PT_F23,
    PT_F24,
    PT_F25,
    PT_F26,
    PT_F27,
    PT_F28,
    PT_F29,
    PT_F30,
    PT_F31,
    PT_F32,
    PT_F33,
    PT_F34,
    PT_F35,
    PT_F36,
    PT_F37,
    PT_F38,
    PT_F39,
    PT_F40,
    PT_F41,
    PT_F42,
    PT_F43,
    PT_F44,
    PT_F45,
    PT_F46,
    PT_F47,
    PT_F48,
    PT_F49,
    PT_F50,
    PT_F51,
    PT_F52,
    PT_F53,
    PT_F54,
    PT_F55,
    PT_F56,
    PT_F57,
    PT_F58,
    PT_F59,
    PT_F60,
    PT_F61,
    PT_F62,
    PT_F63,
    PT_F64,
    PT_F65,
    PT_F66,
    PT_F67,
    PT_F68,
    PT_F69,
    PT_F70,
    PT_F71,
    PT_F72,
    PT_F73,
    PT_F74,
    PT_F75,
    PT_F76,
    PT_F77,
    PT_F78,
    PT_F79,
    PT_F80,
    PT_F81,
    PT_F82,
    PT_F83,
    PT_F84,
    PT_F85,
    PT_F86,
    PT_F87,
    PT_F88,
    PT_F89,
    PT_F90,
    PT_F91,
    PT_F92,
    PT_F93,
    PT_F94,
    PT_F95,
    PT_F96,
    PT_F97,
    PT_F98,
    PT_F99,
    PT_F100,
    PT_F101,
    PT_F102,
    PT_F103,
    PT_F104,
    PT_F105,
    PT_F106,
    PT_F107,
    PT_F108,
    PT_F109,
    PT_F110,
    PT_F111,
    PT_F112,
    PT_F113,
    PT_F114,
    PT_F115,
    PT_F116,
    PT_F117,
    PT_F118,
    PT_F119,
    PT_F120,
    PT_F121,
    PT_F122,
    PT_F123,
    PT_F124,
    PT_F125,
    PT_F126,
    PT_F127,
    /* predicate registers - we don't fetch these individually */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* branch registers */
    PT_B0,
    PT_B1,
    PT_B2,
    PT_B3,
    PT_B4,
    PT_B5,
    PT_B6,
    PT_B7,
    /* virtual frame pointer and virtual return address pointer */
    -1, -1,
    /* other registers */
    PT_PR,
    PT_CR_IIP,	/* ip */
    PT_CR_IPSR, /* psr */
    PT_CFM,	/* cfm */
    /* kernel registers not visible via ptrace interface (?) */
    -1, -1, -1, -1, -1, -1, -1, -1,
    /* hole */
    -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_RSC,
    PT_AR_BSP,
    PT_AR_BSPSTORE,
    PT_AR_RNAT,
    -1,
    -1,		/* Not available: FCR, IA32 floating control register */
    -1, -1,
    -1,		/* Not available: EFLAG */
    -1,		/* Not available: CSD */
    -1,		/* Not available: SSD */
    -1,		/* Not available: CFLG */
    -1,		/* Not available: FSR */
    -1,		/* Not available: FIR */
    -1,		/* Not available: FDR */
    -1,
    PT_AR_CCV,
    -1, -1, -1,
    PT_AR_UNAT,
    -1, -1, -1,
    PT_AR_FPSR,
    -1, -1, -1,
    -1,		/* Not available: ITC */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1,
    PT_AR_PFS,
    PT_AR_LC,
    -1,		/* Not available: EC, the Epilog Count register */
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    -1,
    /* nat bits - not fetched directly; instead we obtain these bits from
       either rnat or unat or from memory. */
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
    -1, -1, -1, -1, -1, -1, -1, -1,
  };

CORE_ADDR
register_addr (int regno, CORE_ADDR blockend)
{
  CORE_ADDR addr;

  if (regno < 0 || regno >= NUM_REGS)
    error ("Invalid register number %d.", regno);

  if (u_offsets[regno] == -1)
    addr = 0;
  else
    addr = (CORE_ADDR) u_offsets[regno];

  return addr;
}

int ia64_cannot_fetch_register (regno)
     int regno;
{
  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
}

int ia64_cannot_store_register (regno)
     int regno;
{
  /* Rationale behind not permitting stores to bspstore...
  
     The IA-64 architecture provides bspstore and bsp which refer
     memory locations in the RSE's backing store.  bspstore is the
     next location which will be written when the RSE needs to write
     to memory.  bsp is the address at which r32 in the current frame
     would be found if it were written to the backing store.

     The IA-64 architecture provides read-only access to bsp and
     read/write access to bspstore (but only when the RSE is in
     the enforced lazy mode).  It should be noted that stores
     to bspstore also affect the value of bsp.  Changing bspstore
     does not affect the number of dirty entries between bspstore
     and bsp, so changing bspstore by N words will also cause bsp
     to be changed by (roughly) N as well.  (It could be N-1 or N+1
     depending upon where the NaT collection bits fall.)

     OTOH, the Linux kernel provides read/write access to bsp (and
     currently read/write access to bspstore as well).  But it
     is definitely the case that if you change one, the other
     will change at the same time.  It is more useful to gdb to
     be able to change bsp.  So in order to prevent strange and
     undesirable things from happening when a dummy stack frame
     is popped (after calling an inferior function), we allow
     bspstore to be read, but not written.  (Note that popping
     a (generic) dummy stack frame causes all registers that
     were previously read from the inferior process to be written
     back.)  */

  return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
         || regno == IA64_BSPSTORE_REGNUM;
}

void
supply_gregset (gregset_t *gregsetp)
{
  int regi;
  greg_t *regp = (greg_t *) gregsetp;

  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
    {
      supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
    }

  /* FIXME: NAT collection bits are at index 32; gotta deal with these
     somehow... */

  supply_register (IA64_PR_REGNUM, (char *) (regp + 33));

  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
    {
      supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
    }

  supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
  supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
  supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
  supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
  supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
  supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
  supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
  supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
  supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
  supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
  supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
  supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
  supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
}

void
fill_gregset (gregset_t *gregsetp, int regno)
{
  int regi;
  greg_t *regp = (greg_t *) gregsetp;

#define COPY_REG(_idx_,_regi_) \
  if ((regno == -1) || regno == _regi_) \
    memcpy (regp + _idx_, &deprecated_registers[REGISTER_BYTE (_regi_)], \
	    REGISTER_RAW_SIZE (_regi_))

  for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
    {
      COPY_REG (regi - IA64_GR0_REGNUM, regi);
    }

  /* FIXME: NAT collection bits at index 32? */

  COPY_REG (33, IA64_PR_REGNUM);

  for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
    {
      COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
    }

  COPY_REG (42, IA64_IP_REGNUM);
  COPY_REG (43, IA64_CFM_REGNUM);
  COPY_REG (44, IA64_PSR_REGNUM);
  COPY_REG (45, IA64_RSC_REGNUM);
  COPY_REG (46, IA64_BSP_REGNUM);
  COPY_REG (47, IA64_BSPSTORE_REGNUM);
  COPY_REG (48, IA64_RNAT_REGNUM);
  COPY_REG (49, IA64_CCV_REGNUM);
  COPY_REG (50, IA64_UNAT_REGNUM);
  COPY_REG (51, IA64_FPSR_REGNUM);
  COPY_REG (52, IA64_PFS_REGNUM);
  COPY_REG (53, IA64_LC_REGNUM);
  COPY_REG (54, IA64_EC_REGNUM);
}

/*  Given a pointer to a floating point register set in /proc format
   (fpregset_t *), unpack the register contents and supply them as gdb's
   idea of the current floating point register values. */

void
supply_fpregset (fpregset_t *fpregsetp)
{
  int regi;
  char *from;

  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
    {
      from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
      supply_register (regi, from);
    }
}

/*  Given a pointer to a floating point register set in /proc format
   (fpregset_t *), update the register specified by REGNO from gdb's idea
   of the current floating point register set.  If REGNO is -1, update
   them all. */

void
fill_fpregset (fpregset_t *fpregsetp, int regno)
{
  int regi;
  char *to;
  char *from;

  for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
    {
      if ((regno == -1) || (regno == regi))
	{
	  from = (char *) &deprecated_registers[REGISTER_BYTE (regi)];
	  to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
	  memcpy (to, from, REGISTER_RAW_SIZE (regi));
	}
    }
}

#define IA64_PSR_DB (1UL << 24)
#define IA64_PSR_DD (1UL << 39)

static void
enable_watchpoints_in_psr (ptid_t ptid)
{
  CORE_ADDR psr;

  psr = read_register_pid (IA64_PSR_REGNUM, ptid);
  if (!(psr & IA64_PSR_DB))
    {
      psr |= IA64_PSR_DB;	/* Set the db bit - this enables hardware
			           watchpoints and breakpoints. */
      write_register_pid (IA64_PSR_REGNUM, psr, ptid);
    }
}

static long
fetch_debug_register (ptid_t ptid, int idx)
{
  long val;
  int tid;

  tid = TIDGET (ptid);
  if (tid == 0)
    tid = PIDGET (ptid);

  val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0);

  return val;
}

static void
store_debug_register (ptid_t ptid, int idx, long val)
{
  int tid;

  tid = TIDGET (ptid);
  if (tid == 0)
    tid = PIDGET (ptid);

  (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val);
}

static void
fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
{
  if (dbr_addr)
    *dbr_addr = fetch_debug_register (ptid, 2 * idx);
  if (dbr_mask)
    *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
}

static void
store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
{
  if (dbr_addr)
    store_debug_register (ptid, 2 * idx, *dbr_addr);
  if (dbr_mask)
    store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
}

static int
is_power_of_2 (int val)
{
  int i, onecount;

  onecount = 0;
  for (i = 0; i < 8 * sizeof (val); i++)
    if (val & (1 << i))
      onecount++;

  return onecount <= 1;
}

int
ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
{
  int idx;
  long dbr_addr, dbr_mask;
  int max_watchpoints = 4;

  if (len <= 0 || !is_power_of_2 (len))
    return -1;

  for (idx = 0; idx < max_watchpoints; idx++)
    {
      fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
      if ((dbr_mask & (0x3UL << 62)) == 0)
	{
	  /* Exit loop if both r and w bits clear */
	  break;
	}
    }

  if (idx == max_watchpoints)
    return -1;

  dbr_addr = (long) addr;
  dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
  dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
  switch (rw)
    {
    case hw_write:
      dbr_mask |= (1L << 62);			/* Set w bit */
      break;
    case hw_read:
      dbr_mask |= (1L << 63);			/* Set r bit */
      break;
    case hw_access:
      dbr_mask |= (3L << 62);			/* Set both r and w bits */
      break;
    default:
      return -1;
    }

  store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
  enable_watchpoints_in_psr (ptid);

  return 0;
}

int
ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
{
  int idx;
  long dbr_addr, dbr_mask;
  int max_watchpoints = 4;

  if (len <= 0 || !is_power_of_2 (len))
    return -1;

  for (idx = 0; idx < max_watchpoints; idx++)
    {
      fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
      if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
	{
	  dbr_addr = 0;
	  dbr_mask = 0;
	  store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
	  return 0;
	}
    }
  return -1;
}

CORE_ADDR
ia64_linux_stopped_by_watchpoint (ptid_t ptid)
{
  CORE_ADDR psr;
  int tid;
  struct siginfo siginfo;

  tid = TIDGET(ptid);
  if (tid == 0)
    tid = PIDGET (ptid);
  
  errno = 0;
  ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo);

  if (errno != 0 || siginfo.si_signo != SIGTRAP || 
      (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
    return 0;

  psr = read_register_pid (IA64_PSR_REGNUM, ptid);
  psr |= IA64_PSR_DD;	/* Set the dd bit - this will disable the watchpoint
                           for the next instruction */
  write_register_pid (IA64_PSR_REGNUM, psr, ptid);

  return (CORE_ADDR) siginfo.si_addr;
}
Commit	Line	Data
ca557f44 AC	1	/* Functions specific to running gdb native on IA-64 running
	2	GNU/Linux.
	3
2555fe1a AC	4	Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation,
2555fe1a AC	5	Inc.
16461d7d KB	6
	7	This file is part of GDB.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2 of the License, or
	12	(at your option) any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; if not, write to the Free Software
	21	Foundation, Inc., 59 Temple Place - Suite 330,
	22	Boston, MA 02111-1307, USA. */
	23
	24	#include "defs.h"
e162d11b	25	#include "gdb_string.h"
16461d7d KB	26	#include "inferior.h"
	27	#include "target.h"
	28	#include "gdbcore.h"
4e052eda	29	#include "regcache.h"
16461d7d KB	30
	31	#include <signal.h>
	32	#include <sys/ptrace.h>
2555fe1a	33	#include "gdb_wait.h"
16461d7d KB	34	#ifdef HAVE_SYS_REG_H
	35	#include <sys/reg.h>
	36	#endif
	37	#include <sys/user.h>
	38
	39	#include <asm/ptrace_offsets.h>
	40	#include <sys/procfs.h>
	41
c60c0f5f MS	42	/* Prototypes for supply_gregset etc. */
	43	#include "gregset.h"
	44
16461d7d KB	45	/* These must match the order of the register names.
	46
	47	Some sort of lookup table is needed because the offsets associated
	48	with the registers are all over the board. */
	49
	50	static int u_offsets[] =
	51	{
	52	/* general registers */
	53	-1, /* gr0 not available; i.e, it's always zero */
	54	PT_R1,
	55	PT_R2,
	56	PT_R3,
	57	PT_R4,
	58	PT_R5,
	59	PT_R6,
	60	PT_R7,
	61	PT_R8,
	62	PT_R9,
	63	PT_R10,
	64	PT_R11,
	65	PT_R12,
	66	PT_R13,
	67	PT_R14,
	68	PT_R15,
	69	PT_R16,
	70	PT_R17,
	71	PT_R18,
	72	PT_R19,
	73	PT_R20,
	74	PT_R21,
	75	PT_R22,
	76	PT_R23,
	77	PT_R24,
	78	PT_R25,
	79	PT_R26,
	80	PT_R27,
	81	PT_R28,
	82	PT_R29,
	83	PT_R30,
	84	PT_R31,
	85	/* gr32 through gr127 not directly available via the ptrace interface */
	86	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	87	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	88	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	89	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	90	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	91	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	92	/* Floating point registers */
	93	-1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
	94	PT_F2,
	95	PT_F3,
	96	PT_F4,
	97	PT_F5,
	98	PT_F6,
	99	PT_F7,
	100	PT_F8,
	101	PT_F9,
	102	PT_F10,
	103	PT_F11,
	104	PT_F12,
	105	PT_F13,
	106	PT_F14,
	107	PT_F15,
	108	PT_F16,
109	PT_F17,
110	PT_F18,
111	PT_F19,
112	PT_F20,
113	PT_F21,
114	PT_F22,
115	PT_F23,
116	PT_F24,
117	PT_F25,
118	PT_F26,
119	PT_F27,
120	PT_F28,
121	PT_F29,
122	PT_F30,
123	PT_F31,
124	PT_F32,
125	PT_F33,
126	PT_F34,
127	PT_F35,
128	PT_F36,
129	PT_F37,
130	PT_F38,
131	PT_F39,
132	PT_F40,
133	PT_F41,
134	PT_F42,
135	PT_F43,
136	PT_F44,
137	PT_F45,
138	PT_F46,
139	PT_F47,
140	PT_F48,
141	PT_F49,
142	PT_F50,
143	PT_F51,
144	PT_F52,
145	PT_F53,
146	PT_F54,
147	PT_F55,
148	PT_F56,
149	PT_F57,
150	PT_F58,
151	PT_F59,
152	PT_F60,
153	PT_F61,
154	PT_F62,
155	PT_F63,
156	PT_F64,
157	PT_F65,
158	PT_F66,
159	PT_F67,
160	PT_F68,
161	PT_F69,
162	PT_F70,
163	PT_F71,
164	PT_F72,
165	PT_F73,
166	PT_F74,
167	PT_F75,
168	PT_F76,
169	PT_F77,
170	PT_F78,
171	PT_F79,
172	PT_F80,
173	PT_F81,
174	PT_F82,
175	PT_F83,
176	PT_F84,
177	PT_F85,
178	PT_F86,
179	PT_F87,
180	PT_F88,
181	PT_F89,
182	PT_F90,
183	PT_F91,
184	PT_F92,
185	PT_F93,
186	PT_F94,
187	PT_F95,
188	PT_F96,
189	PT_F97,
190	PT_F98,
191	PT_F99,
192	PT_F100,
193	PT_F101,
194	PT_F102,
195	PT_F103,
196	PT_F104,
197	PT_F105,
198	PT_F106,
199	PT_F107,
200	PT_F108,
201	PT_F109,
202	PT_F110,
203	PT_F111,
204	PT_F112,
205	PT_F113,
206	PT_F114,
207	PT_F115,
208	PT_F116,
209	PT_F117,
210	PT_F118,
211	PT_F119,
212	PT_F120,
213	PT_F121,
214	PT_F122,
215	PT_F123,
216	PT_F124,
217	PT_F125,
218	PT_F126,
219	PT_F127,
220	/* predicate registers - we don't fetch these individually */
221	-1, -1, -1, -1, -1, -1, -1, -1,
222	-1, -1, -1, -1, -1, -1, -1, -1,
223	-1, -1, -1, -1, -1, -1, -1, -1,
224	-1, -1, -1, -1, -1, -1, -1, -1,
225	-1, -1, -1, -1, -1, -1, -1, -1,
226	-1, -1, -1, -1, -1, -1, -1, -1,
227	-1, -1, -1, -1, -1, -1, -1, -1,
228	-1, -1, -1, -1, -1, -1, -1, -1,
229	/* branch registers */
230	PT_B0,
231	PT_B1,
232	PT_B2,
233	PT_B3,
234	PT_B4,
235	PT_B5,
236	PT_B6,
237	PT_B7,
238	/* virtual frame pointer and virtual return address pointer */
239	-1, -1,
240	/* other registers */
241	PT_PR,
242	PT_CR_IIP, /* ip */
243	PT_CR_IPSR, /* psr */
9ac12c35	244	PT_CFM, /* cfm */
16461d7d KB	245	/* kernel registers not visible via ptrace interface (?) */
	246	-1, -1, -1, -1, -1, -1, -1, -1,
	247	/* hole */
	248	-1, -1, -1, -1, -1, -1, -1, -1,
	249	PT_AR_RSC,
	250	PT_AR_BSP,
	251	PT_AR_BSPSTORE,
	252	PT_AR_RNAT,
	253	-1,
	254	-1, /* Not available: FCR, IA32 floating control register */
	255	-1, -1,
	256	-1, /* Not available: EFLAG */
	257	-1, /* Not available: CSD */
	258	-1, /* Not available: SSD */
	259	-1, /* Not available: CFLG */
	260	-1, /* Not available: FSR */
	261	-1, /* Not available: FIR */
	262	-1, /* Not available: FDR */
	263	-1,
	264	PT_AR_CCV,
	265	-1, -1, -1,
	266	PT_AR_UNAT,
	267	-1, -1, -1,
	268	PT_AR_FPSR,
	269	-1, -1, -1,
	270	-1, /* Not available: ITC */
	271	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	272	-1, -1, -1, -1, -1, -1, -1, -1, -1,
	273	PT_AR_PFS,
	274	PT_AR_LC,
	275	-1, /* Not available: EC, the Epilog Count register */
	276	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	277	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	278	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	279	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	280	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	281	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
	282	-1,
	283	/* nat bits - not fetched directly; instead we obtain these bits from
	284	either rnat or unat or from memory. */
	285	-1, -1, -1, -1, -1, -1, -1, -1,
	286	-1, -1, -1, -1, -1, -1, -1, -1,
	287	-1, -1, -1, -1, -1, -1, -1, -1,
	288	-1, -1, -1, -1, -1, -1, -1, -1,
	289	-1, -1, -1, -1, -1, -1, -1, -1,
	290	-1, -1, -1, -1, -1, -1, -1, -1,
	291	-1, -1, -1, -1, -1, -1, -1, -1,
	292	-1, -1, -1, -1, -1, -1, -1, -1,
	293	-1, -1, -1, -1, -1, -1, -1, -1,
	294	-1, -1, -1, -1, -1, -1, -1, -1,
	295	-1, -1, -1, -1, -1, -1, -1, -1,
	296	-1, -1, -1, -1, -1, -1, -1, -1,
	297	-1, -1, -1, -1, -1, -1, -1, -1,
	298	-1, -1, -1, -1, -1, -1, -1, -1,
	299	-1, -1, -1, -1, -1, -1, -1, -1,
	300	-1, -1, -1, -1, -1, -1, -1, -1,
	301	};
	302
	303	CORE_ADDR
fba45db2	304	register_addr (int regno, CORE_ADDR blockend)
16461d7d KB	305	{
	306	CORE_ADDR addr;
	307
	308	if (regno < 0 \|\| regno >= NUM_REGS)
	309	error ("Invalid register number %d.", regno);
	310
	311	if (u_offsets[regno] == -1)
	312	addr = 0;
	313	else
	314	addr = (CORE_ADDR) u_offsets[regno];
	315
	316	return addr;
	317	}
	318
	319	int ia64_cannot_fetch_register (regno)
	320	int regno;
	321	{
	322	return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1;
	323	}
	324
	325	int ia64_cannot_store_register (regno)
	326	int regno;
	327	{
	328	/* Rationale behind not permitting stores to bspstore...
	329
	330	The IA-64 architecture provides bspstore and bsp which refer
	331	memory locations in the RSE's backing store. bspstore is the
	332	next location which will be written when the RSE needs to write
	333	to memory. bsp is the address at which r32 in the current frame
	334	would be found if it were written to the backing store.
	335
	336	The IA-64 architecture provides read-only access to bsp and
	337	read/write access to bspstore (but only when the RSE is in
	338	the enforced lazy mode). It should be noted that stores
	339	to bspstore also affect the value of bsp. Changing bspstore
	340	does not affect the number of dirty entries between bspstore
	341	and bsp, so changing bspstore by N words will also cause bsp
	342	to be changed by (roughly) N as well. (It could be N-1 or N+1
	343	depending upon where the NaT collection bits fall.)
	344
92362027	345	OTOH, the Linux kernel provides read/write access to bsp (and
16461d7d KB	346	currently read/write access to bspstore as well). But it
	347	is definitely the case that if you change one, the other
	348	will change at the same time. It is more useful to gdb to
	349	be able to change bsp. So in order to prevent strange and
	350	undesirable things from happening when a dummy stack frame
	351	is popped (after calling an inferior function), we allow
	352	bspstore to be read, but not written. (Note that popping
	353	a (generic) dummy stack frame causes all registers that
	354	were previously read from the inferior process to be written
	355	back.) */
	356
	357	return regno < 0 \|\| regno >= NUM_REGS \|\| u_offsets[regno] == -1
	358	\|\| regno == IA64_BSPSTORE_REGNUM;
	359	}
	360
	361	void
fba45db2	362	supply_gregset (gregset_t *gregsetp)
16461d7d KB	363	{
	364	int regi;
	365	greg_t regp = (greg_t ) gregsetp;
	366
	367	for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
	368	{
	369	supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM)));
	370	}
	371
	372	/* FIXME: NAT collection bits are at index 32; gotta deal with these
	373	somehow... */
	374
	375	supply_register (IA64_PR_REGNUM, (char *) (regp + 33));
	376
	377	for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
	378	{
	379	supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
	380	}
	381
	382	supply_register (IA64_IP_REGNUM, (char *) (regp + 42));
	383	supply_register (IA64_CFM_REGNUM, (char *) (regp + 43));
	384	supply_register (IA64_PSR_REGNUM, (char *) (regp + 44));
	385	supply_register (IA64_RSC_REGNUM, (char *) (regp + 45));
	386	supply_register (IA64_BSP_REGNUM, (char *) (regp + 46));
	387	supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47));
	388	supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48));
	389	supply_register (IA64_CCV_REGNUM, (char *) (regp + 49));
	390	supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50));
	391	supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51));
	392	supply_register (IA64_PFS_REGNUM, (char *) (regp + 52));
	393	supply_register (IA64_LC_REGNUM, (char *) (regp + 53));
	394	supply_register (IA64_EC_REGNUM, (char *) (regp + 54));
	395	}
	396
	397	void
fba45db2	398	fill_gregset (gregset_t *gregsetp, int regno)
16461d7d	399	{
76d689a6 KB	400	int regi;
	401	greg_t regp = (greg_t ) gregsetp;
	402
	403	#define COPY_REG(_idx_,_regi_) \
	404	if ((regno == -1) \|\| regno == _regi_) \
524d7c18	405	memcpy (regp + _idx_, &deprecated_registers[REGISTER_BYTE (_regi_)], \
76d689a6 KB	406	REGISTER_RAW_SIZE (_regi_))
	407
	408	for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
	409	{
	410	COPY_REG (regi - IA64_GR0_REGNUM, regi);
	411	}
	412
	413	/* FIXME: NAT collection bits at index 32? */
	414
	415	COPY_REG (33, IA64_PR_REGNUM);
	416
	417	for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
	418	{
	419	COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
	420	}
	421
	422	COPY_REG (42, IA64_IP_REGNUM);
	423	COPY_REG (43, IA64_CFM_REGNUM);
	424	COPY_REG (44, IA64_PSR_REGNUM);
	425	COPY_REG (45, IA64_RSC_REGNUM);
	426	COPY_REG (46, IA64_BSP_REGNUM);
	427	COPY_REG (47, IA64_BSPSTORE_REGNUM);
	428	COPY_REG (48, IA64_RNAT_REGNUM);
	429	COPY_REG (49, IA64_CCV_REGNUM);
	430	COPY_REG (50, IA64_UNAT_REGNUM);
	431	COPY_REG (51, IA64_FPSR_REGNUM);
	432	COPY_REG (52, IA64_PFS_REGNUM);
	433	COPY_REG (53, IA64_LC_REGNUM);
	434	COPY_REG (54, IA64_EC_REGNUM);
	435	}
	436
	437	/* Given a pointer to a floating point register set in /proc format
	438	(fpregset_t *), unpack the register contents and supply them as gdb's
	439	idea of the current floating point register values. */
	440
	441	void
fba45db2	442	supply_fpregset (fpregset_t *fpregsetp)
76d689a6	443	{
52f0bd74	444	int regi;
76d689a6 KB	445	char *from;
	446
	447	for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
	448	{
	449	from = (char ) &((fpregsetp)[regi - IA64_FR0_REGNUM]);
	450	supply_register (regi, from);
	451	}
	452	}
	453
	454	/* Given a pointer to a floating point register set in /proc format
	455	(fpregset_t *), update the register specified by REGNO from gdb's idea
	456	of the current floating point register set. If REGNO is -1, update
	457	them all. */
	458
	459	void
fba45db2	460	fill_fpregset (fpregset_t *fpregsetp, int regno)
76d689a6 KB	461	{
	462	int regi;
	463	char *to;
	464	char *from;
	465
	466	for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
	467	{
	468	if ((regno == -1) \|\| (regno == regi))
	469	{
524d7c18	470	from = (char *) &deprecated_registers[REGISTER_BYTE (regi)];
76d689a6 KB	471	to = (char ) &((fpregsetp)[regi - IA64_FR0_REGNUM]);
	472	memcpy (to, from, REGISTER_RAW_SIZE (regi));
	473	}
	474	}
16461d7d	475	}
acf7b9e1 KB	476
	477	#define IA64_PSR_DB (1UL << 24)
	478	#define IA64_PSR_DD (1UL << 39)
	479
	480	static void
39f77062	481	enable_watchpoints_in_psr (ptid_t ptid)
acf7b9e1 KB	482	{
	483	CORE_ADDR psr;
	484
39f77062	485	psr = read_register_pid (IA64_PSR_REGNUM, ptid);
acf7b9e1 KB	486	if (!(psr & IA64_PSR_DB))
	487	{
	488	psr \|= IA64_PSR_DB; /* Set the db bit - this enables hardware
	489	watchpoints and breakpoints. */
39f77062	490	write_register_pid (IA64_PSR_REGNUM, psr, ptid);
acf7b9e1 KB	491	}
	492	}
	493
	494	static long
39f77062	495	fetch_debug_register (ptid_t ptid, int idx)
acf7b9e1 KB	496	{
	497	long val;
	498	int tid;
	499
39f77062	500	tid = TIDGET (ptid);
acf7b9e1	501	if (tid == 0)
39f77062	502	tid = PIDGET (ptid);
acf7b9e1 KB	503
	504	val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0);
	505
	506	return val;
	507	}
	508
	509	static void
39f77062	510	store_debug_register (ptid_t ptid, int idx, long val)
acf7b9e1 KB	511	{
	512	int tid;
	513
39f77062	514	tid = TIDGET (ptid);
acf7b9e1	515	if (tid == 0)
39f77062	516	tid = PIDGET (ptid);
acf7b9e1 KB	517
	518	(void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val);
	519	}
	520
	521	static void
39f77062	522	fetch_debug_register_pair (ptid_t ptid, int idx, long dbr_addr, long dbr_mask)
acf7b9e1 KB	523	{
acf7b9e1 KB	524	if (dbr_addr)
39f77062	525	dbr_addr = fetch_debug_register (ptid, 2 idx);
acf7b9e1	526	if (dbr_mask)
39f77062	527	dbr_mask = fetch_debug_register (ptid, 2 idx + 1);
acf7b9e1 KB	528	}
	529
	530	static void
39f77062	531	store_debug_register_pair (ptid_t ptid, int idx, long dbr_addr, long dbr_mask)
acf7b9e1 KB	532	{
acf7b9e1 KB	533	if (dbr_addr)
39f77062	534	store_debug_register (ptid, 2 * idx, *dbr_addr);
acf7b9e1	535	if (dbr_mask)
39f77062	536	store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
acf7b9e1 KB	537	}
	538
	539	static int
	540	is_power_of_2 (int val)
	541	{
	542	int i, onecount;
	543
	544	onecount = 0;
	545	for (i = 0; i < 8 * sizeof (val); i++)
	546	if (val & (1 << i))
	547	onecount++;
	548
	549	return onecount <= 1;
	550	}
	551
	552	int
39f77062	553	ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
acf7b9e1 KB	554	{
	555	int idx;
	556	long dbr_addr, dbr_mask;
	557	int max_watchpoints = 4;
	558
	559	if (len <= 0 \|\| !is_power_of_2 (len))
	560	return -1;
	561
	562	for (idx = 0; idx < max_watchpoints; idx++)
	563	{
39f77062	564	fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
acf7b9e1 KB	565	if ((dbr_mask & (0x3UL << 62)) == 0)
	566	{
	567	/* Exit loop if both r and w bits clear */
	568	break;
	569	}
	570	}
	571
	572	if (idx == max_watchpoints)
	573	return -1;
	574
	575	dbr_addr = (long) addr;
	576	dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
	577	dbr_mask \|= 0x0800000000000000L; /* Only match privilege level 3 */
	578	switch (rw)
	579	{
	580	case hw_write:
	581	dbr_mask \|= (1L << 62); /* Set w bit */
	582	break;
	583	case hw_read:
	584	dbr_mask \|= (1L << 63); /* Set r bit */
	585	break;
	586	case hw_access:
	587	dbr_mask \|= (3L << 62); /* Set both r and w bits */
	588	break;
	589	default:
	590	return -1;
	591	}
	592
39f77062 KB	593	store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
39f77062 KB	594	enable_watchpoints_in_psr (ptid);
acf7b9e1 KB	595
	596	return 0;
	597	}
	598
	599	int
39f77062	600	ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
acf7b9e1 KB	601	{
	602	int idx;
	603	long dbr_addr, dbr_mask;
	604	int max_watchpoints = 4;
	605
	606	if (len <= 0 \|\| !is_power_of_2 (len))
	607	return -1;
	608
	609	for (idx = 0; idx < max_watchpoints; idx++)
	610	{
39f77062	611	fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
acf7b9e1 KB	612	if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
	613	{
	614	dbr_addr = 0;
	615	dbr_mask = 0;
39f77062	616	store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
acf7b9e1 KB	617	return 0;
	618	}
	619	}
	620	return -1;
	621	}
	622
	623	CORE_ADDR
39f77062	624	ia64_linux_stopped_by_watchpoint (ptid_t ptid)
acf7b9e1 KB	625	{
	626	CORE_ADDR psr;
	627	int tid;
	628	struct siginfo siginfo;
	629
39f77062	630	tid = TIDGET(ptid);
acf7b9e1	631	if (tid == 0)
39f77062	632	tid = PIDGET (ptid);
acf7b9e1 KB	633
	634	errno = 0;
	635	ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo);
	636
705b278b JJ	637	if (errno != 0 \|\| siginfo.si_signo != SIGTRAP \|\|
705b278b JJ	638	(siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
acf7b9e1 KB	639	return 0;
acf7b9e1 KB	640
39f77062	641	psr = read_register_pid (IA64_PSR_REGNUM, ptid);
acf7b9e1 KB	642	psr \|= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
acf7b9e1 KB	643	for the next instruction */
39f77062	644	write_register_pid (IA64_PSR_REGNUM, psr, ptid);
acf7b9e1 KB	645
	646	return (CORE_ADDR) siginfo.si_addr;
	647	}