[binutils.git] / include / coff / arm.h

/* ARM COFF support for BFD.
   Copyright 1998, 1999, 2000, 2002, 2003, 2010, 2013
   Free Software Foundation, Inc.

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software Foundation,
   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#define COFFARM 1

#define L_LNNO_SIZE 2
#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
#include "coff/external.h"

/* Bits for f_flags:
 	F_RELFLG	relocation info stripped from file
 	F_EXEC		file is executable (no unresolved external references)
 	F_LNNO		line numbers stripped from file
 	F_LSYMS		local symbols stripped from file
        F_INTERWORK     file supports switching between ARM and Thumb instruction sets
        F_INTERWORK_SET the F_INTERWORK bit is valid
 	F_APCS_FLOAT	code passes float arguments in float registers
 	F_PIC		code is reentrant/position-independent
 	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax)
 	F_APCS_26	file uses 26 bit ARM Procedure Calling Standard
 	F_APCS_SET	the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised
 	F_SOFT_FLOAT	code does not use floating point instructions.  */

#define F_RELFLG	(0x0001)
#define F_EXEC		(0x0002)
#define F_LNNO		(0x0004)
#define F_LSYMS		(0x0008)
#define F_INTERWORK	(0x0010)
#define F_INTERWORK_SET	(0x0020)
#define F_APCS_FLOAT	(0x0040)
#undef  F_AR16WR
#define F_PIC		(0x0080)
#define	F_AR32WR	(0x0100)
#define F_APCS_26	(0x0400)
#define F_APCS_SET	(0x0800)
#define F_SOFT_FLOAT	(0x2000)
#define F_VFP_FLOAT	(0x4000)

/* Bits stored in flags field of the internal_f structure */

#define F_INTERWORK	(0x0010)
#define F_APCS_FLOAT	(0x0040)
#define F_PIC		(0x0080)
#define F_APCS26	(0x1000)
#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400)
#define F_ARM_2		(0x0400)
#define F_ARM_2a	(0x0800)
#define F_ARM_3		(0x0c00)
#define F_ARM_3M	(0x4000)
#define F_ARM_4		(0x4400)
#define F_ARM_4T	(0x4800)
#define F_ARM_5		(0x4c00)

/*
  ARMMAGIC ought to encoded the procesor type,
  but it is too late to change it now, instead
  the flags field of the internal_f structure
  is used as shown above.
 
  XXX - NC 5/6/97.  */

#define	ARMMAGIC	0xa00  /* I just made this up */

#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC))

#define	ARMPEMAGIC	0x1c0
#define	THUMBPEMAGIC	0x1c2
#define	ARMV7PEMAGIC	0x1c4

#undef  ARMBADMAG
#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC) && ((x).f_magic != ARMV7PEMAGIC))

#define OMAGIC          0404    /* object files, eg as output */
#define ZMAGIC          0413    /* demand load format, eg normal ld output */
#define STMAGIC		0401	/* target shlib */
#define SHMAGIC		0443	/* host   shlib */

/* define some NT default values */
/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
#define NT_SECTION_ALIGNMENT 0x1000
#define NT_FILE_ALIGNMENT    0x200  
#define NT_DEF_RESERVE       0x100000
#define NT_DEF_COMMIT        0x1000

/* We use the .rdata section to hold read only data.  */
#define _LIT	".rdata"

/********************** RELOCATION DIRECTIVES **********************/
#ifdef ARM_WINCE
struct external_reloc
{
  char r_vaddr[4];
  char r_symndx[4];
  char r_type[2];
};

#define RELOC struct external_reloc
#define RELSZ 10

#else
struct external_reloc
{
  char r_vaddr[4];
  char r_symndx[4];
  char r_type[2];
  char r_offset[4];
};

#define RELOC struct external_reloc
#define RELSZ 14
#endif

#define ARM_NOTE_SECTION ".note"
Commit	Line	Data
db688e87	1	/* ARM COFF support for BFD.
4f15c893 NC	2	Copyright 1998, 1999, 2000, 2002, 2003, 2010, 2013
4f15c893 NC	3	Free Software Foundation, Inc.
db688e87 NC	4
	5	This file is part of BFD, the Binary File Descriptor library.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
e4e42b45	9	the Free Software Foundation; either version 3 of the License, or
db688e87 NC	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software Foundation,
e172dbf8	19	Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 RH	20
	21	#define COFFARM 1
	22
4f1d9bd8 NC	23	#define L_LNNO_SIZE 2
	24	#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
	25	#include "coff/external.h"
252b5132 RH	26
252b5132 RH	27	/* Bits for f_flags:
4f1d9bd8 NC	28	F_RELFLG relocation info stripped from file
	29	F_EXEC file is executable (no unresolved external references)
	30	F_LNNO line numbers stripped from file
	31	F_LSYMS local symbols stripped from file
	32	F_INTERWORK file supports switching between ARM and Thumb instruction sets
	33	F_INTERWORK_SET the F_INTERWORK bit is valid
	34	F_APCS_FLOAT code passes float arguments in float registers
	35	F_PIC code is reentrant/position-independent
	36	F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax)
	37	F_APCS_26 file uses 26 bit ARM Procedure Calling Standard
	38	F_APCS_SET the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised
	39	F_SOFT_FLOAT code does not use floating point instructions. */
252b5132 RH	40
	41	#define F_RELFLG (0x0001)
	42	#define F_EXEC (0x0002)
	43	#define F_LNNO (0x0004)
	44	#define F_LSYMS (0x0008)
	45	#define F_INTERWORK (0x0010)
	46	#define F_INTERWORK_SET (0x0020)
	47	#define F_APCS_FLOAT (0x0040)
	48	#undef F_AR16WR
	49	#define F_PIC (0x0080)
	50	#define F_AR32WR (0x0100)
	51	#define F_APCS_26 (0x0400)
	52	#define F_APCS_SET (0x0800)
c2c594b8	53	#define F_SOFT_FLOAT (0x2000)
ca4ebd1e	54	#define F_VFP_FLOAT (0x4000)
252b5132 RH	55
	56	/* Bits stored in flags field of the internal_f structure */
	57
	58	#define F_INTERWORK (0x0010)
252b5132	59	#define F_APCS_FLOAT (0x0040)
a74ffb02 NC	60	#define F_PIC (0x0080)
	61	#define F_APCS26 (0x1000)
	62	#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400)
	63	#define F_ARM_2 (0x0400)
	64	#define F_ARM_2a (0x0800)
	65	#define F_ARM_3 (0x0c00)
	66	#define F_ARM_3M (0x4000)
	67	#define F_ARM_4 (0x4400)
	68	#define F_ARM_4T (0x4800)
849a0ebf	69	#define F_ARM_5 (0x4c00)
252b5132 RH	70
252b5132 RH	71	/*
4f1d9bd8 NC	72	ARMMAGIC ought to encoded the procesor type,
	73	but it is too late to change it now, instead
	74	the flags field of the internal_f structure
	75	is used as shown above.
	76
	77	XXX - NC 5/6/97. */
252b5132	78
056350c6	79	#define ARMMAGIC 0xa00 /* I just made this up */
252b5132 RH	80
	81	#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC))
	82
056350c6 NC	83	#define ARMPEMAGIC 0x1c0
056350c6 NC	84	#define THUMBPEMAGIC 0x1c2
4f15c893	85	#define ARMV7PEMAGIC 0x1c4
056350c6 NC	86
056350c6 NC	87	#undef ARMBADMAG
4f15c893	88	#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC) && ((x).f_magic != ARMV7PEMAGIC))
056350c6	89
252b5132 RH	90	#define OMAGIC 0404 /* object files, eg as output */
	91	#define ZMAGIC 0413 /* demand load format, eg normal ld output */
	92	#define STMAGIC 0401 /* target shlib */
	93	#define SHMAGIC 0443 /* host shlib */
	94
252b5132 RH	95	/* define some NT default values */
	96	/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */
	97	#define NT_SECTION_ALIGNMENT 0x1000
	98	#define NT_FILE_ALIGNMENT 0x200
	99	#define NT_DEF_RESERVE 0x100000
	100	#define NT_DEF_COMMIT 0x1000
	101
252b5132 RH	102	/* We use the .rdata section to hold read only data. */
	103	#define _LIT ".rdata"
	104
252b5132	105	/******************** RELOCATION DIRECTIVES ********************/
056350c6 NC	106	#ifdef ARM_WINCE
	107	struct external_reloc
	108	{
	109	char r_vaddr[4];
	110	char r_symndx[4];
	111	char r_type[2];
	112	};
	113
	114	#define RELOC struct external_reloc
	115	#define RELSZ 10
	116
	117	#else
db688e87 NC	118	struct external_reloc
db688e87 NC	119	{
252b5132 RH	120	char r_vaddr[4];
	121	char r_symndx[4];
	122	char r_type[2];
	123	char r_offset[4];
	124	};
	125
252b5132 RH	126	#define RELOC struct external_reloc
252b5132 RH	127	#define RELSZ 14
056350c6	128	#endif
e16bb312 NC	129
e16bb312 NC	130	#define ARM_NOTE_SECTION ".note"