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c906108c | 1 | /* Native-dependent code for GDB, for NYU Ultra3 running Sym1 OS. |
4e052eda AC |
2 | Copyright 1988, 1989, 1991, 1992, 2001 Free Software Foundation, |
3 | Inc. | |
c906108c SS |
4 | Contributed by David Wood ([email protected]) at New York University. |
5 | ||
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | #define DEBUG | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
4e052eda | 29 | #include "regcache.h" |
c906108c SS |
30 | |
31 | #include <sys/types.h> | |
32 | #include <sys/param.h> | |
33 | #include <signal.h> | |
34 | #include <sys/ioctl.h> | |
c5aa993b | 35 | #include <fcntl.h> |
c906108c SS |
36 | |
37 | #include "gdbcore.h" | |
38 | ||
39 | #include <sys/file.h> | |
40 | #include "gdb_stat.h" | |
41 | ||
a14ed312 | 42 | static void fetch_core_registers (char *, unsigned, int, CORE_ADDR); |
c906108c SS |
43 | |
44 | /* Assumes support for AMD's Binary Compatibility Standard | |
45 | for ptrace(). If you define ULTRA3, the ultra3 extensions to | |
46 | ptrace() are used allowing the reading of more than one register | |
47 | at a time. | |
48 | ||
49 | This file assumes KERNEL_DEBUGGING is turned off. This means | |
50 | that if the user/gdb tries to read gr64-gr95 or any of the | |
51 | protected special registers we silently return -1 (see the | |
52 | CANNOT_STORE/FETCH_REGISTER macros). */ | |
53 | #define ULTRA3 | |
54 | ||
55 | #if !defined (offsetof) | |
c5aa993b | 56 | #define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER) |
c906108c SS |
57 | #endif |
58 | ||
59 | extern int errno; | |
60 | struct ptrace_user pt_struct; | |
61 | ||
62 | /* Get all available registers from the inferior. Registers that are | |
63 | * defined in REGISTER_NAMES, but not available to the user/gdb are | |
64 | * supplied as -1. This may include gr64-gr95 and the protected special | |
65 | * purpose registers. | |
66 | */ | |
67 | ||
68 | void | |
fba45db2 | 69 | fetch_inferior_registers (int regno) |
c906108c | 70 | { |
c5aa993b | 71 | register int i, j, ret_val = 0; |
c906108c SS |
72 | char buf[128]; |
73 | ||
c5aa993b JM |
74 | if (regno != -1) |
75 | { | |
76 | fetch_register (regno); | |
77 | return; | |
78 | } | |
c906108c SS |
79 | |
80 | /* Global Registers */ | |
81 | #ifdef ULTRA3 | |
82 | errno = 0; | |
83 | ptrace (PT_READ_STRUCT, inferior_pid, | |
c5aa993b JM |
84 | (PTRACE_ARG3_TYPE) register_addr (GR96_REGNUM, 0), |
85 | (int) &pt_struct.pt_gr[0], 32 * 4); | |
86 | if (errno != 0) | |
87 | { | |
c906108c SS |
88 | perror_with_name ("reading global registers"); |
89 | ret_val = -1; | |
c5aa993b JM |
90 | } |
91 | else | |
92 | for (regno = GR96_REGNUM, j = 0; j < 32; regno++, j++) | |
93 | { | |
94 | supply_register (regno, &pt_struct.pt_gr[j]); | |
95 | } | |
c906108c | 96 | #else |
c5aa993b JM |
97 | for (regno = GR96_REGNUM; !ret_val && regno < GR96_REGNUM + 32; regno++) |
98 | fetch_register (regno); | |
c906108c SS |
99 | #endif |
100 | ||
101 | /* Local Registers */ | |
102 | #ifdef ULTRA3 | |
103 | errno = 0; | |
104 | ptrace (PT_READ_STRUCT, inferior_pid, | |
c5aa993b JM |
105 | (PTRACE_ARG3_TYPE) register_addr (LR0_REGNUM, 0), |
106 | (int) &pt_struct.pt_lr[0], 128 * 4); | |
107 | if (errno != 0) | |
108 | { | |
c906108c SS |
109 | perror_with_name ("reading local registers"); |
110 | ret_val = -1; | |
c5aa993b JM |
111 | } |
112 | else | |
113 | for (regno = LR0_REGNUM, j = 0; j < 128; regno++, j++) | |
114 | { | |
115 | supply_register (regno, &pt_struct.pt_lr[j]); | |
116 | } | |
c906108c | 117 | #else |
c5aa993b JM |
118 | for (regno = LR0_REGNUM; !ret_val && regno < LR0_REGNUM + 128; regno++) |
119 | fetch_register (regno); | |
c906108c SS |
120 | #endif |
121 | ||
122 | /* Special Registers */ | |
c5aa993b JM |
123 | fetch_register (GR1_REGNUM); |
124 | fetch_register (CPS_REGNUM); | |
125 | fetch_register (PC_REGNUM); | |
126 | fetch_register (NPC_REGNUM); | |
127 | fetch_register (PC2_REGNUM); | |
128 | fetch_register (IPC_REGNUM); | |
129 | fetch_register (IPA_REGNUM); | |
130 | fetch_register (IPB_REGNUM); | |
131 | fetch_register (Q_REGNUM); | |
132 | fetch_register (BP_REGNUM); | |
133 | fetch_register (FC_REGNUM); | |
134 | ||
135 | /* Fake any registers that are in REGISTER_NAMES, but not available to gdb */ | |
136 | registers_fetched (); | |
c906108c SS |
137 | } |
138 | ||
139 | /* Store our register values back into the inferior. | |
140 | * If REGNO is -1, do this for all registers. | |
141 | * Otherwise, REGNO specifies which register (so we can save time). | |
142 | * NOTE: Assumes AMD's binary compatibility standard. | |
143 | */ | |
144 | ||
145 | void | |
fba45db2 | 146 | store_inferior_registers (int regno) |
c906108c SS |
147 | { |
148 | register unsigned int regaddr; | |
149 | char buf[80]; | |
150 | ||
151 | if (regno >= 0) | |
152 | { | |
c5aa993b | 153 | if (CANNOT_STORE_REGISTER (regno)) |
c906108c SS |
154 | return; |
155 | regaddr = register_addr (regno, 0); | |
156 | errno = 0; | |
157 | ptrace (PT_WRITE_U, inferior_pid, | |
c5aa993b | 158 | (PTRACE_ARG3_TYPE) regaddr, read_register (regno)); |
c906108c SS |
159 | if (errno != 0) |
160 | { | |
161 | sprintf (buf, "writing register %s (#%d)", REGISTER_NAME (regno), regno); | |
162 | perror_with_name (buf); | |
163 | } | |
164 | } | |
165 | else | |
166 | { | |
167 | #ifdef ULTRA3 | |
c5aa993b JM |
168 | pt_struct.pt_gr1 = read_register (GR1_REGNUM); |
169 | for (regno = GR96_REGNUM; regno < GR96_REGNUM + 32; regno++) | |
170 | pt_struct.pt_gr[regno] = read_register (regno); | |
171 | for (regno = LR0_REGNUM; regno < LR0_REGNUM + 128; regno++) | |
172 | pt_struct.pt_gr[regno] = read_register (regno); | |
c906108c SS |
173 | errno = 0; |
174 | ptrace (PT_WRITE_STRUCT, inferior_pid, | |
c5aa993b JM |
175 | (PTRACE_ARG3_TYPE) register_addr (GR1_REGNUM, 0), |
176 | (int) &pt_struct.pt_gr1, (1 * 32 * 128) * 4); | |
c906108c SS |
177 | if (errno != 0) |
178 | { | |
c5aa993b JM |
179 | sprintf (buf, "writing all local/global registers"); |
180 | perror_with_name (buf); | |
c906108c | 181 | } |
c5aa993b JM |
182 | pt_struct.pt_psr = read_register (CPS_REGNUM); |
183 | pt_struct.pt_pc0 = read_register (NPC_REGNUM); | |
184 | pt_struct.pt_pc1 = read_register (PC_REGNUM); | |
185 | pt_struct.pt_pc2 = read_register (PC2_REGNUM); | |
186 | pt_struct.pt_ipc = read_register (IPC_REGNUM); | |
187 | pt_struct.pt_ipa = read_register (IPA_REGNUM); | |
188 | pt_struct.pt_ipb = read_register (IPB_REGNUM); | |
189 | pt_struct.pt_q = read_register (Q_REGNUM); | |
190 | pt_struct.pt_bp = read_register (BP_REGNUM); | |
191 | pt_struct.pt_fc = read_register (FC_REGNUM); | |
c906108c SS |
192 | errno = 0; |
193 | ptrace (PT_WRITE_STRUCT, inferior_pid, | |
c5aa993b JM |
194 | (PTRACE_ARG3_TYPE) register_addr (CPS_REGNUM, 0), |
195 | (int) &pt_struct.pt_psr, (10) * 4); | |
c906108c SS |
196 | if (errno != 0) |
197 | { | |
c5aa993b JM |
198 | sprintf (buf, "writing all special registers"); |
199 | perror_with_name (buf); | |
200 | return; | |
c906108c SS |
201 | } |
202 | #else | |
c5aa993b JM |
203 | store_inferior_registers (GR1_REGNUM); |
204 | for (regno = GR96_REGNUM; regno < GR96_REGNUM + 32; regno++) | |
205 | store_inferior_registers (regno); | |
206 | for (regno = LR0_REGNUM; regno < LR0_REGNUM + 128; regno++) | |
207 | store_inferior_registers (regno); | |
208 | store_inferior_registers (CPS_REGNUM); | |
209 | store_inferior_registers (PC_REGNUM); | |
210 | store_inferior_registers (NPC_REGNUM); | |
211 | store_inferior_registers (PC2_REGNUM); | |
212 | store_inferior_registers (IPC_REGNUM); | |
213 | store_inferior_registers (IPA_REGNUM); | |
214 | store_inferior_registers (IPB_REGNUM); | |
215 | store_inferior_registers (Q_REGNUM); | |
216 | store_inferior_registers (BP_REGNUM); | |
217 | store_inferior_registers (FC_REGNUM); | |
218 | #endif /* ULTRA3 */ | |
c906108c SS |
219 | } |
220 | } | |
221 | ||
222 | /* | |
223 | * Fetch an individual register (and supply it). | |
224 | * return 0 on success, -1 on failure. | |
225 | * NOTE: Assumes AMD's Binary Compatibility Standard for ptrace(). | |
226 | */ | |
227 | static void | |
fba45db2 | 228 | fetch_register (int regno) |
c906108c SS |
229 | { |
230 | char buf[128]; | |
c5aa993b JM |
231 | int val; |
232 | ||
233 | if (CANNOT_FETCH_REGISTER (regno)) | |
234 | { | |
235 | val = -1; | |
c906108c SS |
236 | supply_register (regno, &val); |
237 | } | |
c5aa993b JM |
238 | else |
239 | { | |
240 | errno = 0; | |
241 | val = ptrace (PT_READ_U, inferior_pid, | |
242 | (PTRACE_ARG3_TYPE) register_addr (regno, 0), 0); | |
243 | if (errno != 0) | |
244 | { | |
245 | sprintf (buf, "reading register %s (#%d)", REGISTER_NAME (regno), regno); | |
246 | perror_with_name (buf); | |
247 | } | |
248 | else | |
249 | { | |
250 | supply_register (regno, &val); | |
251 | } | |
252 | } | |
c906108c SS |
253 | } |
254 | ||
255 | ||
256 | /* | |
257 | * Read AMD's Binary Compatibilty Standard conforming core file. | |
258 | * struct ptrace_user is the first thing in the core file | |
3ed9691f KB |
259 | * |
260 | * CORE_REG_SECT, CORE_REG_SIZE, WHICH, and REG_ADDR are all ignored. | |
c906108c SS |
261 | */ |
262 | ||
263 | static void | |
3ed9691f KB |
264 | fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, |
265 | int which, CORE_ADDR reg_addr) | |
c906108c SS |
266 | { |
267 | register int regno; | |
c5aa993b JM |
268 | int val; |
269 | char buf[4]; | |
270 | ||
271 | for (regno = 0; regno < NUM_REGS; regno++) | |
272 | { | |
273 | if (!CANNOT_FETCH_REGISTER (regno)) | |
274 | { | |
275 | val = bfd_seek (core_bfd, (file_ptr) register_addr (regno, 0), SEEK_SET); | |
276 | if (val < 0 || (val = bfd_read (buf, sizeof buf, 1, core_bfd)) < 0) | |
277 | { | |
278 | char *buffer = (char *) alloca (strlen (REGISTER_NAME (regno)) + 35); | |
279 | strcpy (buffer, "Reading core register "); | |
280 | strcat (buffer, REGISTER_NAME (regno)); | |
281 | perror_with_name (buffer); | |
282 | } | |
283 | supply_register (regno, buf); | |
284 | } | |
c906108c | 285 | } |
c906108c | 286 | |
c5aa993b JM |
287 | /* Fake any registers that are in REGISTER_NAMES, but not available to gdb */ |
288 | registers_fetched (); | |
c906108c SS |
289 | } |
290 | ||
291 | ||
292 | /* | |
293 | * Takes a register number as defined in tm.h via REGISTER_NAMES, and maps | |
294 | * it to an offset in a struct ptrace_user defined by AMD's BCS. | |
295 | * That is, it defines the mapping between gdb register numbers and items in | |
296 | * a struct ptrace_user. | |
297 | * A register protection scheme is set up here. If a register not | |
298 | * available to the user is specified in 'regno', then an address that | |
299 | * will cause ptrace() to fail is returned. | |
300 | */ | |
301 | CORE_ADDR | |
fba45db2 | 302 | register_addr (int regno, CORE_ADDR blockend) |
c906108c | 303 | { |
c5aa993b JM |
304 | if ((regno >= LR0_REGNUM) && (regno < LR0_REGNUM + 128)) |
305 | { | |
306 | return (offsetof (struct ptrace_user, pt_lr[regno - LR0_REGNUM])); | |
307 | } | |
308 | else if ((regno >= GR96_REGNUM) && (regno < GR96_REGNUM + 32)) | |
309 | { | |
310 | return (offsetof (struct ptrace_user, pt_gr[regno - GR96_REGNUM])); | |
311 | } | |
312 | else | |
313 | { | |
314 | switch (regno) | |
315 | { | |
316 | case GR1_REGNUM: | |
317 | return (offsetof (struct ptrace_user, pt_gr1)); | |
318 | case CPS_REGNUM: | |
319 | return (offsetof (struct ptrace_user, pt_psr)); | |
320 | case NPC_REGNUM: | |
321 | return (offsetof (struct ptrace_user, pt_pc0)); | |
322 | case PC_REGNUM: | |
323 | return (offsetof (struct ptrace_user, pt_pc1)); | |
324 | case PC2_REGNUM: | |
325 | return (offsetof (struct ptrace_user, pt_pc2)); | |
326 | case IPC_REGNUM: | |
327 | return (offsetof (struct ptrace_user, pt_ipc)); | |
328 | case IPA_REGNUM: | |
329 | return (offsetof (struct ptrace_user, pt_ipa)); | |
330 | case IPB_REGNUM: | |
331 | return (offsetof (struct ptrace_user, pt_ipb)); | |
332 | case Q_REGNUM: | |
333 | return (offsetof (struct ptrace_user, pt_q)); | |
334 | case BP_REGNUM: | |
335 | return (offsetof (struct ptrace_user, pt_bp)); | |
336 | case FC_REGNUM: | |
337 | return (offsetof (struct ptrace_user, pt_fc)); | |
c906108c | 338 | default: |
c5aa993b JM |
339 | fprintf_filtered (gdb_stderr, "register_addr():Bad register %s (%d)\n", |
340 | REGISTER_NAME (regno), regno); | |
341 | return (0xffffffff); /* Should make ptrace() fail */ | |
342 | } | |
c906108c | 343 | } |
c906108c | 344 | } |
c906108c | 345 | \f |
c5aa993b | 346 | |
c906108c SS |
347 | /* Register that we are able to handle ultra3 core file formats. |
348 | FIXME: is this really bfd_target_unknown_flavour? */ | |
349 | ||
350 | static struct core_fns ultra3_core_fns = | |
351 | { | |
2acceee2 JM |
352 | bfd_target_unknown_flavour, /* core_flavour */ |
353 | default_check_format, /* check_format */ | |
354 | default_core_sniffer, /* core_sniffer */ | |
355 | fetch_core_registers, /* core_read_registers */ | |
356 | NULL /* next */ | |
c906108c SS |
357 | }; |
358 | ||
359 | void | |
fba45db2 | 360 | _initialize_core_ultra3 (void) |
c906108c SS |
361 | { |
362 | add_core_fns (&ultra3_core_fns); | |
363 | } |