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66d05e03 | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
00dd4fd9 | 2 | Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc. |
9faacb92 SC |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
6c9638b4 | 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
9faacb92 SC |
19 | |
20 | /* | |
21 | Contributed by Steve Chamberlain | |
22 | [email protected] | |
23 | */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
27 | #include "obstack.h" | |
28 | #include "symtab.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "gdbcmd.h" | |
66d05e03 | 31 | #include "gdbcore.h" |
9faacb92 SC |
32 | #include "value.h" |
33 | #include "dis-asm.h" | |
69992fc8 | 34 | #include "inferior.h" /* for BEFORE_TEXT_END etc. */ |
5f2f2809 | 35 | |
cd21cbc4 MA |
36 | extern int remote_write_size; /* in remote.c */ |
37 | ||
00dd4fd9 SS |
38 | /* Default to the original SH. */ |
39 | ||
40 | #define DEFAULT_SH_TYPE "sh" | |
41 | ||
42 | /* This value is the model of SH in use. */ | |
43 | ||
44 | char *sh_processor_type; | |
45 | ||
46 | char *tmp_sh_processor_type; | |
47 | ||
48 | /* A set of original names, to be used when restoring back to generic | |
49 | registers from a specific set. */ | |
50 | ||
51 | char *sh_generic_reg_names[] = REGISTER_NAMES; | |
52 | ||
53 | char *sh_reg_names[] = { | |
12ffa10c SS |
54 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
55 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
56 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
57 | "", "", | |
58 | "", "", "", "", "", "", "", "", | |
59 | "", "", "", "", "", "", "", "", | |
60 | "", "", | |
61 | "", "", "", "", "", "", "", "", | |
62 | "", "", "", "", "", "", "", "", | |
00dd4fd9 SS |
63 | }; |
64 | ||
65 | char *sh3_reg_names[] = { | |
12ffa10c SS |
66 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
67 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
68 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
69 | "", "", | |
70 | "", "", "", "", "", "", "", "", | |
71 | "", "", "", "", "", "", "", "", | |
72 | "ssr", "spc", | |
05535e79 | 73 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
12ffa10c | 74 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" |
05535e79 SS |
75 | }; |
76 | ||
77 | char *sh3e_reg_names[] = { | |
12ffa10c SS |
78 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
79 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
80 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
81 | "fpul", "fpscr", | |
82 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
83 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
84 | "ssr", "spc", | |
05535e79 SS |
85 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
86 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
00dd4fd9 SS |
87 | }; |
88 | ||
89 | struct { | |
90 | char *name; | |
91 | char **regnames; | |
92 | } sh_processor_type_table[] = { | |
93 | { "sh", sh_reg_names }, | |
94 | { "sh3", sh3_reg_names }, | |
05535e79 | 95 | { "sh3e", sh3e_reg_names }, |
00dd4fd9 SS |
96 | { NULL, NULL } |
97 | }; | |
98 | ||
9faacb92 SC |
99 | /* Prologue looks like |
100 | [mov.l <regs>,@-r15]... | |
101 | [sts.l pr,@-r15] | |
102 | [mov.l r14,@-r15] | |
103 | [mov r15,r14] | |
104 | */ | |
105 | ||
106 | #define IS_STS(x) ((x) == 0x4f22) | |
107 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) | |
108 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) | |
109 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
110 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
c4deed18 SC |
111 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
112 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
113 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) | |
9faacb92 SC |
114 | |
115 | /* Skip any prologue before the guts of a function */ | |
116 | ||
117 | CORE_ADDR | |
118 | sh_skip_prologue (start_pc) | |
119 | CORE_ADDR start_pc; | |
9faacb92 SC |
120 | { |
121 | int w; | |
122 | ||
123 | w = read_memory_integer (start_pc, 2); | |
124 | while (IS_STS (w) | |
125 | || IS_PUSH (w) | |
c4deed18 | 126 | || IS_MOV_SP_FP (w) |
5f2f2809 SC |
127 | || IS_MOV_R3 (w) |
128 | || IS_ADD_R3SP (w) | |
129 | || IS_ADD_SP (w) | |
130 | || IS_SHLL_R3 (w)) | |
9faacb92 SC |
131 | { |
132 | start_pc += 2; | |
133 | w = read_memory_integer (start_pc, 2); | |
134 | } | |
135 | ||
136 | return start_pc; | |
137 | } | |
138 | ||
18b46e7c | 139 | /* Disassemble an instruction. */ |
9faacb92 SC |
140 | |
141 | int | |
18b46e7c SS |
142 | gdb_print_insn_sh (memaddr, info) |
143 | bfd_vma memaddr; | |
144 | disassemble_info *info; | |
9faacb92 | 145 | { |
5f2f2809 | 146 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
5076ecd0 | 147 | return print_insn_sh (memaddr, info); |
5f2f2809 | 148 | else |
5076ecd0 | 149 | return print_insn_shl (memaddr, info); |
9faacb92 | 150 | } |
18b46e7c | 151 | |
9faacb92 SC |
152 | /* Given a GDB frame, determine the address of the calling function's frame. |
153 | This will be used to create a new GDB frame struct, and then | |
154 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
155 | ||
156 | For us, the frame address is its stack pointer value, so we look up | |
157 | the function prologue to determine the caller's sp value, and return it. */ | |
158 | ||
669caa9c SS |
159 | CORE_ADDR |
160 | sh_frame_chain (frame) | |
161 | struct frame_info *frame; | |
9faacb92 | 162 | { |
69992fc8 MS |
163 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) |
164 | return frame->frame; /* dummy frame same as caller's frame */ | |
669caa9c SS |
165 | if (!inside_entry_file (frame->pc)) |
166 | return read_memory_integer (FRAME_FP (frame) + frame->f_offset, 4); | |
9faacb92 SC |
167 | else |
168 | return 0; | |
169 | } | |
170 | ||
69992fc8 MS |
171 | /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing |
172 | we might want to do here is to check REGNUM against the clobber mask, and | |
173 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
174 | would provide a graceful failure mode when trying to get the value of | |
175 | caller-saves registers for an inner frame. */ | |
176 | ||
177 | CORE_ADDR | |
178 | sh_find_callers_reg (fi, regnum) | |
179 | struct frame_info *fi; | |
180 | int regnum; | |
181 | { | |
182 | struct frame_saved_regs fsr; | |
183 | ||
184 | for (; fi; fi = fi->next) | |
185 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
186 | /* When the caller requests PR from the dummy frame, we return PC because | |
187 | that's where the previous routine appears to have done a call from. */ | |
dc1b349d | 188 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); |
69992fc8 MS |
189 | else |
190 | { | |
191 | FRAME_FIND_SAVED_REGS(fi, fsr); | |
192 | if (fsr.regs[regnum] != 0) | |
193 | return read_memory_integer (fsr.regs[regnum], | |
194 | REGISTER_RAW_SIZE(regnum)); | |
195 | } | |
196 | return read_register (regnum); | |
197 | } | |
198 | ||
66d05e03 SS |
199 | /* Put here the code to store, into a struct frame_saved_regs, the |
200 | addresses of the saved registers of frame described by FRAME_INFO. | |
9faacb92 | 201 | This includes special registers such as pc and fp saved in special |
66d05e03 SS |
202 | ways in the stack frame. sp is even more special: the address we |
203 | return for it IS the sp for the next frame. */ | |
9faacb92 SC |
204 | |
205 | void | |
69992fc8 | 206 | sh_frame_find_saved_regs (fi, fsr) |
9faacb92 SC |
207 | struct frame_info *fi; |
208 | struct frame_saved_regs *fsr; | |
209 | { | |
7ccb1e44 | 210 | int where[NUM_REGS]; |
9faacb92 SC |
211 | int rn; |
212 | int have_fp = 0; | |
213 | int depth; | |
214 | int pc; | |
215 | int opc; | |
216 | int insn; | |
c4deed18 | 217 | int r3_val = 0; |
dc1b349d | 218 | char * dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame); |
69992fc8 MS |
219 | |
220 | if (dummy_regs) | |
221 | { | |
222 | /* DANGER! This is ONLY going to work if the char buffer format of | |
223 | the saved registers is byte-for-byte identical to the | |
224 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
225 | memcpy (&fsr->regs, dummy_regs, sizeof(fsr)); | |
226 | return; | |
227 | } | |
9faacb92 SC |
228 | |
229 | opc = pc = get_pc_function_start (fi->pc); | |
230 | ||
231 | insn = read_memory_integer (pc, 2); | |
232 | ||
c4deed18 SC |
233 | fi->leaf_function = 1; |
234 | fi->f_offset = 0; | |
235 | ||
9faacb92 SC |
236 | for (rn = 0; rn < NUM_REGS; rn++) |
237 | where[rn] = -1; | |
238 | ||
239 | depth = 0; | |
240 | ||
241 | /* Loop around examining the prologue insns, but give up | |
242 | after 15 of them, since we're getting silly then */ | |
243 | while (pc < opc + 15 * 2) | |
244 | { | |
245 | /* See where the registers will be saved to */ | |
246 | if (IS_PUSH (insn)) | |
247 | { | |
248 | pc += 2; | |
249 | rn = GET_PUSHED_REG (insn); | |
250 | where[rn] = depth; | |
251 | insn = read_memory_integer (pc, 2); | |
252 | depth += 4; | |
253 | } | |
254 | else if (IS_STS (insn)) | |
255 | { | |
256 | pc += 2; | |
257 | where[PR_REGNUM] = depth; | |
258 | insn = read_memory_integer (pc, 2); | |
c4deed18 SC |
259 | /* If we're storing the pr then this isn't a leaf */ |
260 | fi->leaf_function = 0; | |
9faacb92 SC |
261 | depth += 4; |
262 | } | |
c4deed18 SC |
263 | else if (IS_MOV_R3 (insn)) |
264 | { | |
5f2f2809 SC |
265 | r3_val = (char) (insn & 0xff); |
266 | pc += 2; | |
c4deed18 SC |
267 | insn = read_memory_integer (pc, 2); |
268 | } | |
269 | else if (IS_SHLL_R3 (insn)) | |
270 | { | |
5f2f2809 SC |
271 | r3_val <<= 1; |
272 | pc += 2; | |
c4deed18 SC |
273 | insn = read_memory_integer (pc, 2); |
274 | } | |
275 | else if (IS_ADD_R3SP (insn)) | |
276 | { | |
277 | depth += -r3_val; | |
5f2f2809 | 278 | pc += 2; |
c4deed18 SC |
279 | insn = read_memory_integer (pc, 2); |
280 | } | |
9faacb92 SC |
281 | else if (IS_ADD_SP (insn)) |
282 | { | |
283 | pc += 2; | |
284 | depth += -((char) (insn & 0xff)); | |
285 | insn = read_memory_integer (pc, 2); | |
286 | } | |
df14b38b SC |
287 | else |
288 | break; | |
9faacb92 SC |
289 | } |
290 | ||
291 | /* Now we know how deep things are, we can work out their addresses */ | |
292 | ||
293 | for (rn = 0; rn < NUM_REGS; rn++) | |
294 | { | |
295 | if (where[rn] >= 0) | |
296 | { | |
297 | if (rn == FP_REGNUM) | |
298 | have_fp = 1; | |
299 | ||
300 | fsr->regs[rn] = fi->frame - where[rn] + depth - 4; | |
301 | } | |
302 | else | |
303 | { | |
304 | fsr->regs[rn] = 0; | |
305 | } | |
306 | } | |
307 | ||
308 | if (have_fp) | |
309 | { | |
9faacb92 SC |
310 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[FP_REGNUM], 4); |
311 | } | |
312 | else | |
313 | { | |
314 | fsr->regs[SP_REGNUM] = fi->frame - 4; | |
315 | } | |
316 | ||
c4deed18 | 317 | fi->f_offset = depth - where[FP_REGNUM] - 4; |
9faacb92 SC |
318 | /* Work out the return pc - either from the saved pr or the pr |
319 | value */ | |
9faacb92 SC |
320 | } |
321 | ||
322 | /* initialize the extra info saved in a FRAME */ | |
323 | ||
324 | void | |
69992fc8 | 325 | sh_init_extra_frame_info (fromleaf, fi) |
9faacb92 SC |
326 | int fromleaf; |
327 | struct frame_info *fi; | |
328 | { | |
69992fc8 | 329 | struct frame_saved_regs fsr; |
66d05e03 | 330 | |
5c8ba017 | 331 | if (fi->next) |
69992fc8 | 332 | fi->pc = FRAME_SAVED_PC (fi->next); |
5c8ba017 | 333 | |
69992fc8 MS |
334 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
335 | { | |
336 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
337 | by assuming it's always FP. */ | |
dc1b349d MS |
338 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, |
339 | SP_REGNUM); | |
340 | fi->return_pc = generic_read_register_dummy (fi->pc, fi->frame, | |
341 | PC_REGNUM); | |
69992fc8 MS |
342 | fi->f_offset = -(CALL_DUMMY_LENGTH + 4); |
343 | fi->leaf_function = 0; | |
344 | return; | |
345 | } | |
346 | else | |
347 | { | |
348 | FRAME_FIND_SAVED_REGS (fi, fsr); | |
349 | fi->return_pc = sh_find_callers_reg (fi, PR_REGNUM); | |
350 | } | |
9faacb92 SC |
351 | } |
352 | ||
9faacb92 SC |
353 | /* Discard from the stack the innermost frame, |
354 | restoring all saved registers. */ | |
355 | ||
356 | void | |
69992fc8 | 357 | sh_pop_frame () |
9faacb92 | 358 | { |
669caa9c | 359 | register struct frame_info *frame = get_current_frame (); |
9faacb92 SC |
360 | register CORE_ADDR fp; |
361 | register int regnum; | |
362 | struct frame_saved_regs fsr; | |
9faacb92 | 363 | |
69992fc8 MS |
364 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) |
365 | generic_pop_dummy_frame (); | |
366 | else | |
367 | { | |
368 | fp = FRAME_FP (frame); | |
369 | get_frame_saved_regs (frame, &fsr); | |
9faacb92 | 370 | |
69992fc8 MS |
371 | /* Copy regs from where they were saved in the frame */ |
372 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
9faacb92 | 373 | if (fsr.regs[regnum]) |
69992fc8 MS |
374 | write_register (regnum, read_memory_integer (fsr.regs[regnum], 4)); |
375 | ||
376 | write_register (PC_REGNUM, frame->return_pc); | |
377 | write_register (SP_REGNUM, fp + 4); | |
378 | } | |
379 | flush_cached_frames (); | |
380 | } | |
381 | ||
382 | /* Function: push_arguments | |
383 | Setup the function arguments for calling a function in the inferior. | |
384 | ||
385 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
386 | which are dedicated for passing function arguments. Up to the first | |
387 | four arguments (depending on size) may go into these registers. | |
388 | The rest go on the stack. | |
389 | ||
390 | Arguments that are smaller than 4 bytes will still take up a whole | |
391 | register or a whole 32-bit word on the stack, and will be | |
392 | right-justified in the register or the stack word. This includes | |
393 | chars, shorts, and small aggregate types. | |
394 | ||
395 | Arguments that are larger than 4 bytes may be split between two or | |
396 | more registers. If there are not enough registers free, an argument | |
397 | may be passed partly in a register (or registers), and partly on the | |
398 | stack. This includes doubles, long longs, and larger aggregates. | |
399 | As far as I know, there is no upper limit to the size of aggregates | |
400 | that will be passed in this way; in other words, the convention of | |
401 | passing a pointer to a large aggregate instead of a copy is not used. | |
402 | ||
403 | An exceptional case exists for struct arguments (and possibly other | |
404 | aggregates such as arrays) if the size is larger than 4 bytes but | |
405 | not a multiple of 4 bytes. In this case the argument is never split | |
406 | between the registers and the stack, but instead is copied in its | |
407 | entirety onto the stack, AND also copied into as many registers as | |
408 | there is room for. In other words, space in registers permitting, | |
409 | two copies of the same argument are passed in. As far as I can tell, | |
410 | only the one on the stack is used, although that may be a function | |
411 | of the level of compiler optimization. I suspect this is a compiler | |
412 | bug. Arguments of these odd sizes are left-justified within the | |
413 | word (as opposed to arguments smaller than 4 bytes, which are | |
414 | right-justified). | |
415 | ||
416 | ||
417 | If the function is to return an aggregate type such as a struct, it | |
418 | is either returned in the normal return value register R0 (if its | |
419 | size is no greater than one byte), or else the caller must allocate | |
420 | space into which the callee will copy the return value (if the size | |
421 | is greater than one byte). In this case, a pointer to the return | |
422 | value location is passed into the callee in register R2, which does | |
423 | not displace any of the other arguments passed in via registers R4 | |
424 | to R7. */ | |
425 | ||
426 | CORE_ADDR | |
427 | sh_push_arguments (nargs, args, sp, struct_return, struct_addr) | |
428 | int nargs; | |
429 | value_ptr *args; | |
430 | CORE_ADDR sp; | |
431 | unsigned char struct_return; | |
432 | CORE_ADDR struct_addr; | |
433 | { | |
dc1b349d | 434 | int stack_offset, stack_alloc; |
69992fc8 MS |
435 | int argreg; |
436 | int argnum; | |
dc1b349d | 437 | struct type *type; |
69992fc8 MS |
438 | CORE_ADDR regval; |
439 | char *val; | |
440 | char valbuf[4]; | |
441 | int len; | |
dc1b349d | 442 | int odd_sized_struct; |
69992fc8 MS |
443 | |
444 | /* first force sp to a 4-byte alignment */ | |
445 | sp = sp & ~3; | |
446 | ||
447 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
448 | register */ | |
449 | if (struct_return) | |
450 | write_register (STRUCT_RETURN_REGNUM, struct_addr); | |
451 | ||
dc1b349d MS |
452 | /* Now make sure there's space on the stack */ |
453 | for (argnum = 0, stack_alloc = 0; | |
454 | argnum < nargs; argnum++) | |
455 | stack_alloc += ((TYPE_LENGTH(VALUE_TYPE(args[argnum])) + 3) & ~3); | |
456 | sp -= stack_alloc; /* make room on stack for args */ | |
457 | ||
458 | ||
459 | /* Now load as many as possible of the first arguments into | |
460 | registers, and push the rest onto the stack. There are 16 bytes | |
461 | in four registers available. Loop thru args from first to last. */ | |
462 | ||
463 | argreg = ARG0_REGNUM; | |
464 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
69992fc8 | 465 | { |
dc1b349d MS |
466 | type = VALUE_TYPE (args[argnum]); |
467 | len = TYPE_LENGTH (type); | |
468 | memset(valbuf, 0, sizeof(valbuf)); | |
69992fc8 | 469 | if (len < 4) |
dc1b349d MS |
470 | { /* value gets right-justified in the register or stack word */ |
471 | memcpy(valbuf + (4 - len), | |
69992fc8 | 472 | (char *) VALUE_CONTENTS (args[argnum]), len); |
dc1b349d MS |
473 | val = valbuf; |
474 | } | |
69992fc8 | 475 | else |
dc1b349d | 476 | val = (char *) VALUE_CONTENTS (args[argnum]); |
69992fc8 | 477 | |
dc1b349d MS |
478 | if (len > 4 && (len & 3) != 0) |
479 | odd_sized_struct = 1; /* such structs go entirely on stack */ | |
480 | else | |
481 | odd_sized_struct = 0; | |
69992fc8 | 482 | while (len > 0) |
9faacb92 | 483 | { |
dc1b349d | 484 | if (argreg > ARGLAST_REGNUM || odd_sized_struct) |
409f64ae | 485 | { /* must go on the stack */ |
dc1b349d MS |
486 | write_memory (sp + stack_offset, val, 4); |
487 | stack_offset += 4; | |
69992fc8 | 488 | } |
dc1b349d MS |
489 | /* NOTE WELL!!!!! This is not an "else if" clause!!! |
490 | That's because some *&^%$ things get passed on the stack | |
491 | AND in the registers! */ | |
492 | if (argreg <= ARGLAST_REGNUM) | |
409f64ae | 493 | { /* there's room in a register */ |
dc1b349d MS |
494 | regval = extract_address (val, REGISTER_RAW_SIZE(argreg)); |
495 | write_register (argreg++, regval); | |
496 | } | |
497 | /* Store the value 4 bytes at a time. This means that things | |
498 | larger than 4 bytes may go partly in registers and partly | |
499 | on the stack. */ | |
500 | len -= REGISTER_RAW_SIZE(argreg); | |
501 | val += REGISTER_RAW_SIZE(argreg); | |
9faacb92 SC |
502 | } |
503 | } | |
dc1b349d MS |
504 | return sp; |
505 | } | |
9faacb92 | 506 | |
dc1b349d MS |
507 | /* Function: push_return_address (pc) |
508 | Set up the return address for the inferior function call. | |
509 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
69992fc8 | 510 | |
dc1b349d MS |
511 | CORE_ADDR |
512 | sh_push_return_address (pc, sp) | |
513 | CORE_ADDR pc; | |
514 | CORE_ADDR sp; | |
515 | { | |
409f64ae | 516 | write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ()); |
dc1b349d MS |
517 | return sp; |
518 | } | |
69992fc8 | 519 | |
dc1b349d MS |
520 | /* Function: fix_call_dummy |
521 | Poke the callee function's address into the destination part of | |
522 | the CALL_DUMMY. The address is actually stored in a data word | |
523 | following the actualy CALL_DUMMY instructions, which will load | |
524 | it into a register using PC-relative addressing. This function | |
525 | expects the CALL_DUMMY to look like this: | |
69992fc8 | 526 | |
dc1b349d MS |
527 | mov.w @(2,PC), R8 |
528 | jsr @R8 | |
529 | nop | |
530 | trap | |
531 | <destination> | |
532 | */ | |
533 | ||
534 | int | |
535 | sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) | |
536 | char *dummy; | |
537 | CORE_ADDR pc; | |
538 | CORE_ADDR fun; | |
539 | int nargs; | |
540 | value_ptr *args; | |
541 | struct type *type; | |
542 | int gcc_p; | |
543 | { | |
544 | *(unsigned long *) (dummy + 8) = fun; | |
69992fc8 MS |
545 | } |
546 | ||
dc1b349d MS |
547 | /* Function: get_saved_register |
548 | Just call the generic_get_saved_register function. */ | |
69992fc8 MS |
549 | |
550 | void | |
dc1b349d MS |
551 | get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) |
552 | char *raw_buffer; | |
553 | int *optimized; | |
554 | CORE_ADDR *addrp; | |
555 | struct frame_info *frame; | |
556 | int regnum; | |
557 | enum lval_type *lval; | |
69992fc8 | 558 | { |
dc1b349d MS |
559 | generic_get_saved_register (raw_buffer, optimized, addrp, |
560 | frame, regnum, lval); | |
9faacb92 | 561 | } |
edd01519 | 562 | |
dc1b349d | 563 | |
00dd4fd9 SS |
564 | /* Command to set the processor type. */ |
565 | ||
566 | void | |
567 | sh_set_processor_type_command (args, from_tty) | |
568 | char *args; | |
569 | int from_tty; | |
570 | { | |
571 | int i; | |
572 | char *temp; | |
573 | ||
574 | /* The `set' commands work by setting the value, then calling the hook, | |
575 | so we let the general command modify a scratch location, then decide | |
576 | here if we really want to modify the processor type. */ | |
577 | if (tmp_sh_processor_type == NULL || *tmp_sh_processor_type == '\0') | |
578 | { | |
579 | printf_unfiltered ("The known SH processor types are as follows:\n\n"); | |
580 | for (i = 0; sh_processor_type_table[i].name != NULL; ++i) | |
581 | printf_unfiltered ("%s\n", sh_processor_type_table[i].name); | |
582 | ||
583 | /* Restore the value. */ | |
584 | tmp_sh_processor_type = strsave (sh_processor_type); | |
585 | ||
586 | return; | |
587 | } | |
588 | ||
589 | if (!sh_set_processor_type (tmp_sh_processor_type)) | |
590 | { | |
591 | /* Restore to a valid value before erroring out. */ | |
592 | temp = tmp_sh_processor_type; | |
593 | tmp_sh_processor_type = strsave (sh_processor_type); | |
594 | error ("Unknown processor type `%s'.", temp); | |
595 | } | |
596 | } | |
597 | ||
12ffa10c SS |
598 | /* This is a dummy not actually run. */ |
599 | ||
00dd4fd9 SS |
600 | static void |
601 | sh_show_processor_type_command (args, from_tty) | |
602 | char *args; | |
603 | int from_tty; | |
604 | { | |
605 | } | |
606 | ||
607 | /* Modify the actual processor type. */ | |
608 | ||
609 | int | |
610 | sh_set_processor_type (str) | |
611 | char *str; | |
612 | { | |
613 | int i, j; | |
614 | ||
615 | if (str == NULL) | |
616 | return 0; | |
617 | ||
618 | for (i = 0; sh_processor_type_table[i].name != NULL; ++i) | |
619 | { | |
620 | if (strcasecmp (str, sh_processor_type_table[i].name) == 0) | |
621 | { | |
622 | sh_processor_type = str; | |
623 | ||
624 | for (j = 0; j < NUM_REGS; ++j) | |
625 | reg_names[j] = sh_processor_type_table[i].regnames[j]; | |
626 | ||
627 | return 1; | |
628 | } | |
629 | } | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
edd01519 | 634 | /* Print the registers in a form similar to the E7000 */ |
669caa9c | 635 | |
edd01519 | 636 | static void |
69992fc8 | 637 | sh_show_regs (args, from_tty) |
669caa9c SS |
638 | char *args; |
639 | int from_tty; | |
edd01519 | 640 | { |
5f2f2809 SC |
641 | printf_filtered ("PC=%08x SR=%08x PR=%08x MACH=%08x MACHL=%08x\n", |
642 | read_register (PC_REGNUM), | |
643 | read_register (SR_REGNUM), | |
644 | read_register (PR_REGNUM), | |
645 | read_register (MACH_REGNUM), | |
646 | read_register (MACL_REGNUM)); | |
647 | ||
648 | printf_filtered ("R0-R7 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
649 | read_register (0), | |
650 | read_register (1), | |
651 | read_register (2), | |
652 | read_register (3), | |
653 | read_register (4), | |
654 | read_register (5), | |
655 | read_register (6), | |
656 | read_register (7)); | |
657 | printf_filtered ("R8-R15 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
658 | read_register (8), | |
659 | read_register (9), | |
660 | read_register (10), | |
661 | read_register (11), | |
662 | read_register (12), | |
663 | read_register (13), | |
664 | read_register (14), | |
665 | read_register (15)); | |
edd01519 | 666 | } |
69992fc8 | 667 | |
dc1b349d MS |
668 | /* Function: extract_return_value |
669 | Find a function's return value in the appropriate registers (in regbuf), | |
670 | and copy it into valbuf. */ | |
671 | ||
69992fc8 MS |
672 | void |
673 | sh_extract_return_value (type, regbuf, valbuf) | |
674 | struct type *type; | |
675 | void *regbuf; | |
676 | void *valbuf; | |
677 | { | |
678 | int len = TYPE_LENGTH(type); | |
679 | ||
680 | if (len <= 4) | |
681 | memcpy (valbuf, ((char *) regbuf) + 4 - len, len); | |
682 | else if (len <= 8) | |
683 | memcpy (valbuf, ((char *) regbuf) + 8 - len, len); | |
684 | else | |
685 | error ("bad size for return value"); | |
686 | } | |
687 | ||
976bb0be | 688 | void |
df14b38b SC |
689 | _initialize_sh_tdep () |
690 | { | |
00dd4fd9 SS |
691 | struct cmd_list_element *c; |
692 | ||
18b46e7c SS |
693 | tm_print_insn = gdb_print_insn_sh; |
694 | ||
00dd4fd9 SS |
695 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
696 | (char *) &tmp_sh_processor_type, | |
697 | "Set the type of SH processor in use.\n\ | |
698 | Set this to be able to access processor-type-specific registers.\n\ | |
699 | ", | |
700 | &setlist); | |
701 | c->function.cfunc = sh_set_processor_type_command; | |
702 | c = add_show_from_set (c, &showlist); | |
703 | c->function.cfunc = sh_show_processor_type_command; | |
704 | ||
705 | tmp_sh_processor_type = strsave (DEFAULT_SH_TYPE); | |
706 | sh_set_processor_type_command (strsave (DEFAULT_SH_TYPE), 0); | |
707 | ||
69992fc8 | 708 | add_com ("regs", class_vars, sh_show_regs, "Print all registers"); |
cd21cbc4 MA |
709 | |
710 | /* Reduce the remote write size because some CMONs can't take | |
711 | more than 400 bytes in a packet. 300 seems like a safe bet. */ | |
712 | remote_write_size = 300; | |
df14b38b | 713 | } |
69992fc8 | 714 |