]> Git Repo - binutils.git/blame - opcodes/ChangeLog
Add an index operand to some of the iq2000 co-processor instructions
[binutils.git] / opcodes / ChangeLog
CommitLineData
4030fa5a
NC
12004-10-27 Nick Clifton <[email protected]>
2
3 * opcodes/iq2000-asm.c: Regenerate.
4 * opcodes/iq2000-desc.c: Regenerate.
5 * opcodes/iq2000-desc.h: Regenerate.
6 * opcodes/iq2000-dis.c: Regenerate.
7 * opcodes/iq2000-ibld.c: Regenerate.
8 * opcodes/iq2000-opc.c: Regenerate.
9 * opcodes/iq2000-opc.h: Regenerate.
10
fc3d45e8
TL
112004-10-21 Tomer Levi <[email protected]>
12
13 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
14 us4, us5 (respectively).
15 Remove unsupported 'popa' instruction.
16 Reverse operands order in store co-processor instructions.
17
3c55da70
AM
182004-10-15 Alan Modra <[email protected]>
19
20 * Makefile.am: Run "make dep-am"
21 * Makefile.in: Regenerate.
22
7fa3d080
BW
232004-10-12 Bob Wilson <[email protected]>
24
25 * xtensa-dis.c: Use ISO C90 formatting.
26
e612bb4d
AM
272004-10-09 Alan Modra <[email protected]>
28
29 * ppc-opc.c: Revert 2004-09-09 change.
30
43cd72b9
BW
312004-10-07 Bob Wilson <[email protected]>
32
33 * xtensa-dis.c (state_names): Delete.
34 (fetch_data): Use xtensa_isa_maxlength.
35 (print_xtensa_operand): Replace operand parameter with opcode/operand
36 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
37 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
38 instruction bundles. Use xmalloc instead of malloc.
39
bbac1f2a
NC
402004-10-07 David Gibson <[email protected]>
41
42 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
43 initializers.
44
48c9f030
NC
452004-10-07 Tomer Levi <[email protected]>
46
47 * crx-opc.c (crx_instruction): Support Co-processor insns.
48 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
49 (getregliststring): Change function to use the above enum.
50 (print_arg): Handle CO-Processor insns.
51 (crx_cinvs): Add 'b' option to invalidate the branch-target
52 cache.
53
12c64a4e
AH
542004-10-06 Aldy Hernandez <[email protected]>
55
56 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
57 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
58 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
59 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
60 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
61
14127cc4
NC
622004-10-01 Bill Farmer <[email protected]>
63
64 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
65 rather than add it.
66
0dd132b6
NC
672004-09-30 Paul Brook <[email protected]>
68
69 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
70 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
71
3f85e526
L
722004-09-17 H.J. Lu <[email protected]>
73
74 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
75 (CONFIG_STATUS_DEPENDENCIES): New.
76 (Makefile): Removed.
77 (config.status): Likewise.
78 * Makefile.in: Regenerated.
79
8ae85421
AM
802004-09-17 Alan Modra <[email protected]>
81
82 * Makefile.am: Run "make dep-am".
83 * Makefile.in: Regenerate.
84 * aclocal.m4: Regenerate.
85 * configure: Regenerate.
86 * po/POTFILES.in: Regenerate.
87 * po/opcodes.pot: Regenerate.
88
24443139
AS
892004-09-11 Andreas Schwab <[email protected]>
90
91 * configure: Rebuild.
92
2a309db0
AM
932004-09-09 Segher Boessenkool <[email protected]>
94
95 * ppc-opc.c (L): Make this field not optional.
96
42851540
NC
972004-09-03 Tomer Levi <[email protected]>
98
99 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
100 Fix parameter to 'm[t|f]csr' insns.
101
979273e3
NN
1022004-08-30 Nathanael Nerode <[email protected]>
103
104 * configure.in: Autoupdate to autoconf 2.59.
105 * aclocal.m4: Rebuild with aclocal 1.4p6.
106 * configure: Rebuild with autoconf 2.59.
107 * Makefile.in: Rebuild with automake 1.4p6 (picking up
108 bfd changes for autoconf 2.59 on the way).
109 * config.in: Rebuild with autoheader 2.59.
110
ac28a1cb
RS
1112004-08-27 Richard Sandiford <[email protected]>
112
113 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
114
30d1c836
ML
1152004-07-30 Michal Ludvig <[email protected]>
116
117 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
118 (GRPPADLCK2): New define.
119 (twobyte_has_modrm): True for 0xA6.
120 (grps): GRPPADLCK2 for opcode 0xA6.
121
0b0ac059
AO
1222004-07-29 Alexandre Oliva <[email protected]>
123
124 Introduce SH2a support.
125 * sh-opc.h (arch_sh2a_base): Renumber.
126 (arch_sh2a_nofpu_base): Remove.
127 (arch_sh_base_mask): Adjust.
128 (arch_opann_mask): New.
129 (arch_sh2a, arch_sh2a_nofpu): Adjust.
130 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
131 (sh_table): Adjust whitespace.
132 2004-02-24 Corinna Vinschen <[email protected]>
133 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
134 instruction list throughout.
135 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
136 of arch_sh2a in instruction list throughout.
137 (arch_sh2e_up): Accomodate above changes.
138 (arch_sh2_up): Ditto.
139 2004-02-20 Corinna Vinschen <[email protected]>
140 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
141 2004-02-18 Corinna Vinschen <[email protected]>
142 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
143 * sh-opc.h (arch_sh2a_nofpu): New.
144 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
145 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
146 instruction.
147 2004-01-20 DJ Delorie <[email protected]>
148 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
149 2003-12-29 DJ Delorie <[email protected]>
150 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
151 sh_opcode_info, sh_table): Add sh2a support.
152 (arch_op32): New, to tag 32-bit opcodes.
153 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
154 2003-12-02 Michael Snyder <[email protected]>
155 * sh-opc.h (arch_sh2a): Add.
156 * sh-dis.c (arch_sh2a): Handle.
157 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
158
670ec21d
NC
1592004-07-27 Tomer Levi <[email protected]>
160
161 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
162
ed049af3
NC
1632004-07-22 Nick Clifton <[email protected]>
164
165 PR/280
166 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
167 insns - this is done by objdump itself.
168 * h8500-dis.c (print_insn_h8500): Likewise.
169
20f0a1fc
NC
1702004-07-21 Jan Beulich <[email protected]>
171
172 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
173 regardless of address size prefix in effect.
174 (ptr_reg): Size or address registers does not depend on rex64, but
175 on the presence of an address size override.
176 (OP_MMX): Use rex.x only for xmm registers.
177 (OP_EM): Use rex.z only for xmm registers.
178
6f14957b
MR
1792004-07-20 Maciej W. Rozycki <[email protected]>
180
181 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
182 move/branch operations to the bottom so that VR5400 multimedia
183 instructions take precedence in disassembly.
184
1586d91e
MR
1852004-07-20 Maciej W. Rozycki <[email protected]>
186
187 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
188 ISA-specific "break" encoding.
189
982de27a
NC
1902004-07-13 Elvis Chiang <[email protected]>
191
192 * arm-opc.h: Fix typo in comment.
193
4300ab10
AS
1942004-07-11 Andreas Schwab <[email protected]>
195
196 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
197
8577e690
AS
1982004-07-09 Andreas Schwab <[email protected]>
199
200 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
201
1fe1f39c
NC
2022004-07-07 Tomer Levi <[email protected]>
203
204 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
205 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
206 (crx-dis.lo): New target.
207 (crx-opc.lo): Likewise.
208 * Makefile.in: Regenerate.
209 * configure.in: Handle bfd_crx_arch.
210 * configure: Regenerate.
211 * crx-dis.c: New file.
212 * crx-opc.c: New file.
213 * disassemble.c (ARCH_crx): Define.
214 (disassembler): Handle ARCH_crx.
215
7a33b495
JW
2162004-06-29 James E Wilson <[email protected]>
217
218 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
219 * ia64-asmtab.c: Regnerate.
220
98e69875
AM
2212004-06-28 Alan Modra <[email protected]>
222
223 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
224 (extract_fxm): Don't test dialect.
225 (XFXFXM_MASK): Include the power4 bit.
226 (XFXM): Add p4 param.
227 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
228
a53b85e2
AO
2292004-06-27 Alexandre Oliva <[email protected]>
230
231 2003-07-21 Richard Sandiford <[email protected]>
232 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
233
d0618d1c
AM
2342004-06-26 Alan Modra <[email protected]>
235
236 * ppc-opc.c (BH, XLBH_MASK): Define.
237 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
238
1d9f512f
AM
2392004-06-24 Alan Modra <[email protected]>
240
241 * i386-dis.c (x_mode): Comment.
242 (two_source_ops): File scope.
243 (float_mem): Correct fisttpll and fistpll.
244 (float_mem_mode): New table.
245 (dofloat): Use it.
246 (OP_E): Correct intel mode PTR output.
247 (ptr_reg): Use open_char and close_char.
248 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
249 operands. Set two_source_ops.
250
52886d70
AM
2512004-06-15 Alan Modra <[email protected]>
252
253 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
254 instead of _raw_size.
255
bad9ceea
JJ
2562004-06-08 Jakub Jelinek <[email protected]>
257
258 * ia64-gen.c (in_iclass): Handle more postinc st
259 and ld variants.
260 * ia64-asmtab.c: Rebuilt.
261
0451f5df
MS
2622004-06-01 Martin Schwidefsky <[email protected]>
263
264 * s390-opc.txt: Correct architecture mask for some opcodes.
265 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
266 in the esa mode as well.
267
f6f9408f
JR
2682004-05-28 Andrew Stubbs <[email protected]>
269
270 * sh-dis.c (target_arch): Make unsigned.
271 (print_insn_sh): Replace (most of) switch with a call to
272 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
273 * sh-opc.h: Redefine architecture flags values.
274 Add sh3-nommu architecture.
275 Reorganise <arch>_up macros so they make more visual sense.
276 (SH_MERGE_ARCH_SET): Define new macro.
277 (SH_VALID_BASE_ARCH_SET): Likewise.
278 (SH_VALID_MMU_ARCH_SET): Likewise.
279 (SH_VALID_CO_ARCH_SET): Likewise.
280 (SH_VALID_ARCH_SET): Likewise.
281 (SH_MERGE_ARCH_SET_VALID): Likewise.
282 (SH_ARCH_SET_HAS_FPU): Likewise.
283 (SH_ARCH_SET_HAS_DSP): Likewise.
284 (SH_ARCH_UNKNOWN_ARCH): Likewise.
285 (sh_get_arch_from_bfd_mach): Add prototype.
286 (sh_get_arch_up_from_bfd_mach): Likewise.
287 (sh_get_bfd_mach_from_arch_set): Likewise.
288 (sh_merge_bfd_arc): Likewise.
289
be8c092b
NC
2902004-05-24 Peter Barada <[email protected]>
291
292 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
293 into new match_insn_m68k function. Loop over canidate
294 matches and select first that completely matches.
295 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
296 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
297 to verify addressing for MAC/EMAC.
298 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
299 reigster halves since 'fpu' and 'spl' look misleading.
300 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
301 * m68k-opc.c: Rearragne mac/emac cases to use longest for
302 first, tighten up match masks.
303 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
304 'size' from special case code in print_insn_m68k to
305 determine decode size of insns.
306
a30e9cc4
AM
3072004-05-19 Alan Modra <[email protected]>
308
309 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
310 well as when -mpower4.
311
9598fbe5
NC
3122004-05-13 Nick Clifton <[email protected]>
313
314 * po/fr.po: Updated French translation.
315
6b6e92f4
NC
3162004-05-05 Peter Barada <[email protected]>
317
318 * m68k-dis.c(print_insn_m68k): Add new chips, use core
319 variants in arch_mask. Only set m68881/68851 for 68k chips.
320 * m68k-op.c: Switch from ColdFire chips to core variants.
321
a404d431
AM
3222004-05-05 Alan Modra <[email protected]>
323
a30e9cc4 324 PR 147.
a404d431
AM
325 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
326
f3806e43
BE
3272004-04-29 Ben Elliston <[email protected]>
328
520ceea4
BE
329 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
330 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 331
1f1799d5
KK
3322004-04-22 Kaz Kojima <[email protected]>
333
334 * sh-dis.c (print_insn_sh): Print the value in constant pool
335 as a symbol if it looks like a symbol.
336
fd99574b
NC
3372004-04-22 Peter Barada <[email protected]>
338
339 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
340 appropriate ColdFire architectures.
341 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
342 mask addressing.
343 Add EMAC instructions, fix MAC instructions. Remove
344 macmw/macml/msacmw/msacml instructions since mask addressing now
345 supported.
346
b4781d44
JJ
3472004-04-20 Jakub Jelinek <[email protected]>
348
349 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
350 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
351 suffix. Use fmov*x macros, create all 3 fpsize variants in one
352 macro. Adjust all users.
353
91809fda
NC
3542004-04-15 Anil Paranjpe <[email protected]>
355
356 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
357 separately.
358
f4453dfa
NC
3592004-03-30 Kazuhiro Inaoka <[email protected]>
360
361 * m32r-asm.c: Regenerate.
362
9b0de91a
SS
3632004-03-29 Stan Shebs <[email protected]>
364
365 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
366 used.
367
e20c0b3d
AM
3682004-03-19 Alan Modra <[email protected]>
369
370 * aclocal.m4: Regenerate.
371 * config.in: Regenerate.
372 * configure: Regenerate.
373 * po/POTFILES.in: Regenerate.
374 * po/opcodes.pot: Regenerate.
375
fdd12ef3
AM
3762004-03-16 Alan Modra <[email protected]>
377
378 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
379 PPC_OPERANDS_GPR_0.
380 * ppc-opc.c (RA0): Define.
381 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
382 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 383 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 384
2dc111b3 3852004-03-15 Aldy Hernandez <[email protected]>
fdd12ef3
AM
386
387 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 388
7bfeee7b
AM
3892004-03-15 Alan Modra <[email protected]>
390
391 * sparc-dis.c (print_insn_sparc): Update getword prototype.
392
7ffdda93
ML
3932004-03-12 Michal Ludvig <[email protected]>
394
395 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 396 (grps): Delete GRPPLOCK entry.
7ffdda93 397
cc0ec051
AM
3982004-03-12 Alan Modra <[email protected]>
399
400 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
401 (M, Mp): Use OP_M.
402 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
403 (GRPPADLCK): Define.
404 (dis386): Use NOP_Fixup on "nop".
405 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
406 (twobyte_has_modrm): Set for 0xa7.
407 (padlock_table): Delete. Move to..
408 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
409 and clflush.
410 (print_insn): Revert PADLOCK_SPECIAL code.
411 (OP_E): Delete sfence, lfence, mfence checks.
412
4fd61dcb
JJ
4132004-03-12 Jakub Jelinek <[email protected]>
414
415 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
416 (INVLPG_Fixup): New function.
417 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
418
0f10071e
ML
4192004-03-12 Michal Ludvig <[email protected]>
420
421 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
422 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
423 (padlock_table): New struct with PadLock instructions.
424 (print_insn): Handle PADLOCK_SPECIAL.
425
c02908d2
AM
4262004-03-12 Alan Modra <[email protected]>
427
428 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
429 (OP_E): Twiddle clflush to sfence here.
430
d5bb7600
NC
4312004-03-08 Nick Clifton <[email protected]>
432
433 * po/de.po: Updated German translation.
434
ae51a426
JR
4352003-03-03 Andrew Stubbs <[email protected]>
436
437 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
438 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
439 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
440 accordingly.
441
676a64f4
RS
4422004-03-01 Richard Sandiford <[email protected]>
443
444 * frv-asm.c: Regenerate.
445 * frv-desc.c: Regenerate.
446 * frv-desc.h: Regenerate.
447 * frv-dis.c: Regenerate.
448 * frv-ibld.c: Regenerate.
449 * frv-opc.c: Regenerate.
450 * frv-opc.h: Regenerate.
451
c7a48b9a
RS
4522004-03-01 Richard Sandiford <[email protected]>
453
454 * frv-desc.c, frv-opc.c: Regenerate.
455
8ae0baa2
RS
4562004-03-01 Richard Sandiford <[email protected]>
457
458 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
459
ce11586c
JR
4602004-02-26 Andrew Stubbs <[email protected]>
461
462 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
463 Also correct mistake in the comment.
464
6a5709a5
JR
4652004-02-26 Andrew Stubbs <[email protected]>
466
467 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
468 ensure that double registers have even numbers.
469 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
470 that reserved instruction 0xfffd does not decode the same
471 as 0xfdfd (ftrv).
472 * sh-opc.h: Add REG_N_D nibble type and use it whereever
473 REG_N refers to a double register.
474 Add REG_N_B01 nibble type and use it instead of REG_NM
475 in ftrv.
476 Adjust the bit patterns in a few comments.
477
e5d2b64f 4782004-02-25 Aldy Hernandez <[email protected]>
7bfeee7b
AM
479
480 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 481
1f04b05f
AH
4822004-02-20 Aldy Hernandez <[email protected]>
483
484 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
485
2f3b8700
AH
4862004-02-20 Aldy Hernandez <[email protected]>
487
488 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
489
f0b26da6 4902004-02-20 Aldy Hernandez <[email protected]>
7bfeee7b
AM
491
492 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
493 mtivor32, mtivor33, mtivor34.
f0b26da6 494
23d59c56 4952004-02-19 Aldy Hernandez <[email protected]>
7bfeee7b
AM
496
497 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 498
34920d91
NC
4992004-02-10 Petko Manolov <[email protected]>
500
501 * arm-opc.h Maverick accumulator register opcode fixes.
502
44d86481
BE
5032004-02-13 Ben Elliston <[email protected]>
504
505 * m32r-dis.c: Regenerate.
506
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MS
5072004-01-27 Michael Snyder <[email protected]>
508
509 * sh-opc.h (sh_table): "fsrra", not "fssra".
510
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5112004-01-23 Andrew Over <[email protected]>
512
513 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
514 contraints.
515
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5162004-01-19 Andrew Over <[email protected]>
517
518 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
519
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5202004-01-19 Alan Modra <[email protected]>
521
522 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
523 1. Don't print scale factor on AT&T mode when index missing.
524
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AO
5252004-01-16 Alexandre Oliva <[email protected]>
526
527 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
528 when loaded into XR registers.
529
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RS
5302004-01-14 Richard Sandiford <[email protected]>
531
532 * frv-desc.h: Regenerate.
533 * frv-desc.c: Regenerate.
534 * frv-opc.c: Regenerate.
535
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5362004-01-13 Michael Snyder <[email protected]>
537
538 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
539
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PB
5402004-01-09 Paul Brook <[email protected]>
541
542 * arm-opc.h (arm_opcodes): Move generic mcrr after known
543 specific opcodes.
544
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DJ
5452004-01-07 Daniel Jacobowitz <[email protected]>
546
547 * Makefile.am (libopcodes_la_DEPENDENCIES)
548 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
549 comment about the problem.
550 * Makefile.in: Regenerate.
551
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AO
5522004-01-06 Alexandre Oliva <[email protected]>
553
554 2003-12-19 Alexandre Oliva <[email protected]>
555 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
556 cut&paste errors in shifting/truncating numerical operands.
557 2003-08-04 Alexandre Oliva <[email protected]>
558 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
559 (parse_uslo16): Likewise.
560 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
561 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
562 (parse_s12): Likewise.
563 2003-08-04 Alexandre Oliva <[email protected]>
564 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
565 (parse_uslo16): Likewise.
566 (parse_uhi16): Parse gothi and gotfuncdeschi.
567 (parse_d12): Parse got12 and gotfuncdesc12.
568 (parse_s12): Likewise.
569
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5702004-01-02 Albert Bartoszko <[email protected]>
571
572 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
573 instruction which looks similar to an 'rla' instruction.
a0bd404e 574
c9e214e5 575For older changes see ChangeLog-0203
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576\f
577Local Variables:
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578mode: change-log
579left-margin: 8
580fill-column: 74
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581version-control: never
582End:
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