projects / binutils.git / blame
| Commit | Line | Data |
|---|---|---|
| 8c4c1818 JM |
1 | /* CPU family header for bpfbf. |
| 2 | ||
| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
| 4 | ||
| 3666a048 | 5 | Copyright (C) 1996-2021 Free Software Foundation, Inc. |
| 8c4c1818 JM |
6 | |
| 7 | This file is part of the GNU simulators. | |
| 8 | ||
| 9 | This file is free software; you can redistribute it and/or modify | |
| 10 | it under the terms of the GNU General Public License as published by | |
| 11 | the Free Software Foundation; either version 3, or (at your option) | |
| 12 | any later version. | |
| 13 | ||
| 14 | It is distributed in the hope that it will be useful, but WITHOUT | |
| 15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 17 | License for more details. | |
| 18 | ||
| 19 | You should have received a copy of the GNU General Public License along | |
| 20 | with this program; if not, write to the Free Software Foundation, Inc., | |
| 21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
| 22 | ||
| 23 | */ | |
| 24 | ||
| 25 | #ifndef CPU_BPFBF_H | |
| 26 | #define CPU_BPFBF_H | |
| 27 | ||
| 28 | /* Maximum number of instructions that are fetched at a time. | |
| 29 | This is for LIW type instructions sets (e.g. m32r). */ | |
| 30 | #define MAX_LIW_INSNS 1 | |
| 31 | ||
| 32 | /* Maximum number of instructions that can be executed in parallel. */ | |
| 33 | #define MAX_PARALLEL_INSNS 1 | |
| 34 | ||
| 35 | /* The size of an "int" needed to hold an instruction word. | |
| 36 | This is usually 32 bits, but some architectures needs 64 bits. */ | |
| 37 | typedef CGEN_INSN_LGUINT CGEN_INSN_WORD; | |
| 38 | ||
| 39 | #include "cgen-engine.h" | |
| 40 | ||
| 41 | /* CPU state information. */ | |
| 42 | typedef struct { | |
| 43 | /* Hardware elements. */ | |
| 44 | struct { | |
| 45 | /* General Purpose Registers */ | |
| 46 | DI h_gpr[16]; | |
| 47 | #define GET_H_GPR(a1) CPU (h_gpr)[a1] | |
| 48 | #define SET_H_GPR(a1, x) (CPU (h_gpr)[a1] = (x)) | |
| 49 | /* program counter */ | |
| 50 | UDI h_pc; | |
| 51 | #define GET_H_PC() CPU (h_pc) | |
| 52 | #define SET_H_PC(x) \ | |
| 53 | do { \ | |
| 54 | CPU (h_pc) = (x);\ | |
| 55 | ;} while (0) | |
| 56 | } hardware; | |
| 57 | #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) | |
| 58 | } BPFBF_CPU_DATA; | |
| 59 | ||
| 60 | /* Cover fns for register access. */ | |
| 61 | DI bpfbf_h_gpr_get (SIM_CPU *, UINT); | |
| 62 | void bpfbf_h_gpr_set (SIM_CPU *, UINT, DI); | |
| 63 | UDI bpfbf_h_pc_get (SIM_CPU *); | |
| 64 | void bpfbf_h_pc_set (SIM_CPU *, UDI); | |
| 65 | ||
| 66 | /* These must be hand-written. */ | |
| 67 | extern CPUREG_FETCH_FN bpfbf_fetch_register; | |
| 68 | extern CPUREG_STORE_FN bpfbf_store_register; | |
| 69 | ||
| 70 | typedef struct { | |
| 71 | int empty; | |
| 72 | } MODEL_BPF_DEF_DATA; | |
| 73 | ||
| 74 | /* Collection of various things for the trace handler to use. */ | |
| 75 | ||
| 76 | typedef struct trace_record { | |
| 77 | IADDR pc; | |
| 78 | /* FIXME:wip */ | |
| 79 | } TRACE_RECORD; | |
| 80 | ||
| 81 | #endif /* CPU_BPFBF_H */ |