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2002-01-10 Michael Snyder <[email protected]>
[binutils.git] / opcodes / xstormy16-desc.c
CommitLineData
93fbbb04
GK		 1/* CPU data for xstormy16.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "xstormy16-desc.h"
32#include "xstormy16-opc.h"
33#include "opintl.h"
34#include "libiberty.h"
35
36/* Attributes. */
37
38static const CGEN_ATTR_ENTRY bool_attr[] =
39{
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
43};
44
45static const CGEN_ATTR_ENTRY MACH_attr[] =
46{
47 { "base", MACH_BASE },
48 { "xstormy16", MACH_XSTORMY16 },
49 { "max", MACH_MAX },
50 { 0, 0 }
51};
52
53static const CGEN_ATTR_ENTRY ISA_attr[] =
54{
55 { "xstormy16", ISA_XSTORMY16 },
56 { "max", ISA_MAX },
57 { 0, 0 }
58};
59
60const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
61{
62 { "MACH", & MACH_attr[0], & MACH_attr[0] },
63 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
64 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
65 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
66 { "RESERVED", &bool_attr[0], &bool_attr[0] },
67 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
68 { "SIGNED", &bool_attr[0], &bool_attr[0] },
69 { 0, 0, 0 }
70};
71
72const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
73{
74 { "MACH", & MACH_attr[0], & MACH_attr[0] },
75 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
76 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
77 { "PC", &bool_attr[0], &bool_attr[0] },
78 { "PROFILE", &bool_attr[0], &bool_attr[0] },
79 { 0, 0, 0 }
80};
81
82const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
83{
84 { "MACH", & MACH_attr[0], & MACH_attr[0] },
85 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
86 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
87 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
89 { "SIGNED", &bool_attr[0], &bool_attr[0] },
90 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
91 { "RELAX", &bool_attr[0], &bool_attr[0] },
92 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
93 { 0, 0, 0 }
94};
95
96const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
97{
98 { "MACH", & MACH_attr[0], & MACH_attr[0] },
99 { "ALIAS", &bool_attr[0], &bool_attr[0] },
100 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
101 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
102 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
103 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
104 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
105 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
106 { "RELAX", &bool_attr[0], &bool_attr[0] },
107 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
108 { "PBB", &bool_attr[0], &bool_attr[0] },
109 { 0, 0, 0 }
110};
111
112/* Instruction set variants. */
113
114static const CGEN_ISA xstormy16_cgen_isa_table[] = {
115 { "xstormy16", 32, 32, 16, 32 },
116 { 0, 0, 0, 0, 0 }
117};
118
119/* Machine variants. */
120
121static const CGEN_MACH xstormy16_cgen_mach_table[] = {
122 { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
123 { 0, 0, 0, 0 }
124};
125
126static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
127{
128 { "r0", 0, {0, {0}}, 0, 0 },
129 { "r1", 1, {0, {0}}, 0, 0 },
130 { "r2", 2, {0, {0}}, 0, 0 },
131 { "r3", 3, {0, {0}}, 0, 0 },
132 { "r4", 4, {0, {0}}, 0, 0 },
133 { "r5", 5, {0, {0}}, 0, 0 },
134 { "r6", 6, {0, {0}}, 0, 0 },
135 { "r7", 7, {0, {0}}, 0, 0 },
136 { "r8", 8, {0, {0}}, 0, 0 },
137 { "r9", 9, {0, {0}}, 0, 0 },
138 { "r10", 10, {0, {0}}, 0, 0 },
139 { "r11", 11, {0, {0}}, 0, 0 },
140 { "r12", 12, {0, {0}}, 0, 0 },
141 { "r13", 13, {0, {0}}, 0, 0 },
142 { "r14", 14, {0, {0}}, 0, 0 },
143 { "r15", 15, {0, {0}}, 0, 0 },
144 { "psw", 14, {0, {0}}, 0, 0 },
145 { "sp", 15, {0, {0}}, 0, 0 }
146};
147
148CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
149{
150 & xstormy16_cgen_opval_gr_names_entries[0],
151 18,
152 0, 0, 0, 0, ""
153};
154
155static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rbj_names_entries[] =
156{
157 { "r8", 0, {0, {0}}, 0, 0 },
158 { "r9", 1, {0, {0}}, 0, 0 }
159};
160
161CGEN_KEYWORD xstormy16_cgen_opval_gr_Rbj_names =
162{
163 & xstormy16_cgen_opval_gr_Rbj_names_entries[0],
164 2,
165 0, 0, 0, 0, ""
166};
167
168static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
169{
170 { "ge", 0, {0, {0}}, 0, 0 },
171 { "nc", 1, {0, {0}}, 0, 0 },
172 { "lt", 2, {0, {0}}, 0, 0 },
173 { "c", 3, {0, {0}}, 0, 0 },
174 { "gt", 4, {0, {0}}, 0, 0 },
175 { "hi", 5, {0, {0}}, 0, 0 },
176 { "le", 6, {0, {0}}, 0, 0 },
177 { "ls", 7, {0, {0}}, 0, 0 },
178 { "pl", 8, {0, {0}}, 0, 0 },
179 { "nv", 9, {0, {0}}, 0, 0 },
180 { "mi", 10, {0, {0}}, 0, 0 },
181 { "v", 11, {0, {0}}, 0, 0 },
182 { "nz.b", 12, {0, {0}}, 0, 0 },
183 { "nz", 13, {0, {0}}, 0, 0 },
184 { "z.b", 14, {0, {0}}, 0, 0 },
185 { "z", 15, {0, {0}}, 0, 0 }
186};
187
188CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
189{
190 & xstormy16_cgen_opval_h_branchcond_entries[0],
191 16,
192 0, 0, 0, 0, ""
193};
194
195static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
196{
197 { ".b", 0, {0, {0}}, 0, 0 },
198 { ".w", 1, {0, {0}}, 0, 0 },
199 { "", 1, {0, {0}}, 0, 0 }
200};
201
202CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
203{
204 & xstormy16_cgen_opval_h_wordsize_entries[0],
205 3,
206 0, 0, 0, 0, ""
207};
208
209
210/* The hardware table. */
211
212#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
213#define A(a) (1 << CGEN_HW_##a)
214#else
215#define A(a) (1 << CGEN_HW_/**/a)
216#endif
217
218const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
219{
220 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
221 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
222 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
223 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
224 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
225 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
226 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
227 { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rbj_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
228 { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
229 { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
230 { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
231 { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
232 { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
233 { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
234 { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
235 { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
236 { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } },
237 { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } },
238 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
239};
240
241#undef A
242
243
244/* The instruction field table. */
245
246#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
247#define A(a) (1 << CGEN_IFLD_##a)
248#else
249#define A(a) (1 << CGEN_IFLD_/**/a)
250#endif
251
252const CGEN_IFLD xstormy16_cgen_ifld_table[] =
253{
254 { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
255 { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
256 { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
257 { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } },
258 { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
259 { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
260 { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
261 { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } },
262 { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
263 { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
264 { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
265 { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } },
266 { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
267 { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } },
268 { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
269 { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
270 { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } },
271 { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
272 { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } },
273 { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } },
274 { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } },
275 { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } },
276 { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
277 { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
278 { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
279 { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
280 { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } },
281 { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
282 { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
283 { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
284 { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
285 { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
286 { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
287 { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
288 { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
289 { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
290 { 0, 0, 0, 0, 0, 0, {0, {0}} }
291};
292
293#undef A
294
295
296/* The operand table. */
297
298#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
299#define A(a) (1 << CGEN_OPERAND_##a)
300#else
301#define A(a) (1 << CGEN_OPERAND_/**/a)
302#endif
303#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
304#define OPERAND(op) XSTORMY16_OPERAND_##op
305#else
306#define OPERAND(op) XSTORMY16_OPERAND_/**/op
307#endif
308
309const CGEN_OPERAND xstormy16_cgen_operand_table[] =
310{
311/* pc: program counter */
312 { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
313 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
314/* psw-z8: */
315 { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
316 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
317/* psw-z16: */
318 { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
319 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
320/* psw-cy: */
321 { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
322 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
323/* psw-hc: */
324 { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
325 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
326/* psw-ov: */
327 { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
328 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
329/* psw-pt: */
330 { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
331 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
332/* psw-s: */
333 { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
334 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
335/* Rd: general register destination */
336 { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
337 { 0, { (1<<MACH_BASE) } } },
338/* Rdm: general register destination */
339 { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
340 { 0, { (1<<MACH_BASE) } } },
341/* Rm: general register for memory */
342 { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
343 { 0, { (1<<MACH_BASE) } } },
344/* Rs: general register source */
345 { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
346 { 0, { (1<<MACH_BASE) } } },
347/* Rb: base register */
348 { "Rb", XSTORMY16_OPERAND_RB, HW_H_GR, 17, 3,
349 { 0, { (1<<MACH_BASE) } } },
350/* Rbj: base register for jump */
351 { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
352 { 0, { (1<<MACH_BASE) } } },
353/* bcond2: branch condition opcode */
354 { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
355 { 0, { (1<<MACH_BASE) } } },
356/* ws2: word size opcode */
357 { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
358 { 0, { (1<<MACH_BASE) } } },
359/* bcond5: branch condition opcode */
360 { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
361 { 0, { (1<<MACH_BASE) } } },
362/* imm2: 2 bit unsigned immediate */
363 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
364 { 0, { (1<<MACH_BASE) } } },
365/* imm3: 3 bit unsigned immediate */
366 { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
367 { 0, { (1<<MACH_BASE) } } },
368/* imm3b: 3 bit unsigned immediate for bit tests */
369 { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
370 { 0, { (1<<MACH_BASE) } } },
371/* imm4: 4 bit unsigned immediate */
372 { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
373 { 0, { (1<<MACH_BASE) } } },
374/* imm8: 8 bit unsigned immediate */
375 { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
376 { 0, { (1<<MACH_BASE) } } },
377/* imm8small: 8 bit unsigned immediate */
378 { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
379 { 0, { (1<<MACH_BASE) } } },
380/* imm12: 12 bit signed immediate */
381 { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
382 { 0, { (1<<MACH_BASE) } } },
383/* imm16: 16 bit immediate */
384 { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
385 { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
386/* lmem8: 8 bit unsigned immediate low memory */
387 { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
388 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
389/* hmem8: 8 bit unsigned immediate high memory */
390 { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
391 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
392/* rel8-2: 8 bit relative address */
393 { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
394 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
395/* rel8-4: 8 bit relative address */
396 { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
397 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
398/* rel12: 12 bit relative address */
399 { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
400 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
401/* rel12a: 12 bit relative address */
402 { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
403 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
404/* abs24: 24 bit absolute address */
405 { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
406 { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
407/* psw: program status word */
408 { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
409 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
410/* Rpsw: N0-N3 of the program status word */
411 { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
412 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
413/* sp: stack pointer */
414 { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
415 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
416/* R0: R0 */
417 { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
418 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
419/* R1: R1 */
420 { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
421 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
422/* R2: R2 */
423 { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
424 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
425/* R8: R8 */
426 { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
427 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
428 { 0, 0, 0, 0, 0, {0, {0}} }
429};
430
431#undef A
432
433
434/* The instruction table. */
435
436#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
437#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
438#define A(a) (1 << CGEN_INSN_##a)
439#else
440#define A(a) (1 << CGEN_INSN_/**/a)
441#endif
442
443static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
444{
445 /* Special null first entry.
446 A `num' value of zero is thus invalid.
447 Also, the special `invalid' insn resides here. */
448 { 0, 0, 0, 0, {0, {0}} },
449/* mov$ws2 $lmem8,#$imm16 */
450 {
451 XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
452 { 0, { (1<<MACH_BASE) } }
453 },
454/* mov$ws2 $hmem8,#$imm16 */
455 {
456 XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
457 { 0, { (1<<MACH_BASE) } }
458 },
459/* mov$ws2 $Rm,$lmem8 */
460 {
461 XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
462 { 0, { (1<<MACH_BASE) } }
463 },
464/* mov$ws2 $Rm,$hmem8 */
465 {
466 XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
467 { 0, { (1<<MACH_BASE) } }
468 },
469/* mov$ws2 $lmem8,$Rm */
470 {
471 XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
472 { 0, { (1<<MACH_BASE) } }
473 },
474/* mov$ws2 $hmem8,$Rm */
475 {
476 XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
477 { 0, { (1<<MACH_BASE) } }
478 },
479/* mov$ws2 $Rdm,($Rs) */
480 {
481 XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
482 { 0, { (1<<MACH_BASE) } }
483 },
484/* mov$ws2 $Rdm,($Rs++) */
485 {
486 XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
487 { 0, { (1<<MACH_BASE) } }
488 },
489/* mov$ws2 $Rdm,(--$Rs) */
490 {
491 XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
492 { 0, { (1<<MACH_BASE) } }
493 },
494/* mov$ws2 ($Rs),$Rdm */
495 {
496 XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
497 { 0, { (1<<MACH_BASE) } }
498 },
499/* mov$ws2 ($Rs++),$Rdm */
500 {
501 XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
502 { 0, { (1<<MACH_BASE) } }
503 },
504/* mov$ws2 (--$Rs),$Rdm */
505 {
506 XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
507 { 0, { (1<<MACH_BASE) } }
508 },
509/* mov$ws2 $Rdm,($Rs,$imm12) */
510 {
511 XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
512 { 0, { (1<<MACH_BASE) } }
513 },
514/* mov$ws2 $Rdm,($Rs++,$imm12) */
515 {
516 XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
517 { 0, { (1<<MACH_BASE) } }
518 },
519/* mov$ws2 $Rdm,(--$Rs,$imm12) */
520 {
521 XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
522 { 0, { (1<<MACH_BASE) } }
523 },
524/* mov$ws2 ($Rs,$imm12),$Rdm */
525 {
526 XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
527 { 0, { (1<<MACH_BASE) } }
528 },
529/* mov$ws2 ($Rs++,$imm12),$Rdm */
530 {
531 XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
532 { 0, { (1<<MACH_BASE) } }
533 },
534/* mov$ws2 (--$Rs,$imm12),$Rdm */
535 {
536 XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
537 { 0, { (1<<MACH_BASE) } }
538 },
539/* mov $Rd,$Rs */
540 {
541 XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
542 { 0, { (1<<MACH_BASE) } }
543 },
544/* mov.w Rx,#$imm8 */
545 {
546 XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
547 { 0, { (1<<MACH_BASE) } }
548 },
549/* mov.w $Rm,#$imm8small */
550 {
551 XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
552 { 0, { (1<<MACH_BASE) } }
553 },
554/* mov.w $Rd,#$imm16 */
555 {
556 XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
557 { 0, { (1<<MACH_BASE) } }
558 },
559/* mov.b $Rd,RxL */
560 {
561 XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
562 { 0, { (1<<MACH_BASE) } }
563 },
564/* mov.b $Rd,RxH */
565 {
566 XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
567 { 0, { (1<<MACH_BASE) } }
568 },
569/* movf$ws2 $Rdm,($Rs) */
570 {
571 XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
572 { 0, { (1<<MACH_BASE) } }
573 },
574/* movf$ws2 $Rdm,($Rs++) */
575 {
576 XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
577 { 0, { (1<<MACH_BASE) } }
578 },
579/* movf$ws2 $Rdm,(--$Rs) */
580 {
581 XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
582 { 0, { (1<<MACH_BASE) } }
583 },
584/* movf$ws2 ($Rs),$Rdm */
585 {
586 XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
587 { 0, { (1<<MACH_BASE) } }
588 },
589/* movf$ws2 ($Rs++),$Rdm */
590 {
591 XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
592 { 0, { (1<<MACH_BASE) } }
593 },
594/* movf$ws2 (--$Rs),$Rdm */
595 {
596 XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
597 { 0, { (1<<MACH_BASE) } }
598 },
599/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
600 {
601 XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
602 { 0, { (1<<MACH_BASE) } }
603 },
604/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
605 {
606 XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
607 { 0, { (1<<MACH_BASE) } }
608 },
609/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
610 {
611 XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
612 { 0, { (1<<MACH_BASE) } }
613 },
614/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
615 {
616 XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
617 { 0, { (1<<MACH_BASE) } }
618 },
619/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
620 {
621 XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
622 { 0, { (1<<MACH_BASE) } }
623 },
624/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
625 {
626 XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
627 { 0, { (1<<MACH_BASE) } }
628 },
629/* mask $Rd,$Rs */
630 {
631 XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
632 { 0, { (1<<MACH_BASE) } }
633 },
634/* mask $Rd,#$imm16 */
635 {
636 XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
637 { 0, { (1<<MACH_BASE) } }
638 },
639/* push $Rd */
640 {
641 XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
642 { 0, { (1<<MACH_BASE) } }
643 },
644/* pop $Rd */
645 {
646 XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
647 { 0, { (1<<MACH_BASE) } }
648 },
649/* swpn $Rd */
650 {
651 XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
652 { 0, { (1<<MACH_BASE) } }
653 },
654/* swpb $Rd */
655 {
656 XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
657 { 0, { (1<<MACH_BASE) } }
658 },
659/* swpw $Rd,$Rs */
660 {
661 XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
662 { 0, { (1<<MACH_BASE) } }
663 },
664/* and $Rd,$Rs */
665 {
666 XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
667 { 0, { (1<<MACH_BASE) } }
668 },
669/* and Rx,#$imm8 */
670 {
671 XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
672 { 0, { (1<<MACH_BASE) } }
673 },
674/* and $Rd,#$imm16 */
675 {
676 XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
677 { 0, { (1<<MACH_BASE) } }
678 },
679/* or $Rd,$Rs */
680 {
681 XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
682 { 0, { (1<<MACH_BASE) } }
683 },
684/* or Rx,#$imm8 */
685 {
686 XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
687 { 0, { (1<<MACH_BASE) } }
688 },
689/* or $Rd,#$imm16 */
690 {
691 XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
692 { 0, { (1<<MACH_BASE) } }
693 },
694/* xor $Rd,$Rs */
695 {
696 XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
697 { 0, { (1<<MACH_BASE) } }
698 },
699/* xor Rx,#$imm8 */
700 {
701 XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
702 { 0, { (1<<MACH_BASE) } }
703 },
704/* xor $Rd,#$imm16 */
705 {
706 XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
707 { 0, { (1<<MACH_BASE) } }
708 },
709/* not $Rd */
710 {
711 XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
712 { 0, { (1<<MACH_BASE) } }
713 },
714/* add $Rd,$Rs */
715 {
716 XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
717 { 0, { (1<<MACH_BASE) } }
718 },
719/* add $Rd,#$imm4 */
720 {
721 XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
722 { 0, { (1<<MACH_BASE) } }
723 },
724/* add Rx,#$imm8 */
725 {
726 XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
727 { 0, { (1<<MACH_BASE) } }
728 },
729/* add $Rd,#$imm16 */
730 {
731 XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
732 { 0, { (1<<MACH_BASE) } }
733 },
734/* adc $Rd,$Rs */
735 {
736 XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
737 { 0, { (1<<MACH_BASE) } }
738 },
739/* adc $Rd,#$imm4 */
740 {
741 XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
742 { 0, { (1<<MACH_BASE) } }
743 },
744/* adc Rx,#$imm8 */
745 {
746 XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
747 { 0, { (1<<MACH_BASE) } }
748 },
749/* adc $Rd,#$imm16 */
750 {
751 XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
752 { 0, { (1<<MACH_BASE) } }
753 },
754/* sub $Rd,$Rs */
755 {
756 XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
757 { 0, { (1<<MACH_BASE) } }
758 },
759/* sub $Rd,#$imm4 */
760 {
761 XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
762 { 0, { (1<<MACH_BASE) } }
763 },
764/* sub Rx,#$imm8 */
765 {
766 XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
767 { 0, { (1<<MACH_BASE) } }
768 },
769/* sub $Rd,#$imm16 */
770 {
771 XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
772 { 0, { (1<<MACH_BASE) } }
773 },
774/* sbc $Rd,$Rs */
775 {
776 XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
777 { 0, { (1<<MACH_BASE) } }
778 },
779/* sbc $Rd,#$imm4 */
780 {
781 XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
782 { 0, { (1<<MACH_BASE) } }
783 },
784/* sbc Rx,#$imm8 */
785 {
786 XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
787 { 0, { (1<<MACH_BASE) } }
788 },
789/* sbc $Rd,#$imm16 */
790 {
791 XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
792 { 0, { (1<<MACH_BASE) } }
793 },
794/* inc $Rd,#$imm2 */
795 {
796 XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
797 { 0, { (1<<MACH_BASE) } }
798 },
799/* dec $Rd,#$imm2 */
800 {
801 XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
802 { 0, { (1<<MACH_BASE) } }
803 },
804/* rrc $Rd,$Rs */
805 {
806 XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
807 { 0, { (1<<MACH_BASE) } }
808 },
809/* rrc $Rd,#$imm4 */
810 {
811 XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
812 { 0, { (1<<MACH_BASE) } }
813 },
814/* rlc $Rd,$Rs */
815 {
816 XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
817 { 0, { (1<<MACH_BASE) } }
818 },
819/* rlc $Rd,#$imm4 */
820 {
821 XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
822 { 0, { (1<<MACH_BASE) } }
823 },
824/* shr $Rd,$Rs */
825 {
826 XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
827 { 0, { (1<<MACH_BASE) } }
828 },
829/* shr $Rd,#$imm4 */
830 {
831 XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
832 { 0, { (1<<MACH_BASE) } }
833 },
834/* shl $Rd,$Rs */
835 {
836 XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
837 { 0, { (1<<MACH_BASE) } }
838 },
839/* shl $Rd,#$imm4 */
840 {
841 XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
842 { 0, { (1<<MACH_BASE) } }
843 },
844/* asr $Rd,$Rs */
845 {
846 XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
847 { 0, { (1<<MACH_BASE) } }
848 },
849/* asr $Rd,#$imm4 */
850 {
851 XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
852 { 0, { (1<<MACH_BASE) } }
853 },
854/* set1 $Rd,#$imm4 */
855 {
856 XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
857 { 0, { (1<<MACH_BASE) } }
858 },
859/* set1 $Rd,$Rs */
860 {
861 XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
862 { 0, { (1<<MACH_BASE) } }
863 },
864/* set1 $lmem8,#$imm3 */
865 {
866 XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
867 { 0, { (1<<MACH_BASE) } }
868 },
869/* set1 $hmem8,#$imm3 */
870 {
871 XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
872 { 0, { (1<<MACH_BASE) } }
873 },
874/* clr1 $Rd,#$imm4 */
875 {
876 XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
877 { 0, { (1<<MACH_BASE) } }
878 },
879/* clr1 $Rd,$Rs */
880 {
881 XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
882 { 0, { (1<<MACH_BASE) } }
883 },
884/* clr1 $lmem8,#$imm3 */
885 {
886 XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
887 { 0, { (1<<MACH_BASE) } }
888 },
889/* clr1 $hmem8,#$imm3 */
890 {
891 XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
892 { 0, { (1<<MACH_BASE) } }
893 },
894/* cbw $Rd */
895 {
896 XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
897 { 0, { (1<<MACH_BASE) } }
898 },
899/* rev $Rd */
900 {
901 XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
902 { 0, { (1<<MACH_BASE) } }
903 },
904/* b$bcond5 $Rd,$Rs,$rel12 */
905 {
906 XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
907 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
908 },
909/* b$bcond5 $Rm,#$imm8,$rel12 */
910 {
911 XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
912 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
913 },
914/* b$bcond2 Rx,#$imm16,${rel8-4} */
915 {
916 XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
917 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
918 },
919/* bn $Rd,#$imm4,$rel12 */
920 {
921 XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
922 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
923 },
924/* bn $Rd,$Rs,$rel12 */
925 {
926 XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
927 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
928 },
929/* bn $lmem8,#$imm3b,$rel12 */
930 {
931 XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
932 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
933 },
934/* bn $hmem8,#$imm3b,$rel12 */
935 {
936 XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
937 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
938 },
939/* bp $Rd,#$imm4,$rel12 */
940 {
941 XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
942 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
943 },
944/* bp $Rd,$Rs,$rel12 */
945 {
946 XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
947 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
948 },
949/* bp $lmem8,#$imm3b,$rel12 */
950 {
951 XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
952 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
953 },
954/* bp $hmem8,#$imm3b,$rel12 */
955 {
956 XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
957 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
958 },
959/* b$bcond2 ${rel8-2} */
960 {
961 XSTORMY16_INSN_BCC, "bcc", "b", 16,
962 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
963 },
964/* br $Rd */
965 {
966 XSTORMY16_INSN_BGR, "bgr", "br", 16,
967 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
968 },
969/* br $rel12a */
970 {
971 XSTORMY16_INSN_BR, "br", "br", 16,
972 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
973 },
974/* jmp $Rbj,$Rd */
975 {
976 XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
977 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
978 },
979/* jmpf $abs24 */
980 {
981 XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
982 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
983 },
984/* callr $Rd */
985 {
986 XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
987 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
988 },
989/* callr $rel12a */
990 {
991 XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
992 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
993 },
994/* call $Rbj,$Rd */
995 {
996 XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
997 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
998 },
999/* callf $abs24 */
1000 {
1001 XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
1002 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1003 },
1004/* icallr $Rd */
1005 {
1006 XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
1007 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1008 },
1009/* icall $Rbj,$Rd */
1010 {
1011 XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
1012 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1013 },
1014/* icallf $abs24 */
1015 {
1016 XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
1017 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1018 },
1019/* iret */
1020 {
1021 XSTORMY16_INSN_IRET, "iret", "iret", 16,
1022 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1023 },
1024/* ret */
1025 {
1026 XSTORMY16_INSN_RET, "ret", "ret", 16,
1027 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1028 },
1029/* mul */
1030 {
1031 XSTORMY16_INSN_MUL, "mul", "mul", 16,
1032 { 0, { (1<<MACH_BASE) } }
1033 },
1034/* div */
1035 {
1036 XSTORMY16_INSN_DIV, "div", "div", 16,
1037 { 0, { (1<<MACH_BASE) } }
1038 },
1039/* nop */
1040 {
1041 XSTORMY16_INSN_NOP, "nop", "nop", 16,
1042 { 0, { (1<<MACH_BASE) } }
1043 },
1044/* halt */
1045 {
1046 XSTORMY16_INSN_HALT, "halt", "halt", 16,
1047 { 0, { (1<<MACH_BASE) } }
1048 },
1049/* hold */
1050 {
1051 XSTORMY16_INSN_HOLD, "hold", "hold", 16,
1052 { 0, { (1<<MACH_BASE) } }
1053 },
1054/* brk */
1055 {
1056 XSTORMY16_INSN_BRK, "brk", "brk", 16,
1057 { 0, { (1<<MACH_BASE) } }
1058 },
1059/* --unused-- */
1060 {
1061 XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
1062 { 0, { (1<<MACH_BASE) } }
1063 },
1064};
1065
1066#undef OP
1067#undef A
1068
1069/* Initialize anything needed to be done once, before any cpu_open call. */
1070static void init_tables PARAMS ((void));
1071
1072static void
1073init_tables ()
1074{
1075}
1076
1077static const CGEN_MACH * lookup_mach_via_bfd_name
1078 PARAMS ((const CGEN_MACH *, const char *));
1079static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
1080static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
1081static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1082static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
1083static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1084
1085/* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */
1086
1087static const CGEN_MACH *
1088lookup_mach_via_bfd_name (table, name)
1089 const CGEN_MACH *table;
1090 const char *name;
1091{
1092 while (table->name)
1093 {
1094 if (strcmp (name, table->bfd_name) == 0)
1095 return table;
1096 ++table;
1097 }
1098 abort ();
1099}
1100
1101/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1102
1103static void
1104build_hw_table (cd)
1105 CGEN_CPU_TABLE *cd;
1106{
1107 int i;
1108 int machs = cd->machs;
1109 const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
1110 /* MAX_HW is only an upper bound on the number of selected entries.
1111 However each entry is indexed by it's enum so there can be holes in
1112 the table. */
1113 const CGEN_HW_ENTRY **selected =
1114 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1115
1116 cd->hw_table.init_entries = init;
1117 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1118 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1119 /* ??? For now we just use machs to determine which ones we want. */
1120 for (i = 0; init[i].name != NULL; ++i)
1121 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1122 & machs)
1123 selected[init[i].type] = &init[i];
1124 cd->hw_table.entries = selected;
1125 cd->hw_table.num_entries = MAX_HW;
1126}
1127
1128/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1129
1130static void
1131build_ifield_table (cd)
1132 CGEN_CPU_TABLE *cd;
1133{
1134 cd->ifld_table = & xstormy16_cgen_ifld_table[0];
1135}
1136
1137/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1138
1139static void
1140build_operand_table (cd)
1141 CGEN_CPU_TABLE *cd;
1142{
1143 int i;
1144 int machs = cd->machs;
1145 const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
1146 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1147 However each entry is indexed by it's enum so there can be holes in
1148 the table. */
1149 const CGEN_OPERAND **selected =
1150 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1151
1152 cd->operand_table.init_entries = init;
1153 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1154 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1155 /* ??? For now we just use mach to determine which ones we want. */
1156 for (i = 0; init[i].name != NULL; ++i)
1157 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1158 & machs)
1159 selected[init[i].type] = &init[i];
1160 cd->operand_table.entries = selected;
1161 cd->operand_table.num_entries = MAX_OPERANDS;
1162}
1163
1164/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
1165 ??? This could leave out insns not supported by the specified mach/isa,
1166 but that would cause errors like "foo only supported by bar" to become
1167 "unknown insn", so for now we include all insns and require the app to
1168 do the checking later.
1169 ??? On the other hand, parsing of such insns may require their hardware or
1170 operand elements to be in the table [which they mightn't be]. */
1171
1172static void
1173build_insn_table (cd)
1174 CGEN_CPU_TABLE *cd;
1175{
1176 int i;
1177 const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
1178 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1179
1180 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1181 for (i = 0; i < MAX_INSNS; ++i)
1182 insns[i].base = &ib[i];
1183 cd->insn_table.init_entries = insns;
1184 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1185 cd->insn_table.num_init_entries = MAX_INSNS;
1186}
1187
1188/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */
1189
1190static void
1191xstormy16_cgen_rebuild_tables (cd)
1192 CGEN_CPU_TABLE *cd;
1193{
1194 int i;
1195 unsigned int isas = cd->isas;
1196 unsigned int machs = cd->machs;
1197
1198 cd->int_insn_p = CGEN_INT_INSN_P;
1199
1200 /* Data derived from the isa spec. */
1201#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1202 cd->default_insn_bitsize = UNSET;
1203 cd->base_insn_bitsize = UNSET;
1204 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1205 cd->max_insn_bitsize = 0;
1206 for (i = 0; i < MAX_ISAS; ++i)
1207 if (((1 << i) & isas) != 0)
1208 {
1209 const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
1210
1211 /* Default insn sizes of all selected isas must be
1212 equal or we set the result to 0, meaning "unknown". */
1213 if (cd->default_insn_bitsize == UNSET)
1214 cd->default_insn_bitsize = isa->default_insn_bitsize;
1215 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1216 ; /* this is ok */
1217 else
1218 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1219
1220 /* Base insn sizes of all selected isas must be equal
1221 or we set the result to 0, meaning "unknown". */
1222 if (cd->base_insn_bitsize == UNSET)
1223 cd->base_insn_bitsize = isa->base_insn_bitsize;
1224 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1225 ; /* this is ok */
1226 else
1227 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1228
1229 /* Set min,max insn sizes. */
1230 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1231 cd->min_insn_bitsize = isa->min_insn_bitsize;
1232 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1233 cd->max_insn_bitsize = isa->max_insn_bitsize;
1234 }
1235
1236 /* Data derived from the mach spec. */
1237 for (i = 0; i < MAX_MACHS; ++i)
1238 if (((1 << i) & machs) != 0)
1239 {
1240 const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
1241
1242 if (mach->insn_chunk_bitsize != 0)
1243 {
1244 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1245 {
1246 fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1247 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1248 abort ();
1249 }
1250
1251 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1252 }
1253 }
1254
1255 /* Determine which hw elements are used by MACH. */
1256 build_hw_table (cd);
1257
1258 /* Build the ifield table. */
1259 build_ifield_table (cd);
1260
1261 /* Determine which operands are used by MACH/ISA. */
1262 build_operand_table (cd);
1263
1264 /* Build the instruction table. */
1265 build_insn_table (cd);
1266}
1267
1268/* Initialize a cpu table and return a descriptor.
1269 It's much like opening a file, and must be the first function called.
1270 The arguments are a set of (type/value) pairs, terminated with
1271 CGEN_CPU_OPEN_END.
1272
1273 Currently supported values:
1274 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1275 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1276 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1277 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1278 CGEN_CPU_OPEN_END: terminates arguments
1279
1280 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1281 precluded.
1282
1283 ??? We only support ISO C stdargs here, not K&R.
1284 Laziness, plus experiment to see if anything requires K&R - eventually
1285 K&R will no longer be supported - e.g. GDB is currently trying this. */
1286
1287CGEN_CPU_DESC
1288xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1289{
1290 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1291 static int init_p;
1292 unsigned int isas = 0; /* 0 = "unspecified" */
1293 unsigned int machs = 0; /* 0 = "unspecified" */
1294 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1295 va_list ap;
1296
1297 if (! init_p)
1298 {
1299 init_tables ();
1300 init_p = 1;
1301 }
1302
1303 memset (cd, 0, sizeof (*cd));
1304
1305 va_start (ap, arg_type);
1306 while (arg_type != CGEN_CPU_OPEN_END)
1307 {
1308 switch (arg_type)
1309 {
1310 case CGEN_CPU_OPEN_ISAS :
1311 isas = va_arg (ap, unsigned int);
1312 break;
1313 case CGEN_CPU_OPEN_MACHS :
1314 machs = va_arg (ap, unsigned int);
1315 break;
1316 case CGEN_CPU_OPEN_BFDMACH :
1317 {
1318 const char *name = va_arg (ap, const char *);
1319 const CGEN_MACH *mach =
1320 lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
1321
1322 machs |= 1 << mach->num;
1323 break;
1324 }
1325 case CGEN_CPU_OPEN_ENDIAN :
1326 endian = va_arg (ap, enum cgen_endian);
1327 break;
1328 default :
1329 fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
1330 arg_type);
1331 abort (); /* ??? return NULL? */
1332 }
1333 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1334 }
1335 va_end (ap);
1336
1337 /* mach unspecified means "all" */
1338 if (machs == 0)
1339 machs = (1 << MAX_MACHS) - 1;
1340 /* base mach is always selected */
1341 machs |= 1;
1342 /* isa unspecified means "all" */
1343 if (isas == 0)
1344 isas = (1 << MAX_ISAS) - 1;
1345 if (endian == CGEN_ENDIAN_UNKNOWN)
1346 {
1347 /* ??? If target has only one, could have a default. */
1348 fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
1349 abort ();
1350 }
1351
1352 cd->isas = isas;
1353 cd->machs = machs;
1354 cd->endian = endian;
1355 /* FIXME: for the sparc case we can determine insn-endianness statically.
1356 The worry here is where both data and insn endian can be independently
1357 chosen, in which case this function will need another argument.
1358 Actually, will want to allow for more arguments in the future anyway. */
1359 cd->insn_endian = endian;
1360
1361 /* Table (re)builder. */
1362 cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
1363 xstormy16_cgen_rebuild_tables (cd);
1364
1365 /* Default to not allowing signed overflow. */
1366 cd->signed_overflow_ok_p = 0;
1367
1368 return (CGEN_CPU_DESC) cd;
1369}
1370
1371/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1372 MACH_NAME is the bfd name of the mach. */
1373
1374CGEN_CPU_DESC
1375xstormy16_cgen_cpu_open_1 (mach_name, endian)
1376 const char *mach_name;
1377 enum cgen_endian endian;
1378{
1379 return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1380 CGEN_CPU_OPEN_ENDIAN, endian,
1381 CGEN_CPU_OPEN_END);
1382}
1383
1384/* Close a cpu table.
1385 ??? This can live in a machine independent file, but there's currently
1386 no place to put this file (there's no libcgen). libopcodes is the wrong
1387 place as some simulator ports use this but they don't use libopcodes. */
1388
1389void
1390xstormy16_cgen_cpu_close (cd)
1391 CGEN_CPU_DESC cd;
1392{
1393 if (cd->insn_table.init_entries)
1394 free ((CGEN_INSN *) cd->insn_table.init_entries);
1395 if (cd->hw_table.entries)
1396 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1397 free (cd);
1398}
1399
Empty description
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