projects / binutils.git / blame
| Commit | Line | Data |
|---|---|---|
| 0c101d49 SG |
1 | /* Macro definitions for GDB for a Fujitsu SPARClite. |
| 2 | Copyright 1993 Free Software Foundation, Inc. | |
| 3 | ||
| 4 | This file is part of GDB. | |
| 5 | ||
| 6 | This program is free software; you can redistribute it and/or modify | |
| 7 | it under the terms of the GNU General Public License as published by | |
| 8 | the Free Software Foundation; either version 2 of the License, or | |
| 9 | (at your option) any later version. | |
| 10 | ||
| 11 | This program is distributed in the hope that it will be useful, | |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | GNU General Public License for more details. | |
| 15 | ||
| 16 | You should have received a copy of the GNU General Public License | |
| 17 | along with this program; if not, write to the Free Software | |
| 18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
| 19 | ||
| cd3508f1 KH |
20 | #define TARGET_SPARCLITE 1 |
| 21 | ||
| 0c101d49 | 22 | #include "sparc/tm-sparc.h" |
| cd3508f1 KH |
23 | |
| 24 | /* Amount PC must be decremented by after a hardware instruction breakpoint. | |
| 25 | This is often the number of bytes in BREAKPOINT | |
| 26 | but not always. */ | |
| 27 | ||
| 28 | #define DECR_PC_AFTER_HW_BREAK 4 | |
| 29 | ||
| 30 | #undef NUM_REGS | |
| 31 | #define NUM_REGS 80 | |
| 32 | ||
| 33 | #undef REGISTER_BYTES | |
| 34 | #define REGISTER_BYTES (32*4+32*4+8*4+8*4) | |
| 35 | ||
| 36 | #undef REGISTER_NAMES | |
| 37 | #define REGISTER_NAMES \ | |
| 38 | { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ | |
| 39 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", \ | |
| 40 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \ | |
| 41 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", \ | |
| 42 | \ | |
| 43 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ | |
| 44 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ | |
| 45 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ | |
| 46 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \ | |
| 47 | \ | |
| 48 | "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr", \ | |
| 49 | "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" } | |
| 50 | ||
| 51 | #define DIA1_REGNUM 72 /* debug instr address register 1 */ | |
| 52 | #define DIA2_REGNUM 73 /* debug instr address register 2 */ | |
| 53 | #define DDA1_REGNUM 74 /* debug data address register 1 */ | |
| 54 | #define DDA2_REGNUM 75 /* debug data address register 2 */ | |
| 55 | #define DDV1_REGNUM 76 /* debug data value register 1 */ | |
| 56 | #define DDV2_REGNUM 77 /* debug data value register 2 */ | |
| 57 | #define DCR_REGNUM 78 /* debug control register */ | |
| 58 | #define DSR_REGNUM 79 /* debug status regsiter */ | |
| 59 | ||
| 60 | #define TARGET_HW_BREAK_LIMIT 2 | |
| 61 | #define TARGET_HW_WATCH_LIMIT 2 | |
| 62 | ||
| f5a8f1a6 SG |
63 | /* Enable watchpoint macro's */ |
| 64 | ||
| 65 | #define TARGET_HAS_HARDWARE_WATCHPOINTS | |
| 66 | ||
| cd3508f1 KH |
67 | #define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) \ |
| 68 | sparclite_check_watch_resources (type, cnt, ot) | |
| 69 | ||
| 70 | /* When a hardware watchpoint fires off the PC will be left at the | |
| 71 | instruction which caused the watchpoint. It will be necessary for | |
| 72 | GDB to step over the watchpoint. *** | |
| 73 | ||
| 74 | #define STOPPED_BY_WATCHPOINT(W) \ | |
| 75 | ((W).kind == TARGET_WAITKIND_STOPPED \ | |
| 76 | && (W).value.sig == TARGET_SIGNAL_TRAP \ | |
| 77 | && ((int) read_register (IPSW_REGNUM) & 0x00100000)) | |
| 78 | */ | |
| 79 | ||
| 80 | /* Use these macros for watchpoint insertion/deletion. */ | |
| 81 | #define target_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type) | |
| 82 | #define target_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type) | |
| 83 | #define target_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len) | |
| 84 | #define target_remove_hw_breakpoint(addr, len) sparclite_remove_hw_breakpoint (addr, len) | |
| 85 | #define target_stopped_data_address() sparclite_stopped_data_address() |