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c906108c SS |
1 | /* MIPS-dependent portions of the RPC protocol |
2 | used with a VxWorks target | |
3 | ||
c5aa993b | 4 | Contributed by Wind River Systems. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | #include <stdio.h> | |
24 | #include "defs.h" | |
25 | ||
c5aa993b | 26 | #include "vx-share/regPacket.h" |
c906108c SS |
27 | #include "frame.h" |
28 | #include "inferior.h" | |
03f2053f | 29 | #include "gdb_wait.h" |
c906108c SS |
30 | #include "target.h" |
31 | #include "gdbcore.h" | |
32 | #include "command.h" | |
33 | #include "symtab.h" | |
34 | #include "symfile.h" /* for struct complaint */ | |
35 | ||
36 | #include "gdb_string.h" | |
37 | #include <errno.h> | |
38 | #include <signal.h> | |
39 | #include <fcntl.h> | |
40 | #include <sys/types.h> | |
41 | #include <sys/time.h> | |
42 | #include <sys/socket.h> | |
43 | #include <rpc/rpc.h> | |
44 | #include <sys/time.h> /* UTek's <rpc/rpc.h> doesn't #incl this */ | |
45 | #include <netdb.h> | |
46 | #include "vx-share/ptrace.h" | |
47 | #include "vx-share/xdr_ptrace.h" | |
48 | #include "vx-share/xdr_ld.h" | |
49 | #include "vx-share/xdr_rdb.h" | |
50 | #include "vx-share/dbgRpcLib.h" | |
51 | ||
52 | /* get rid of value.h if possible */ | |
53 | #include <value.h> | |
54 | #include <symtab.h> | |
55 | ||
56 | /* Flag set if target has fpu */ | |
57 | ||
58 | extern int target_has_fp; | |
59 | ||
60 | /* Generic register read/write routines in remote-vx.c. */ | |
61 | ||
62 | extern void net_read_registers (); | |
63 | extern void net_write_registers (); | |
64 | ||
65 | /* Read a register or registers from the VxWorks target. | |
66 | REGNO is the register to read, or -1 for all; currently, | |
67 | it is ignored. FIXME look at regno to improve efficiency. */ | |
68 | ||
69 | void | |
70 | vx_read_register (regno) | |
71 | int regno; | |
72 | { | |
73 | char mips_greg_packet[MIPS_GREG_PLEN]; | |
74 | char mips_fpreg_packet[MIPS_FPREG_PLEN]; | |
75 | ||
76 | /* Get general-purpose registers. */ | |
77 | ||
78 | net_read_registers (mips_greg_packet, MIPS_GREG_PLEN, PTRACE_GETREGS); | |
79 | ||
80 | /* this code copies the registers obtained by RPC | |
81 | stored in a structure(s) like this : | |
c5aa993b JM |
82 | |
83 | Register(s) Offset(s) | |
84 | gp 0-31 0x00 | |
85 | hi 0x80 | |
86 | lo 0x84 | |
87 | sr 0x88 | |
88 | pc 0x8c | |
89 | ||
c906108c | 90 | into a stucture like this: |
c5aa993b JM |
91 | |
92 | 0x00 GP 0-31 | |
93 | 0x80 SR | |
94 | 0x84 LO | |
95 | 0x88 HI | |
96 | 0x8C BAD --- Not available currently | |
97 | 0x90 CAUSE --- Not available currently | |
98 | 0x94 PC | |
99 | 0x98 FP 0-31 | |
100 | 0x118 FCSR | |
101 | 0x11C FIR --- Not available currently | |
102 | 0x120 FP --- Not available currently | |
103 | ||
c906108c | 104 | structure is 0x124 (292) bytes in length */ |
c5aa993b | 105 | |
c906108c | 106 | /* Copy the general registers. */ |
c5aa993b | 107 | |
c906108c | 108 | bcopy (&mips_greg_packet[MIPS_R_GP0], ®isters[0], 32 * MIPS_GREG_SIZE); |
c5aa993b | 109 | |
c906108c | 110 | /* Copy SR, LO, HI, and PC. */ |
c5aa993b | 111 | |
c906108c | 112 | bcopy (&mips_greg_packet[MIPS_R_SR], |
c5aa993b | 113 | ®isters[REGISTER_BYTE (PS_REGNUM)], MIPS_GREG_SIZE); |
c906108c | 114 | bcopy (&mips_greg_packet[MIPS_R_LO], |
c5aa993b | 115 | ®isters[REGISTER_BYTE (LO_REGNUM)], MIPS_GREG_SIZE); |
c906108c | 116 | bcopy (&mips_greg_packet[MIPS_R_HI], |
c5aa993b | 117 | ®isters[REGISTER_BYTE (HI_REGNUM)], MIPS_GREG_SIZE); |
c906108c | 118 | bcopy (&mips_greg_packet[MIPS_R_PC], |
c5aa993b JM |
119 | ®isters[REGISTER_BYTE (PC_REGNUM)], MIPS_GREG_SIZE); |
120 | ||
c906108c SS |
121 | /* If the target has floating point registers, fetch them. |
122 | Otherwise, zero the floating point register values in | |
123 | registers[] for good measure, even though we might not | |
124 | need to. */ | |
c5aa993b | 125 | |
c906108c SS |
126 | if (target_has_fp) |
127 | { | |
128 | net_read_registers (mips_fpreg_packet, MIPS_FPREG_PLEN, | |
129 | PTRACE_GETFPREGS); | |
130 | ||
131 | /* Copy the floating point registers. */ | |
132 | ||
c5aa993b | 133 | bcopy (&mips_fpreg_packet[MIPS_R_FP0], |
c906108c SS |
134 | ®isters[REGISTER_BYTE (FP0_REGNUM)], |
135 | REGISTER_RAW_SIZE (FP0_REGNUM) * 32); | |
136 | ||
137 | /* Copy the floating point control/status register (fpcsr). */ | |
138 | ||
c5aa993b | 139 | bcopy (&mips_fpreg_packet[MIPS_R_FPCSR], |
c906108c SS |
140 | ®isters[REGISTER_BYTE (FCRCS_REGNUM)], |
141 | REGISTER_RAW_SIZE (FCRCS_REGNUM)); | |
c5aa993b | 142 | } |
c906108c | 143 | else |
c5aa993b | 144 | { |
c906108c SS |
145 | bzero ((char *) ®isters[REGISTER_BYTE (FP0_REGNUM)], |
146 | REGISTER_RAW_SIZE (FP0_REGNUM) * 32); | |
147 | bzero ((char *) ®isters[REGISTER_BYTE (FCRCS_REGNUM)], | |
148 | REGISTER_RAW_SIZE (FCRCS_REGNUM)); | |
c5aa993b | 149 | } |
c906108c SS |
150 | |
151 | /* Mark the register cache valid. */ | |
152 | ||
153 | registers_fetched (); | |
154 | } | |
155 | ||
156 | /* Store a register or registers into the VxWorks target. | |
157 | REGNO is the register to store, or -1 for all; currently, | |
158 | it is ignored. FIXME look at regno to improve efficiency. */ | |
159 | ||
160 | vx_write_register (regno) | |
161 | int regno; | |
162 | { | |
163 | char mips_greg_packet[MIPS_GREG_PLEN]; | |
164 | char mips_fpreg_packet[MIPS_FPREG_PLEN]; | |
165 | ||
166 | /* Store general registers. */ | |
167 | ||
168 | bcopy (®isters[0], &mips_greg_packet[MIPS_R_GP0], 32 * MIPS_GREG_SIZE); | |
c5aa993b | 169 | |
c906108c | 170 | /* Copy SR, LO, HI, and PC. */ |
c5aa993b | 171 | |
c906108c | 172 | bcopy (®isters[REGISTER_BYTE (PS_REGNUM)], |
c5aa993b | 173 | &mips_greg_packet[MIPS_R_SR], MIPS_GREG_SIZE); |
c906108c | 174 | bcopy (®isters[REGISTER_BYTE (LO_REGNUM)], |
c5aa993b | 175 | &mips_greg_packet[MIPS_R_LO], MIPS_GREG_SIZE); |
c906108c | 176 | bcopy (®isters[REGISTER_BYTE (HI_REGNUM)], |
c5aa993b | 177 | &mips_greg_packet[MIPS_R_HI], MIPS_GREG_SIZE); |
c906108c | 178 | bcopy (®isters[REGISTER_BYTE (PC_REGNUM)], |
c5aa993b JM |
179 | &mips_greg_packet[MIPS_R_PC], MIPS_GREG_SIZE); |
180 | ||
c906108c SS |
181 | net_write_registers (mips_greg_packet, MIPS_GREG_PLEN, PTRACE_SETREGS); |
182 | ||
183 | /* Store floating point registers if the target has them. */ | |
184 | ||
185 | if (target_has_fp) | |
186 | { | |
187 | /* Copy the floating point data registers. */ | |
188 | ||
189 | bcopy (®isters[REGISTER_BYTE (FP0_REGNUM)], | |
c5aa993b | 190 | &mips_fpreg_packet[MIPS_R_FP0], |
c906108c SS |
191 | REGISTER_RAW_SIZE (FP0_REGNUM) * 32); |
192 | ||
193 | /* Copy the floating point control/status register (fpcsr). */ | |
194 | ||
195 | bcopy (®isters[REGISTER_BYTE (FCRCS_REGNUM)], | |
c5aa993b | 196 | &mips_fpreg_packet[MIPS_R_FPCSR], |
c906108c SS |
197 | REGISTER_RAW_SIZE (FCRCS_REGNUM)); |
198 | ||
199 | net_write_registers (mips_fpreg_packet, MIPS_FPREG_PLEN, | |
200 | PTRACE_SETFPREGS); | |
201 | } | |
202 | } |