[binutils.git] / opcodes / tic30-dis.c

/* Disassembly routines for TMS320C30 architecture
   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
   Contributed by Steven Haworth ([email protected])

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

#include <errno.h>
#include <math.h>
#include "sysdep.h"
#include "dis-asm.h"
#include "opcode/tic30.h"

#define NORMAL_INSN   1
#define PARALLEL_INSN 2

/* Gets the type of instruction based on the top 2 or 3 bits of the
   instruction word.  */
#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)

/* Instruction types.  */
#define TWO_OPERAND_1 0x00000000
#define TWO_OPERAND_2 0x40000000
#define THREE_OPERAND 0x20000000
#define PAR_STORE     0xC0000000
#define MUL_ADDS      0x80000000
#define BRANCHES      0x60000000

/* Specific instruction id bits.  */
#define NORMAL_IDEN    0x1F800000
#define PAR_STORE_IDEN 0x3E000000
#define MUL_ADD_IDEN   0x2C000000
#define BR_IMM_IDEN    0x1F000000
#define BR_COND_IDEN   0x1C3F0000

/* Addressing modes.  */
#define AM_REGISTER 0x00000000
#define AM_DIRECT   0x00200000
#define AM_INDIRECT 0x00400000
#define AM_IMM      0x00600000

#define P_FIELD 0x03000000

#define REG_AR0 0x08
#define LDP_INSN 0x08700000

/* TMS320C30 program counter for current instruction.  */
static unsigned int _pc;

struct instruction
{
  int type;
  template *tm;
  partemplate *ptm;
};

int get_tic30_instruction PARAMS ((unsigned long, struct instruction *));
int print_two_operand
  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
int print_three_operand
  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
int print_par_insn
  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
int print_branch
  PARAMS ((disassemble_info *, unsigned long, struct instruction *));
int get_indirect_operand PARAMS ((unsigned short, int, char *));
int get_register_operand PARAMS ((unsigned char, char *));
int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *));

int
print_insn_tic30 (pc, info)
     bfd_vma pc;
     disassemble_info *info;
{
  unsigned long insn_word;
  struct instruction insn = { 0, NULL, NULL };
  bfd_vma bufaddr = pc - info->buffer_vma;
  /* Obtain the current instruction word from the buffer.  */
  insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
    (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
  _pc = pc / 4;
  /* Get the instruction refered to by the current instruction word
     and print it out based on its type.  */
  if (!get_tic30_instruction (insn_word, &insn))
    return -1;
  switch (GET_TYPE (insn_word))
    {
    case TWO_OPERAND_1:
    case TWO_OPERAND_2:
      if (!print_two_operand (info, insn_word, &insn))
	return -1;
      break;
    case THREE_OPERAND:
      if (!print_three_operand (info, insn_word, &insn))
	return -1;
      break;
    case PAR_STORE:
    case MUL_ADDS:
      if (!print_par_insn (info, insn_word, &insn))
	return -1;
      break;
    case BRANCHES:
      if (!print_branch (info, insn_word, &insn))
	return -1;
      break;
    }
  return 4;
}

int
get_tic30_instruction (insn_word, insn)
     unsigned long insn_word;
     struct instruction *insn;
{
  switch (GET_TYPE (insn_word))
    {
    case TWO_OPERAND_1:
    case TWO_OPERAND_2:
    case THREE_OPERAND:
      insn->type = NORMAL_INSN;
      {
	template *current_optab = (template *) tic30_optab;
	for (; current_optab < tic30_optab_end; current_optab++)
	  {
	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
	      {
		if (current_optab->operands == 0)
		  {
		    if (current_optab->base_opcode == insn_word)
		      {
			insn->tm = current_optab;
			break;
		      }
		  }
		else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
		  {
		    insn->tm = current_optab;
		    break;
		  }
	      }
	  }
      }
      break;
    case PAR_STORE:
      insn->type = PARALLEL_INSN;
      {
	partemplate *current_optab = (partemplate *) tic30_paroptab;
	for (; current_optab < tic30_paroptab_end; current_optab++)
	  {
	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
	      {
		if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN))
		  {
		    insn->ptm = current_optab;
		    break;
		  }
	      }
	  }
      }
      break;
    case MUL_ADDS:
      insn->type = PARALLEL_INSN;
      {
	partemplate *current_optab = (partemplate *) tic30_paroptab;
	for (; current_optab < tic30_paroptab_end; current_optab++)
	  {
	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
	      {
		if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN))
		  {
		    insn->ptm = current_optab;
		    break;
		  }
	      }
	  }
      }
      break;
    case BRANCHES:
      insn->type = NORMAL_INSN;
      {
	template *current_optab = (template *) tic30_optab;
	for (; current_optab < tic30_optab_end; current_optab++)
	  {
	    if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
	      {
		if (current_optab->operand_types[0] & Imm24)
		  {
		    if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN))
		      {
			insn->tm = current_optab;
			break;
		      }
		  }
		else if (current_optab->operands > 0)
		  {
		    if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN))
		      {
			insn->tm = current_optab;
			break;
		      }
		  }
		else
		  {
		    if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000)))
		      {
			insn->tm = current_optab;
			break;
		      }
		  }
	      }
	  }
      }
      break;
    default:
      return 0;
    }
  return 1;
}

int
print_two_operand (info, insn_word, insn)
     disassemble_info *info;
     unsigned long insn_word;
     struct instruction *insn;
{
  char name[12];
  char operand[2][13] =
  {
    {0},
    {0}};
  float f_number;

  if (insn->tm == NULL)
    return 0;
  strcpy (name, insn->tm->name);
  if (insn->tm->opcode_modifier == AddressMode)
    {
      int src_op, dest_op;
      /* Determine whether instruction is a store or a normal instruction.  */
      if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect))
	{
	  src_op = 1;
	  dest_op = 0;
	}
      else
	{
	  src_op = 0;
	  dest_op = 1;
	}
      /* Get the destination register.  */
      if (insn->tm->operands == 2)
	get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
      /* Get the source operand based on addressing mode.  */
      switch (insn_word & AddressMode)
	{
	case AM_REGISTER:
	  /* Check for the NOP instruction before getting the operand.  */
	  if ((insn->tm->operand_types[0] & NotReq) == 0)
	    get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
	  break;
	case AM_DIRECT:
	  sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
	  break;
	case AM_INDIRECT:
	  get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
	  break;
	case AM_IMM:
	  /* Get the value of the immediate operand based on variable type.  */
	  switch (insn->tm->imm_arg_type)
	    {
	    case Imm_Float:
	      cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
	      sprintf (operand[src_op], "%2.2f", f_number);
	      break;
	    case Imm_SInt:
	      sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
	      break;
	    case Imm_UInt:
	      sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
	      break;
	    default:
	      return 0;
	    }
	  /* Handle special case for LDP instruction.  */
	  if ((insn_word & 0xFFFFFF00) == LDP_INSN)
	    {
	      strcpy (name, "ldp");
	      sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
	      operand[1][0] = '\0';
	    }
	}
    }
  /* Handle case for stack and rotate instructions.  */
  else if (insn->tm->operands == 1)
    {
      if (insn->tm->opcode_modifier == StackOp)
	{
	  get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
	}
    }
  /* Output instruction to stream.  */
  info->fprintf_func (info->stream, "   %s %s%c%s", name,
		      operand[0][0] ? operand[0] : "",
		      operand[1][0] ? ',' : ' ',
		      operand[1][0] ? operand[1] : "");
  return 1;
}

int
print_three_operand (info, insn_word, insn)
     disassemble_info *info;
     unsigned long insn_word;
     struct instruction *insn;
{
  char operand[3][13] =
  {
    {0},
    {0},
    {0}};

  if (insn->tm == NULL)
    return 0;
  switch (insn_word & AddressMode)
    {
    case AM_REGISTER:
      get_register_operand ((insn_word & 0x000000FF), operand[0]);
      get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
      break;
    case AM_DIRECT:
      get_register_operand ((insn_word & 0x000000FF), operand[0]);
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
      break;
    case AM_INDIRECT:
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
      get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
      break;
    case AM_IMM:
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
      break;
    default:
      return 0;
    }
  if (insn->tm->operands == 3)
    get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
  info->fprintf_func (info->stream, "   %s %s,%s%c%s", insn->tm->name,
		      operand[0], operand[1],
		      operand[2][0] ? ',' : ' ',
		      operand[2][0] ? operand[2] : "");
  return 1;
}

int
print_par_insn (info, insn_word, insn)
     disassemble_info *info;
     unsigned long insn_word;
     struct instruction *insn;
{
  size_t i, len;
  char *name1, *name2;
  char operand[2][3][13] =
  {
    {
      {0},
      {0},
      {0}},
    {
      {0},
      {0},
      {0}}};

  if (insn->ptm == NULL)
    return 0;
  /* Parse out the names of each of the parallel instructions from the
     q_insn1_insn2 format.  */
  name1 = (char *) strdup (insn->ptm->name + 2);
  name2 = "";
  len = strlen (name1);
  for (i = 0; i < len; i++)
    {
      if (name1[i] == '_')
	{
	  name2 = &name1[i + 1];
	  name1[i] = '\0';
	  break;
	}
    }
  /* Get the operands of the instruction based on the operand order.  */
  switch (insn->ptm->oporder)
    {
    case OO_4op1:
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
      break;
    case OO_4op2:
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
      get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
      break;
    case OO_4op3:
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
      break;
    case OO_5op1:
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
      get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
      break;
    case OO_5op2:
      get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
      get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
      get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
      get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
      get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
      break;
    case OO_PField:
      if (insn_word & 0x00800000)
	get_register_operand (0x01, operand[0][2]);
      else
	get_register_operand (0x00, operand[0][2]);
      if (insn_word & 0x00400000)
	get_register_operand (0x03, operand[1][2]);
      else
	get_register_operand (0x02, operand[1][2]);
      switch (insn_word & P_FIELD)
	{
	case 0x00000000:
	  get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
	  get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
	  get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
	  get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
	  break;
	case 0x01000000:
	  get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
	  get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
	  get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
	  get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
	  break;
	case 0x02000000:
	  get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
	  get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
	  get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
	  get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
	  break;
	case 0x03000000:
	  get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
	  get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
	  get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
	  get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
	  break;
	}
      break;
    default:
      return 0;
    }
  info->fprintf_func (info->stream, "   %s %s,%s%c%s", name1,
		      operand[0][0], operand[0][1],
		      operand[0][2][0] ? ',' : ' ',
		      operand[0][2][0] ? operand[0][2] : "");
  info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2,
		      operand[1][0], operand[1][1],
		      operand[1][2][0] ? ',' : ' ',
		      operand[1][2][0] ? operand[1][2] : "");
  free (name1);
  return 1;
}

int
print_branch (info, insn_word, insn)
     disassemble_info *info;
     unsigned long insn_word;
     struct instruction *insn;
{
  char operand[2][13] =
  {
    {0},
    {0}};
  unsigned long address;
  int print_label = 0;

  if (insn->tm == NULL)
    return 0;
  /* Get the operands for 24-bit immediate jumps.  */
  if (insn->tm->operand_types[0] & Imm24)
    {
      address = insn_word & 0x00FFFFFF;
      sprintf (operand[0], "0x%lX", address);
      print_label = 1;
    }
  /* Get the operand for the trap instruction.  */
  else if (insn->tm->operand_types[0] & IVector)
    {
      address = insn_word & 0x0000001F;
      sprintf (operand[0], "0x%lX", address);
    }
  else
    {
      address = insn_word & 0x0000FFFF;
      /* Get the operands for the DB instructions.  */
      if (insn->tm->operands == 2)
	{
	  get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
	  if (insn_word & PCRel)
	    {
	      sprintf (operand[1], "%d", (short) address);
	      print_label = 1;
	    }
	  else
	    get_register_operand (insn_word & 0x0000001F, operand[1]);
	}
      /* Get the operands for the standard branches.  */
      else if (insn->tm->operands == 1)
	{
	  if (insn_word & PCRel)
	    {
	      address = (short) address;
	      sprintf (operand[0], "%ld", address);
	      print_label = 1;
	    }
	  else
	    get_register_operand (insn_word & 0x0000001F, operand[0]);
	}
    }
  info->fprintf_func (info->stream, "   %s %s%c%s", insn->tm->name,
		      operand[0][0] ? operand[0] : "",
		      operand[1][0] ? ',' : ' ',
		      operand[1][0] ? operand[1] : "");
  /* Print destination of branch in relation to current symbol.  */
  if (print_label && info->symbols)
    {
      asymbol *sym = *info->symbols;

      if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
	{
	  address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
	  /* Check for delayed instruction, if so adjust destination.  */
	  if (insn_word & 0x00200000)
	    address += 2;
	}
      else
	{
	  address -= ((sym->section->vma + sym->value) / 4);
	}
      if (address == 0)
	info->fprintf_func (info->stream, " <%s>", sym->name);
      else
	info->fprintf_func (info->stream, " <%s %c %d>", sym->name,
			    ((short) address < 0) ? '-' : '+',
			    abs (address));
    }
  return 1;
}

int
get_indirect_operand (fragment, size, buffer)
     unsigned short fragment;
     int size;
     char *buffer;
{
  unsigned char mod;
  unsigned arnum;
  unsigned char disp;

  if (buffer == NULL)
    return 0;
  /* Determine which bits identify the sections of the indirect
     operand based on the size in bytes.  */
  switch (size)
    {
    case 1:
      mod = (fragment & 0x00F8) >> 3;
      arnum = (fragment & 0x0007);
      disp = 0;
      break;
    case 2:
      mod = (fragment & 0xF800) >> 11;
      arnum = (fragment & 0x0700) >> 8;
      disp = (fragment & 0x00FF);
      break;
    default:
      return 0;
    }
  {
    const ind_addr_type *current_ind = tic30_indaddr_tab;
    for (; current_ind < tic30_indaddrtab_end; current_ind++)
      {
	if (current_ind->modfield == mod)
	  {
	    if (current_ind->displacement == IMPLIED_DISP && size == 2)
	      {
		continue;
	      }
	    else
	      {
		size_t i, len;
		int bufcnt;

		len = strlen (current_ind->syntax);
		for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
		  {
		    buffer[bufcnt] = current_ind->syntax[i];
		    if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
		      buffer[++bufcnt] = arnum + '0';
		    if (buffer[bufcnt] == '('
			&& current_ind->displacement == DISP_REQUIRED)
		      {
			sprintf (&buffer[bufcnt + 1], "%u", disp);
			bufcnt += strlen (&buffer[bufcnt + 1]);
		      }
		  }
		buffer[bufcnt + 1] = '\0';
		break;
	      }
	  }
      }
  }
  return 1;
}

int
get_register_operand (fragment, buffer)
     unsigned char fragment;
     char *buffer;
{
  const reg *current_reg = tic30_regtab;

  if (buffer == NULL)
    return 0;
  for (; current_reg < tic30_regtab_end; current_reg++)
    {
      if ((fragment & 0x1F) == current_reg->opcode)
	{
	  strcpy (buffer, current_reg->name);
	  return 1;
	}
    }
  return 0;
}

int
cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat)
     unsigned long tmsfloat;
     int size;
     float *ieeefloat;
{
  unsigned long exp, sign, mant;

  if (size == 2)
    {
      if ((tmsfloat & 0x0000F000) == 0x00008000)
	tmsfloat = 0x80000000;
      else
	{
	  tmsfloat <<= 16;
	  tmsfloat = (long) tmsfloat >> 4;
	}
    }
  exp = tmsfloat & 0xFF000000;
  if (exp == 0x80000000)
    {
      *ieeefloat = 0.0;
      return 1;
    }
  exp += 0x7F000000;
  sign = (tmsfloat & 0x00800000) << 8;
  mant = tmsfloat & 0x007FFFFF;
  if (exp == 0xFF000000)
    {
      if (mant == 0)
	*ieeefloat = ERANGE;
      if (sign == 0)
	*ieeefloat = 1.0 / 0.0;
      else
	*ieeefloat = -1.0 / 0.0;
      return 1;
    }
  exp >>= 1;
  if (sign)
    {
      mant = (~mant) & 0x007FFFFF;
      mant += 1;
      exp += mant & 0x00800000;
      exp &= 0x7F800000;
      mant &= 0x007FFFFF;
    }
  if (tmsfloat == 0x80000000)
    sign = mant = exp = 0;
  tmsfloat = sign | exp | mant;
  *ieeefloat = *((float *) &tmsfloat);
  return 1;
}
Commit	Line	Data
252b5132	1	/* Disassembly routines for TMS320C30 architecture
060d22b0	2	Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
252b5132 RH	3	Contributed by Steven Haworth ([email protected])
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
	18	02111-1307, USA. */
	19
	20	#include <errno.h>
	21	#include <math.h>
6094e721	22	#include "sysdep.h"
252b5132 RH	23	#include "dis-asm.h"
	24	#include "opcode/tic30.h"
	25
	26	#define NORMAL_INSN 1
	27	#define PARALLEL_INSN 2
	28
	29	/* Gets the type of instruction based on the top 2 or 3 bits of the
bf830eae	30	instruction word. */
252b5132 RH	31	#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
252b5132 RH	32
bf830eae	33	/* Instruction types. */
252b5132 RH	34	#define TWO_OPERAND_1 0x00000000
	35	#define TWO_OPERAND_2 0x40000000
	36	#define THREE_OPERAND 0x20000000
	37	#define PAR_STORE 0xC0000000
	38	#define MUL_ADDS 0x80000000
	39	#define BRANCHES 0x60000000
	40
bf830eae	41	/* Specific instruction id bits. */
252b5132 RH	42	#define NORMAL_IDEN 0x1F800000
	43	#define PAR_STORE_IDEN 0x3E000000
	44	#define MUL_ADD_IDEN 0x2C000000
	45	#define BR_IMM_IDEN 0x1F000000
	46	#define BR_COND_IDEN 0x1C3F0000
	47
bf830eae	48	/* Addressing modes. */
252b5132 RH	49	#define AM_REGISTER 0x00000000
	50	#define AM_DIRECT 0x00200000
	51	#define AM_INDIRECT 0x00400000
	52	#define AM_IMM 0x00600000
	53
	54	#define P_FIELD 0x03000000
	55
	56	#define REG_AR0 0x08
	57	#define LDP_INSN 0x08700000
	58
bf830eae	59	/* TMS320C30 program counter for current instruction. */
252b5132 RH	60	static unsigned int _pc;
	61
	62	struct instruction
bf830eae KH	63	{
	64	int type;
	65	template *tm;
	66	partemplate *ptm;
	67	};
252b5132 RH	68
	69	int get_tic30_instruction PARAMS ((unsigned long, struct instruction *));
	70	int print_two_operand
	71	PARAMS ((disassemble_info , unsigned long, struct instruction ));
	72	int print_three_operand
	73	PARAMS ((disassemble_info , unsigned long, struct instruction ));
	74	int print_par_insn
	75	PARAMS ((disassemble_info , unsigned long, struct instruction ));
	76	int print_branch
	77	PARAMS ((disassemble_info , unsigned long, struct instruction ));
	78	int get_indirect_operand PARAMS ((unsigned short, int, char *));
	79	int get_register_operand PARAMS ((unsigned char, char *));
	80	int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *));
	81
	82	int
	83	print_insn_tic30 (pc, info)
	84	bfd_vma pc;
	85	disassemble_info *info;
	86	{
	87	unsigned long insn_word;
bf830eae	88	struct instruction insn = { 0, NULL, NULL };
252b5132	89	bfd_vma bufaddr = pc - info->buffer_vma;
bf830eae	90	/* Obtain the current instruction word from the buffer. */
252b5132 RH	91	insn_word = ((info->buffer + bufaddr) << 24) \| ((info->buffer + bufaddr + 1) << 16) \|
	92	((info->buffer + bufaddr + 2) << 8) \| (info->buffer + bufaddr + 3);
	93	_pc = pc / 4;
	94	/* Get the instruction refered to by the current instruction word
bf830eae	95	and print it out based on its type. */
252b5132 RH	96	if (!get_tic30_instruction (insn_word, &insn))
	97	return -1;
	98	switch (GET_TYPE (insn_word))
	99	{
	100	case TWO_OPERAND_1:
	101	case TWO_OPERAND_2:
	102	if (!print_two_operand (info, insn_word, &insn))
	103	return -1;
	104	break;
	105	case THREE_OPERAND:
	106	if (!print_three_operand (info, insn_word, &insn))
	107	return -1;
	108	break;
	109	case PAR_STORE:
	110	case MUL_ADDS:
	111	if (!print_par_insn (info, insn_word, &insn))
	112	return -1;
	113	break;
	114	case BRANCHES:
	115	if (!print_branch (info, insn_word, &insn))
	116	return -1;
	117	break;
	118	}
	119	return 4;
	120	}
	121
	122	int
	123	get_tic30_instruction (insn_word, insn)
	124	unsigned long insn_word;
	125	struct instruction *insn;
	126	{
	127	switch (GET_TYPE (insn_word))
	128	{
	129	case TWO_OPERAND_1:
	130	case TWO_OPERAND_2:
	131	case THREE_OPERAND:
	132	insn->type = NORMAL_INSN;
	133	{
	134	template current_optab = (template ) tic30_optab;
	135	for (; current_optab < tic30_optab_end; current_optab++)
	136	{
	137	if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
	138	{
	139	if (current_optab->operands == 0)
	140	{
	141	if (current_optab->base_opcode == insn_word)
	142	{
	143	insn->tm = current_optab;
	144	break;
	145	}
	146	}
	147	else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
	148	{
	149	insn->tm = current_optab;
	150	break;
	151	}
	152	}
	153	}
	154	}
	155	break;
	156	case PAR_STORE:
	157	insn->type = PARALLEL_INSN;
	158	{
	159	partemplate current_optab = (partemplate ) tic30_paroptab;
160	for (; current_optab < tic30_paroptab_end; current_optab++)
161	{
162	if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
163	{
164	if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN))
165	{
166	insn->ptm = current_optab;
167	break;
168	}
169	}
170	}
171	}
172	break;
173	case MUL_ADDS:
174	insn->type = PARALLEL_INSN;
175	{
176	partemplate current_optab = (partemplate ) tic30_paroptab;
177	for (; current_optab < tic30_paroptab_end; current_optab++)
178	{
179	if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
180	{
181	if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN))
182	{
183	insn->ptm = current_optab;
184	break;
185	}
186	}
187	}
188	}
189	break;
190	case BRANCHES:
191	insn->type = NORMAL_INSN;
192	{
193	template current_optab = (template ) tic30_optab;
194	for (; current_optab < tic30_optab_end; current_optab++)
195	{
196	if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
197	{
198	if (current_optab->operand_types[0] & Imm24)
199	{
200	if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN))
201	{
202	insn->tm = current_optab;
203	break;
204	}
205	}
206	else if (current_optab->operands > 0)
207	{
208	if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN))
209	{
210	insn->tm = current_optab;
211	break;
212	}
213	}
214	else
215	{
216	if ((current_optab->base_opcode & (BR_COND_IDEN \| 0x00800000)) == (insn_word & (BR_COND_IDEN \| 0x00800000)))
217	{
218	insn->tm = current_optab;
219	break;
220	}
221	}
222	}
223	}
224	}
225	break;
226	default:
227	return 0;
228	}
229	return 1;
230	}
231
232	int
233	print_two_operand (info, insn_word, insn)
234	disassemble_info *info;
235	unsigned long insn_word;
236	struct instruction *insn;
237	{
238	char name[12];
239	char operand[2][13] =
240	{
241	{0},
242	{0}};
243	float f_number;
244
245	if (insn->tm == NULL)
246	return 0;
247	strcpy (name, insn->tm->name);
248	if (insn->tm->opcode_modifier == AddressMode)
249	{
250	int src_op, dest_op;
bf830eae	251	/* Determine whether instruction is a store or a normal instruction. */
252b5132 RH	252	if ((insn->tm->operand_types[1] & (Direct \| Indirect)) == (Direct \| Indirect))
	253	{
	254	src_op = 1;
	255	dest_op = 0;
	256	}
	257	else
	258	{
	259	src_op = 0;
	260	dest_op = 1;
	261	}
bf830eae	262	/* Get the destination register. */
252b5132 RH	263	if (insn->tm->operands == 2)
252b5132 RH	264	get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
bf830eae	265	/* Get the source operand based on addressing mode. */
252b5132 RH	266	switch (insn_word & AddressMode)
	267	{
	268	case AM_REGISTER:
bf830eae	269	/* Check for the NOP instruction before getting the operand. */
252b5132 RH	270	if ((insn->tm->operand_types[0] & NotReq) == 0)
	271	get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
	272	break;
	273	case AM_DIRECT:
	274	sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
	275	break;
	276	case AM_INDIRECT:
	277	get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
	278	break;
	279	case AM_IMM:
bf830eae	280	/* Get the value of the immediate operand based on variable type. */
252b5132 RH	281	switch (insn->tm->imm_arg_type)
	282	{
	283	case Imm_Float:
	284	cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
	285	sprintf (operand[src_op], "%2.2f", f_number);
	286	break;
	287	case Imm_SInt:
	288	sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
	289	break;
	290	case Imm_UInt:
	291	sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
	292	break;
	293	default:
	294	return 0;
	295	}
bf830eae	296	/* Handle special case for LDP instruction. */
252b5132 RH	297	if ((insn_word & 0xFFFFFF00) == LDP_INSN)
	298	{
	299	strcpy (name, "ldp");
	300	sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
	301	operand[1][0] = '\0';
	302	}
	303	}
	304	}
bf830eae	305	/* Handle case for stack and rotate instructions. */
252b5132 RH	306	else if (insn->tm->operands == 1)
	307	{
	308	if (insn->tm->opcode_modifier == StackOp)
	309	{
	310	get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
	311	}
	312	}
bf830eae	313	/* Output instruction to stream. */
252b5132 RH	314	info->fprintf_func (info->stream, " %s %s%c%s", name,
	315	operand[0][0] ? operand[0] : "",
	316	operand[1][0] ? ',' : ' ',
	317	operand[1][0] ? operand[1] : "");
	318	return 1;
	319	}
	320
	321	int
	322	print_three_operand (info, insn_word, insn)
	323	disassemble_info *info;
	324	unsigned long insn_word;
	325	struct instruction *insn;
	326	{
	327	char operand[3][13] =
	328	{
	329	{0},
	330	{0},
	331	{0}};
	332
	333	if (insn->tm == NULL)
	334	return 0;
	335	switch (insn_word & AddressMode)
	336	{
	337	case AM_REGISTER:
	338	get_register_operand ((insn_word & 0x000000FF), operand[0]);
	339	get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
	340	break;
	341	case AM_DIRECT:
	342	get_register_operand ((insn_word & 0x000000FF), operand[0]);
	343	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
	344	break;
	345	case AM_INDIRECT:
	346	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
	347	get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
	348	break;
	349	case AM_IMM:
	350	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
	351	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
	352	break;
	353	default:
	354	return 0;
	355	}
	356	if (insn->tm->operands == 3)
	357	get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
	358	info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name,
	359	operand[0], operand[1],
	360	operand[2][0] ? ',' : ' ',
	361	operand[2][0] ? operand[2] : "");
	362	return 1;
	363	}
	364
	365	int
	366	print_par_insn (info, insn_word, insn)
	367	disassemble_info *info;
	368	unsigned long insn_word;
	369	struct instruction *insn;
	370	{
	371	size_t i, len;
	372	char name1, name2;
	373	char operand[2][3][13] =
	374	{
	375	{
	376	{0},
	377	{0},
378	{0}},
379	{
380	{0},
381	{0},
382	{0}}};
383
384	if (insn->ptm == NULL)
385	return 0;
386	/* Parse out the names of each of the parallel instructions from the
bf830eae	387	q_insn1_insn2 format. */
252b5132 RH	388	name1 = (char *) strdup (insn->ptm->name + 2);
	389	name2 = "";
	390	len = strlen (name1);
	391	for (i = 0; i < len; i++)
	392	{
	393	if (name1[i] == '_')
	394	{
	395	name2 = &name1[i + 1];
	396	name1[i] = '\0';
	397	break;
	398	}
	399	}
bf830eae	400	/* Get the operands of the instruction based on the operand order. */
252b5132 RH	401	switch (insn->ptm->oporder)
	402	{
	403	case OO_4op1:
	404	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
	405	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
	406	get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
	407	get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
	408	break;
	409	case OO_4op2:
	410	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
	411	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
	412	get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
	413	get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
	414	break;
	415	case OO_4op3:
	416	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
	417	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
	418	get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
	419	get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
	420	break;
	421	case OO_5op1:
	422	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
	423	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
	424	get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
	425	get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
	426	get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
	427	break;
	428	case OO_5op2:
	429	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
	430	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
	431	get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
	432	get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
	433	get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
	434	break;
	435	case OO_PField:
	436	if (insn_word & 0x00800000)
	437	get_register_operand (0x01, operand[0][2]);
	438	else
	439	get_register_operand (0x00, operand[0][2]);
	440	if (insn_word & 0x00400000)
	441	get_register_operand (0x03, operand[1][2]);
	442	else
	443	get_register_operand (0x02, operand[1][2]);
	444	switch (insn_word & P_FIELD)
	445	{
	446	case 0x00000000:
	447	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
	448	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
	449	get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
	450	get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
	451	break;
	452	case 0x01000000:
	453	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
	454	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
	455	get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
	456	get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
	457	break;
	458	case 0x02000000:
	459	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
	460	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
	461	get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
	462	get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
	463	break;
	464	case 0x03000000:
465	get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
466	get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
467	get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
468	get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
469	break;
470	}
471	break;
472	default:
473	return 0;
474	}
475	info->fprintf_func (info->stream, " %s %s,%s%c%s", name1,
476	operand[0][0], operand[0][1],
477	operand[0][2][0] ? ',' : ' ',
478	operand[0][2][0] ? operand[0][2] : "");
479	info->fprintf_func (info->stream, "\n\t\t\t\|\| %s %s,%s%c%s", name2,
480	operand[1][0], operand[1][1],
481	operand[1][2][0] ? ',' : ' ',
482	operand[1][2][0] ? operand[1][2] : "");
483	free (name1);
484	return 1;
485	}
486
487	int
488	print_branch (info, insn_word, insn)
489	disassemble_info *info;
490	unsigned long insn_word;
491	struct instruction *insn;
492	{
493	char operand[2][13] =
494	{
495	{0},
496	{0}};
497	unsigned long address;
498	int print_label = 0;
499
500	if (insn->tm == NULL)
501	return 0;
bf830eae	502	/* Get the operands for 24-bit immediate jumps. */
252b5132 RH	503	if (insn->tm->operand_types[0] & Imm24)
	504	{
	505	address = insn_word & 0x00FFFFFF;
	506	sprintf (operand[0], "0x%lX", address);
	507	print_label = 1;
	508	}
bf830eae	509	/* Get the operand for the trap instruction. */
252b5132 RH	510	else if (insn->tm->operand_types[0] & IVector)
	511	{
	512	address = insn_word & 0x0000001F;
	513	sprintf (operand[0], "0x%lX", address);
	514	}
	515	else
	516	{
	517	address = insn_word & 0x0000FFFF;
bf830eae	518	/* Get the operands for the DB instructions. */
252b5132 RH	519	if (insn->tm->operands == 2)
	520	{
	521	get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
	522	if (insn_word & PCRel)
	523	{
	524	sprintf (operand[1], "%d", (short) address);
	525	print_label = 1;
	526	}
	527	else
	528	get_register_operand (insn_word & 0x0000001F, operand[1]);
	529	}
bf830eae	530	/* Get the operands for the standard branches. */
252b5132 RH	531	else if (insn->tm->operands == 1)
	532	{
	533	if (insn_word & PCRel)
	534	{
	535	address = (short) address;
	536	sprintf (operand[0], "%ld", address);
	537	print_label = 1;
	538	}
	539	else
	540	get_register_operand (insn_word & 0x0000001F, operand[0]);
	541	}
	542	}
	543	info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name,
	544	operand[0][0] ? operand[0] : "",
	545	operand[1][0] ? ',' : ' ',
	546	operand[1][0] ? operand[1] : "");
bf830eae	547	/* Print destination of branch in relation to current symbol. */
252b5132 RH	548	if (print_label && info->symbols)
	549	{
	550	asymbol sym = info->symbols;
	551
	552	if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
	553	{
	554	address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
bf830eae	555	/* Check for delayed instruction, if so adjust destination. */
252b5132 RH	556	if (insn_word & 0x00200000)
	557	address += 2;
	558	}
	559	else
	560	{
	561	address -= ((sym->section->vma + sym->value) / 4);
	562	}
	563	if (address == 0)
	564	info->fprintf_func (info->stream, " <%s>", sym->name);
	565	else
	566	info->fprintf_func (info->stream, " <%s %c %d>", sym->name,
	567	((short) address < 0) ? '-' : '+',
	568	abs (address));
	569	}
	570	return 1;
	571	}
	572
	573	int
	574	get_indirect_operand (fragment, size, buffer)
	575	unsigned short fragment;
	576	int size;
	577	char *buffer;
	578	{
	579	unsigned char mod;
	580	unsigned arnum;
	581	unsigned char disp;
	582
	583	if (buffer == NULL)
	584	return 0;
bf830eae KH	585	/* Determine which bits identify the sections of the indirect
bf830eae KH	586	operand based on the size in bytes. */
252b5132 RH	587	switch (size)
	588	{
	589	case 1:
	590	mod = (fragment & 0x00F8) >> 3;
	591	arnum = (fragment & 0x0007);
	592	disp = 0;
	593	break;
	594	case 2:
	595	mod = (fragment & 0xF800) >> 11;
	596	arnum = (fragment & 0x0700) >> 8;
	597	disp = (fragment & 0x00FF);
	598	break;
	599	default:
	600	return 0;
	601	}
	602	{
	603	const ind_addr_type *current_ind = tic30_indaddr_tab;
	604	for (; current_ind < tic30_indaddrtab_end; current_ind++)
	605	{
	606	if (current_ind->modfield == mod)
	607	{
	608	if (current_ind->displacement == IMPLIED_DISP && size == 2)
	609	{
	610	continue;
	611	}
	612	else
	613	{
	614	size_t i, len;
	615	int bufcnt;
bf830eae	616
252b5132 RH	617	len = strlen (current_ind->syntax);
	618	for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
	619	{
	620	buffer[bufcnt] = current_ind->syntax[i];
	621	if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
	622	buffer[++bufcnt] = arnum + '0';
bf830eae KH	623	if (buffer[bufcnt] == '('
bf830eae KH	624	&& current_ind->displacement == DISP_REQUIRED)
252b5132 RH	625	{
	626	sprintf (&buffer[bufcnt + 1], "%u", disp);
	627	bufcnt += strlen (&buffer[bufcnt + 1]);
	628	}
	629	}
	630	buffer[bufcnt + 1] = '\0';
	631	break;
	632	}
	633	}
	634	}
	635	}
	636	return 1;
	637	}
	638
	639	int
	640	get_register_operand (fragment, buffer)
	641	unsigned char fragment;
	642	char *buffer;
	643	{
	644	const reg *current_reg = tic30_regtab;
	645
	646	if (buffer == NULL)
	647	return 0;
	648	for (; current_reg < tic30_regtab_end; current_reg++)
	649	{
	650	if ((fragment & 0x1F) == current_reg->opcode)
	651	{
	652	strcpy (buffer, current_reg->name);
	653	return 1;
	654	}
	655	}
	656	return 0;
	657	}
	658
	659	int
	660	cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat)
	661	unsigned long tmsfloat;
	662	int size;
	663	float *ieeefloat;
	664	{
	665	unsigned long exp, sign, mant;
	666
	667	if (size == 2)
	668	{
	669	if ((tmsfloat & 0x0000F000) == 0x00008000)
	670	tmsfloat = 0x80000000;
	671	else
	672	{
	673	tmsfloat <<= 16;
	674	tmsfloat = (long) tmsfloat >> 4;
	675	}
	676	}
	677	exp = tmsfloat & 0xFF000000;
	678	if (exp == 0x80000000)
	679	{
	680	*ieeefloat = 0.0;
	681	return 1;
	682	}
	683	exp += 0x7F000000;
	684	sign = (tmsfloat & 0x00800000) << 8;
	685	mant = tmsfloat & 0x007FFFFF;
	686	if (exp == 0xFF000000)
	687	{
	688	if (mant == 0)
689	*ieeefloat = ERANGE;
690	if (sign == 0)
691	*ieeefloat = 1.0 / 0.0;
692	else
693	*ieeefloat = -1.0 / 0.0;
694	return 1;
695	}
696	exp >>= 1;
697	if (sign)
698	{
699	mant = (~mant) & 0x007FFFFF;
700	mant += 1;
701	exp += mant & 0x00800000;
702	exp &= 0x7F800000;
703	mant &= 0x007FFFFF;
704	}
705	if (tmsfloat == 0x80000000)
706	sign = mant = exp = 0;
707	tmsfloat = sign \| exp \| mant;
708	ieeefloat = ((float *) &tmsfloat);
709	return 1;
710	}