[binutils.git] / sim / mn10300 / mn10300_sim.h

#include <stdio.h>
#include <ctype.h>
#include "ansidecl.h"
#include "callback.h"
#include "opcode/mn10300.h"
#include <limits.h>
#include "remote-sim.h"
#include "bfd.h"

#ifndef INLINE
#ifdef __GNUC__
#define INLINE inline
#else
#define INLINE
#endif
#endif

extern host_callback *mn10300_callback;
extern SIM_DESC simulator;

#define DEBUG_TRACE		0x00000001
#define DEBUG_VALUES		0x00000002

extern int mn10300_debug;

#if UCHAR_MAX == 255
typedef unsigned char uint8;
typedef signed char int8;
#else
#error "Char is not an 8-bit type"
#endif

#if SHRT_MAX == 32767
typedef unsigned short uint16;
typedef signed short int16;
#else
#error "Short is not a 16-bit type"
#endif

#if INT_MAX == 2147483647

typedef unsigned int uint32;
typedef signed int int32;

#else
#  if LONG_MAX == 2147483647

typedef unsigned long uint32;
typedef signed long int32;

#  else
#  error "Neither int nor long is a 32-bit type"
#  endif
#endif

typedef uint32 reg_t;

struct simops 
{
  long opcode;
  long mask;
  void (*func)();
  int length;
  int format;
  int numops;
  int operands[16];
};

/* The current state of the processor; registers, memory, etc.  */

struct _state
{
  reg_t regs[32];		/* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
				   lir, lar, mdrq, plus some room for processor
				   specific regs.  */
  uint8 *mem;			/* main memory */
  int exception;
  int exited;

  /* All internal state modified by signal_exception() that may need to be
     rolled back for passing moment-of-exception image back to gdb. */
  reg_t exc_trigger_regs[32];
  reg_t exc_suspend_regs[32];
  int exc_suspended;

#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
};

extern struct _state State;
extern uint32 OP[4];
extern struct simops Simops[];

#define PC	(State.regs[REG_PC])
#define SP	(State.regs[REG_SP])

#define PSW (State.regs[11])
#define PSW_Z 0x1
#define PSW_N 0x2
#define PSW_C 0x4
#define PSW_V 0x8
#define PSW_IE LSBIT (11)
#define PSW_LM LSMASK (10, 8)

#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)

#define REG_D0 0
#define REG_A0 4
#define REG_SP 8
#define REG_PC 9
#define REG_MDR 10
#define REG_PSW 11
#define REG_LIR 12
#define REG_LAR 13
#define REG_MDRQ 14
#define REG_E0 15
#define REG_SSP 23
#define REG_MSP 24
#define REG_USP 25
#define REG_MCRH 26
#define REG_MCRL 27
#define REG_MCVF 28

#if WITH_COMMON
/* These definitions conflict with similar macros in common.  */
#else
#define SEXT3(x)	((((x)&0x7)^(~0x3))+0x4)	

/* sign-extend a 4-bit number */
#define SEXT4(x)	((((x)&0xf)^(~0x7))+0x8)	

/* sign-extend a 5-bit number */
#define SEXT5(x)	((((x)&0x1f)^(~0xf))+0x10)	

/* sign-extend an 8-bit number */
#define SEXT8(x)	((((x)&0xff)^(~0x7f))+0x80)

/* sign-extend a 9-bit number */
#define SEXT9(x)	((((x)&0x1ff)^(~0xff))+0x100)

/* sign-extend a 16-bit number */
#define SEXT16(x)	((((x)&0xffff)^(~0x7fff))+0x8000)

/* sign-extend a 22-bit number */
#define SEXT22(x)	((((x)&0x3fffff)^(~0x1fffff))+0x200000)

#define MAX32	0x7fffffffLL
#define MIN32	0xff80000000LL
#define MASK32	0xffffffffLL
#define MASK40	0xffffffffffLL
#endif  /* not WITH_COMMON */

#ifdef _WIN32
#define SIGTRAP 5
#define SIGQUIT 3
#endif

#if WITH_COMMON

#define FETCH32(a,b,c,d) \
 ((a)+((b)<<8)+((c)<<16)+((d)<<24))

#define FETCH24(a,b,c) \
 ((a)+((b)<<8)+((c)<<16))

#define FETCH16(a,b) ((a)+((b)<<8))

#define load_byte(ADDR) \
sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))

#define load_half(ADDR) \
sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))

#define load_word(ADDR) \
sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))

#define store_byte(ADDR, DATA) \
sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
			    PC, write_map, (ADDR), (DATA))


#define store_half(ADDR, DATA) \
sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
			    PC, write_map, (ADDR), (DATA))


#define store_word(ADDR, DATA) \
sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
			    PC, write_map, (ADDR), (DATA))
#endif  /* WITH_COMMON */

#if WITH_COMMON
#else
#define load_mem_big(addr,len) \
  (len == 1 ? *((addr) + State.mem) : \
   len == 2 ? ((*((addr) + State.mem) << 8) \
	       | *(((addr) + 1) + State.mem)) : \
   len == 3 ? ((*((addr) + State.mem) << 16) \
	       | (*(((addr) + 1) + State.mem) << 8) \
	       | *(((addr) + 2) + State.mem)) : \
	      ((*((addr) + State.mem) << 24) \
	       | (*(((addr) + 1) + State.mem) << 16) \
	       | (*(((addr) + 2) + State.mem) << 8) \
	       | *(((addr) + 3) + State.mem)))

static INLINE uint32
load_byte (addr)
     SIM_ADDR addr;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  return p[0];
}

static INLINE uint32
load_half (addr)
     SIM_ADDR addr;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  return p[1] << 8 | p[0];
}

static INLINE uint32
load_3_byte (addr)
     SIM_ADDR addr;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  return p[2] << 16 | p[1] << 8 | p[0];
}

static INLINE uint32
load_word (addr)
     SIM_ADDR addr;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
}

static INLINE uint32
load_mem (addr, len)
     SIM_ADDR addr;
     int len;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  switch (len)
    {
    case 1:
      return p[0];
    case 2:
      return p[1] << 8 | p[0];
    case 3:
      return p[2] << 16 | p[1] << 8 | p[0];
    case 4:
      return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
    default:
      abort ();
    }
}

static INLINE void
store_byte (addr, data)
     SIM_ADDR addr;
     uint32 data;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  p[0] = data;
}

static INLINE void
store_half (addr, data)
     SIM_ADDR addr;
     uint32 data;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  p[0] = data;
  p[1] = data >> 8;
}

static INLINE void
store_3_byte (addr, data)
     SIM_ADDR addr;
     uint32 data;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  p[0] = data;
  p[1] = data >> 8;
  p[2] = data >> 16;
}

static INLINE void
store_word (addr, data)
     SIM_ADDR addr;
     uint32 data;
{
  uint8 *p = (addr & 0xffffff) + State.mem;

#ifdef CHECK_ADDR
  if ((addr & 0xffffff) > max_mem)
    abort ();
#endif

  p[0] = data;
  p[1] = data >> 8;
  p[2] = data >> 16;
  p[3] = data >> 24;
}
#endif  /* not WITH_COMMON */

/* Function declarations.  */

uint32 get_word PARAMS ((uint8 *));
uint16 get_half PARAMS ((uint8 *));
uint8 get_byte PARAMS ((uint8 *));
void put_word PARAMS ((uint8 *, uint32));
void put_half PARAMS ((uint8 *, uint16));
void put_byte PARAMS ((uint8 *, uint8));

extern uint8 *map PARAMS ((SIM_ADDR addr));

INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned long source, unsigned long destReg));
INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned long source, unsigned long destReg));
INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned long source, unsigned long destReg));
INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned long source, unsigned long destReg));
INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb,
						struct cb_syscall *sc,
						unsigned long taddr,
						char *buf,
						int bytes)); 
INLINE_SIM_MAIN (int) syscall_write_mem PARAMS ((host_callback *cb,
						struct cb_syscall *sc,
						unsigned long taddr,
						const char *buf,
						int bytes)); 
INLINE_SIM_MAIN (void) do_syscall PARAMS ((void));
void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);

void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
Commit	Line	Data
c906108c SS	1	#include <stdio.h>
	2	#include <ctype.h>
	3	#include "ansidecl.h"
	4	#include "callback.h"
	5	#include "opcode/mn10300.h"
	6	#include <limits.h>
	7	#include "remote-sim.h"
	8	#include "bfd.h"
	9
	10	#ifndef INLINE
	11	#ifdef __GNUC__
	12	#define INLINE inline
	13	#else
	14	#define INLINE
	15	#endif
	16	#endif
	17
	18	extern host_callback *mn10300_callback;
	19	extern SIM_DESC simulator;
	20
	21	#define DEBUG_TRACE 0x00000001
	22	#define DEBUG_VALUES 0x00000002
	23
	24	extern int mn10300_debug;
	25
	26	#if UCHAR_MAX == 255
	27	typedef unsigned char uint8;
	28	typedef signed char int8;
	29	#else
	30	#error "Char is not an 8-bit type"
	31	#endif
	32
	33	#if SHRT_MAX == 32767
	34	typedef unsigned short uint16;
	35	typedef signed short int16;
	36	#else
	37	#error "Short is not a 16-bit type"
	38	#endif
	39
	40	#if INT_MAX == 2147483647
	41
	42	typedef unsigned int uint32;
	43	typedef signed int int32;
	44
	45	#else
	46	# if LONG_MAX == 2147483647
	47
	48	typedef unsigned long uint32;
	49	typedef signed long int32;
	50
	51	# else
	52	# error "Neither int nor long is a 32-bit type"
	53	# endif
	54	#endif
	55
	56	typedef uint32 reg_t;
	57
	58	struct simops
	59	{
	60	long opcode;
	61	long mask;
	62	void (*func)();
	63	int length;
	64	int format;
65	int numops;
66	int operands[16];
67	};
68
69	/* The current state of the processor; registers, memory, etc. */
70
71	struct _state
72	{
73	reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
74	lir, lar, mdrq, plus some room for processor
75	specific regs. */
76	uint8 mem; / main memory */
77	int exception;
78	int exited;
79
80	/* All internal state modified by signal_exception() that may need to be
81	rolled back for passing moment-of-exception image back to gdb. */
82	reg_t exc_trigger_regs[32];
83	reg_t exc_suspend_regs[32];
84	int exc_suspended;
85
86	#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
87	#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
88	#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
89	};
90
91	extern struct _state State;
92	extern uint32 OP[4];
93	extern struct simops Simops[];
94
95	#define PC (State.regs[REG_PC])
96	#define SP (State.regs[REG_SP])
97
98	#define PSW (State.regs[11])
99	#define PSW_Z 0x1
100	#define PSW_N 0x2
101	#define PSW_C 0x4
102	#define PSW_V 0x8
103	#define PSW_IE LSBIT (11)
104	#define PSW_LM LSMASK (10, 8)
105
106	#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
107	#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
108
109	#define REG_D0 0
110	#define REG_A0 4
111	#define REG_SP 8
112	#define REG_PC 9
113	#define REG_MDR 10
114	#define REG_PSW 11
115	#define REG_LIR 12
116	#define REG_LAR 13
117	#define REG_MDRQ 14
c2d11a7d JM	118	#define REG_E0 15
	119	#define REG_SSP 23
	120	#define REG_MSP 24
	121	#define REG_USP 25
	122	#define REG_MCRH 26
	123	#define REG_MCRL 27
	124	#define REG_MCVF 28
c906108c SS	125
	126	#if WITH_COMMON
	127	/* These definitions conflict with similar macros in common. */
	128	#else
	129	#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
	130
	131	/* sign-extend a 4-bit number */
	132	#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
	133
	134	/* sign-extend a 5-bit number */
	135	#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
	136
	137	/* sign-extend an 8-bit number */
	138	#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
	139
	140	/* sign-extend a 9-bit number */
	141	#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
	142
	143	/* sign-extend a 16-bit number */
	144	#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
	145
	146	/* sign-extend a 22-bit number */
	147	#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
	148
	149	#define MAX32 0x7fffffffLL
	150	#define MIN32 0xff80000000LL
	151	#define MASK32 0xffffffffLL
	152	#define MASK40 0xffffffffffLL
	153	#endif /* not WITH_COMMON */
	154
	155	#ifdef _WIN32
	156	#define SIGTRAP 5
	157	#define SIGQUIT 3
	158	#endif
	159
	160	#if WITH_COMMON
	161
	162	#define FETCH32(a,b,c,d) \
	163	((a)+((b)<<8)+((c)<<16)+((d)<<24))
	164
	165	#define FETCH24(a,b,c) \
	166	((a)+((b)<<8)+((c)<<16))
	167
	168	#define FETCH16(a,b) ((a)+((b)<<8))
	169
	170	#define load_byte(ADDR) \
	171	sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
	172
	173	#define load_half(ADDR) \
	174	sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
	175
	176	#define load_word(ADDR) \
	177	sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
	178
	179	#define store_byte(ADDR, DATA) \
	180	sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
	181	PC, write_map, (ADDR), (DATA))
	182
	183
	184	#define store_half(ADDR, DATA) \
	185	sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
	186	PC, write_map, (ADDR), (DATA))
	187
	188
189	#define store_word(ADDR, DATA) \
190	sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
191	PC, write_map, (ADDR), (DATA))
192	#endif /* WITH_COMMON */
193
194	#if WITH_COMMON
195	#else
196	#define load_mem_big(addr,len) \
197	(len == 1 ? *((addr) + State.mem) : \
198	len == 2 ? ((*((addr) + State.mem) << 8) \
199	\| *(((addr) + 1) + State.mem)) : \
200	len == 3 ? ((*((addr) + State.mem) << 16) \
201	\| (*(((addr) + 1) + State.mem) << 8) \
202	\| *(((addr) + 2) + State.mem)) : \
203	((*((addr) + State.mem) << 24) \
204	\| (*(((addr) + 1) + State.mem) << 16) \
205	\| (*(((addr) + 2) + State.mem) << 8) \
206	\| *(((addr) + 3) + State.mem)))
207
208	static INLINE uint32
209	load_byte (addr)
210	SIM_ADDR addr;
211	{
212	uint8 *p = (addr & 0xffffff) + State.mem;
213
214	#ifdef CHECK_ADDR
215	if ((addr & 0xffffff) > max_mem)
216	abort ();
217	#endif
218
219	return p[0];
220	}
221
222	static INLINE uint32
223	load_half (addr)
224	SIM_ADDR addr;
225	{
226	uint8 *p = (addr & 0xffffff) + State.mem;
227
228	#ifdef CHECK_ADDR
229	if ((addr & 0xffffff) > max_mem)
230	abort ();
231	#endif
232
233	return p[1] << 8 \| p[0];
234	}
235
236	static INLINE uint32
237	load_3_byte (addr)
238	SIM_ADDR addr;
239	{
240	uint8 *p = (addr & 0xffffff) + State.mem;
241
242	#ifdef CHECK_ADDR
243	if ((addr & 0xffffff) > max_mem)
244	abort ();
245	#endif
246
247	return p[2] << 16 \| p[1] << 8 \| p[0];
248	}
249
250	static INLINE uint32
251	load_word (addr)
252	SIM_ADDR addr;
253	{
254	uint8 *p = (addr & 0xffffff) + State.mem;
255
256	#ifdef CHECK_ADDR
257	if ((addr & 0xffffff) > max_mem)
258	abort ();
259	#endif
260
261	return p[3] << 24 \| p[2] << 16 \| p[1] << 8 \| p[0];
262	}
263
264	static INLINE uint32
265	load_mem (addr, len)
266	SIM_ADDR addr;
267	int len;
268	{
269	uint8 *p = (addr & 0xffffff) + State.mem;
270
271	#ifdef CHECK_ADDR
272	if ((addr & 0xffffff) > max_mem)
273	abort ();
274	#endif
275
276	switch (len)
277	{
278	case 1:
279	return p[0];
280	case 2:
281	return p[1] << 8 \| p[0];
282	case 3:
283	return p[2] << 16 \| p[1] << 8 \| p[0];
284	case 4:
285	return p[3] << 24 \| p[2] << 16 \| p[1] << 8 \| p[0];
286	default:
287	abort ();
288	}
289	}
290
291	static INLINE void
292	store_byte (addr, data)
293	SIM_ADDR addr;
294	uint32 data;
295	{
296	uint8 *p = (addr & 0xffffff) + State.mem;
297
298	#ifdef CHECK_ADDR
299	if ((addr & 0xffffff) > max_mem)
300	abort ();
301	#endif
302
303	p[0] = data;
304	}
305
306	static INLINE void
307	store_half (addr, data)
308	SIM_ADDR addr;
309	uint32 data;
310	{
311	uint8 *p = (addr & 0xffffff) + State.mem;
312
313	#ifdef CHECK_ADDR
314	if ((addr & 0xffffff) > max_mem)
315	abort ();
316	#endif
317
318	p[0] = data;
319	p[1] = data >> 8;
320	}
321
322	static INLINE void
323	store_3_byte (addr, data)
324	SIM_ADDR addr;
325	uint32 data;
326	{
327	uint8 *p = (addr & 0xffffff) + State.mem;
328
329	#ifdef CHECK_ADDR
330	if ((addr & 0xffffff) > max_mem)
331	abort ();
332	#endif
333
334	p[0] = data;
335	p[1] = data >> 8;
336	p[2] = data >> 16;
337	}
338
339	static INLINE void
340	store_word (addr, data)
341	SIM_ADDR addr;
342	uint32 data;
343	{
344	uint8 *p = (addr & 0xffffff) + State.mem;
345
346	#ifdef CHECK_ADDR
347	if ((addr & 0xffffff) > max_mem)
348	abort ();
349	#endif
350
351	p[0] = data;
352	p[1] = data >> 8;
353	p[2] = data >> 16;
354	p[3] = data >> 24;
355	}
356	#endif /* not WITH_COMMON */
357
358	/* Function declarations. */
359
360	uint32 get_word PARAMS ((uint8 *));
361	uint16 get_half PARAMS ((uint8 *));
362	uint8 get_byte PARAMS ((uint8 *));
363	void put_word PARAMS ((uint8 *, uint32));
364	void put_half PARAMS ((uint8 *, uint16));
365	void put_byte PARAMS ((uint8 *, uint8));
366
367	extern uint8 *map PARAMS ((SIM_ADDR addr));
368
369	INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned long source, unsigned long destReg));
370	INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned long source, unsigned long destReg));
371	INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
372	INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned long source, unsigned long destReg));
373	INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned long source, unsigned long destReg));
374	INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned long leftOpnd, unsigned long rightOpnd));
375	INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb,
376	struct cb_syscall *sc,
377	unsigned long taddr,
378	char *buf,
379	int bytes));
380	INLINE_SIM_MAIN (int) syscall_write_mem PARAMS ((host_callback *cb,
381	struct cb_syscall *sc,
382	unsigned long taddr,
383	const char *buf,
384	int bytes));
385	INLINE_SIM_MAIN (void) do_syscall PARAMS ((void));
386	void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
387
388	void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
389	void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
390	void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);