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* sim-endian.h: Move host {LITTLE,BIG}_ENDIAN support from here,
[binutils.git] / sim / d10v / simops.c
CommitLineData
fd435e9f
MM		 1#include "config.h"
2
4f425a32 3#include <signal.h>
63a91cfb
MM		 4#include <errno.h>
5#include <sys/types.h>
6#include <sys/stat.h>
fd435e9f 7#ifdef HAVE_UNISTD_H
63a91cfb 8#include <unistd.h>
fd435e9f 9#endif
63a91cfb 10
2934d1c9
MH		 11#include "d10v_sim.h"
12#include "simops.h"
8719be26 13#include "sys/syscall.h"
2934d1c9 14
c422ecc7
MH		 15extern char *strrchr ();
16
87178dbd
MM		 17enum op_types {
18 OP_VOID,
19 OP_REG,
20 OP_REG_OUTPUT,
21 OP_DREG,
22 OP_DREG_OUTPUT,
23 OP_ACCUM,
24 OP_ACCUM_OUTPUT,
25 OP_ACCUM_REVERSE,
26 OP_CR,
27 OP_CR_OUTPUT,
28 OP_CR_REVERSE,
29 OP_FLAG,
60fc5b72 30 OP_FLAG_OUTPUT,
87178dbd 31 OP_CONSTANT16,
a18cb100 32 OP_CONSTANT8,
87178dbd
MM		 33 OP_CONSTANT3,
34 OP_CONSTANT4,
35 OP_MEMREF,
36 OP_MEMREF2,
37 OP_POSTDEC,
38 OP_POSTINC,
a18cb100
MM		 39 OP_PREDEC,
40 OP_R2,
8918b3a7
MM		 41 OP_R3,
42 OP_R4,
43 OP_R2R3
87178dbd
MM		 44};
45
7eebfc62 46#ifdef DEBUG
a49a15ad
MM		 47static void trace_input_func PARAMS ((char *name,
48 enum op_types in1,
49 enum op_types in2,
50 enum op_types in3));
87178dbd 51
a49a15ad
MM		 52#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
53
54static void trace_output_func PARAMS ((enum op_types result));
55
56#define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
57
87178dbd 58#ifndef SIZE_INSTRUCTION
a49a15ad 59#define SIZE_INSTRUCTION 8
87178dbd
MM		 60#endif
61
62#ifndef SIZE_OPERANDS
a49a15ad 63#define SIZE_OPERANDS 18
87178dbd
MM		 64#endif
65
66#ifndef SIZE_VALUES
67#define SIZE_VALUES 13
68#endif
69
a49a15ad
MM		 70#ifndef SIZE_LOCATION
71#define SIZE_LOCATION 20
72#endif
73
891513ee
MM		 74#ifndef SIZE_PC
75#define SIZE_PC 6
76#endif
77
78#ifndef SIZE_LINE_NUMBER
79#define SIZE_LINE_NUMBER 4
80#endif
81
87178dbd 82static void
a49a15ad 83trace_input_func (name, in1, in2, in3)
87178dbd
MM		 84 char *name;
85 enum op_types in1;
86 enum op_types in2;
87 enum op_types in3;
88{
89 char *comma;
90 enum op_types in[3];
91 int i;
a49a15ad 92 char buf[1024];
87178dbd
MM		 93 char *p;
94 long tmp;
95 char *type;
a49a15ad
MM		 96 const char *filename;
97 const char *functionname;
98 unsigned int linenumber;
99 bfd_vma byte_pc;
87178dbd 100
7eebfc62
MM		 101 if ((d10v_debug & DEBUG_TRACE) == 0)
102 return;
103
87178dbd
MM		 104 switch (State.ins_type)
105 {
106 default:
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
c422ecc7
MH		 112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
87178dbd
MM		 116 case INS_LONG: type = " B"; break;
117 }
118
a49a15ad
MM		 119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 121 "0x%.*x %s: %-*s ",
891513ee
MM		 122 SIZE_PC, (unsigned)PC,
123 type,
a49a15ad
MM		 124 SIZE_INSTRUCTION, name);
125
126 else
127 {
891513ee 128 buf[0] = '\0';
b30cdd35 129 byte_pc = decode_pc ();
a49a15ad
MM		 130 if (text && byte_pc >= text_start && byte_pc < text_end)
131 {
132 filename = (const char *)0;
133 functionname = (const char *)0;
134 linenumber = 0;
0535fa1a 135 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
a49a15ad
MM		 136 &filename, &functionname, &linenumber))
137 {
138 p = buf;
139 if (linenumber)
140 {
891513ee 141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
a49a15ad
MM		 142 p += strlen (p);
143 }
891513ee
MM		 144 else
145 {
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
148 }
a49a15ad
MM		 149
150 if (functionname)
151 {
152 sprintf (p, "%s ", functionname);
153 p += strlen (p);
154 }
155 else if (filename)
156 {
c422ecc7 157 char *q = strrchr (filename, '/');
a49a15ad
MM		 158 sprintf (p, "%s ", (q) ? q+1 : filename);
159 p += strlen (p);
160 }
161
162 if (*p == ' ')
163 *p = '\0';
164 }
165 }
166
167 (*d10v_callback->printf_filtered) (d10v_callback,
f061ddf6 168 "0x%.*x %s: %-*.*s %-*s ",
891513ee
MM		 169 SIZE_PC, (unsigned)PC,
170 type,
a49a15ad
MM		 171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
173 }
87178dbd
MM		 174
175 in[0] = in1;
176 in[1] = in2;
177 in[2] = in3;
178 comma = "";
179 p = buf;
180 for (i = 0; i < 3; i++)
181 {
182 switch (in[i])
183 {
184 case OP_VOID:
a18cb100
MM		 185 case OP_R2:
186 case OP_R3:
8918b3a7 187 case OP_R4:
c422ecc7 188 case OP_R2R3:
87178dbd
MM		 189 break;
190
191 case OP_REG:
192 case OP_REG_OUTPUT:
193 case OP_DREG:
194 case OP_DREG_OUTPUT:
195 sprintf (p, "%sr%d", comma, OP[i]);
196 p += strlen (p);
197 comma = ",";
198 break;
199
200 case OP_CR:
201 case OP_CR_OUTPUT:
202 case OP_CR_REVERSE:
203 sprintf (p, "%scr%d", comma, OP[i]);
204 p += strlen (p);
205 comma = ",";
206 break;
207
208 case OP_ACCUM:
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
212 p += strlen (p);
213 comma = ",";
214 break;
215
216 case OP_CONSTANT16:
217 sprintf (p, "%s%d", comma, OP[i]);
218 p += strlen (p);
219 comma = ",";
220 break;
221
a18cb100
MM		 222 case OP_CONSTANT8:
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
224 p += strlen (p);
225 comma = ",";
226 break;
227
87178dbd
MM		 228 case OP_CONSTANT4:
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
230 p += strlen (p);
231 comma = ",";
232 break;
233
234 case OP_CONSTANT3:
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
236 p += strlen (p);
237 comma = ",";
238 break;
239
240 case OP_MEMREF:
241 sprintf (p, "%s@r%d", comma, OP[i]);
242 p += strlen (p);
243 comma = ",";
244 break;
245
246 case OP_MEMREF2:
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
248 p += strlen (p);
249 comma = ",";
250 break;
251
252 case OP_POSTINC:
253 sprintf (p, "%s@r%d+", comma, OP[i]);
254 p += strlen (p);
255 comma = ",";
256 break;
257
258 case OP_POSTDEC:
259 sprintf (p, "%s@r%d-", comma, OP[i]);
260 p += strlen (p);
261 comma = ",";
262 break;
263
264 case OP_PREDEC:
265 sprintf (p, "%s@-r%d", comma, OP[i]);
266 p += strlen (p);
267 comma = ",";
268 break;
269
270 case OP_FLAG:
60fc5b72 271 case OP_FLAG_OUTPUT:
87178dbd
MM		 272 if (OP[i] == 0)
273 sprintf (p, "%sf0", comma);
274
275 else if (OP[i] == 1)
276 sprintf (p, "%sf1", comma);
277
278 else
60fc5b72 279 sprintf (p, "%sc", comma);
87178dbd
MM		 280
281 p += strlen (p);
282 comma = ",";
283 break;
284 }
285 }
286
7eebfc62
MM		 287 if ((d10v_debug & DEBUG_VALUES) == 0)
288 {
289 *p++ = '\n';
290 *p = '\0';
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
292 }
293 else
294 {
295 *p = '\0';
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
87178dbd 297
7eebfc62
MM		 298 p = buf;
299 for (i = 0; i < 3; i++)
300 {
301 buf[0] = '\0';
302 switch (in[i])
303 {
304 case OP_VOID:
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
306 break;
307
308 case OP_REG_OUTPUT:
309 case OP_DREG_OUTPUT:
310 case OP_CR_OUTPUT:
311 case OP_ACCUM_OUTPUT:
60fc5b72 312 case OP_FLAG_OUTPUT:
7eebfc62
MM		 313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
314 break;
315
316 case OP_REG:
317 case OP_MEMREF:
318 case OP_POSTDEC:
319 case OP_POSTINC:
320 case OP_PREDEC:
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
323 break;
324
325 case OP_DREG:
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
328 break;
329
330 case OP_CR:
331 case OP_CR_REVERSE:
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
334 break;
335
336 case OP_ACCUM:
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
341 break;
342
343 case OP_CONSTANT16:
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
345 (uint16)OP[i]);
346 break;
347
348 case OP_CONSTANT4:
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
351 break;
352
a18cb100
MM		 353 case OP_CONSTANT8:
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
356 break;
357
7eebfc62
MM		 358 case OP_CONSTANT3:
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
361 break;
362
363 case OP_FLAG:
364 if (OP[i] == 0)
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
366 State.F0 != 0);
367
368 else if (OP[i] == 1)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
370 State.F1 != 0);
371
372 else
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
374 State.C != 0);
375
376 break;
377
378 case OP_MEMREF2:
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16)OP[i]);
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
383 break;
a18cb100
MM		 384
385 case OP_R2:
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
388 break;
389
390 case OP_R3:
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
393 break;
8918b3a7
MM		 394
395 case OP_R4:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
398 break;
c422ecc7
MH		 399
400 case OP_R2R3:
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
405 i++;
406 break;
7eebfc62
MM		 407 }
408 }
409 }
fd435e9f
MM		 410
411 (*d10v_callback->flush_stdout) (d10v_callback);
7eebfc62 412}
87178dbd 413
7eebfc62 414static void
a49a15ad 415trace_output_func (result)
7eebfc62
MM		 416 enum op_types result;
417{
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
87178dbd 419 {
7eebfc62 420 long tmp;
87178dbd 421
7eebfc62
MM		 422 switch (result)
423 {
424 default:
425 putchar ('\n');
87178dbd
MM		 426 break;
427
428 case OP_REG:
7eebfc62
MM		 429 case OP_REG_OUTPUT:
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 433 break;
434
435 case OP_DREG:
7eebfc62
MM		 436 case OP_DREG_OUTPUT:
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 440 break;
441
442 case OP_CR:
7eebfc62
MM		 443 case OP_CR_OUTPUT:
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 447 break;
448
7eebfc62
MM		 449 case OP_CR_REVERSE:
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 453 break;
454
7eebfc62
MM		 455 case OP_ACCUM:
456 case OP_ACCUM_OUTPUT:
069398aa 457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 461 break;
462
7eebfc62 463 case OP_ACCUM_REVERSE:
069398aa 464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
7eebfc62
MM		 465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd
MM		 468 break;
469
470 case OP_FLAG:
60fc5b72 471 case OP_FLAG_OUTPUT:
7eebfc62
MM		 472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
87178dbd 474 break;
8918b3a7
MM		 475
476 case OP_R2:
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
480 break;
481
482 case OP_R2R3:
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
486 break;
87178dbd
MM		 487 }
488 }
fd435e9f
MM		 489
490 (*d10v_callback->flush_stdout) (d10v_callback);
87178dbd
MM		 491}
492
493#else
494#define trace_input(NAME, IN1, IN2, IN3)
495#define trace_output(RESULT)
496#endif
2934d1c9
MH		 497
498/* abs */
499void
500OP_4607 ()
501{
87178dbd 502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
2934d1c9
MH		 503 State.F1 = State.F0;
504 if ((int16)(State.regs[OP[0]]) < 0)
505 {
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
507 State.F0 = 1;
508 }
509 else
510 State.F0 = 0;
87178dbd 511 trace_output (OP_REG);
2934d1c9
MH		 512}
513
514/* abs */
515void
516OP_5607 ()
517{
518 int64 tmp;
519
87178dbd 520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32
MH		 521 State.F1 = State.F0;
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
523
4c38885c 524 if (State.a[OP[0]] < 0 )
2934d1c9 525 {
4c38885c 526 tmp = -State.a[OP[0]];
2934d1c9
MH		 527 if (State.ST)
528 {
4c38885c 529 if (tmp > MAX32)
2934d1c9 530 State.a[OP[0]] = MAX32;
4c38885c 531 else if (tmp < MIN32)
2934d1c9
MH		 532 State.a[OP[0]] = MIN32;
533 else
4f425a32 534 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 535 }
536 else
4f425a32 537 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 538 State.F0 = 1;
539 }
540 else
541 State.F0 = 0;
87178dbd 542 trace_output (OP_ACCUM);
2934d1c9
MH		 543}
544
545/* add */
546void
547OP_200 ()
548{
549 uint16 tmp = State.regs[OP[0]];
87178dbd 550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
553 State.C = 1;
554 else
555 State.C = 0;
87178dbd 556 trace_output (OP_REG);
2934d1c9
MH		 557}
558
559/* add */
560void
561OP_1201 ()
562{
4c38885c 563 int64 tmp;
4f425a32 564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
87178dbd
MM		 565
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
4c38885c
MH		 567 if (State.ST)
568 {
569 if ( tmp > MAX32)
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
573 else
4f425a32 574 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 575 }
576 else
4f425a32 577 State.a[OP[0]] = tmp & MASK40;
87178dbd 578 trace_output (OP_ACCUM);
2934d1c9
MH		 579}
580
581/* add */
582void
583OP_1203 ()
584{
4c38885c 585 int64 tmp;
4f425a32 586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
87178dbd
MM		 587
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c
MH		 589 if (State.ST)
590 {
591 if (tmp > MAX32)
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
595 else
4f425a32 596 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 597 }
598 else
4f425a32 599 State.a[OP[0]] = tmp & MASK40;
87178dbd 600 trace_output (OP_ACCUM);
2934d1c9
MH		 601}
602
603/* add2w */
604void
605OP_1200 ()
606{
607 uint32 tmp;
f4b022d3
MM		 608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
87178dbd
MM		 610
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 612 tmp = a + b;
613 State.C = (tmp < a);
2934d1c9
MH		 614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
87178dbd 616 trace_output (OP_DREG);
2934d1c9
MH		 617}
618
619/* add3 */
620void
621OP_1000000 ()
622{
f4b022d3
MM		 623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
87178dbd
MM		 625
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
f4b022d3 627 State.C = (State.regs[OP[0]] < tmp);
87178dbd 628 trace_output (OP_REG);
2934d1c9
MH		 629}
630
631/* addac3 */
632void
633OP_17000200 ()
634{
4c38885c 635 int64 tmp;
4f425a32 636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
87178dbd
MM		 637
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4c38885c
MH		 639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 641 trace_output (OP_DREG);
2934d1c9
MH		 642}
643
644/* addac3 */
645void
646OP_17000202 ()
647{
4c38885c 648 int64 tmp;
4f425a32 649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
87178dbd
MM		 650
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4c38885c
MH		 652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 654 trace_output (OP_DREG);
2934d1c9
MH		 655}
656
657/* addac3s */
658void
659OP_17001200 ()
660{
4c38885c 661 int64 tmp;
4c38885c 662 State.F1 = State.F0;
87178dbd
MM		 663
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32 665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
4c38885c
MH		 666 if ( tmp > MAX32)
667 {
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
670 State.F0 = 1;
671 }
672 else if (tmp < MIN32)
673 {
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
676 State.F0 = 1;
677 }
678 else
679 {
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
682 State.F0 = 0;
683 }
87178dbd 684 trace_output (OP_DREG);
2934d1c9
MH		 685}
686
687/* addac3s */
688void
689OP_17001202 ()
690{
4c38885c 691 int64 tmp;
4c38885c 692 State.F1 = State.F0;
87178dbd
MM		 693
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32 695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
4c38885c
MH		 696 if ( tmp > MAX32)
697 {
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
700 State.F0 = 1;
701 }
702 else if (tmp < MIN32)
703 {
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
706 State.F0 = 1;
707 }
708 else
709 {
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
712 State.F0 = 0;
713 }
87178dbd 714 trace_output (OP_DREG);
2934d1c9
MH		 715}
716
717/* addi */
718void
719OP_201 ()
720{
2254cd90 721 uint tmp = State.regs[OP[0]];
4f425a32
MH		 722 if (OP[1] == 0)
723 OP[1] = 16;
f4b022d3 724
87178dbd 725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 726 State.regs[OP[0]] += OP[1];
f4b022d3 727 State.C = (State.regs[OP[0]] < tmp);
87178dbd 728 trace_output (OP_REG);
2934d1c9
MH		 729}
730
731/* and */
732void
733OP_C00 ()
734{
87178dbd 735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
2934d1c9 736 State.regs[OP[0]] &= State.regs[OP[1]];
87178dbd 737 trace_output (OP_REG);
2934d1c9
MH		 738}
739
740/* and3 */
741void
742OP_6000000 ()
743{
87178dbd 744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
87178dbd 746 trace_output (OP_REG);
2934d1c9
MH		 747}
748
749/* bclri */
750void
751OP_C01 ()
752{
87178dbd 753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
87178dbd 755 trace_output (OP_REG);
2934d1c9
MH		 756}
757
758/* bl.s */
759void
760OP_4900 ()
761{
a18cb100 762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
2934d1c9 763 State.regs[13] = PC+1;
fd435e9f 764 JMP( PC + SEXT8 (OP[0]));
87178dbd 765 trace_output (OP_VOID);
2934d1c9
MH		 766}
767
768/* bl.l */
769void
770OP_24800000 ()
771{
a18cb100 772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
2934d1c9 773 State.regs[13] = PC+1;
fd435e9f 774 JMP (PC + OP[0]);
87178dbd 775 trace_output (OP_VOID);
2934d1c9
MH		 776}
777
778/* bnoti */
779void
780OP_A01 ()
781{
87178dbd 782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
87178dbd 784 trace_output (OP_REG);
2934d1c9
MH		 785}
786
787/* bra.s */
788void
789OP_4800 ()
790{
a18cb100 791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
fd435e9f 792 JMP (PC + SEXT8 (OP[0]));
87178dbd 793 trace_output (OP_VOID);
2934d1c9
MH		 794}
795
796/* bra.l */
797void
798OP_24000000 ()
799{
87178dbd 800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
fd435e9f 801 JMP (PC + OP[0]);
87178dbd 802 trace_output (OP_VOID);
2934d1c9
MH		 803}
804
805/* brf0f.s */
806void
807OP_4A00 ()
808{
a18cb100 809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 810 if (State.F0 == 0)
fd435e9f 811 JMP (PC + SEXT8 (OP[0]));
87178dbd 812 trace_output (OP_FLAG);
2934d1c9
MH		 813}
814
815/* brf0f.l */
816void
817OP_25000000 ()
818{
87178dbd 819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 820 if (State.F0 == 0)
fd435e9f 821 JMP (PC + OP[0]);
87178dbd 822 trace_output (OP_FLAG);
2934d1c9
MH		 823}
824
825/* brf0t.s */
826void
827OP_4B00 ()
828{
a18cb100 829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
2934d1c9 830 if (State.F0)
fd435e9f 831 JMP (PC + SEXT8 (OP[0]));
87178dbd 832 trace_output (OP_FLAG);
2934d1c9
MH		 833}
834
835/* brf0t.l */
836void
837OP_25800000 ()
838{
87178dbd 839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
2934d1c9 840 if (State.F0)
fd435e9f 841 JMP (PC + OP[0]);
87178dbd 842 trace_output (OP_FLAG);
2934d1c9
MH		 843}
844
845/* bseti */
846void
847OP_801 ()
848{
87178dbd 849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 850 State.regs[OP[0]] |= 0x8000 >> OP[1];
87178dbd 851 trace_output (OP_REG);
2934d1c9
MH		 852}
853
854/* btsti */
855void
856OP_E01 ()
857{
87178dbd 858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 859 State.F1 = State.F0;
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
87178dbd 861 trace_output (OP_FLAG);
2934d1c9
MH		 862}
863
864/* clrac */
865void
866OP_5601 ()
867{
87178dbd 868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
2934d1c9 869 State.a[OP[0]] = 0;
87178dbd 870 trace_output (OP_ACCUM);
2934d1c9
MH		 871}
872
873/* cmp */
874void
875OP_600 ()
876{
87178dbd 877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 878 State.F1 = State.F0;
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
87178dbd 880 trace_output (OP_FLAG);
2934d1c9
MH		 881}
882
883/* cmp */
884void
885OP_1603 ()
886{
87178dbd 887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 888 State.F1 = State.F0;
4f425a32 889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
87178dbd 890 trace_output (OP_FLAG);
2934d1c9
MH		 891}
892
893/* cmpeq */
894void
895OP_400 ()
896{
87178dbd 897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 898 State.F1 = State.F0;
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
87178dbd 900 trace_output (OP_FLAG);
2934d1c9
MH		 901}
902
903/* cmpeq */
904void
905OP_1403 ()
906{
87178dbd 907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
4c38885c 908 State.F1 = State.F0;
fd435e9f 909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
87178dbd 910 trace_output (OP_FLAG);
2934d1c9
MH		 911}
912
913/* cmpeqi.s */
914void
915OP_401 ()
916{
c12f5c67 917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 918 State.F1 = State.F0;
c12f5c67 919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
87178dbd 920 trace_output (OP_FLAG);
2934d1c9
MH		 921}
922
923/* cmpeqi.l */
924void
925OP_2000000 ()
926{
87178dbd 927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 928 State.F1 = State.F0;
c12f5c67 929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
87178dbd 930 trace_output (OP_FLAG);
2934d1c9
MH		 931}
932
933/* cmpi.s */
934void
935OP_601 ()
936{
87178dbd 937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
2934d1c9 938 State.F1 = State.F0;
c12f5c67 939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
87178dbd 940 trace_output (OP_FLAG);
2934d1c9
MH		 941}
942
943/* cmpi.l */
944void
945OP_3000000 ()
946{
87178dbd 947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 948 State.F1 = State.F0;
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
87178dbd 950 trace_output (OP_FLAG);
2934d1c9
MH		 951}
952
953/* cmpu */
954void
955OP_4600 ()
956{
87178dbd 957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
2934d1c9
MH		 958 State.F1 = State.F0;
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
87178dbd 960 trace_output (OP_FLAG);
2934d1c9
MH		 961}
962
963/* cmpui */
964void
965OP_23000000 ()
966{
87178dbd 967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 968 State.F1 = State.F0;
c12f5c67 969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
87178dbd 970 trace_output (OP_FLAG);
2934d1c9
MH		 971}
972
973/* cpfg */
974void
975OP_4E09 ()
976{
977 uint8 *src, *dst;
2934d1c9 978
60fc5b72 979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
2934d1c9
MH		 980 if (OP[0] == 0)
981 dst = &State.F0;
982 else
983 dst = &State.F1;
984
985 if (OP[1] == 0)
986 src = &State.F0;
987 else if (OP[1] == 1)
988 src = &State.F1;
989 else
990 src = &State.C;
991
992 *dst = *src;
87178dbd 993 trace_output (OP_FLAG);
2934d1c9
MH		 994}
995
996/* dbt */
997void
998OP_5F20 ()
999{
a49a15ad 1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
4f425a32 1001 State.exception = SIGTRAP;
2934d1c9
MH		 1002}
1003
1004/* divs */
1005void
1006OP_14002800 ()
1007{
1008 uint16 foo, tmp, tmpf;
87178dbd
MM		 1009
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
2934d1c9
MH		 1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
87178dbd 1016 trace_output (OP_DREG);
2934d1c9
MH		 1017}
1018
1019/* exef0f */
1020void
1021OP_4E04 ()
1022{
87178dbd 1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1024 State.exe = (State.F0 == 0);
87178dbd 1025 trace_output (OP_FLAG);
2934d1c9
MH		 1026}
1027
1028/* exef0t */
1029void
1030OP_4E24 ()
1031{
87178dbd 1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1033 State.exe = (State.F0 != 0);
87178dbd 1034 trace_output (OP_FLAG);
2934d1c9
MH		 1035}
1036
1037/* exef1f */
1038void
1039OP_4E40 ()
1040{
87178dbd 1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1042 State.exe = (State.F1 == 0);
87178dbd 1043 trace_output (OP_FLAG);
2934d1c9
MH		 1044}
1045
1046/* exef1t */
1047void
1048OP_4E42 ()
1049{
87178dbd 1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1051 State.exe = (State.F1 != 0);
87178dbd 1052 trace_output (OP_FLAG);
2934d1c9
MH		 1053}
1054
1055/* exefaf */
1056void
1057OP_4E00 ()
1058{
87178dbd 1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
87178dbd 1061 trace_output (OP_FLAG);
2934d1c9
MH		 1062}
1063
1064/* exefat */
1065void
1066OP_4E02 ()
1067{
87178dbd 1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
87178dbd 1070 trace_output (OP_FLAG);
2934d1c9
MH		 1071}
1072
1073/* exetaf */
1074void
1075OP_4E20 ()
1076{
87178dbd 1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
87178dbd 1079 trace_output (OP_FLAG);
2934d1c9
MH		 1080}
1081
1082/* exetat */
1083void
1084OP_4E22 ()
1085{
87178dbd 1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
293c76a3 1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
87178dbd 1088 trace_output (OP_FLAG);
2934d1c9
MH		 1089}
1090
1091/* exp */
1092void
1093OP_15002A00 ()
1094{
1095 uint32 tmp, foo;
1096 int i;
1097
87178dbd 1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
4c38885c
MH		 1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
2934d1c9 1101 else
4c38885c 1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2934d1c9
MH		 1103
1104 foo = 0x40000000;
4c38885c 1105 for (i=1;i<17;i++)
2934d1c9
MH		 1106 {
1107 if (tmp & foo)
1108 {
1109 State.regs[OP[0]] = i-1;
87178dbd 1110 trace_output (OP_REG);
2934d1c9
MH		 1111 return;
1112 }
4c38885c 1113 foo >>= 1;
2934d1c9
MH		 1114 }
1115 State.regs[OP[0]] = 16;
87178dbd 1116 trace_output (OP_REG);
2934d1c9
MH		 1117}
1118
1119/* exp */
1120void
1121OP_15002A02 ()
1122{
4c38885c
MH		 1123 int64 tmp, foo;
1124 int i;
87178dbd
MM		 1125
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
fd435e9f
MM		 1127 tmp = SEXT40(State.a[OP[1]]);
1128 if (tmp < 0)
1129 tmp = ~tmp & MASK40;
4c38885c
MH		 1130
1131 foo = 0x4000000000LL;
1132 for (i=1;i<25;i++)
1133 {
1134 if (tmp & foo)
1135 {
1136 State.regs[OP[0]] = i-9;
87178dbd 1137 trace_output (OP_REG);
4c38885c
MH		 1138 return;
1139 }
1140 foo >>= 1;
1141 }
1142 State.regs[OP[0]] = 16;
87178dbd 1143 trace_output (OP_REG);
2934d1c9
MH		 1144}
1145
1146/* jl */
1147void
1148OP_4D00 ()
1149{
a18cb100 1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
2934d1c9 1151 State.regs[13] = PC+1;
fd435e9f 1152 JMP (State.regs[OP[0]]);
87178dbd 1153 trace_output (OP_VOID);
2934d1c9
MH		 1154}
1155
1156/* jmp */
1157void
1158OP_4C00 ()
1159{
a18cb100
MM		 1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1163
fd435e9f 1164 JMP (State.regs[OP[0]]);
87178dbd 1165 trace_output (OP_VOID);
2934d1c9
MH		 1166}
1167
1168/* ld */
1169void
1170OP_30000000 ()
1171{
87178dbd 1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
87178dbd 1174 trace_output (OP_REG);
2934d1c9
MH		 1175}
1176
1177/* ld */
1178void
1179OP_6401 ()
1180{
87178dbd 1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 1182 if ( OP[1] == 15 )
1183 {
1184 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
1185 State.exception = SIGILL;
1186 return;
1187 }
4c38885c 1188 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1189 INC_ADDR(State.regs[OP[1]],-2);
87178dbd 1190 trace_output (OP_REG);
2934d1c9
MH		 1191}
1192
1193/* ld */
1194void
1195OP_6001 ()
1196{
87178dbd 1197 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
4c38885c 1198 State.regs[OP[0]] = RW (State.regs[OP[1]]);
4f425a32 1199 INC_ADDR(State.regs[OP[1]],2);
87178dbd 1200 trace_output (OP_REG);
2934d1c9
MH		 1201}
1202
1203/* ld */
1204void
1205OP_6000 ()
1206{
87178dbd 1207 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1208 State.regs[OP[0]] = RW (State.regs[OP[1]]);
87178dbd 1209 trace_output (OP_REG);
2934d1c9
MH		 1210}
1211
1212/* ld2w */
1213void
1214OP_31000000 ()
1215{
8918b3a7 1216 uint16 addr = State.regs[OP[2]];
308f64d3 1217 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
8918b3a7
MM		 1218 State.regs[OP[0]] = RW (OP[1] + addr);
1219 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
87178dbd 1220 trace_output (OP_DREG);
2934d1c9
MH		 1221}
1222
1223/* ld2w */
1224void
1225OP_6601 ()
1226{
8918b3a7 1227 uint16 addr = State.regs[OP[1]];
87178dbd 1228 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 1229 if ( OP[1] == 15 )
1230 {
1231 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
1232 State.exception = SIGILL;
1233 return;
1234 }
8918b3a7
MM		 1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1237 INC_ADDR(State.regs[OP[1]],-4);
87178dbd 1238 trace_output (OP_DREG);
2934d1c9
MH		 1239}
1240
1241/* ld2w */
1242void
1243OP_6201 ()
1244{
8918b3a7 1245 uint16 addr = State.regs[OP[1]];
87178dbd 1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
8918b3a7
MM		 1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
4f425a32 1249 INC_ADDR(State.regs[OP[1]],4);
8918b3a7 1250 trace_output (OP_DREG);
2934d1c9
MH		 1251}
1252
1253/* ld2w */
1254void
1255OP_6200 ()
1256{
8918b3a7 1257 uint16 addr = State.regs[OP[1]];
addb61a5 1258 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
8918b3a7
MM		 1259 State.regs[OP[0]] = RW (addr);
1260 State.regs[OP[0]+1] = RW (addr+2);
1261 trace_output (OP_DREG);
2934d1c9
MH		 1262}
1263
1264/* ldb */
1265void
1266OP_38000000 ()
1267{
87178dbd 1268 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
c422ecc7 1269 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
87178dbd 1270 trace_output (OP_REG);
2934d1c9
MH		 1271}
1272
1273/* ldb */
1274void
1275OP_7000 ()
1276{
87178dbd 1277 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
c422ecc7 1278 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
87178dbd 1279 trace_output (OP_REG);
2934d1c9
MH		 1280}
1281
1282/* ldi.s */
1283void
1284OP_4001 ()
1285{
87178dbd 1286 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
2934d1c9 1287 State.regs[OP[0]] = SEXT4(OP[1]);
87178dbd 1288 trace_output (OP_REG);
2934d1c9
MH		 1289}
1290
1291/* ldi.l */
1292void
1293OP_20000000 ()
1294{
fd435e9f 1295 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
2934d1c9 1296 State.regs[OP[0]] = OP[1];
87178dbd 1297 trace_output (OP_REG);
2934d1c9
MH		 1298}
1299
1300/* ldub */
1301void
1302OP_39000000 ()
1303{
87178dbd 1304 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
2934d1c9 1305 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
87178dbd 1306 trace_output (OP_REG);
2934d1c9
MH		 1307}
1308
1309/* ldub */
1310void
1311OP_7200 ()
1312{
87178dbd 1313 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
2934d1c9 1314 State.regs[OP[0]] = RB (State.regs[OP[1]]);
87178dbd 1315 trace_output (OP_REG);
2934d1c9
MH		 1316}
1317
1318/* mac */
1319void
1320OP_2A00 ()
1321{
4c38885c 1322 int64 tmp;
87178dbd
MM		 1323
1324 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
4f425a32 1325 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
4c38885c
MH		 1326
1327 if (State.FX)
4f425a32 1328 tmp = SEXT40( (tmp << 1) & MASK40);
4c38885c
MH		 1329
1330 if (State.ST && tmp > MAX32)
1331 tmp = MAX32;
1332
4f425a32 1333 tmp += SEXT40(State.a[OP[0]]);
4c38885c
MH		 1334 if (State.ST)
1335 {
1336 if (tmp > MAX32)
1337 State.a[OP[0]] = MAX32;
1338 else if (tmp < MIN32)
1339 State.a[OP[0]] = MIN32;
1340 else
4f425a32 1341 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 1342 }
1343 else
4f425a32 1344 State.a[OP[0]] = tmp & MASK40;
87178dbd 1345 trace_output (OP_ACCUM);
2934d1c9
MH		 1346}
1347
1348/* macsu */
1349void
1350OP_1A00 ()
1351{
4f425a32 1352 int64 tmp;
87178dbd
MM		 1353
1354 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1355 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1356 if (State.FX)
1357 tmp = SEXT40( (tmp << 1) & MASK40);
1358
1359 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1360 trace_output (OP_ACCUM);
2934d1c9
MH		 1361}
1362
1363/* macu */
1364void
1365OP_3A00 ()
1366{
4f425a32 1367 int64 tmp;
87178dbd
MM		 1368
1369 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1370 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1371 if (State.FX)
1372 tmp = SEXT40( (tmp << 1) & MASK40);
1373 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
87178dbd 1374 trace_output (OP_ACCUM);
2934d1c9
MH		 1375}
1376
1377/* max */
1378void
1379OP_2600 ()
1380{
87178dbd 1381 trace_input ("max", OP_REG, OP_REG, OP_VOID);
2934d1c9 1382 State.F1 = State.F0;
ea2155e8 1383 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
2934d1c9
MH		 1384 {
1385 State.regs[OP[0]] = State.regs[OP[1]];
1386 State.F0 = 1;
1387 }
1388 else
1389 State.F0 = 0;
87178dbd 1390 trace_output (OP_REG);
2934d1c9
MH		 1391}
1392
1393/* max */
1394void
1395OP_3600 ()
1396{
4f425a32 1397 int64 tmp;
87178dbd
MM		 1398
1399 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1400 State.F1 = State.F0;
1401 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1402 if (tmp > SEXT40(State.a[OP[0]]))
1403 {
1404 State.a[OP[0]] = tmp & MASK40;
1405 State.F0 = 1;
1406 }
1407 else
1408 State.F0 = 0;
87178dbd 1409 trace_output (OP_ACCUM);
2934d1c9
MH		 1410}
1411
1412/* max */
1413void
1414OP_3602 ()
1415{
87178dbd 1416 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1417 State.F1 = State.F0;
1418 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1419 {
1420 State.a[OP[0]] = State.a[OP[1]];
1421 State.F0 = 1;
1422 }
1423 else
1424 State.F0 = 0;
87178dbd 1425 trace_output (OP_ACCUM);
2934d1c9
MH		 1426}
1427
4f425a32 1428
2934d1c9
MH		 1429/* min */
1430void
1431OP_2601 ()
1432{
87178dbd 1433 trace_input ("min", OP_REG, OP_REG, OP_VOID);
2934d1c9 1434 State.F1 = State.F0;
ea2155e8 1435 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
2934d1c9
MH		 1436 {
1437 State.regs[OP[0]] = State.regs[OP[1]];
1438 State.F0 = 1;
1439 }
1440 else
1441 State.F0 = 0;
87178dbd 1442 trace_output (OP_REG);
2934d1c9
MH		 1443}
1444
1445/* min */
1446void
1447OP_3601 ()
1448{
4f425a32 1449 int64 tmp;
87178dbd
MM		 1450
1451 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 1452 State.F1 = State.F0;
1453 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1454 if (tmp < SEXT40(State.a[OP[0]]))
1455 {
1456 State.a[OP[0]] = tmp & MASK40;
1457 State.F0 = 1;
1458 }
1459 else
1460 State.F0 = 0;
87178dbd 1461 trace_output (OP_ACCUM);
2934d1c9
MH		 1462}
1463
1464/* min */
1465void
1466OP_3603 ()
1467{
87178dbd 1468 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 1469 State.F1 = State.F0;
1470 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1471 {
1472 State.a[OP[0]] = State.a[OP[1]];
1473 State.F0 = 1;
1474 }
1475 else
1476 State.F0 = 0;
87178dbd 1477 trace_output (OP_ACCUM);
2934d1c9
MH		 1478}
1479
1480/* msb */
1481void
1482OP_2800 ()
1483{
4f425a32 1484 int64 tmp;
87178dbd
MM		 1485
1486 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1487 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1488
1489 if (State.FX)
1490 tmp = SEXT40 ((tmp << 1) & MASK40);
1491
1492 if (State.ST && tmp > MAX32)
1493 tmp = MAX32;
1494
1495 tmp = SEXT40(State.a[OP[0]]) - tmp;
1496 if (State.ST)
1497 {
1498 if (tmp > MAX32)
1499 State.a[OP[0]] = MAX32;
1500 else if (tmp < MIN32)
1501 State.a[OP[0]] = MIN32;
1502 else
1503 State.a[OP[0]] = tmp & MASK40;
1504 }
1505 else
1506 State.a[OP[0]] = tmp & MASK40;
87178dbd 1507 trace_output (OP_ACCUM);
2934d1c9
MH		 1508}
1509
1510/* msbsu */
1511void
1512OP_1800 ()
1513{
4f425a32 1514 int64 tmp;
87178dbd
MM		 1515
1516 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1517 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1518 if (State.FX)
1519 tmp = SEXT40( (tmp << 1) & MASK40);
1520
1521 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1522 trace_output (OP_ACCUM);
2934d1c9
MH		 1523}
1524
1525/* msbu */
1526void
1527OP_3800 ()
1528{
4f425a32 1529 int64 tmp;
87178dbd
MM		 1530
1531 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
4f425a32
MH		 1532 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1533 if (State.FX)
1534 tmp = SEXT40( (tmp << 1) & MASK40);
1535
1536 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
87178dbd 1537 trace_output (OP_ACCUM);
2934d1c9
MH		 1538}
1539
1540/* mul */
1541void
1542OP_2E00 ()
1543{
87178dbd 1544 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
2934d1c9 1545 State.regs[OP[0]] *= State.regs[OP[1]];
87178dbd 1546 trace_output (OP_REG);
2934d1c9
MH		 1547}
1548
1549/* mulx */
1550void
1551OP_2C00 ()
1552{
4f425a32 1553 int64 tmp;
87178dbd
MM		 1554
1555 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1556 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1557
1558 if (State.FX)
1559 tmp = SEXT40 ((tmp << 1) & MASK40);
1560
1561 if (State.ST && tmp > MAX32)
1562 State.a[OP[0]] = MAX32;
1563 else
1564 State.a[OP[0]] = tmp & MASK40;
87178dbd 1565 trace_output (OP_ACCUM);
2934d1c9
MH		 1566}
1567
1568/* mulxsu */
1569void
1570OP_1C00 ()
1571{
4f425a32 1572 int64 tmp;
87178dbd
MM		 1573
1574 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1575 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1576
1577 if (State.FX)
1578 tmp <<= 1;
1579
1580 State.a[OP[0]] = tmp & MASK40;
87178dbd 1581 trace_output (OP_ACCUM);
2934d1c9
MH		 1582}
1583
1584/* mulxu */
1585void
1586OP_3C00 ()
1587{
4f425a32 1588 int64 tmp;
87178dbd
MM		 1589
1590 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
4f425a32
MH		 1591 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1592
1593 if (State.FX)
1594 tmp <<= 1;
1595
1596 State.a[OP[0]] = tmp & MASK40;
87178dbd 1597 trace_output (OP_ACCUM);
2934d1c9
MH		 1598}
1599
1600/* mv */
1601void
1602OP_4000 ()
1603{
87178dbd 1604 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1605 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1606 trace_output (OP_REG);
2934d1c9
MH		 1607}
1608
1609/* mv2w */
1610void
1611OP_5000 ()
1612{
87178dbd 1613 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
2934d1c9
MH		 1614 State.regs[OP[0]] = State.regs[OP[1]];
1615 State.regs[OP[0]+1] = State.regs[OP[1]+1];
87178dbd 1616 trace_output (OP_DREG);
2934d1c9
MH		 1617}
1618
1619/* mv2wfac */
1620void
1621OP_3E00 ()
1622{
87178dbd 1623 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1624 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1625 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
87178dbd 1626 trace_output (OP_DREG);
2934d1c9
MH		 1627}
1628
1629/* mv2wtac */
1630void
1631OP_3E01 ()
1632{
fd435e9f 1633 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
4f425a32 1634 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
fd435e9f 1635 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1636}
1637
1638/* mvac */
1639void
1640OP_3E03 ()
1641{
87178dbd 1642 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1643 State.a[OP[0]] = State.a[OP[1]];
87178dbd 1644 trace_output (OP_ACCUM);
2934d1c9
MH		 1645}
1646
1647/* mvb */
1648void
1649OP_5400 ()
1650{
87178dbd 1651 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1652 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
87178dbd 1653 trace_output (OP_REG);
2934d1c9
MH		 1654}
1655
1656/* mvf0f */
1657void
1658OP_4400 ()
1659{
87178dbd 1660 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1661 if (State.F0 == 0)
1662 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1663 trace_output (OP_REG);
2934d1c9
MH		 1664}
1665
1666/* mvf0t */
1667void
1668OP_4401 ()
1669{
87178dbd 1670 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9
MH		 1671 if (State.F0)
1672 State.regs[OP[0]] = State.regs[OP[1]];
87178dbd 1673 trace_output (OP_REG);
2934d1c9
MH		 1674}
1675
1676/* mvfacg */
1677void
1678OP_1E04 ()
1679{
87178dbd 1680 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1681 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
87178dbd 1682 trace_output (OP_ACCUM);
2934d1c9
MH		 1683}
1684
1685/* mvfachi */
1686void
1687OP_1E00 ()
1688{
87178dbd 1689 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1690 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
87178dbd 1691 trace_output (OP_REG);
2934d1c9
MH		 1692}
1693
1694/* mvfaclo */
1695void
1696OP_1E02 ()
1697{
87178dbd 1698 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2934d1c9 1699 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
87178dbd 1700 trace_output (OP_REG);
2934d1c9
MH		 1701}
1702
1703/* mvfc */
1704void
1705OP_5200 ()
1706{
87178dbd 1707 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2934d1c9
MH		 1708 if (OP[1] == 0)
1709 {
1710 /* PSW is treated specially */
1711 PSW = 0;
1712 if (State.SM) PSW |= 0x8000;
1713 if (State.EA) PSW |= 0x2000;
1714 if (State.DB) PSW |= 0x1000;
1715 if (State.IE) PSW |= 0x400;
1716 if (State.RP) PSW |= 0x200;
1717 if (State.MD) PSW |= 0x100;
1718 if (State.FX) PSW |= 0x80;
1719 if (State.ST) PSW |= 0x40;
1720 if (State.F0) PSW |= 8;
1721 if (State.F1) PSW |= 4;
1722 if (State.C) PSW |= 1;
1723 }
1724 State.regs[OP[0]] = State.cregs[OP[1]];
87178dbd 1725 trace_output (OP_REG);
2934d1c9
MH		 1726}
1727
1728/* mvtacg */
1729void
1730OP_1E41 ()
1731{
87178dbd 1732 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9
MH		 1733 State.a[OP[1]] &= MASK32;
1734 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
87178dbd 1735 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1736}
1737
1738/* mvtachi */
1739void
1740OP_1E01 ()
1741{
1742 uint16 tmp;
87178dbd
MM		 1743
1744 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2934d1c9 1745 tmp = State.a[OP[1]] & 0xffff;
4f425a32 1746 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
87178dbd 1747 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1748}
1749
1750/* mvtaclo */
1751void
1752OP_1E21 ()
1753{
87178dbd 1754 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
4f425a32 1755 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
87178dbd 1756 trace_output (OP_ACCUM_REVERSE);
2934d1c9
MH		 1757}
1758
1759/* mvtc */
1760void
1761OP_5600 ()
1762{
87178dbd 1763 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2934d1c9
MH		 1764 State.cregs[OP[1]] = State.regs[OP[0]];
1765 if (OP[1] == 0)
1766 {
1767 /* PSW is treated specially */
1768 State.SM = (PSW & 0x8000) ? 1 : 0;
1769 State.EA = (PSW & 0x2000) ? 1 : 0;
1770 State.DB = (PSW & 0x1000) ? 1 : 0;
1771 State.IE = (PSW & 0x400) ? 1 : 0;
1772 State.RP = (PSW & 0x200) ? 1 : 0;
1773 State.MD = (PSW & 0x100) ? 1 : 0;
1774 State.FX = (PSW & 0x80) ? 1 : 0;
1775 State.ST = (PSW & 0x40) ? 1 : 0;
1776 State.F0 = (PSW & 8) ? 1 : 0;
1777 State.F1 = (PSW & 4) ? 1 : 0;
1778 State.C = PSW & 1;
1779 if (State.ST && !State.FX)
1780 {
7eebfc62
MM		 1781 (*d10v_callback->printf_filtered) (d10v_callback,
1782 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1783 PC<<2);
4f425a32 1784 State.exception = SIGILL;
2934d1c9
MH		 1785 }
1786 }
87178dbd 1787 trace_output (OP_CR_REVERSE);
2934d1c9
MH		 1788}
1789
1790/* mvub */
1791void
1792OP_5401 ()
1793{
87178dbd 1794 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2934d1c9 1795 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
87178dbd 1796 trace_output (OP_REG);
2934d1c9
MH		 1797}
1798
1799/* neg */
1800void
1801OP_4605 ()
1802{
87178dbd 1803 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1804 State.regs[OP[0]] = 0 - State.regs[OP[0]];
87178dbd 1805 trace_output (OP_REG);
2934d1c9
MH		 1806}
1807
1808/* neg */
1809void
1810OP_5605 ()
1811{
1812 int64 tmp;
87178dbd
MM		 1813
1814 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
4f425a32 1815 tmp = -SEXT40(State.a[OP[0]]);
2934d1c9
MH		 1816 if (State.ST)
1817 {
4c38885c 1818 if ( tmp > MAX32)
2934d1c9 1819 State.a[OP[0]] = MAX32;
4c38885c 1820 else if (tmp < MIN32)
2934d1c9
MH		 1821 State.a[OP[0]] = MIN32;
1822 else
4f425a32 1823 State.a[OP[0]] = tmp & MASK40;
2934d1c9
MH		 1824 }
1825 else
4f425a32 1826 State.a[OP[0]] = tmp & MASK40;
87178dbd 1827 trace_output (OP_ACCUM);
2934d1c9
MH		 1828}
1829
1830
1831/* nop */
1832void
1833OP_5E00 ()
1834{
87178dbd 1835 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
7eebfc62 1836
c422ecc7
MH		 1837 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1838 switch (State.ins_type)
1839 {
1840 default:
1841 ins_type_counters[ (int)INS_UNKNOWN ]++;
1842 break;
1843
1844 case INS_LEFT_PARALLEL:
1845 /* Don't count a parallel op that includes a NOP as a true parallel op */
1846 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1847 ins_type_counters[ (int)INS_RIGHT ]++;
1848 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1849 break;
1850
1851 case INS_LEFT:
1852 case INS_LEFT_COND_EXE:
1853 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1854 break;
1855
1856 case INS_RIGHT_PARALLEL:
1857 /* Don't count a parallel op that includes a NOP as a true parallel op */
1858 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1859 ins_type_counters[ (int)INS_LEFT ]++;
1860 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1861 break;
1862
1863 case INS_RIGHT:
1864 case INS_RIGHT_COND_EXE:
1865 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1866 break;
1867 }
1868
1869 trace_output (OP_VOID);
2934d1c9
MH		 1870}
1871
1872/* not */
1873void
1874OP_4603 ()
1875{
87178dbd 1876 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2934d1c9 1877 State.regs[OP[0]] = ~(State.regs[OP[0]]);
87178dbd 1878 trace_output (OP_REG);
2934d1c9
MH		 1879}
1880
1881/* or */
1882void
1883OP_800 ()
1884{
87178dbd 1885 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2934d1c9 1886 State.regs[OP[0]] |= State.regs[OP[1]];
87178dbd 1887 trace_output (OP_REG);
2934d1c9
MH		 1888}
1889
1890/* or3 */
1891void
1892OP_4000000 ()
1893{
87178dbd 1894 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2934d1c9 1895 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
87178dbd 1896 trace_output (OP_REG);
2934d1c9
MH		 1897}
1898
1899/* rac */
1900void
1901OP_5201 ()
1902{
1903 int64 tmp;
1904 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1905
1906 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
166acb9f
MH		 1907 if (OP[1] != 0)
1908 {
7eebfc62
MM		 1909 (*d10v_callback->printf_filtered) (d10v_callback,
1910 "ERROR at PC 0x%x: instruction only valid for A0\n",
1911 PC<<2);
166acb9f
MH		 1912 State.exception = SIGILL;
1913 }
1914
2934d1c9
MH		 1915 State.F1 = State.F0;
1916 if (shift >=0)
1917 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1918 else
1919 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
166acb9f 1920 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
4c38885c 1921 if (tmp > MAX32)
2934d1c9
MH		 1922 {
1923 State.regs[OP[0]] = 0x7fff;
1924 State.regs[OP[0]+1] = 0xffff;
1925 State.F0 = 1;
1926 }
4c38885c 1927 else if (tmp < MIN32)
2934d1c9
MH		 1928 {
1929 State.regs[OP[0]] = 0x8000;
1930 State.regs[OP[0]+1] = 0;
1931 State.F0 = 1;
1932 }
1933 else
1934 {
1935 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1936 State.regs[OP[0]+1] = tmp & 0xffff;
1937 State.F0 = 0;
1938 }
87178dbd 1939 trace_output (OP_DREG);
2934d1c9
MH		 1940}
1941
1942/* rachi */
1943void
1944OP_4201 ()
1945{
4c38885c
MH		 1946 int64 tmp;
1947 int shift = SEXT3 (OP[2]);
87178dbd
MM		 1948
1949 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
4c38885c
MH		 1950 State.F1 = State.F0;
1951 if (shift >=0)
166acb9f 1952 tmp = SEXT44 (State.a[1]) << shift;
4c38885c 1953 else
166acb9f 1954 tmp = SEXT44 (State.a[1]) >> -shift;
4c38885c 1955 tmp += 0x8000;
63a91cfb 1956
4c38885c
MH		 1957 if (tmp > MAX32)
1958 {
1959 State.regs[OP[0]] = 0x7fff;
1960 State.F0 = 1;
1961 }
1962 else if (tmp < 0xfff80000000LL)
1963 {
1964 State.regs[OP[0]] = 0x8000;
1965 State.F0 = 1;
1966 }
1967 else
1968 {
1969 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1970 State.F0 = 0;
1971 }
87178dbd 1972 trace_output (OP_REG);
2934d1c9
MH		 1973}
1974
1975/* rep */
1976void
1977OP_27000000 ()
1978{
87178dbd 1979 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 1980 RPT_S = PC + 1;
1981 RPT_E = PC + OP[1];
1982 RPT_C = State.regs[OP[0]];
1983 State.RP = 1;
1984 if (RPT_C == 0)
1985 {
7eebfc62 1986 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
4f425a32 1987 State.exception = SIGILL;
2934d1c9 1988 }
4c38885c
MH		 1989 if (OP[1] < 4)
1990 {
7eebfc62 1991 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
4f425a32 1992 State.exception = SIGILL;
4c38885c 1993 }
87178dbd 1994 trace_output (OP_VOID);
2934d1c9
MH		 1995}
1996
1997/* repi */
1998void
1999OP_2F000000 ()
2000{
87178dbd 2001 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2934d1c9
MH		 2002 RPT_S = PC + 1;
2003 RPT_E = PC + OP[1];
2004 RPT_C = OP[0];
2005 State.RP = 1;
2006 if (RPT_C == 0)
2007 {
7eebfc62 2008 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
4f425a32 2009 State.exception = SIGILL;
4c38885c
MH		 2010 }
2011 if (OP[1] < 4)
2012 {
7eebfc62 2013 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
4f425a32 2014 State.exception = SIGILL;
2934d1c9 2015 }
87178dbd 2016 trace_output (OP_VOID);
2934d1c9
MH		 2017}
2018
2019/* rtd */
2020void
2021OP_5F60 ()
2022{
7eebfc62 2023 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
87178dbd 2024 State.exception = SIGILL;
2934d1c9
MH		 2025}
2026
2027/* rte */
2028void
2029OP_5F40 ()
2030{
87178dbd 2031 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
4c38885c
MH		 2032 PC = BPC;
2033 PSW = BPSW;
87178dbd 2034 trace_output (OP_VOID);
2934d1c9
MH		 2035}
2036
2037/* sadd */
2038void
2039OP_1223 ()
2040{
4c38885c 2041 int64 tmp;
87178dbd
MM		 2042
2043 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32 2044 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
4c38885c
MH		 2045 if (State.ST)
2046 {
2047 if (tmp > MAX32)
2048 State.a[OP[0]] = MAX32;
2049 else if (tmp < MIN32)
2050 State.a[OP[0]] = MIN32;
2051 else
4f425a32 2052 State.a[OP[0]] = tmp & MASK40;
4c38885c
MH		 2053 }
2054 else
4f425a32 2055 State.a[OP[0]] = tmp & MASK40;
87178dbd 2056 trace_output (OP_ACCUM);
2934d1c9
MH		 2057}
2058
2059/* setf0f */
2060void
2061OP_4611 ()
2062{
87178dbd 2063 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2064 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
87178dbd 2065 trace_output (OP_REG);
2934d1c9
MH		 2066}
2067
2068/* setf0t */
2069void
2070OP_4613 ()
2071{
87178dbd 2072 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
4c38885c 2073 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
87178dbd 2074 trace_output (OP_REG);
2934d1c9
MH		 2075}
2076
2077/* sleep */
2078void
2079OP_5FC0 ()
2080{
87178dbd 2081 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
4c38885c 2082 State.IE = 1;
87178dbd 2083 trace_output (OP_VOID);
2934d1c9
MH		 2084}
2085
2086/* sll */
2087void
2088OP_2200 ()
2089{
87178dbd 2090 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2934d1c9 2091 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
87178dbd 2092 trace_output (OP_REG);
2934d1c9
MH		 2093}
2094
2095/* sll */
2096void
2097OP_3200 ()
2098{
4c38885c 2099 int64 tmp;
87178dbd 2100 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2101 if ((State.regs[OP[1]] & 31) <= 16)
4c38885c 2102 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
069398aa
MM		 2103 else
2104 {
2105 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2106 State.exception = SIGILL;
2107 return;
2108 }
4c38885c
MH		 2109
2110 if (State.ST)
2111 {
2112 if (tmp > MAX32)
2113 State.a[OP[0]] = MAX32;
2114 else if (tmp < 0xffffff80000000LL)
2115 State.a[OP[0]] = MIN32;
2116 else
2117 State.a[OP[0]] = tmp & MASK40;
2118 }
2119 else
2120 State.a[OP[0]] = tmp & MASK40;
87178dbd 2121 trace_output (OP_ACCUM);
2934d1c9
MH		 2122}
2123
2124/* slli */
2125void
2126OP_2201 ()
2127{
87178dbd 2128 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2129 State.regs[OP[0]] <<= OP[1];
87178dbd 2130 trace_output (OP_REG);
2934d1c9
MH		 2131}
2132
2133/* slli */
2134void
2135OP_3201 ()
2136{
4c38885c 2137 int64 tmp;
4f425a32
MH		 2138
2139 if (OP[1] == 0)
2140 OP[1] = 16;
4f425a32 2141
87178dbd 2142 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
4f425a32 2143 tmp = SEXT40(State.a[OP[0]]) << OP[1];
4c38885c
MH		 2144
2145 if (State.ST)
2146 {
2147 if (tmp > MAX32)
2148 State.a[OP[0]] = MAX32;
2149 else if (tmp < 0xffffff80000000LL)
2150 State.a[OP[0]] = MIN32;
2151 else
2152 State.a[OP[0]] = tmp & MASK40;
2153 }
2154 else
2155 State.a[OP[0]] = tmp & MASK40;
87178dbd 2156 trace_output (OP_ACCUM);
2934d1c9
MH		 2157}
2158
2159/* slx */
2160void
2161OP_460B ()
2162{
87178dbd 2163 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9 2164 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
87178dbd 2165 trace_output (OP_REG);
2934d1c9
MH		 2166}
2167
2168/* sra */
2169void
2170OP_2400 ()
2171{
87178dbd 2172 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2934d1c9 2173 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
87178dbd 2174 trace_output (OP_REG);
2934d1c9
MH		 2175}
2176
2177/* sra */
2178void
2179OP_3400 ()
2180{
87178dbd 2181 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2182 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2183 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
069398aa
MM		 2184 else
2185 {
2186 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2187 State.exception = SIGILL;
2188 return;
2189 }
2190
87178dbd 2191 trace_output (OP_ACCUM);
2934d1c9
MH		 2192}
2193
2194/* srai */
2195void
2196OP_2401 ()
2197{
87178dbd 2198 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2199 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
87178dbd 2200 trace_output (OP_REG);
2934d1c9
MH		 2201}
2202
2203/* srai */
2204void
2205OP_3401 ()
2206{
4f425a32
MH		 2207 if (OP[1] == 0)
2208 OP[1] = 16;
87178dbd
MM		 2209
2210 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2211 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
87178dbd 2212 trace_output (OP_ACCUM);
2934d1c9
MH		 2213}
2214
2215/* srl */
2216void
2217OP_2000 ()
2218{
87178dbd 2219 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2934d1c9 2220 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
87178dbd 2221 trace_output (OP_REG);
2934d1c9
MH		 2222}
2223
2224/* srl */
2225void
2226OP_3000 ()
2227{
87178dbd 2228 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
069398aa 2229 if ((State.regs[OP[1]] & 31) <= 16)
fd435e9f 2230 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
069398aa
MM		 2231 else
2232 {
2233 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2234 State.exception = SIGILL;
2235 return;
2236 }
2237
87178dbd 2238 trace_output (OP_ACCUM);
2934d1c9
MH		 2239}
2240
2241/* srli */
2242void
2243OP_2001 ()
2244{
87178dbd 2245 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2934d1c9 2246 State.regs[OP[0]] >>= OP[1];
87178dbd 2247 trace_output (OP_REG);
2934d1c9
MH		 2248}
2249
2250/* srli */
2251void
2252OP_3001 ()
2253{
4f425a32
MH		 2254 if (OP[1] == 0)
2255 OP[1] = 16;
87178dbd
MM		 2256
2257 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
fd435e9f 2258 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
87178dbd 2259 trace_output (OP_ACCUM);
2934d1c9
MH		 2260}
2261
2262/* srx */
2263void
2264OP_4609 ()
2265{
2266 uint16 tmp;
87178dbd
MM		 2267
2268 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2934d1c9
MH		 2269 tmp = State.F0 << 15;
2270 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
87178dbd 2271 trace_output (OP_REG);
2934d1c9
MH		 2272}
2273
2274/* st */
2275void
2276OP_34000000 ()
2277{
87178dbd 2278 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2934d1c9 2279 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
87178dbd 2280 trace_output (OP_VOID);
2934d1c9
MH		 2281}
2282
2283/* st */
2284void
2285OP_6800 ()
2286{
87178dbd 2287 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2934d1c9 2288 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2289 trace_output (OP_VOID);
2934d1c9
MH		 2290}
2291
2292/* st */
2293void
2294OP_6C1F ()
2295{
87178dbd 2296 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2297 if ( OP[1] != 15 )
2298 {
7eebfc62 2299 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2300 State.exception = SIGILL;
2301 return;
4c38885c
MH		 2302 }
2303 State.regs[OP[1]] -= 2;
2304 SW (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2305 trace_output (OP_VOID);
2934d1c9
MH		 2306}
2307
2308/* st */
2309void
2310OP_6801 ()
2311{
87178dbd 2312 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
4c38885c 2313 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2314 INC_ADDR (State.regs[OP[1]],2);
87178dbd 2315 trace_output (OP_VOID);
2934d1c9
MH		 2316}
2317
2318/* st */
2319void
2320OP_6C01 ()
2321{
87178dbd 2322 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 2323 if ( OP[1] == 15 )
2324 {
2325 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2326 State.exception = SIGILL;
2327 return;
2328 }
4c38885c 2329 SW (State.regs[OP[1]], State.regs[OP[0]]);
4f425a32 2330 INC_ADDR (State.regs[OP[1]],-2);
87178dbd 2331 trace_output (OP_VOID);
2934d1c9
MH		 2332}
2333
2334/* st2w */
2335void
2336OP_35000000 ()
2337{
87178dbd 2338 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
4f425a32
MH		 2339 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2340 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
87178dbd 2341 trace_output (OP_VOID);
2934d1c9
MH		 2342}
2343
2344/* st2w */
2345void
2346OP_6A00 ()
2347{
a18cb100 2348 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
4c38885c
MH		 2349 SW (State.regs[OP[1]], State.regs[OP[0]]);
2350 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2351 trace_output (OP_VOID);
2934d1c9
MH		 2352}
2353
2354/* st2w */
2355void
2356OP_6E1F ()
2357{
a18cb100 2358 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
4c38885c
MH		 2359 if ( OP[1] != 15 )
2360 {
7eebfc62 2361 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
4f425a32
MH		 2362 State.exception = SIGILL;
2363 return;
4c38885c
MH		 2364 }
2365 State.regs[OP[1]] -= 4;
2366 SW (State.regs[OP[1]], State.regs[OP[0]]);
2367 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
87178dbd 2368 trace_output (OP_VOID);
2934d1c9
MH		 2369}
2370
2371/* st2w */
2372void
2373OP_6A01 ()
2374{
a18cb100 2375 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
fd435e9f
MM		 2376 if ( OP[1] == 15 )
2377 {
2378 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2379 State.exception = SIGILL;
2380 return;
2381 }
4c38885c
MH		 2382 SW (State.regs[OP[1]], State.regs[OP[0]]);
2383 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2384 INC_ADDR (State.regs[OP[1]],4);
87178dbd 2385 trace_output (OP_VOID);
2934d1c9
MH		 2386}
2387
2388/* st2w */
2389void
2390OP_6E01 ()
2391{
a18cb100 2392 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
4c38885c
MH		 2393 SW (State.regs[OP[1]], State.regs[OP[0]]);
2394 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
4f425a32 2395 INC_ADDR (State.regs[OP[1]],-4);
87178dbd 2396 trace_output (OP_VOID);
2934d1c9
MH		 2397}
2398
2399/* stb */
2400void
2401OP_3C000000 ()
2402{
87178dbd 2403 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
4f425a32 2404 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
87178dbd 2405 trace_output (OP_VOID);
2934d1c9
MH		 2406}
2407
2408/* stb */
2409void
2410OP_7800 ()
2411{
87178dbd 2412 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
4c38885c 2413 SB (State.regs[OP[1]], State.regs[OP[0]]);
87178dbd 2414 trace_output (OP_VOID);
2934d1c9
MH		 2415}
2416
2417/* stop */
2418void
2419OP_5FE0 ()
2420{
87178dbd 2421 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
a49a15ad 2422 State.exception = SIG_D10V_STOP;
87178dbd 2423 trace_output (OP_VOID);
2934d1c9
MH		 2424}
2425
2426/* sub */
2427void
2428OP_0 ()
4c38885c 2429{
f4b022d3 2430 uint16 tmp;
87178dbd
MM		 2431
2432 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
f4b022d3
MM		 2433 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2434 State.C = (tmp > State.regs[OP[0]]);
2435 State.regs[OP[0]] = tmp;
87178dbd 2436 trace_output (OP_REG);
4c38885c
MH		 2437}
2438
2439/* sub */
2440void
2441OP_1001 ()
2442{
4f425a32 2443 int64 tmp;
87178dbd
MM		 2444
2445 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
4f425a32
MH		 2446 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2447 if (State.ST)
2448 {
2449 if ( tmp > MAX32)
2450 State.a[OP[0]] = MAX32;
2451 else if ( tmp < MIN32)
2452 State.a[OP[0]] = MIN32;
2453 else
2454 State.a[OP[0]] = tmp & MASK40;
2455 }
2456 else
2457 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2458
2459 trace_output (OP_ACCUM);
4c38885c
MH		 2460}
2461
2462/* sub */
2463
2464void
2465OP_1003 ()
2934d1c9 2466{
4f425a32 2467 int64 tmp;
87178dbd
MM		 2468
2469 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
4f425a32
MH		 2470 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2471 if (State.ST)
2472 {
2473 if (tmp > MAX32)
2474 State.a[OP[0]] = MAX32;
2475 else if ( tmp < MIN32)
2476 State.a[OP[0]] = MIN32;
2477 else
2478 State.a[OP[0]] = tmp & MASK40;
2479 }
2480 else
2481 State.a[OP[0]] = tmp & MASK40;
87178dbd
MM		 2482
2483 trace_output (OP_ACCUM);
2934d1c9
MH		 2484}
2485
2486/* sub2w */
2487void
2488OP_1000 ()
2489{
f4b022d3 2490 uint32 tmp,a,b;
4c38885c 2491
87178dbd 2492 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
f4b022d3
MM		 2493 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2494 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2495 tmp = a-b;
2496 State.C = (tmp > a);
4c38885c
MH		 2497 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2498 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2499 trace_output (OP_DREG);
2934d1c9
MH		 2500}
2501
2502/* subac3 */
2503void
2504OP_17000000 ()
2505{
4f425a32 2506 int64 tmp;
87178dbd
MM		 2507
2508 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2509 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2510 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2511 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2512 trace_output (OP_DREG);
2934d1c9
MH		 2513}
2514
2515/* subac3 */
2516void
2517OP_17000002 ()
2518{
4f425a32 2519 int64 tmp;
87178dbd
MM		 2520
2521 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2522 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2523 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2524 State.regs[OP[0]+1] = tmp & 0xffff;
87178dbd 2525 trace_output (OP_DREG);
2934d1c9
MH		 2526}
2527
2528/* subac3s */
2529void
2530OP_17001000 ()
2531{
4f425a32 2532 int64 tmp;
87178dbd
MM		 2533
2534 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
4f425a32
MH		 2535 State.F1 = State.F0;
2536 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2537 if ( tmp > MAX32)
2538 {
2539 State.regs[OP[0]] = 0x7fff;
2540 State.regs[OP[0]+1] = 0xffff;
2541 State.F0 = 1;
2542 }
2543 else if (tmp < MIN32)
2544 {
2545 State.regs[OP[0]] = 0x8000;
2546 State.regs[OP[0]+1] = 0;
2547 State.F0 = 1;
2548 }
2549 else
2550 {
2551 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2552 State.regs[OP[0]+1] = tmp & 0xffff;
2553 State.F0 = 0;
2554 }
87178dbd 2555 trace_output (OP_DREG);
2934d1c9
MH		 2556}
2557
2558/* subac3s */
2559void
2560OP_17001002 ()
2561{
4f425a32 2562 int64 tmp;
87178dbd
MM		 2563
2564 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
4f425a32
MH		 2565 State.F1 = State.F0;
2566 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2567 if ( tmp > MAX32)
2568 {
2569 State.regs[OP[0]] = 0x7fff;
2570 State.regs[OP[0]+1] = 0xffff;
2571 State.F0 = 1;
2572 }
2573 else if (tmp < MIN32)
2574 {
2575 State.regs[OP[0]] = 0x8000;
2576 State.regs[OP[0]+1] = 0;
2577 State.F0 = 1;
2578 }
2579 else
2580 {
2581 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2582 State.regs[OP[0]+1] = tmp & 0xffff;
2583 State.F0 = 0;
2584 }
87178dbd 2585 trace_output (OP_DREG);
2934d1c9
MH		 2586}
2587
2588/* subi */
2589void
2590OP_1 ()
2591{
f4b022d3 2592 uint16 tmp;
4f425a32
MH		 2593 if (OP[1] == 0)
2594 OP[1] = 16;
87178dbd
MM		 2595
2596 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
f4b022d3
MM		 2597 tmp = State.regs[OP[0]] - OP[1];
2598 State.C = (tmp > State.regs[OP[0]]);
2599 State.regs[OP[0]] = tmp;
87178dbd 2600 trace_output (OP_REG);
2934d1c9
MH		 2601}
2602
2603/* trap */
2604void
2605OP_5F00 ()
2606{
a5719092 2607 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
87178dbd 2608 trace_output (OP_VOID);
8918b3a7 2609
63a91cfb 2610 switch (OP[0])
2934d1c9 2611 {
63a91cfb 2612 default:
19d44375 2613#if 0
7eebfc62 2614 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
63a91cfb 2615 State.exception = SIGILL;
19d44375
MM		 2616#else
2617 /* Use any other traps for batch debugging. */
2618 {
2619 int i;
2620 static int first_time = 1;
2621
2622 if (first_time)
2623 {
2624 first_time = 0;
2625 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2626 for (i = 0; i < 16; i++)
2627 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2628 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2629 }
2630
2631 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2632
2633 for (i = 0; i < 16; i++)
2634 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2635
2636 for (i = 0; i < 2; i++)
2637 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
11ec4de6
MM		 2638 ((int)(State.a[i] >> 32) & 0xff),
2639 ((unsigned long)State.a[i]) & 0xffffffff);
19d44375
MM		 2640
2641 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2642 State.F0 != 0, State.F1 != 0, State.C != 0);
fd435e9f 2643 (*d10v_callback->flush_stdout) (d10v_callback);
19d44375
MM		 2644 break;
2645#endif
63a91cfb
MM		 2646
2647 case 0:
2648 /* Trap 0 is used for simulating low-level I/O */
2649 {
63a91cfb
MM		 2650 errno = 0;
2651
2652/* Registers passed to trap 0 */
2653
65c0d7de
MA		 2654#define FUNC State.regs[6] /* function number */
2655#define PARM1 State.regs[2] /* optional parm 1 */
2656#define PARM2 State.regs[3] /* optional parm 2 */
2657#define PARM3 State.regs[4] /* optional parm 3 */
2658#define PARM4 State.regs[5] /* optional parm 3 */
63a91cfb
MM		 2659
2660/* Registers set by trap 0 */
2661
65c0d7de
MA		 2662#define RETVAL State.regs[2] /* return value */
2663#define RETVAL_HIGH State.regs[2] /* return value */
2664#define RETVAL_LOW State.regs[3] /* return value */
2665#define RETERR State.regs[4] /* return error code */
63a91cfb
MM		 2666
2667/* Turn a pointer in a register into a pointer into real memory. */
2668
c422ecc7 2669#define MEMPTR(x) ((char *)(dmem_addr(x)))
63a91cfb
MM		 2670
2671 switch (FUNC)
2672 {
2673#if !defined(__GO32__) && !defined(_WIN32)
63a91cfb
MM		 2674 case SYS_fork:
2675 RETVAL = fork ();
8918b3a7
MM		 2676 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2677 trace_output (OP_R2);
63a91cfb 2678 break;
8918b3a7 2679
57bc1a72
MM		 2680 case SYS_getpid:
2681 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2682 RETVAL = getpid ();
2683 trace_output (OP_R2);
2684 break;
2685
2686 case SYS_kill:
2687 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2688 if (PARM1 == getpid ())
2689 {
2690 trace_output (OP_VOID);
2691 State.exception = PARM2;
2692 }
2693 else
2694 {
2695 int os_sig = -1;
2696 switch (PARM2)
2697 {
2698#ifdef SIGHUP
2699 case 1: os_sig = SIGHUP; break;
2700#endif
2701#ifdef SIGINT
2702 case 2: os_sig = SIGINT; break;
2703#endif
2704#ifdef SIGQUIT
2705 case 3: os_sig = SIGQUIT; break;
2706#endif
2707#ifdef SIGILL
2708 case 4: os_sig = SIGILL; break;
2709#endif
2710#ifdef SIGTRAP
2711 case 5: os_sig = SIGTRAP; break;
2712#endif
2713#ifdef SIGABRT
2714 case 6: os_sig = SIGABRT; break;
2715#elif defined(SIGIOT)
2716 case 6: os_sig = SIGIOT; break;
2717#endif
2718#ifdef SIGEMT
2719 case 7: os_sig = SIGEMT; break;
2720#endif
2721#ifdef SIGFPE
2722 case 8: os_sig = SIGFPE; break;
2723#endif
2724#ifdef SIGKILL
2725 case 9: os_sig = SIGKILL; break;
2726#endif
2727#ifdef SIGBUS
2728 case 10: os_sig = SIGBUS; break;
2729#endif
2730#ifdef SIGSEGV
2731 case 11: os_sig = SIGSEGV; break;
2732#endif
2733#ifdef SIGSYS
2734 case 12: os_sig = SIGSYS; break;
2735#endif
2736#ifdef SIGPIPE
2737 case 13: os_sig = SIGPIPE; break;
2738#endif
2739#ifdef SIGALRM
2740 case 14: os_sig = SIGALRM; break;
2741#endif
2742#ifdef SIGTERM
2743 case 15: os_sig = SIGTERM; break;
2744#endif
2745#ifdef SIGURG
2746 case 16: os_sig = SIGURG; break;
2747#endif
2748#ifdef SIGSTOP
2749 case 17: os_sig = SIGSTOP; break;
2750#endif
2751#ifdef SIGTSTP
2752 case 18: os_sig = SIGTSTP; break;
2753#endif
2754#ifdef SIGCONT
2755 case 19: os_sig = SIGCONT; break;
2756#endif
2757#ifdef SIGCHLD
2758 case 20: os_sig = SIGCHLD; break;
2759#elif defined(SIGCLD)
2760 case 20: os_sig = SIGCLD; break;
2761#endif
2762#ifdef SIGTTIN
2763 case 21: os_sig = SIGTTIN; break;
2764#endif
2765#ifdef SIGTTOU
2766 case 22: os_sig = SIGTTOU; break;
2767#endif
2768#ifdef SIGIO
2769 case 23: os_sig = SIGIO; break;
2770#elif defined (SIGPOLL)
2771 case 23: os_sig = SIGPOLL; break;
2772#endif
2773#ifdef SIGXCPU
2774 case 24: os_sig = SIGXCPU; break;
2775#endif
2776#ifdef SIGXFSZ
2777 case 25: os_sig = SIGXFSZ; break;
2778#endif
2779#ifdef SIGVTALRM
2780 case 26: os_sig = SIGVTALRM; break;
2781#endif
2782#ifdef SIGPROF
2783 case 27: os_sig = SIGPROF; break;
2784#endif
2785#ifdef SIGWINCH
2786 case 28: os_sig = SIGWINCH; break;
2787#endif
2788#ifdef SIGLOST
2789 case 29: os_sig = SIGLOST; break;
2790#endif
2791#ifdef SIGUSR1
2792 case 30: os_sig = SIGUSR1; break;
2793#endif
2794#ifdef SIGUSR2
2795 case 31: os_sig = SIGUSR2; break;
2796#endif
2797 }
2798
2799 if (os_sig == -1)
2800 {
2801 trace_output (OP_VOID);
2802 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
fd435e9f 2803 (*d10v_callback->flush_stdout) (d10v_callback);
57bc1a72
MM		 2804 State.exception = SIGILL;
2805 }
2806 else
2807 {
2808 RETVAL = kill (PARM1, PARM2);
2809 trace_output (OP_R2);
2810 }
2811 }
2812 break;
2813
63a91cfb
MM		 2814 case SYS_execve:
2815 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2816 (char **)MEMPTR (PARM3));
8918b3a7
MM		 2817 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2818 trace_output (OP_R2);
63a91cfb 2819 break;
8918b3a7 2820
63a91cfb
MM		 2821 case SYS_execv:
2822 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
8918b3a7
MM		 2823 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2824 trace_output (OP_R2);
63a91cfb 2825 break;
8918b3a7 2826
63a91cfb
MM		 2827 case SYS_pipe:
2828 {
2829 reg_t buf;
2830 int host_fd[2];
2831
2832 buf = PARM1;
2833 RETVAL = pipe (host_fd);
2834 SW (buf, host_fd[0]);
2835 buf += sizeof(uint16);
2836 SW (buf, host_fd[1]);
8918b3a7
MM		 2837 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2838 trace_output (OP_R2);
63a91cfb
MM		 2839 }
2840 break;
8918b3a7 2841
63a91cfb
MM		 2842 case SYS_wait:
2843 {
2844 int status;
2845
2846 RETVAL = wait (&status);
8918b3a7
MM		 2847 if (PARM1)
2848 SW (PARM1, status);
2849 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2850 trace_output (OP_R2);
63a91cfb
MM		 2851 }
2852 break;
57bc1a72
MM		 2853#else
2854 case SYS_getpid:
2855 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2856 RETVAL = 1;
2857 trace_output (OP_R2);
2858 break;
2859
2860 case SYS_kill:
2861 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2862 trace_output (OP_VOID);
2863 State.exception = PARM2;
2864 break;
63a91cfb 2865#endif
8918b3a7 2866
63a91cfb
MM		 2867 case SYS_read:
2868 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2869 PARM3);
8918b3a7
MM		 2870 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2871 trace_output (OP_R2);
63a91cfb 2872 break;
8918b3a7 2873
63a91cfb
MM		 2874 case SYS_write:
2875 if (PARM1 == 1)
2876 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2877 MEMPTR (PARM2), PARM3);
2878 else
2879 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2880 MEMPTR (PARM2), PARM3);
8918b3a7
MM		 2881 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2882 trace_output (OP_R2);
63a91cfb 2883 break;
8918b3a7 2884
63a91cfb 2885 case SYS_lseek:
65c0d7de
MA		 2886 {
2887 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2888 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2889 PARM4);
2890 RETVAL_HIGH = ret >> 16;
2891 RETVAL_LOW = ret & 0xffff;
2892 }
8918b3a7
MM		 2893 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2894 trace_output (OP_R2R3);
63a91cfb 2895 break;
8918b3a7 2896
63a91cfb
MM		 2897 case SYS_close:
2898 RETVAL = d10v_callback->close (d10v_callback, PARM1);
8918b3a7
MM		 2899 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2900 trace_output (OP_R2);
63a91cfb 2901 break;
8918b3a7 2902
63a91cfb
MM		 2903 case SYS_open:
2904 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2905 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2906 trace_output (OP_R2);
2907 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2908 trace_output (OP_R2);
63a91cfb 2909 break;
8918b3a7 2910
63a91cfb 2911 case SYS_exit:
a49a15ad 2912 State.exception = SIG_D10V_EXIT;
8918b3a7
MM		 2913 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2914 trace_output (OP_VOID);
63a91cfb 2915 break;
63a91cfb 2916
8719be26 2917 case SYS_stat:
63a91cfb
MM		 2918 /* stat system call */
2919 {
2920 struct stat host_stat;
2921 reg_t buf;
2922
2923 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2924
2925 buf = PARM2;
2926
2927 /* The hard-coded offsets and sizes were determined by using
2928 * the D10V compiler on a test program that used struct stat.
2929 */
2930 SW (buf, host_stat.st_dev);
2931 SW (buf+2, host_stat.st_ino);
2932 SW (buf+4, host_stat.st_mode);
2933 SW (buf+6, host_stat.st_nlink);
2934 SW (buf+8, host_stat.st_uid);
2935 SW (buf+10, host_stat.st_gid);
2936 SW (buf+12, host_stat.st_rdev);
2937 SLW (buf+16, host_stat.st_size);
2938 SLW (buf+20, host_stat.st_atime);
2939 SLW (buf+28, host_stat.st_mtime);
2940 SLW (buf+36, host_stat.st_ctime);
2941 }
8918b3a7
MM		 2942 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2943 trace_output (OP_R2);
63a91cfb 2944 break;
63a91cfb 2945
63a91cfb
MM		 2946 case SYS_chown:
2947 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
8918b3a7
MM		 2948 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2949 trace_output (OP_R2);
63a91cfb 2950 break;
8918b3a7 2951
63a91cfb
MM		 2952 case SYS_chmod:
2953 RETVAL = chmod (MEMPTR (PARM1), PARM2);
8918b3a7
MM		 2954 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2955 trace_output (OP_R2);
63a91cfb 2956 break;
8918b3a7 2957
63a91cfb
MM		 2958 case SYS_utime:
2959 /* Cast the second argument to void *, to avoid type mismatch
2960 if a prototype is present. */
2961 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
8918b3a7
MM		 2962 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2963 trace_output (OP_R2);
2964 break;
2965
2966 case SYS_time:
2967 {
2968 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2969 RETVAL_HIGH = ret >> 16;
2970 RETVAL_LOW = ret & 0xffff;
2971 }
2972 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2973 trace_output (OP_R2R3);
63a91cfb 2974 break;
8918b3a7 2975
63a91cfb
MM		 2976 default:
2977 abort ();
2978 }
65c0d7de 2979 RETERR = d10v_callback->get_errno(d10v_callback);
63a91cfb
MM		 2980 break;
2981 }
2982
2983 case 1:
2984 /* Trap 1 prints a string */
2985 {
c422ecc7 2986 char *fstr = dmem_addr(State.regs[2]);
63a91cfb
MM		 2987 fputs (fstr, stdout);
2988 break;
2989 }
2990
2991 case 2:
2992 /* Trap 2 calls printf */
2993 {
c422ecc7 2994 char *fstr = dmem_addr(State.regs[2]);
7eebfc62
MM		 2995 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2996 (int16)State.regs[3],
2997 (int16)State.regs[4],
2998 (int16)State.regs[5]);
fd435e9f 2999 (*d10v_callback->flush_stdout) (d10v_callback);
63a91cfb
MM		 3000 break;
3001 }
3002
3003 case 3:
3004 /* Trap 3 writes a character */
3005 putchar (State.regs[2]);
3006 break;
19d44375 3007 }
2934d1c9
MH		 3008 }
3009}
3010
3011/* tst0i */
3012void
3013OP_7000000 ()
3014{
87178dbd 3015 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3016 State.F1 = State.F0;
4f425a32 3017 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
87178dbd 3018 trace_output (OP_FLAG);
2934d1c9
MH		 3019}
3020
3021/* tst1i */
3022void
3023OP_F000000 ()
3024{
87178dbd 3025 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
4c38885c 3026 State.F1 = State.F0;
4f425a32 3027 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
87178dbd 3028 trace_output (OP_FLAG);
2934d1c9
MH		 3029}
3030
3031/* wait */
3032void
3033OP_5F80 ()
3034{
87178dbd 3035 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
4c38885c 3036 State.IE = 1;
87178dbd 3037 trace_output (OP_VOID);
2934d1c9
MH		 3038}
3039
3040/* xor */
3041void
3042OP_A00 ()
3043{
87178dbd 3044 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
4c38885c 3045 State.regs[OP[0]] ^= State.regs[OP[1]];
87178dbd 3046 trace_output (OP_REG);
2934d1c9
MH		 3047}
3048
3049/* xor3 */
3050void
3051OP_5000000 ()
3052{
87178dbd 3053 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
4c38885c 3054 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
87178dbd 3055 trace_output (OP_REG);
2934d1c9
MH		 3056}
3057
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