]> Git Repo - binutils.git/blame - gdb/i860-tdep.c
projects / binutils.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add Adobe a.out support.
[binutils.git] / gdb / i860-tdep.c
CommitLineData
67278683
FF		 1/* Machine-dependent code which would otherwise be in inflow.c and core.c,
2 for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987 Free Software Foundation, Inc.
4 This code is for the i860 cpu.
be9a2362
FF		 5
6 GDB is distributed in the hope that it will be useful, but WITHOUT ANY
7 WARRANTY. No author or distributor accepts responsibility to anyone
8 for the consequences of using it or for whether it serves any
9 particular purpose or works at all, unless he says so in writing.
10 Refer to the GDB General Public License for full details.
11
12 Everyone is granted permission to copy, modify and redistribute GDB,
13 but only under the conditions described in the GDB General Public
14 License. A copy of this license is supposed to have been given to you
15 along with GDB so you can know your rights and responsibilities. It
16 should be in a file named COPYING. Among other things, the copyright
17 notice and this notice must be preserved on all copies.
18
19 In other words, go ahead and share GDB, but don't try to stop
20 anyone else from sharing it farther. Help stamp out software hoarding!
21 */
67278683 22#include <stdio.h>
2213b721
FF		 23#include <stdlib.h>
24#include <stdarg.h>
25
be9a2362 26
67278683 27#include "defs.h"
be9a2362
FF		 28#include "tm-i860.h"
29#include "frame.h"
30#include "inferior.h"
31#include "obstack.h"
32#include "symtab.h"
33#include "value.h"
34
be9a2362
FF		 35#include "i860-opcode.h"
36
67278683
FF		 37#include "breakpoint.h"
38#include "i860-break.h"
2213b721 39#include "command.h"
67278683 40#include "target.h"
be9a2362
FF		 41
42#ifdef notdef
be9a2362
FF		 43#include <sys/types.h>
44#include <sys/param.h>
45#include <sys/dir.h>
be9a2362
FF		 46#endif
47
48#include <signal.h>
49#include <sys/ioctl.h>
50#include <fcntl.h>
51
52/* #include <sys/reg.h> */
53#include "i860_reg.h"
54
55#include <a.out.h>
56#include <sys/file.h>
be9a2362
FF		 57#include <core.h>
58
59#include <sys/user.h>
be9a2362
FF		 60#include <elf.h>
61#include <sys/elftypes.h>
62#include <sys/elf_860.h>
63#include <libelf.h>
64
65
2213b721
FF		 66extern int read_memory();
67extern int write_memory();
68extern int read_memory_integer();
69extern int print_insn();
70extern void bzero();
71extern void bcopy();
2213b721 72
be9a2362 73int btdebug = 0; /* change value to 1 to enable debugging code */
67278683 74int ansi_conformant;
be9a2362
FF		 75
76#define BTDEBUG if (btdebug) btdebug_message
77
2213b721
FF		 78extern int errno;
79extern int attach_flag;
67278683 80extern char registers[];
ca8820f9 81CORE_ADDR get_saved_basereg();
be9a2362 82
2213b721
FF		 83#define INSTRUCTION_LENGTH 4
84#define REGISTER_LENGTH 4
67278683
FF		 85#define ALIGN_ARG(size,len) ((size + (len-1))&(-len))
86#define NUM_FLOAT_ARG_REGS 8
87#define NUM_INT_ARG_REGS 12
be9a2362 88
2213b721
FF		 89/* routine to print debugging messages */
90void btdebug_message(char *format, ...)
be9a2362
FF		 91{
92 va_list arglist;
93 va_start( arglist, format );
94
95 if( btdebug )
96 vfprintf (stderr, format, arglist );
97 va_end ( arglist );
98}
99
67278683
FF		 100\f
101/* Peggy Fieland. Routine that attempts to find the start of the entry sequence
102 for a routine. */
103/* maximum number of instrutions to search back */
104#define MAX_ROUTINE_SIZE 4096
105CORE_ADDR find_entry_start(pc)
106CORE_ADDR pc;
107{
108 CORE_ADDR instr, top_pc;
109 int i;
110
111 top_pc = pc;
112 for (i = 0; i < MAX_ROUTINE_SIZE; ++i)
113
114 {
115 instr = (unsigned)( adj_read_memory_integer (top_pc));
116 /* Recognize "addu|adds -X,sp,sp" insn. */
117
118 if ((instr & 0xEFFF0000) == 0x84420000)
119 {
120 return (top_pc);
121 }
122 top_pc -= INSTRUCTION_LENGTH;
123 }
124 return (0);
125}
126
127
128\f
129/* Written by Peggy Fieland ([email protected]) */
130/* get the contents of a base register. Used for dwarf OP_BASEREG */
131/* At present, only OP_BASEREG generated is for R28. NOTE that for stuff based on R28,
132 the value we want is the VALUE AT PROCEDURE INVOKATION, and thus is the frame we
133 use to get the value is the caller's frame. */
134CORE_ADDR get_saved_basereg (frame, basereg)
135FRAME frame;
136int basereg;
137{
138 CORE_ADDR addr;
139 if (basereg == R28) /* Unconditionally ??? */
140 {
141 frame = get_prev_frame (frame);
142 get_saved_register((char *) &addr, (int *) NULL, (CORE_ADDR *) NULL, frame,
143 basereg, (enum lval_type *)NULL);
144
145 }
146 else
147 get_saved_register((char *) &addr, (int *) NULL, (CORE_ADDR *) NULL, frame,
148 basereg, (enum lval_type *)NULL);
149
150 return (addr);
151}
152
be9a2362
FF		 153\f
154
155/* return nonzero if the routine containing pc has been
156 * compiled with -g. We assume -g if the first instruction is
157 * an addu|adds -X,sp and the second is st.l fp,XX(sp)
158 *
159 * based on skip_prologue();
160 */
161
2213b721 162static int g_routine(pc)
67278683 163
be9a2362
FF		 164 CORE_ADDR pc;
165{
2213b721 166 CORE_ADDR instr;
be9a2362
FF		 167 CORE_ADDR top_pc;
168
169 top_pc = get_pc_function_start(pc);
67278683
FF		 170 if (top_pc == NULL)
171 top_pc = find_entry_start (pc);
172
2213b721 173 if (top_pc != NULL)
be9a2362 174 {
2213b721 175 instr = (unsigned)( adj_read_memory_integer (top_pc));
be9a2362
FF		 176 /* Recognize "addu|adds -X,sp,sp" insn. */
177
178 if ((instr & 0xEFFF0000) == 0x84420000)
179 {
2213b721
FF		 180 top_pc += INSTRUCTION_LENGTH;
181 instr = (unsigned)(adj_read_memory_integer (top_pc));
be9a2362
FF		 182
183 if( (instr & 0xFFE0F801) == 0x1C401801 ) /* st.l fp,X(sp) */
184 return(1);
185 }
186 }
187 return(0);
188}
189
190
2213b721
FF		 191/* return the stack offset where the fp register is stored */
192static int find_fp_offset(pc)
be9a2362
FF		 193CORE_ADDR pc;
194{
2213b721
FF		 195 int fp_off,i;
196 CORE_ADDR instr;
be9a2362 197
2213b721 198 /* look for the instruction and examine the offset */
be9a2362 199
2213b721
FF		 200 for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH){
201 instr = (unsigned)(adj_read_memory_integer(pc+i));
202 if( (instr & 0xFFE0F801) == 0x1C401801) { /* st.l fp,X(sp) */
203
204 fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) |
205 (instr&0x000007FE));
206 return(fp_off);
be9a2362 207 }
2213b721
FF		 208 }
209 return(0);
210}
211
67278683 212
2213b721 213/* return the stack offset where r1 (return linkage ) register is stored */
67278683
FF		 214static CORE_ADDR find_r1(pc,sp,fp)
215CORE_ADDR pc,sp, fp;
2213b721
FF		 216{
217 int r1_off,i;
67278683 218 CORE_ADDR instr, ret_pc;
be9a2362 219
2213b721 220 /* look for the instruction and examine the offset */
be9a2362 221
67278683
FF		 222 for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH)
223 {
224 instr = (unsigned)( adj_read_memory_integer(pc+i));
225 if ((instr & 0xFFE0F801) == 0x1C400801)
226 {
227 /* st.l r1,X(sp) */
2213b721 228
67278683
FF		 229 r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) |
230 (instr&0x000007FE));
231 ret_pc = read_memory_integer(sp+r1_off,sizeof(long));
232 return(ret_pc);
233 }
234 else if ((instr & 0xFFE0F801) == 0x1C600801)
235 {
236 /* st.l r1,X(fp) */
237 r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) |
238 (instr&0x000007FE));
239 ret_pc = read_memory_integer(fp+r1_off,sizeof(long));
240 return(ret_pc);
241 }
be9a2362 242 }
67278683 243 return(0);
be9a2362
FF		 244}
245
2213b721 246CORE_ADDR skip_prologue(CORE_ADDR);
be9a2362 247
2213b721
FF		 248/* does routine starting at pc build a stack frame of any kind?? */
249static int has_a_frame(pc)
250CORE_ADDR pc;
251{
252 if( skip_prologue(pc) != pc )return(1);
253 else return(0);
254}
be9a2362
FF		 255
256
2213b721
FF		 257/* written by Peggy Fieland [email protected]
258 Routine to validate the return register and the frame pointer
259 This routine is called when the routine we are in doesn't have a frame
260 In that case, we assume that the return address and frame pointer have
261 not been touched. In the following routine, we try to range check them
262 to see if they are valid. */
263
264static int valid_regs (rp, fp)
265CORE_ADDR rp, fp;
be9a2362 266{
2213b721
FF		 267 if ( ( (rp % 4) != 0) | ( (fp % 16) != 0) )
268 return (0);
269 else
270 return (1);
be9a2362 271}
2213b721
FF		 272/* get the pc and frame pointer (or sp )
273 * for the routine that called us
274 * when we (this_pc) is not within a -g routine
275 * if caller is non g we return sp for fp
276 */
be9a2362 277
2213b721
FF		 278/* note this is written for Metaware version R2.1d compiler */
279/* Modified by Peggy Fieland [email protected] */
67278683
FF		 280static int caller_pc(this_pc,this_sp,this_fp,to_pc,to_fp, called_from_frame_chain)
281 CORE_ADDR this_pc,this_sp, this_fp;
2213b721 282 CORE_ADDR *to_pc, *to_fp;
67278683 283 int called_from_frame_chain;
be9a2362 284{
2213b721
FF		 285 CORE_ADDR func_start;
286 int sp_offset,offset;
287 CORE_ADDR sp,pc,fp,instr;
be9a2362 288
2213b721 289 BTDEBUG("caller_pc %x sp = %x\n",this_pc,this_sp);
be9a2362 290
2213b721
FF		 291 func_start = get_pc_function_start(this_pc);
292
67278683
FF		 293 if (func_start == NULL)
294 func_start = find_entry_start (this_pc);
295
2213b721
FF		 296 BTDEBUG("caller_pc func_start %x\n", func_start);
297
67278683
FF		 298 if ((func_start == NULL))
299 {
300 /* error in traceback */
301 fprintf(stderr, "error, unable to find start of function\n");
302 return(0);
303
304 }
305
2213b721 306 if (func_start!= NULL)
be9a2362
FF		 307 {
308 if( has_a_frame(func_start) ){
309
310 BTDEBUG("has_a_frame\n");
311
312 /* if our caller has a preamble and
313 * declares space for a stack frame
314 * then we must work to find our return address
315 */
2213b721 316 instr = (unsigned)( adj_read_memory_integer (func_start));
be9a2362
FF		 317 /* Recognize "addu|adds -X,sp,sp" insn. */
318
319 if ((instr & 0xEFFF0000) == 0x84420000)
320 sp_offset=SIGN_EXT16(instr&0x0000FFFF);
321 }
2213b721
FF		 322 else
323 {
67278683 324 /* if we get here, procedure doesn't have a frame. If we
2213b721
FF		 325 do anything weird, the frame pointer and return register have
326 the values we want. Check them to see if they are valid. */
327
328 CORE_ADDR temp_rp, temp_fp;
329
67278683
FF		 330 /* temporary warning, since at the moment we don't have support for
331 the shared library */
332
2213b721
FF		 333 temp_rp = read_register(RP_REGNUM);
334 temp_fp = read_register(FP_REGNUM);
335
336 if (!valid_regs(temp_rp, temp_fp))
337 {
67278683
FF		 338 fprintf(stderr,
339 "error - unable to find return address, traceback terminating\n");
2213b721
FF		 340 return(0);
341 }
342 BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n",
343 temp_rp, temp_fp);
344 *to_pc = temp_rp;
345 *to_fp = temp_fp;
346 return (1);
347 }
be9a2362
FF		 348
349 BTDEBUG("sp_offset = %d %x\n",sp_offset,sp_offset);
350
67278683 351 pc = find_r1(func_start, this_sp, this_fp);
be9a2362 352
67278683
FF		 353 if(pc == NULL)
354 {
355
356 /* r1 wasn't stored between pc and function start */
357 pc = read_register (RP_REGNUM);
358 }
359
be9a2362
FF		 360 sp= this_sp - sp_offset;
361
362 BTDEBUG("callers pc = %x sp = %x\n",pc,sp);
363
364 /* our caller a -g routine ?
365 * if he is we have to find his real fp
366 * else provide the sp as his fp
367 */
368
369 if( g_routine(pc) ){
370
371 BTDEBUG("caller_a_g\n");
372
373 if( ! (offset = find_fp_offset(func_start)) ) {
67278683
FF		 374 fprintf(stderr, "error - unable to find caller frame for routine at 0x%x, "
375 "traceback terminating\n", func_start);
be9a2362
FF		 376 return(0);
377 }
378 BTDEBUG("offset = %x %d\n",offset,offset);
379
2213b721 380 fp = read_memory_integer(this_sp+offset,sizeof(long));
be9a2362
FF		 381 *to_pc = CLEAN_PC(pc);
382 *to_fp = fp;
383 return(1);
384 }else
385 *to_pc = CLEAN_PC(pc);
386 *to_fp = sp;
387 return(1);
388 } else {
389/* pc = read_register(RP_REGNUM); */
2213b721
FF		 390/* pc = 0; */
391 /* if we get here, procedure doesn't have a frame. If we didn't
392 do anything weird, the frame pointer and return register have
393 the values we want. Check them to see if they are valid. */
394
395 CORE_ADDR temp_rp, temp_fp;
396
397 temp_rp = read_register(RP_REGNUM);
398 temp_fp = read_register(FP_REGNUM);
399
400 if (!valid_regs(temp_rp, temp_fp))
401 {
67278683
FF		 402 fprintf(stderr,
403 "error - unable to find return address, traceback terminating\n");
404
2213b721
FF		 405 return(0);
406 }
407 BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n",
408 temp_rp, temp_fp);
409 *to_pc = temp_rp;
410 *to_fp = temp_fp;
411 return (1);
be9a2362
FF		 412 }
413}
414
2213b721
FF		 415/*
416 ** Figure out address to place next breakpoint. Avoid tricky spots,
417 ** ie. delayed instruction slots etc.
418 ** Need to upgrade this later to allow delayed instruction breakpoints
419 ** with fix-up work done AFTER breakpoint.
420 ** Note that this routine DOES deal with dual instruction mode
421 */
422#define BIM 0x8008
be9a2362 423
2213b721
FF		 424static branch_type
425 place_brk (addr, mode, brk)
426CORE_ADDR addr;
427int mode;
428struct breakpoint *brk;
be9a2362 429{
2213b721
FF		 430 CORE_ADDR instr;
431 CORE_ADDR nextadr, prevadr;
be9a2362
FF		 432 int val = not_branch;
433 long offset; /* Must be signed for sign-extend */
be9a2362
FF		 434 prevadr = nextadr = 0;
435
436 brk->address1 = 0;
437
438 if (mode == SINGLE_STEP_MODE)
439 {
440 if (INDIM || ENDIM)
441 {
2213b721
FF		 442 nextadr = brk->address = (addr + INSTRUCTION_LENGTH*2);
443 instr = (unsigned)(adj_read_memory_integer ((addr + INSTRUCTION_LENGTH)));
be9a2362
FF		 444 brk->mode = DIM;
445 }
446 else
447 {
2213b721
FF		 448 nextadr = brk->address = (addr + INSTRUCTION_LENGTH);
449 instr = (unsigned)(adj_read_memory_integer (addr));
be9a2362
FF		 450 if (STDIM)
451 brk->mode = DIM;
452 else
453 brk->mode = SIM;
454 }
455
456
457 /*
458 ** For br/call one more sequential instruction gets executed and then we
459 ** continue at the current addr + offset. We are definitely going to
460 ** the dest. We are NOT allowed to place a breakpoint in the "delay"
461 ** slot - (the next sequential instruction) so we only place 1 breakpoint
462 ** at the destination.
463 ** For the bc/bnc the next instruction executed is EITHER the next sequential
464 ** or the destination of the branch, we therefore place 2 breakpoints one
465 ** at each location.
466 ** For the bc.t/bnc.t either 1 more sequential instruction is performed
467 ** followed by a branch (like br/call) OR we skip the sequential
468 ** instruction and keep going. We therefore place a breakpoint at the
469 ** destination of the branch AND the second sequential instruction after
470 ** the branch. Again a breakpoint is NOT allowed in the "delay slot"
471 */
472 if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */
473 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
474 {
475 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
476 val = uncond_d;
477 else if ((instr & 0xF4000000) == 0x74000000) /* bc.t/bnc.t */
478 val = cond_d;
479 else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */
480 val = cond;
481 offset = (instr & 0x03ffffff);
482 if (offset & 0x02000000) /*?sign extend*/
483 offset |= 0xFC000000;
484 if (val == uncond_d) /* br/call*/
485 prevadr = 0;
486 else if (val == cond_d) /* bc.t/bnc.t */
487 {
488 if ((INDIM) && !(ENDIM))
2213b721 489 prevadr = nextadr + (2*INSTRUCTION_LENGTH);
be9a2362 490 else
2213b721 491 prevadr = nextadr + INSTRUCTION_LENGTH;
be9a2362
FF		 492 } else { /* bc /bnc */
493 if ((INDIM) && !(ENDIM))
494 prevadr = nextadr;
495 else
496 prevadr = nextadr;
497 }
498 nextadr += (offset << 2);
499 }
500 /*
501 ** We treat the bri/calli the same way as the br/call case.
502 */
503 else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */
504 (instr & 0xFC000000) == 0x40000000) /* bri */
505 {
506 val = uncond_d;
507 offset = ((instr & 0x0000F800) >> 11);
508 nextadr = (read_register(offset + R0) & 0xFFFFFFFC);
509 prevadr = 0;
510 }
511 /*
512 ** We treat the bte/btne the same way as the bc/bnc case.
513 */
514 else if ((instr & 0xF0000000) == 0x50000000) /* bte/btne */
515 {
516 val = cond;
517 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) |
518 (instr & 0x000007FF));
519 if ((INDIM) && !(ENDIM))
520 prevadr = nextadr;
521 else
522 prevadr = nextadr;
523
524 nextadr += (offset << 2);
525 }
526 /*
527 ** We treat the bte/btne the same way as the bc/bnc case.
528 ** With the caveat that the 2 breakpoints may turn out to be at the same
529 ** address in which case we ignore one of them.
530 */
531 else if ((instr & 0xFC000000) == 0xB4000000) /* bla */
532 {
533 val = cond_d;
534 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) |
535 (instr & 0x000007FF));
536 if ((INDIM) && !(ENDIM))
537 {
2213b721 538 prevadr = nextadr + 2*INSTRUCTION_LENGTH;
be9a2362 539 } else {
2213b721 540 prevadr = nextadr + INSTRUCTION_LENGTH;
be9a2362
FF		 541 }
542 nextadr += (offset << 2);
543 if (prevadr == nextadr) prevadr = 0;
544 }
545 } else {
546 int adjust = 0;
547
548 nextadr = addr;
549
550 if (ISDIM(FOPADR(addr)))
551 {
2213b721 552 if (ISDIM(FOPADR(nextadr- INSTRUCTION_LENGTH*2)))
be9a2362 553 {
2213b721
FF		 554 instr = (unsigned)(adj_read_memory_integer(CORADR(addr
555 -(INSTRUCTION_LENGTH*2))));
be9a2362
FF		 556 brk->mode = DIM;
557 } else {
2213b721 558 instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH));
be9a2362
FF		 559 brk->mode = RIM;
560 }
561 } else {
2213b721 562 if (ISDIM(addr-INSTRUCTION_LENGTH))
be9a2362 563 {
2213b721 564 instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH));
be9a2362
FF		 565 brk->mode = BIM;
566 } else {
2213b721 567 instr = (unsigned)(adj_read_memory_integer (addr-INSTRUCTION_LENGTH));
be9a2362
FF		 568 brk->mode = SIM;
569 }
570 }
571
572 /* examine the PREVIOUS instruction to determine if we are in a branch delay
573 slot. If we are, dont set a break here -- set it on the previous instruction.
574 This code also accounts for dual instruction mode */
575 if ((instr & 0xE0000000) == 0x60000000 &&
576 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
577 {
2213b721
FF		 578 adjust++;
579 /* br /call */
580 /* bc /bnc */
581 /* bc.t /bnc.t*/
582 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
67278683 583 BTDEBUG(" Breakpoint adjusted to avoid br/call delay slot and multiple breakpoints\n");
2213b721
FF		 584
585 if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */
67278683
FF		 586 BTDEBUG(" Breakpoint adjusted to avoid bc.t/bnc.t delay slot and"
587 "multiple breakpoints\n");
588
2213b721
FF		 589 /* it IS really OK to set a break on the instruction AFTER the conditional branch
590 -- it DOESN't have a delay slot */
591 if ((instr & 0xF4000000) == 0x70000000) /* bc / bnc */
2213b721
FF		 592 adjust = 0;
593 } else if
594 ((instr & 0xFC00003F) == 0x4C000002 || /* bri/ calli */
595 (instr & 0xFC000000) == 0x40000000)
596 {
597 adjust++;
67278683
FF		 598 BTDEBUG(" Breakpoint adjusted to avoid calli/bri delay slot and"
599 " multiple breakpoints\n");
2213b721
FF		 600 } else if
601 ((instr & 0xF0000000) == 0x50000000) /* bte - btne */
602 {
603 /* it's OK to set a break here -- we are NOT in aa branch delay slot */
604 /*
605 adjust++;
606 printf(" Breakpoint adjusted to avoid bte/btne multiple breakpoints\n");
607 */
608 adjust = 0;
609 } else if
610 ((instr & 0xFC000000) == 0xB4000000)
611 {
612 adjust++;
67278683
FF		 613 BTDEBUG(" Breakpoint adjusted to avoid bla delay slot and"
614 " multiple breakpoints\n");
2213b721
FF		 615 }
616 if (adjust != 0)
617 {
618 if (brk->mode == DIM)
619 {
620 nextadr -= INSTRUCTION_LENGTH*2;
621 nextadr = CORADR(nextadr);
622 }
623 else
624 nextadr -= INSTRUCTION_LENGTH;
625 }
626
627 }
628
629 if (brk->mode == RIM)
630 brk->mode = DIM;
631 if (brk->mode == BIM)
632 brk->mode = SIM;
633
634 if (nextadr != NULL)
635 {
636 if (brk->mode == DIM)
637 {
638 brk->act_addr[0] = CORADR(nextadr);
639 brk->act_addr[1] = FOPADR(nextadr);
640 } else {
641 brk->act_addr[0] = nextadr;
642 brk->act_addr[1] = 0;
643 }
644 }
645
646 if (prevadr != NULL)
647 {
648 brk->address1 = prevadr;
649 if (brk->mode == DIM)
650 {
651 brk->act_addr[2] = CORADR(prevadr);
652 brk->act_addr[3] = FOPADR(prevadr);
653 } else {
654 brk->act_addr[2] = prevadr;
655 brk->act_addr[3] = 0;
656 }
657 } else {
658 brk->act_addr[2] = brk->act_addr[3] = 0;
659 }
660 return val;
661}
662
663/* This routine checks to see if r1 has been stored into the frame between
664 the addresses prologue_start and prologue_end. Recognize stores of r1
665 relative to both the sp and fp registers. */
666static int has_stored_r1(CORE_ADDR prologue_start, CORE_ADDR prologue_end)
667{
668 CORE_ADDR instr;
669 CORE_ADDR addr;
670
671 BTDEBUG("has_stored_r1, prologue_start %x, prologue_end %x\n",
672 prologue_start, prologue_end);
673
674 for (addr = prologue_start; addr <= prologue_end; addr += INSTRUCTION_LENGTH)
675 {
676
677 instr = (unsigned)(adj_read_memory_integer (addr));
678 if ((instr & 0xFFE0F801) == 0x1C400801 /* st.l r1,X(sp) */
679 || (instr & 0xFFE0F801) == 0x1C600801) /* st.l r1,X(fp) */
680 return (1);
681 }
682 return 0;
683}
684/* This is used when GDB is exiting. It gives less chance of error.*/
685
686
687/* Simulate single-step ptrace call for sun4. Code written by Gary
688 Beihl ([email protected]). */
689/* Modified for i860 by Jim Hanko ([email protected]) */
690
691
692static struct breakpoint brk;
693typedef char binsn_quantum[sizeof break_insn];
694
695/* Non-zero if we just simulated a single-step ptrace call. This is
696 needed because we cannot remove the breakpoints in the inferior
697 process until after the `wait' in `wait_for_inferior'. Used for
698 i860. */
699
700int one_stepped;
701
702/* single_step() is called just before we want to resume the inferior,
703 if we want to single-step it but there is no hardware or kernel single-step
704 support. We find all the possible targets of the coming instruction and
705 breakpoint them.
706
707 single_step is also called just after the inferior stops. If we had
708 set up a simulated single-step, we undo our damage. */
709/* Note that we don't need the parameter, but it's dictated as part of the interface. */
710void
711 single_step (signal)
712int signal;
713{
714 CORE_ADDR pc;
715 branch_type place_brk();
67278683
FF		 716 int *shadow0, *shadow1, *shadow2, *shadow3;
717
718 shadow0 = (int *) &brk.shadow_contents[0];
719 shadow1 = (int *) &brk.shadow_contents[4];
720 shadow2 = (int *) &brk.shadow_contents[8];
721 shadow3 = (int *) &brk.shadow_contents[12];
2213b721
FF		 722 pc = read_register (PC_REGNUM);
723
724 if (!one_stepped)
725 {
726 brk.address = pc;
727 place_brk (pc, SINGLE_STEP_MODE, &brk);
67278683 728 *shadow0 = *shadow1 = *shadow2 = *shadow3 = 0;
2213b721
FF		 729
730 if (brk.mode == DIM)
731 {
732 if (btdebug != 0)
733 {
734 btdebug_message(" DIM1 -> %x : ", brk.act_addr[3]);
735 print_insn( brk.act_addr[3], stderr);
736 btdebug_message("\t -|- %x : ", brk.act_addr[2]);
737 print_insn( brk.act_addr[2], stderr);
738 btdebug_message("\n");
739 }
740 if (( brk.address1 != NULL))
741 {
67278683 742 adj_read_memory (brk.act_addr[2], shadow2,
2213b721
FF		 743 INSTRUCTION_LENGTH);
744 adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH);
67278683 745 adj_read_memory (brk.act_addr[3], shadow3,
2213b721
FF		 746 INSTRUCTION_LENGTH);
747 /* adj_write_memory (brk.act_addr[3], float_insn,
748 INSTRUCTION_LENGTH); */
749
750 }
751 if (btdebug != 0)
752 {
753 if ( brk.address1 != 0)
754 btdebug_message(" DIM2 ->");
755 else
756 btdebug_message(" DIM1 ->");
757
758 btdebug_message(" %x : ", brk.act_addr[1]);
759 print_insn( brk.act_addr[1], stderr);
760 btdebug_message("\t -|- %x : ", brk.act_addr[0]);
761 print_insn( brk.act_addr[0], stderr);
762 btdebug_message("\n");
763 }
764
67278683 765 adj_read_memory (brk.act_addr[0], shadow0,
2213b721
FF		 766 INSTRUCTION_LENGTH);
767 adj_write_memory (brk.act_addr[0], break_insn,
768 INSTRUCTION_LENGTH);
67278683 769 adj_read_memory (brk.act_addr[1], shadow1,
2213b721
FF		 770 INSTRUCTION_LENGTH);
771 /* adj_write_memory (brk.act_addr[1], float_insn,
772 INSTRUCTION_LENGTH); */
773
774 }
775 else {
776 if (brk.address1 != NULL)
777 {
778 if (btdebug)
779 {
780 btdebug_message(" SIM1 ->");
781 btdebug_message(" %x : ", brk.act_addr[2]);
782 print_insn( brk.act_addr[2], stderr);
783 btdebug_message("\n");
784 }
67278683 785 adj_read_memory (brk.act_addr[2], shadow2,
2213b721
FF		 786 INSTRUCTION_LENGTH);
787 adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH);
788 }
789 if (btdebug)
790 {
791 if ( brk.address1 != NULL)
792 btdebug_message(" SIM2 ->");
793 else
794 btdebug_message(" SIM1 ->");
795
796 btdebug_message(" %x : ", brk.act_addr[0]);
797 print_insn( brk.act_addr[0], stderr);
798 btdebug_message("\n");
799 }
67278683 800 adj_read_memory (brk.act_addr[0], shadow0,
2213b721
FF		 801 INSTRUCTION_LENGTH);
802 adj_write_memory (brk.act_addr[0], break_insn,INSTRUCTION_LENGTH);
803 }
804
805 /* Let it go */
806 one_stepped = 1;
807 return;
808 }
809 else
810 {
811 /* Remove breakpoints */
812 if (brk.mode == DIM)
813 {
67278683 814 adj_write_memory (brk.act_addr[0], shadow0,
2213b721 815 INSTRUCTION_LENGTH);
67278683 816 adj_write_memory (brk.act_addr[1], shadow1,
2213b721
FF		 817 INSTRUCTION_LENGTH);
818 } else {
67278683 819 adj_write_memory (brk.act_addr[0], shadow0,
2213b721
FF		 820 INSTRUCTION_LENGTH);
821 }
822
823 if (brk.address1 != NULL)
824 {
825 if (brk.mode == DIM)
826 {
67278683 827 adj_write_memory (brk.act_addr[2], shadow2,
2213b721 828 INSTRUCTION_LENGTH);
67278683 829 adj_write_memory (brk.act_addr[3], shadow3,
2213b721
FF		 830 INSTRUCTION_LENGTH);
831 } else {
67278683 832 adj_write_memory (brk.act_addr[2], shadow2,
2213b721
FF		 833 INSTRUCTION_LENGTH);
834 }
835 }
836 one_stepped = 0;
837 }
838}
839
840
841
842/* Written for i860 by Jim Hanko ([email protected]) */
843/* This code was based on SPARC code written by Gary Beihl ([email protected]),
844 by Michael Tiemann ([email protected]). */
845/* This routine returns the first memory address following the prologue code,
846 if there is a prologue. */
847
848struct command_line *get_breakpoint_commands ();
849
850CORE_ADDR
851 skip_prologue (pc)
852CORE_ADDR pc;
853{
854 CORE_ADDR instr;
855 int regno;
856
857 instr = (unsigned)(adj_read_memory_integer (pc));
858
859 /* Recognize "addu|adds -X,sp,sp" insn. */
860 if ((instr & 0xEFFF0000) == 0x84420000)
861 {
862 pc += INSTRUCTION_LENGTH;
863 instr = (unsigned)(adj_read_memory_integer (pc));
864 }
865 else
866 return(pc); /* No frame! */
867
868 /* Recognize store of return addr and frame pointer into frame */
869 for (; ;)
870 {
871 if ((instr & 0xFFE0F801) == 0x1C400801 || /* st.l r1,X(sp) */
872 (instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */
873 {
874 pc += INSTRUCTION_LENGTH;
875 instr = (unsigned)(adj_read_memory_integer (pc));
876 }
877 else
878 break;
879 }
880
881 /* Recognize "addu|adds X,sp,fp" insn. */
882 if ((instr & 0xEFFF0000) == 0x84430000)
883 {
884 pc += INSTRUCTION_LENGTH;
885 instr = (unsigned)(adj_read_memory_integer (pc));
886 }
887
888 /* Now recognize stores into the frame from the registers. */
889
890 for (; ;)
891 {
892 if ((instr & 0xFFA00003) == 0x1C200001 || /* st.l rn,X(fp|sp) */
893 (instr & 0xFFA00001) == 0x4C200000) /* fst.y fn,X(fp|sp) */
894 {
895 regno = (instr >> 11) & 0x1f;
896 if (regno == 0) /* source reg == 0? quit */
897 break;
898 pc += INSTRUCTION_LENGTH;
899 instr = (unsigned)(adj_read_memory_integer (pc));
900 }
901 else
902 break;
903 }
904
905 return(pc);
906}
907
908#if 0
909/* This routine is uncalled. Remove it sometime. */
910/* Set *nextpc to branch target if we find a branch. If it is not a branch,
911 set it to the next instruction (addr + 4) */
912
913
914branch_type
915 isabranch (addr, nextpc)
916CORE_ADDR addr, *nextpc;
917{
918 CORE_ADDR instr;
919 branch_type val = not_branch;
920 long offset; /* Must be signed for sign-extend */
921
922 BTDEBUG(" isabranch\n");
923 *nextpc = addr;
924 instr = (unsigned)(adj_read_memory_integer (addr));
925
926 if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */
927 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
928 {
929 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
930 val = uncond_d;
931 else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */
932 val = cond_d;
933 else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */
934 val = cond;
935
936 offset = (instr & 0x03ffffff);
937 if (offset & 0x02000000) /* sign extend? */
938 offset |= 0xFC000000;
939 *nextpc = addr + 4 + (offset << 2);
940 }
941 else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */
942 (instr & 0xFC000000) == 0x40000000) /* bri */
943 {
944 val = uncond_d;
945 offset = ((instr & 0x0000F800) >> 11);
946 *nextpc = (read_register(offset) & 0xFFFFFFFC);
947 }
948 else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */
949 {
950 val = cond;
951
952 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
953 *nextpc = addr + 4 + (offset << 2);
954 }
955 else if ((instr & 0xFC000000) == 0xB4000000) /* bla */
956 {
957 val = cond_d;
958
959 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
960 *nextpc = addr + 4 + (offset << 2);
961 }
962
963 BTDEBUG(" Final addr - %x\n", *nextpc);
964 /*BTDEBUG("isabranch ret: %d\n",val); */
965 return val;
966}
967#endif
968
969/* set in call_function() [valops.c] to the address of the "call dummy" code
970 so dummy frames can be easily recognized; also used in wait_for_inferior()
971 [infrun.c]. When not used, it points into the ABI's 'reserved area' */
972
973CORE_ADDR call_dummy_set = 0; /* true if dummy call being done */
974CORE_ADDR call_dummy_start; /* address of call dummy code */
975
976/* this routine routine gets the values of the registers stored in the frame
977 and stores their values into the frame_saved_regs structure. */
978
979void
980frame_find_saved_regs(frame_info, frame_saved_regs)
981 struct frame_info *frame_info;
982 struct frame_saved_regs *frame_saved_regs;
983{
984 register CORE_ADDR pc;
985 CORE_ADDR instr;
986 long offset, spdelta = 0;
987 int i, size, reg;
988 int r1_off = -1, fp_off = -1;
989 int framesize;
990
991 bzero (frame_saved_regs, sizeof(*frame_saved_regs));
992
993 if (call_dummy_set && frame_info->pc >= call_dummy_start &&
994 frame_info->pc <= call_dummy_start + CALL_DUMMY_LENGTH)
995 {
996 /* DUMMY frame - all registers stored in order at fp; old sp is
997 at fp + NUM_REGS*4 */
998
999 for (i = 1; i < NUM_REGS; i++) /* skip reg 0 */
67278683
FF		 1000 /* the register numbers used in the instruction and the ones used to index
1001 the regs array are not the same -- compensate */
1002 frame_saved_regs->regs[i+R0] = frame_info->frame + i*REGISTER_LENGTH;
2213b721
FF		 1003
1004 call_dummy_set = 0;
1005 return;
1006 }
1007
1008 pc = get_pc_function_start (frame_info->pc);
67278683
FF		 1009 if (pc == NULL)
1010 pc = find_entry_start (frame_info->pc);
1011
2213b721
FF		 1012 if (pc != NULL)
1013 {
1014 instr = (unsigned)(adj_read_memory_integer (pc));
1015 /* Recognize "addu|adds -X,sp,sp" insn. */
1016 if ((instr & 0xEFFF0000) == 0x84420000)
1017 {
1018 framesize = -SIGN_EXT16(instr & 0x0000FFFF);
1019 pc += INSTRUCTION_LENGTH;
1020 instr = (unsigned)(adj_read_memory_integer (pc));
1021 }
1022 }
1023 else
1024 goto punt; /* No frame! */
1025
1026 /* Recognize store of return addr and frame pointer into frame */
1027 for (; ;)
1028 {
1029 if ((instr & 0xFFE0F801) == 0x1C400801) /* st.l r1,X(sp) */
1030 {
1031 r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE));
1032 pc += INSTRUCTION_LENGTH;
1033 instr = (unsigned)(adj_read_memory_integer (pc));
1034 }
1035 else if ((instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */
1036 {
1037 fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE));
1038 pc += INSTRUCTION_LENGTH;
1039 instr = (unsigned)(adj_read_memory_integer (pc));
1040 }
1041 else
1042 break;
1043 }
1044
1045 /* Recognize "addu|adds X,sp,fp" insn. */
1046 if ((instr & 0xEFFF0000) == 0x84430000)
1047 {
1048 spdelta = SIGN_EXT16(instr & 0x0000FFFF);
1049 pc += INSTRUCTION_LENGTH;
1050 instr = (unsigned)(adj_read_memory_integer (pc));
1051 }
1052
1053 /* Now recognize stores into the frame from the registers. */
1054
1055 for (; ;)
1056 {
1057 if ((instr & 0xFFC00003) == 0x1C400001) /* st.l rn,X(fp|sp) */
1058 {
1059 offset = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE));
1060 reg = (instr >> 11) & 0x1F;
1061 if (reg == 0)
1062 break;
1063 if ((instr & 0x00200000) == 0) /* was this using sp? */
1064 if (spdelta != 0) /* and we know sp-fp delta */
1065 offset -= spdelta; /* if so, adjust the offset */
1066 else
1067 break; /* if not, give up */
1068
1069
1070 /* Handle the case where the return address is stored after the fp
1071 is adjusted */
1072
1073 if (reg == 1)
1074 frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + offset;
1075 else
1076 frame_saved_regs->regs[reg+R0] = frame_info->frame + offset;
1077
1078 pc += INSTRUCTION_LENGTH;
1079 instr = (unsigned)(adj_read_memory_integer (pc));
1080 }
1081 else if ((instr & 0xFFC00001) == 0x2C400000) /* fst.y fn,X(fp|sp) */
1082 {
1083 /*
1084 * The number of words in a floating store based on 3 LSB of instr
1085 */
1086 static int fst_sizes[] = {2, 0, 1, 0, 4, 0, 1, 0};
1087
1088 size = fst_sizes[instr & 7];
1089 reg = ((instr >> 16) & 0x1F) + FP0_REGNUM;
1090 if (reg == 0)
1091 break;
1092
1093 if (size > 1) /* align the offset */
1094 offset = SIGN_EXT16(instr & 0x0000FFF8); /* drop 3 bits */
1095 else
1096 offset = SIGN_EXT16(instr & 0x0000FFFC); /* drop 2 bits */
1097
1098 if ((instr & 0x00200000) == 0) /* was this using sp? */
1099 if (spdelta != 0) /* and we know sp-fp delta */
1100 offset -= spdelta; /* if so, adjust the offset */
1101 else
1102 break; /* if not, give up */
1103
1104 for (i = 0; i < size; i++)
1105 {
1106 frame_saved_regs->regs[reg] = frame_info->frame + offset;
1107
1108 offset += REGISTER_LENGTH;
1109 reg++;
1110 }
1111
1112 pc += INSTRUCTION_LENGTH;
1113 instr = (unsigned)(adj_read_memory_integer (pc));
1114 }
1115 else
1116 break;
1117 }
1118
1119 punt: ;
1120 if (framesize != 0 && spdelta != 0)
1121 frame_saved_regs->regs[SP_REGNUM] = frame_info->frame+(framesize-spdelta);
1122 else
1123 frame_saved_regs->regs[SP_REGNUM] = frame_info->frame + 8;
1124
1125 if ((spdelta != 0) && fp_off != -1)
1126 frame_saved_regs->regs[FP_REGNUM] = frame_info->frame - spdelta + fp_off;
1127 else
1128 frame_saved_regs->regs[FP_REGNUM] = frame_info->frame;
1129
1130 if ((spdelta != 0) && r1_off != -1)
1131 frame_saved_regs->regs[PC_REGNUM] = frame_info->frame - spdelta + r1_off;
1132 else
1133 frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + 4;
1134}
1135
1136
1137/* get the frame pointer of the caller.
1138 * note that only routines that have been compiled with
1139 * -g have full (XX)fp style stack frames
1140 * if we are not returning to a non -g caller then we
1141 * return the sp at entry to us as it is the caller's
1142 * frame reference.
1143 */
1144
1145frame_chain(thisframe)
1146 FRAME thisframe;
1147{
1148 CORE_ADDR fp, pc;
1149 CORE_ADDR func_start;
1150 CORE_ADDR instr;
1151 int offset;
1152 CORE_ADDR thisfp = thisframe->frame;
67278683
FF		 1153 struct frame_saved_regs fsr;
1154 CORE_ADDR thissp;
1155
1156 /* get the frame pointer actually sp for a non -g
2213b721
FF		 1157 * for the routine that called us routine
1158 */
1159
1160 BTDEBUG("FRAME_CHAIN(%x)\n",thisframe);
1161
1162 if ( !read_memory_integer (thisframe->frame,sizeof(long)) )
1163 {
1164 return (0);
1165 }
1166
1167 if( ! g_routine(thisframe->pc) ){
67278683
FF		 1168 thissp = get_saved_basereg (thisframe, SP_REGNUM);
1169
2213b721 1170 BTDEBUG( "non g at %x\n",thisframe->pc);
67278683 1171 caller_pc(thisframe->pc, thissp, thisfp,&pc,&fp, 1);
2213b721
FF		 1172 BTDEBUG("caller_pc returned %x %x \n",pc,fp);
1173 return(fp);
1174
1175 }/* else a -g routine */
1176
1177
1178 fp = read_memory_integer (thisfp, sizeof(long));
1179
1180 if (fp < thisfp || fp > (unsigned) STACK_END_ADDR)
1181 {
1182 /* handle the Metaware-type pseudo-frame */
1183
1184 func_start = get_pc_function_start(thisframe->pc);
67278683
FF		 1185 if (func_start == NULL)
1186 func_start = find_entry_start (thisframe->pc);
1187
2213b721
FF		 1188 if (func_start != NULL)
1189 {
1190
1191 instr = (unsigned)(adj_read_memory_integer (func_start));
1192 /* Recognize "addu|adds -X,sp,sp" insn. */
1193 if ((instr & 0xEFFF0000) == 0x84420000)
1194 offset = SIGN_EXT16(instr & 0x0000FFFF);
be9a2362 1195
be9a2362
FF		 1196 }
1197
2213b721
FF		 1198 fp = 0;
1199 if (offset < 0)
1200 fp = thisfp - offset;
be9a2362 1201 }
2213b721
FF		 1202 BTDEBUG("frame_chain returned %d\n",fp);
1203 return(fp);
1204}
1205
1206/* This function returns 1 if there is no stored r1, 0 otherwise.
1207 The function returns 1 if the pc is in a function prologue,
1208 or the function prologue didn't save the return pointer in
1209 the stack frame, 0 otherwise */
1210
1211int no_stored_rp(CORE_ADDR pc)
1212{
1213 CORE_ADDR func_start, prologue_end;
be9a2362 1214
2213b721 1215 func_start = get_pc_function_start(pc);
67278683
FF		 1216 if (func_start == NULL)
1217 func_start = find_entry_start (pc);
1218
2213b721 1219 if (func_start != NULL)
be9a2362 1220 {
2213b721
FF		 1221 prologue_end = func_start;
1222 SKIP_PROLOGUE(prologue_end);
1223 if ( (pc >= func_start) && (pc <= prologue_end))
be9a2362 1224 {
2213b721
FF		 1225 BTDEBUG("no_stored_rp: pc %x is in prologue \n",pc);
1226 return 1;
1227 }
1228 /* otherwise, see if the entry sequence stored the return pointer.
1229 If it didn't, return 1 */
1230 /* Some procedures , at least, store the return pointer AFTER
1231 the prologue sequence, so check for stores from function start to
1232 present pc value. */
1233 if (!has_stored_r1(func_start, pc))
1234 {
1235 BTDEBUG("no_stored_rp, for pc %x, prologue didn't store r1\n",pc);
1236 return 1;
be9a2362
FF		 1237 }
1238 }
2213b721
FF		 1239 BTDEBUG("no_stored_rp for pc %x return pointer was stored \n", pc);
1240
1241 return 0;
1242}
1243
1244/* get the PC of the caller */
1245CORE_ADDR frame_saved_pc(frame_struct)
1246FRAME frame_struct;
1247{
1248 CORE_ADDR frame;
1249 CORE_ADDR pc;
1250 CORE_ADDR pc1;
1251 CORE_ADDR sp ;
1252 CORE_ADDR fp;
67278683 1253 struct frame_saved_regs fsr;
2213b721
FF		 1254
1255 frame = frame_struct->frame;
1256 pc = frame_struct->pc;
67278683
FF		 1257
1258
2213b721
FF		 1259 BTDEBUG("frame_saved_pc input: frame %x, pc %x",
1260 frame, pc);
1261
1262 /* First see if this is the current frame. If it is, return the value in r1,
1263 as it may not have been stored */
1264
1265 fp = read_register(FP_REGNUM);
1266
1267 /* check to see if we are in an entry sequence, where the return pointer has not yet been stored */
1268 if (fp == frame && no_stored_rp(pc))
1269 {
1270 pc = read_register(RP_REGNUM);
1271 frame_struct->rp = pc;
1272 }
1273 else if( ! g_routine(pc) )
1274 {
67278683
FF		 1275 sp = get_saved_basereg (frame_struct, SP_REGNUM);
1276
1277 caller_pc(pc,sp,frame_struct->frame, &pc,&frame, 0);
2213b721
FF		 1278 }
1279 else
1280 {
1281
1282 pc = read_memory_integer (frame + 4, sizeof(long));
1283
67278683 1284 if (inside_entry_file(pc))
2213b721
FF		 1285 {
1286
67278683 1287 BTDEBUG("pc %x outside entry file \n",pc);
2213b721
FF		 1288
1289 pc1 = read_memory_integer (frame, sizeof(long));
1290
67278683 1291 if (!inside_entry_file(pc1))
2213b721
FF		 1292 pc = pc1;
1293 else
1294 pc = 0;
1295 }
1296 }
1297 BTDEBUG(" returning pc %x\n", CLEAN_PC(pc));
1298 return(CLEAN_PC(pc));
1299
1300 }
1301
1302/* Pass arguments to a function in the inferior process - ABI compliant
67278683
FF		 1303 Modified by Peggy Fieland ([email protected]) to account
1304 for newer ABI conventions. Note that now, unfortunately, we MUST KNOW
1305 if we expect a float or a double. For now, we will assume that the
1306 caller of this routine has the types of these arguments correct....
1307 NOTE THAT THIS ROUTINE DOES NO ARGUMENT COERCION -- it's all in the
1308 caller.
1309 Modified by Peggy Fieland to handle memory argument lists.
1310 */
2213b721 1311
67278683
FF		 1312#define IS_EVEN_REG(fl) (((fl - FP0_REGNUM)%2) == 0)
1313CORE_ADDR
1314pass_function_arguments(args, nargs, struct_return, struct_addr, sp)
2213b721
FF		 1315 value *args;
1316 int nargs;
1317 int struct_return;
67278683
FF		 1318 CORE_ADDR struct_addr;
1319 CORE_ADDR sp;
2213b721 1320{
67278683
FF		 1321 int ireg = (struct_return) ? R17 : R16;
1322 int freg = F8;
2213b721
FF		 1323 int i;
1324 struct type *type;
1325 value arg;
67278683
FF		 1326 signed long tmp;
1327 unsigned long ul_tmp;
1328 signed short s_tmp;
1329 unsigned short us_tmp;
1330 signed char c_tmp;
1331 unsigned char uc_tmp;
1332 CORE_ADDR arg_ptr;
1333 int len;
1334
1335 if (struct_return)
1336 {
1337 write_register(R16, struct_addr);
1338 }
1339
1340 arg_ptr = sp; /* Space was allocated for memory argument list in i860_arg_coerce */
1341
1342 /* Loop through the arguments, putting the values in a register or memory as appropriate. */
2213b721
FF		 1343
1344 for (i = 0; i < nargs; i++)
be9a2362 1345 {
67278683 1346 arg = args[i];
2213b721 1347 type = VALUE_TYPE(arg);
67278683 1348 len = TYPE_LENGTH(type);
2213b721 1349 if (type == builtin_type_double)
be9a2362 1350 {
67278683
FF		 1351 /* see ABI . Note freg MUST BE INCREMENTED even if arg goes into the
1352 memory argument list for this code to work correctly for subsequent
1353 arguments. */
1354 if (!IS_EVEN_REG(freg))
1355 freg += 1;
1356 /* see if argument can be put in a register, or whether it must go
1357 into the memory argument list */
1358 if (freg < F8 + NUM_FLOAT_ARG_REGS)
1359 {
1360 /* It can go in a register */
1361 bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(double));
1362 write_register_bytes(REGISTER_BYTE(freg), (char *) &tmp, TYPE_LENGTH(type));
1363 freg += 2;
1364 }
1365 else
1366 {
1367 /* It goes into memory argument list */
1368 arg_ptr = ALIGN_ARG( arg_ptr, sizeof(double));
1369 write_memory (arg_ptr, VALUE_CONTENTS (arg), len);
1370 arg_ptr += len;
1371 }
1372
1373 }
1374 else if (type == builtin_type_float)
1375 {
1376 if (freg < F8 + NUM_FLOAT_ARG_REGS)
1377 {
1378 /* It can go in a register */
1379 bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(long));
1380 write_register_bytes (REGISTER_BYTE(freg), (char *) &tmp, TYPE_LENGTH(type));
1381 freg++;
1382 }
1383 else
1384 {
1385 /* It goes into the memory argument list */
1386 arg_ptr = ALIGN_ARG(arg_ptr, sizeof(float));
1387 write_memory (arg_ptr, VALUE_CONTENTS (arg), len);
1388 arg_ptr += len;
1389 }
2213b721
FF		 1390 }
1391 else
1392 {
67278683
FF		 1393 /* All structs are passed by value, and hence they all go into the memory
1394 argument list (see ABI); otherwise, as above, see if we have run
1395 out of registers */
1396
1397 /* Cast value correctly so we can load it into a register or into the
1398 memory argument list -- see ABI */
1399 if (TYPE_LENGTH(type) < sizeof(long))
1400 {
1401 if (TYPE_FLAGS(type) & TYPE_FLAG_UNSIGNED)
1402 arg = value_cast(builtin_type_unsigned_int, arg);
1403 else
1404 arg = value_cast (builtin_type_int, arg);
1405 type = VALUE_TYPE(arg);
1406 len = TYPE_LENGTH(type);
1407 }
1408
1409 if ((TYPE_CODE(type) == TYPE_CODE_STRUCT) || (ireg >= R16 + NUM_INT_ARG_REGS))
1410 {
1411 /* It goes into the memory argument list. Minimum alignment requirements
1412 are on a 4-byte boundary */
1413
1414 if ((TYPE_CODE(type) == TYPE_CODE_INT) ||
1415 (TYPE_CODE(type) == TYPE_CODE_ENUM) ||
1416 (TYPE_CODE(type) == TYPE_CODE_CHAR) ||
1417 (TYPE_CODE(type) == TYPE_CODE_BOOL))
1418 arg_ptr = ALIGN_ARG(arg_ptr, len);
1419 else
1420 arg_ptr = ALIGN_ARG (arg_ptr, sizeof(long)); /* align on 4-byte boundary */
1421 write_memory (arg_ptr, VALUE_CONTENTS (arg), len);
1422 arg_ptr += len;
1423 }
1424 else
1425 {
1426
1427 bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(long));
1428 write_register(ireg, tmp);
1429 ireg++;
1430 }
1431
be9a2362 1432 }
be9a2362 1433 }
67278683
FF		 1434
1435
1436 return (sp);
1437
2213b721
FF		 1438}
1439
1440
1441#define SPACES " "
1442#define P_SPACES " "
1443#define BYTE 0xff
1444
1445int screen_lines=24;
1446
1447char *spec_reg[] = {
1448 "fsr", "db", "dirbase", "fir", "psr", "epsr",
1449};
1450
1451char *doro_reg[] = {
1452 "scp", "cbsp", "pt_cs", "intmsk", "intack",
1453};
1454#define NREGS 32
1455
67278683 1456
2213b721
FF		 1457get_reg(regno)
1458{
1459 char raw_buffer[32];
1460 int addr;
1461 int virtual_buffer;
67278683
FF		 1462
1463 /* NOTE that only integer and floating point registers can be relative to a frame */
1464
1465 if ((regno >= R0) && (regno <= F31)) /* user register */
1466 read_relative_register_raw_bytes (regno, raw_buffer);
1467 else
1468 bcopy (&registers[regno << 2], raw_buffer, sizeof (long));
1469
2213b721
FF		 1470 REGISTER_CONVERT_TO_VIRTUAL (addr, raw_buffer, &virtual_buffer);
1471 return(virtual_buffer);
be9a2362 1472}
2213b721
FF		 1473
1474
1475#if 0
1476/* This routine is uncalled. Remove it sometime. */
be9a2362
FF		 1477
1478/*
1479 ** Figure out whether we are in a delayed slot and if so then take necessary
1480 ** action to resume properly - remember trap pre-empts instruction
1481 */
1482int
1483 wasabranch (addr, nextpc, ss)
1484CORE_ADDR addr, *nextpc;
1485int ss;
1486{
2213b721 1487 CORE_ADDR nextadr, instr;
be9a2362
FF		 1488 int val = not_branch;
1489 long offset; /* Must be signed for sign-extend */
1490
1491 if (ss)
1492 {
1493 if (INDIM)
1494 {
2213b721
FF		 1495 nextadr = CORADR((int)(addr + INSTRUCTION_LENGTH*2));
1496 instr = (unsigned)(adj_read_memory_integer (CORADR(addr)));
be9a2362
FF		 1497 }
1498 else
1499 {
2213b721
FF		 1500 nextadr = addr + INSTRUCTION_LENGTH;
1501 instr = (unsigned)(adj_read_memory_integer (addr));
be9a2362
FF		 1502 }
1503 } else {
1504 if (ISDIM(addr))
1505 {
1506 nextadr = CORADR(addr);
2213b721 1507 instr = (unsigned)(adj_read_memory_integer (nextadr));
be9a2362
FF		 1508 }
1509 else
1510 {
1511 nextadr = addr;
2213b721 1512 instr = (unsigned)(adj_read_memory_integer (addr));
be9a2362
FF		 1513 }
1514 }
1515
1516
1517 if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */
1518 (instr & 0xF8000000) != 0x60000000) /* not pfld.y */
1519 {
1520 if ((instr & 0xF8000000) == 0x68000000) /* br or call */
1521 val = uncond_d;
1522 else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */
1523 val = cond_d;
1524 else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */
1525 val = cond;
1526
1527 offset = (instr & 0x03ffffff);
1528 if (offset & 0x02000000) /* sign extend? */
1529 offset |= 0xFC000000;
1530 nextadr += (offset << 2);
1531 }
1532 else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */
1533 (instr & 0xFC000000) == 0x40000000) /* bri */
1534 {
1535 if (ss)
1536 {
1537 val = uncond_d;
1538 offset = ((instr & 0x0000F800) >> 11);
1539 nextadr = (read_register(offset) & 0xFFFFFFFC);
1540 } else {
1541 val = uncond_d;
1542 }
1543 }
1544 else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */
1545 {
1546 val = cond;
1547
1548 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
1549 nextadr += (offset << 2);
1550 }
1551 else if ((instr & 0xFC000000) == 0xB4000000) /* bla */
1552 {
1553 val = cond_d;
1554
1555 offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF));
1556 nextadr += (offset << 2);
1557 }
1558
1559 *nextpc = nextadr;
1560 return val;
1561}
2213b721 1562#endif
be9a2362 1563
be9a2362 1564
2213b721 1565/* i860-specific routine to print the register set. Note that we ALWAYS print information
67278683
FF		 1566 on the floating point registers, so we ignore the parameter fpregs.
1567 NOTE also that only integer and floating point registers can be relative to a frame --
1568 see subroutine get_reg (above ) */
1569
2213b721 1570void i860_do_registers_info(regnum,fpregs)
be9a2362
FF		 1571 int regnum;
1572 int fpregs;
1573{
1574 register int i;
1575 unsigned int val;
1576 unsigned int j,k;
1577
2213b721 1578
be9a2362
FF		 1579 if (regnum == -1)
1580 printf_filtered (
1581 "Register Contents (relative to selected stack frame)\n\n");
1582
1583 if (regnum != -1) /* print one register */
1584 {
67278683 1585 val = get_reg(regnum);
be9a2362
FF		 1586 printf("%-4s 0x%08x\t", reg_names[regnum], val);
1587 printf("\n\t"); fflush(stdout);
1588 }
1589 else /* print all registers */
1590 {
1591
1592 printf("\n Control/Status Registers :- \n\t");
1593 for (j=0; j<=DB; j++)
1594 {
67278683 1595 val = get_reg(j);
be9a2362
FF		 1596 printf("%-4s 0x%08x\t", reg_names[j], val);
1597 }
1598 printf("\n\t"); fflush(stdout);
1599
1600 /* EPSR */
67278683 1601 val = get_reg(EPSR);
be9a2362
FF		 1602 printf("%-4s 0x%08x\t", reg_names[EPSR], val);
1603
1604 /* FSR */
67278683 1605 val = get_reg(FSR);
be9a2362
FF		 1606 printf("%-4s 0x%08x\t", reg_names[FSR], val);
1607
1608 /* CCR */
67278683 1609 val = get_reg(CCR);
be9a2362
FF		 1610 printf("%-4s 0x%08x\t", reg_names[CCR], val);
1611 /* BEAR*/
67278683 1612 val = get_reg(BEAR);
be9a2362
FF		 1613 printf("%-4s 0x%08x\t", reg_names[BEAR], val);
1614
1615
1616#ifdef JIM_ADD_PRIV
1617 for (j=P0; j<=P3; j++)
1618 {
67278683 1619 val = get_reg(j);
be9a2362
FF		 1620 printf("%-4s 0x%08x\t", reg_names[j], val);
1621 }
1622#endif
1623
1624 printf("\n Integer Registers :- \n\t");
1625 for (j=R0; j<=R31; j++)
1626 {
2213b721 1627 if (j != IREGS && (j % REGISTER_LENGTH == 0))
be9a2362
FF		 1628 {
1629 printf("\n\t"); fflush(stdout);
1630 }
67278683 1631 val = get_reg(j);
be9a2362
FF		 1632 printf("%-4s 0x%08x\t", reg_names[j], val);
1633 }
1634
1635 printf("\n Floating Registers :- \n\t");
1636 for (j=F0; j<=F31; j++)
1637 {
2213b721 1638 if (j != FREGS && (j % REGISTER_LENGTH == 0))
be9a2362
FF		 1639 {
1640 printf("\n\t"); fflush(stdout);
1641 }
67278683 1642 val = get_reg(j);
be9a2362
FF		 1643 printf("%-4s 0x%08x\t", reg_names[j], val);
1644 }
1645
1646 printf("\n Special Registers :- \n\t");
1647 for (j=SPC_KI; j<=SPC_MERGE; j+=2)
1648 {
1649 unsigned int valh;
1650 if (j == SPC_T)
1651 {
1652 printf("\n\t"); fflush(stdout);
1653 }
67278683
FF		 1654 val = get_reg(j);
1655 valh = get_reg(j+1);
be9a2362
FF		 1656 printf("%-6s 0x%08x %08x\t", reg_names[j], val,valh);
1657 }
1658
1659 printf("\n Graphics Pipeline :- \n");
1660 {
2213b721 1661 unsigned int valh;
be9a2362 1662 j = PSV_I1;
67278683
FF		 1663 val = get_reg(j);
1664 valh = get_reg(j+1);
be9a2362
FF		 1665 printf("\t\t\t%-8s 0x%08x %08x \n", reg_names[j], val,valh);
1666 }
1667
1668 printf(" Memory Load Pipeline :- \n");
2213b721 1669 for (j=PSV_L1; j<=PSV_L3; j+=REGISTER_LENGTH)
be9a2362
FF		 1670 {
1671 unsigned int valh, val2,val3;
67278683
FF		 1672
1673 val = get_reg(j);
1674 valh = get_reg(j+1);
1675 val2 = get_reg(j+2);
1676 val3 = get_reg(j+3);
1677
be9a2362
FF		 1678 printf("\t\t%-8s 0x%08x %08x %08x %08x\n", reg_names[j],
1679 val,valh,val2,val3);
1680 }
1681
1682 printf("\n Adder Pipeline :-\t\tMultiplier Pipeline :-\t\tFSR results :-\n");
1683 for (i=PSV_FSR1,j=PSV_A1,k=PSV_M1; j<=PSV_A3; i++,j+=2,k+=2)
1684 {
1685 unsigned int valh,val2,val3,val4;
67278683
FF		 1686
1687 val4 = get_reg(i);
1688 val = get_reg(j);
1689 valh = get_reg(j+1);
1690 val2 = get_reg(k);
1691 val3 = get_reg(k+1);
1692
be9a2362
FF		 1693 printf(" %-4s 0x%08x %08x\t", reg_names[j], val,valh);
1694 printf("%-4s 0x%08x %08x\t", reg_names[k], val2,val3);
1695 printf("%-4s 0x%08x\n", reg_names[i], val4);
1696 }
1697
1698 }
1699
1700
1701}
1702
be9a2362 1703
be9a2362
FF		 1704
1705/* The following set of routines was adapted from existing code previously
1706 in an i860-specific version of breakpoint.c by Peggy Fieland
1707 ([email protected]) */
2213b721
FF		 1708/* routines to set a data breakpoint by setting the value in the DB register.
1709 Note that "hitting" the breakpoint will generate a data access trap. We
1710 do not have a special trap handler. */
be9a2362
FF		 1711unsigned int dbrkval, dbrkmod;
1712void i860_dbrk_breakpoint()
1713{
1714 BTDEBUG("i860_dbrk_breakpoint was called , dbrkval %x\n", dbrkval);
1715
2213b721 1716 if (dbrkval != 0)
be9a2362
FF		 1717 {
1718 *(int *)&registers[DB<<2] = dbrkval;
1719 }
1720 else
1721 {
1722 *(int *)&registers[DB<<2] = 0;
1723 }
1724
1725 *(int *)&registers[PSR<<2] &= ~3;
1726 *(int *)&registers[PSR<<2] |= dbrkmod;
1727
1728 store_inferior_registers(DB);
1729 store_inferior_registers(PSR);
1730
1731}
1732
2213b721 1733/* set a "read" data breakpoint. */
be9a2362 1734void
67278683 1735d_ro_break_command(char *arg, int num)
be9a2362
FF		 1736{
1737 dbrkval = strtoul(arg, NULL, 0);
1738 dbrkmod = 0x01;
2213b721 1739 BTDEBUG(" ro_dbreak - %x %x\n", dbrkval, dbrkmod);
be9a2362
FF		 1740}
1741
2213b721 1742/* set a "write" data breakpoint. */
be9a2362 1743void
67278683 1744d_wo_break_command(char *arg, int num)
be9a2362
FF		 1745{
1746 dbrkval = strtoul(arg, NULL, 0);
1747 dbrkmod = 0x02;
2213b721 1748 BTDEBUG(" wo_dbreak - %x %x\n", dbrkval, dbrkmod);
be9a2362
FF		 1749}
1750
2213b721 1751/* set a "read/write" data breakpoint. */
be9a2362 1752void
67278683
FF		 1753d_rw_break_command(char *arg, int num)
1754{
1755 dbrkval = strtoul(arg, NULL, 0);
1756 dbrkmod = 0x03;
1757 BTDEBUG(" rw_dbreak - %x %x\n", dbrkval, dbrkmod);
1758 }
be9a2362 1759
2213b721 1760/* clear data breakpoint. */
67278683
FF		 1761 void clear_dbreak(char *arg, int num)
1762 {
1763 dbrkval = 0;
1764 dbrkmod = 0;
1765 }
1766
1767/* i860-specific breakpoint initialization. Includes adding the
1768i860-specific data breakpoint commands. */
1769void i860_init_breakpoints()
1770{
be9a2362
FF		 1771 dbrkval = dbrkmod = 0;
1772 add_com ("dbro", class_breakpoint, d_ro_break_command,
1773 "Set a data breakpoint READ ONLY, 32-bit data element.");
1774 add_com ("dbwo", class_breakpoint, d_wo_break_command,
1775 "Set a data breakpoint WRITE ONLY, 32-bit data element.");
1776 add_com ("dbrw", class_breakpoint, d_rw_break_command,
1777 "Set a data breakpoint READ/WRITE, 32-bit data element.");
1778 add_com ("dclear", class_breakpoint, clear_dbreak,
1779 "clear the current data breakpoint.");
1780 add_com_alias ("dc", "dclear", class_breakpoint, 1);
1781
1782}
1783
2213b721 1784/* i860-specific code to insert a breakpoint. */
be9a2362
FF		 1785int i860_insert_breakpoint(b)
1786struct breakpoint *b;
1787{
1788 int val;
67278683
FF		 1789 int *shadow0, *shadow1, *shadow2, *shadow3;
1790
1791 shadow0 = (int *)&b->shadow_contents[0];
1792 shadow1 = (int *)&b->shadow_contents[4];
1793 shadow2 = (int *)&b->shadow_contents[8];
1794 shadow3 = (int *)&b->shadow_contents[12];
be9a2362
FF		 1795
1796 place_brk( b->address, BREAK_MODE, b );
67278683 1797
be9a2362
FF		 1798 if (b->mode == DIM)
1799 {
1800
67278683 1801 adj_read_memory (b->act_addr[0], shadow0, INSTRUCTION_LENGTH);
2213b721
FF		 1802 val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH);
1803 if (val != 0 ) return val;
67278683 1804 adj_read_memory (b->act_addr[1], shadow1, INSTRUCTION_LENGTH);
2213b721
FF		 1805 /* val = adj_write_memory (b->act_addr[1], float_insn, INSTRUCTION_LENGTH); */
1806 if (val != 0) return val;
be9a2362
FF		 1807 }
1808 else
1809 {
67278683 1810 adj_read_memory (b->act_addr[0], shadow0, INSTRUCTION_LENGTH);
2213b721 1811 val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH);
be9a2362 1812 }
2213b721 1813 if (b->address1 != 0)
be9a2362
FF		 1814 {
1815 if (b->mode == DIM)
1816 {
1817
67278683 1818 adj_read_memory (b->act_addr[2], shadow2, INSTRUCTION_LENGTH);
2213b721 1819 val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH);
be9a2362 1820 if (val) return val;
67278683 1821 adj_read_memory (b->act_addr[3], shadow3, INSTRUCTION_LENGTH);
2213b721
FF		 1822 /* val = adj_write_memory (b->act_addr[3], float_insn, INSTRUCTION_LENGTH); */
1823 if (val != 0) return val;
be9a2362
FF		 1824 }
1825 else
1826 {
67278683 1827 adj_read_memory (b->act_addr[2], shadow0, INSTRUCTION_LENGTH);
2213b721 1828 val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH);
be9a2362
FF		 1829 }
1830 }
2213b721 1831 if (val != 0)
be9a2362 1832 return val;
67278683 1833
be9a2362
FF		 1834 b->inserted = 1;
1835 return 0;
1836}
1837
1838int i860_remove_breakpoint(b)
1839struct breakpoint *b;
1840{
1841 int val;
67278683
FF		 1842 int *shadow0, *shadow1, *shadow2, *shadow3;
1843
1844 shadow0 = (int *)&b->shadow_contents[0];
1845 shadow1 = (int *)&b->shadow_contents[4];
1846 shadow2 = (int *)&b->shadow_contents[8];
1847 shadow3 = (int *)&b->shadow_contents[12];
1848
be9a2362
FF		 1849
1850 if (b->inserted)
1851 {
1852 if (b->mode == DIM)
1853 {
67278683 1854 val =adj_write_memory (b->act_addr[0], shadow0,
2213b721 1855 INSTRUCTION_LENGTH);
67278683 1856 val =adj_write_memory (b->act_addr[1],shadow1,
2213b721
FF		 1857 INSTRUCTION_LENGTH);
1858 if (b->address1 != NULL)
be9a2362 1859 {
67278683 1860 val =adj_write_memory (b->act_addr[2],shadow2,
2213b721 1861 INSTRUCTION_LENGTH);
67278683 1862 val =adj_write_memory (b->act_addr[3], shadow3,
2213b721 1863 INSTRUCTION_LENGTH);
be9a2362
FF		 1864 }
1865 }
1866 else
1867 {
67278683 1868 val =adj_write_memory (b->act_addr[0], shadow0,
2213b721
FF		 1869 INSTRUCTION_LENGTH);
1870 if (b->address1 != NULL)
be9a2362 1871 {
67278683 1872 val =adj_write_memory (b->act_addr[2],shadow0,
2213b721 1873 INSTRUCTION_LENGTH);
be9a2362
FF		 1874 }
1875 }
2213b721 1876 if (val != 0)
be9a2362
FF		 1877 return val;
1878 b->inserted = 0;
be9a2362
FF		 1879 }
1880
1881 return 0;
1882
1883
1884}
1885
1886
1887#ifdef USE_PROC_FS /* Target dependent support for /proc */
1888
1889#include <sys/procfs.h>
1890
1891/* The following routines were added by Peggy Fieland ([email protected])
1892They were adapted from the m-68k versions of the routines .*/
1893
1894/* Given a pointer to a floating point register set in /proc format
1895 (fpregset_t *), unpack the register contents and supply them as gdb's
1896 idea of the current floating point register values. */
1897
1898void
1899supply_fpregset (fpregsetp)
1900fpregset_t *fpregsetp;
1901{
1902 register int regno;
1903
1904 BTDEBUG("supply_fregset called \n");
1905
1906 for (regno = F0 ; regno <= F31 ; regno++)
1907 {
1908 supply_register (regno, (char *) &(fpregsetp -> fpu.r_freg[regno-F0]));
1909 }
1910}
1911
1912/* Given a pointer to a floating point register set in /proc format
1913 (fpregset_t *), update the register specified by REGNO from gdb's idea
1914 of the current floating point register set. If REGNO is -1, update
1915 them all. */
1916
1917void
1918fill_fpregset (fpregsetp, regno)
1919fpregset_t *fpregsetp;
1920int regno;
1921{
1922 int regi;
1923 char *to;
1924 char *from;
1925 extern char registers[];
1926 BTDEBUG("fill_fregset regno %d\n",regno);
1927
1928 for (regi = F0 ; regi <= F31 ; regi++)
1929 {
1930 if ((regno == -1) || (regno == regi))
1931 {
1932 from = (char *) &registers[REGISTER_BYTE (regi)];
1933 to = (char *) &(fpregsetp -> fpu.r_freg[regi-F0]);
1934 bcopy (from, to, REGISTER_RAW_SIZE (regno));
1935 }
1936 }
1937}
1938
1939
1940/* Given a pointer to a general register set in /proc format (gregset_t *),
1941 unpack the register contents and supply them as gdb's idea of the current
1942 register values. */
1943
1944void
1945supply_gregset (gregsetp)
1946gregset_t *gregsetp;
1947{
1948 register int regno;
1949 register greg_t *regp = (greg_t *) gregsetp;
1950
1951 BTDEBUG("supply_gregset called \n");
1952
1953 for (regno = 0 ; regno <= R31 ; regno++)
1954 {
1955 supply_register (regno, (char *) (regp + regno));
1956 }
1957}
1958
2213b721
FF		 1959/* Given a pointer to a general register set in /proc format (gregset_t *),
1960 update the register specified by REGNO from gdb's idea
1961 of the current general register set. If REGNO is -1, update
1962 them all. */
1963
be9a2362
FF		 1964void
1965fill_gregset (gregsetp, regno)
1966gregset_t *gregsetp;
1967int regno;
1968{
1969 int regi;
1970 extern char registers[];
1971 register greg_t *regp = (greg_t *) gregsetp;
1972 BTDEBUG("fill_gregset regno %d \n",regno);
1973
1974 for (regi = 0 ; regi <= R31 ; regi++)
1975 {
1976 if ((regno == -1) || (regno == regi))
1977 {
1978 *(regp + regi) = *(int *) &registers[REGISTER_BYTE (regi)];
1979 }
1980
1981 }
1982}
1983#endif
67278683
FF		 1984
1985
1986/* Push an empty stack frame, to record the current PC, etc. */
1987/* We have this frame with fp pointing to a block where all GDB-visible
1988 registers are stored in the order GDB knows them, and sp at the next
1989 alignment point below fp. Note: fp + NUM_REGS*4 was the old sp
1990 */
1991extern CORE_ADDR text_end;
1992CORE_ADDR dummy_start_addr;
1993void i860_push_frame()
1994{
1995 register CORE_ADDR old_fp = read_register(FP_REGNUM);
1996 register CORE_ADDR old_sp = read_register(SP_REGNUM);
1997 register CORE_ADDR fp ;
1998 extern char registers[];
1999
2000 fp = old_sp - REGISTER_BYTES;
2001 write_memory(fp, registers, REGISTER_BYTES); /* write out old register values */
2002 /* reset FP and SP */
2003 write_register(FP_REGNUM, fp);
2004 write_register(SP_REGNUM, (fp &~ 15)); /* re-align */
2005 call_dummy_set = 1;
2006}
2007/* Discard from the stack the innermost frame,
2008 restoring all saved registers. */
2009
2010void i860_pop_frame()
2011{ register FRAME frame = get_current_frame ();
2012 register CORE_ADDR fp;
2013 struct frame_info *fi;
2014 int i;
2015
2016 fi = get_frame_info (frame);
2017 fp = fi->frame;
2018
2019 if (call_dummy_set && fi -> pc >= call_dummy_start &&
2020 fi -> pc <= call_dummy_start + CALL_DUMMY_LENGTH)
2021 {
2022
2023 read_memory(fp, registers, REGISTER_BYTES);
2024
2025 target_store_registers(-1);
2026
2027 {
2028 /* since we stomped on code that will be executed when we exit the program,
2029 restore it. */
2030 extern REGISTER_TYPE call_save_code[4];
2031
2032 write_memory (call_dummy_start, (char *) call_save_code, 16);
2033
2034 }
2035 call_dummy_set = 0;
2036 }
2037 else
2038 {
2039 register int regnum;
2040 struct frame_saved_regs fsr;
2041 char raw_buffer[12];
2042
2043 get_frame_saved_regs (fi, &fsr);
2044 for (regnum = FP0_REGNUM + 31; regnum >= FP0_REGNUM; regnum--)
2045 if (fsr.regs[regnum])
2046 write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
2047 for (regnum = R31; regnum >= 1; regnum--)
2048 if (fsr.regs[regnum])
2049 if (regnum != SP_REGNUM)
2050 write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
2051 else
2052 write_register (SP_REGNUM, fsr.regs[SP_REGNUM]);
2053 if (fsr.regs[PS_REGNUM])
2054 write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
2055 if (fsr.regs[FPS_REGNUM])
2056 write_register (FPS_REGNUM, read_memory_integer (fsr.regs[FPS_REGNUM],4));
2057 if (fsr.regs[PC_REGNUM])
2058 write_register (PC_REGNUM,CLEAN_PC( read_memory_integer (fsr.regs[PC_REGNUM], 4)));
2059 }
2060
2061 flush_cached_frames ();
2062
2063 set_current_frame (create_new_frame (read_register (FP_REGNUM),
2064 read_pc ()));
2065
2066}
2067
2068CORE_ADDR i860_arg_coerce(nargs, args, struct_return, sp)
2069 int nargs;
2070 value *args;
2071 int struct_return;
2072 CORE_ADDR sp;
2073{
2074
2075 register int scalar;
2076 register enum type_code code2;
2077 register struct type *type;
2078 int i;
2079 value arg;
2080 int num_int_args = 0;
2081 int num_float_args = 0;
2082 int size = 0;
2083 CORE_ADDR arg_ptr;
2084
2085 /* if we return a structure, it's address is in R16, and thus it uses up one of the integer
2086 argument registers. See the ABI. */
2087 if (struct_return)
2088 num_int_args += 1;
2089
2090 /* loop to do the right thing with all the arguments and calculate the size of the memory
2091 argument list. We keep count of the number of integer and the number of float parameters,
2092 as well as the size of the memory argument list. */
2093
2094 for (i = 0; i < nargs; i++)
2095 {
2096
2097 /* NOTE that this is all hunky dory in spite of the fact that we don't actually
2098 have the signature of the called procedure EXCEPT if we are passing in floats!
2099 This is true, since registers are 4 bytes, and the minimum alignment in the
2100 memory argument list is 4 bytes. See the ABI for more gory details. The switch
2101 "ansi-conformant" is an attempt to get around this problem. */
2102
2103 code2 = TYPE_CODE (VALUE_TYPE(args[i]));
2104
2105 /* Only coerce if we've got switch "ansi-conformant" off.
2106 Actually, it's OK ( and probably helpful) to coerce ALL integer arguments
2107 (see comment above), but never mind, we make them the right size in
2108 pass_function_arguments. */
2109
2110 if ((!ansi_conformant) && (code2 != TYPE_CODE_STRUCT))
2111 value_arg_coerce(args[i]);
2112
2113 arg = args[i];
2114 type = VALUE_TYPE(args[i]);
2115
2116 /* All structures are passed by value in the memory argument list. */
2117 if (code2 == TYPE_CODE_STRUCT)
2118 {
2119 size = ALIGN_ARG(size, sizeof(long));
2120 size += TYPE_LENGTH(type);
2121 }
2122 else if (type == builtin_type_float)
2123 {
2124 num_float_args += 1;
2125 if (num_float_args > NUM_FLOAT_ARG_REGS)
2126 {
2127 size = ALIGN_ARG(size, TYPE_LENGTH(type)) ;
2128 size += TYPE_LENGTH(type);
2129 }
2130 }
2131 else if (type == builtin_type_double)
2132 {
2133 /* floating register alignment -- see ABI */
2134 if ((num_float_args%2) != 0)
2135 num_float_args += 1;
2136
2137 num_float_args += 2; /* use up two registers */
2138
2139 if (num_float_args > NUM_FLOAT_ARG_REGS)
2140 {
2141 size = ALIGN_ARG(size, TYPE_LENGTH(type)) ;
2142 size += TYPE_LENGTH(type);
2143 }
2144 }
2145 else
2146 {
2147 int len = max (sizeof(long), TYPE_LENGTH(type));
2148
2149 num_int_args += 1;
2150
2151 if (num_int_args > NUM_INT_ARG_REGS)
2152 {
2153 /* see ABI -- in-memory arguments have AT LEAST word alignment */
2154 if ((TYPE_CODE(type) == TYPE_CODE_INT) ||
2155 (TYPE_CODE(type) == TYPE_CODE_ENUM) ||
2156 (TYPE_CODE(type) == TYPE_CODE_CHAR) ||
2157 (TYPE_CODE(type) == TYPE_CODE_BOOL))
2158 size = ALIGN_ARG(size, len);
2159 else
2160 size = ALIGN_ARG(size, sizeof(long));
2161 size += len;
2162 }
2163 }
2164
2165 }
2166
2167
2168 /* recalculate the stack pointer, leaving enough space for the memory argument list and
2169 realigning the stack pointer. */
2170 if (size != 0)
2171 {
2172 arg_ptr = sp - size;
2173
2174 arg_ptr = arg_ptr & (-16); /* realign stack */
2175 write_register (R28,arg_ptr);
2176 sp = arg_ptr;
2177 }
2178
2179return (sp);
2180
2181}
2182void i860_extract_return_value(type,regbuf,valbuf)
2183struct type *type;
2184char regbuf[REGISTER_BYTES];
2185char *valbuf;
2186{
2187 register int len = TYPE_LENGTH (type);
2188 double tmp_db;
2189 float tmp_flt;
2190
2191 if ((TYPE_CODE(type) == TYPE_CODE_FLT))
2192 {
2193 if (len == sizeof (float))
2194 {
2195 /* FIXME
2196 NOTE that this assumes that the function declaration was ANSI_CONFORMANT --
2197 at the present time I can't think of ANY WAY to disambiguate the two following
2198 cases:
2199 float really_does_return_a_float(float ff)
2200 { ...}
2201 and
2202 float actually_returns_a_double(ff)
2203 float ff;
2204 {...}
2205 */
2206 bcopy ((char *) (regbuf) + REGISTER_BYTE(ADJ_FREG(F8)), (valbuf), TYPE_LENGTH (type)) ;
2207 }
2208 else
2209 bcopy ((char *) (regbuf) + REGISTER_BYTE(F8), (valbuf), TYPE_LENGTH (type)) ;
2210 }
2211 else
2212 bcopy ((char *) (regbuf) + REGISTER_BYTE(R16), (valbuf), TYPE_LENGTH (type));
2213
2214}
2215void i860_store_return_value(type,valbuf)
2216struct type *type;
2217char *valbuf;
2218{
2219 register int len = TYPE_LENGTH (type);
2220 double tmp_db;
2221
2222 if ((TYPE_CODE(type) == TYPE_CODE_FLT) )
2223 {
2224 write_register_bytes (REGISTER_BYTE (F8), valbuf, len);
2225 }
2226 else
2227 write_register_bytes (REGISTER_BYTE (R16), valbuf, TYPE_LENGTH (type));
2228
2229}
ca8820f9 2230
Empty description
This page took 0.370406 seconds and 4 git commands to generate.