[binutils.git] / opcodes / xstormy16-dis.c

/* Disassembler interface for targets using CGEN. -*- C -*-
   CGEN: Cpu tools GENerator

   THIS FILE IS MACHINE GENERATED WITH CGEN.
   - the resultant file is machine generated, cgen-dis.in isn't

   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
   2008  Free Software Foundation, Inc.

   This file is part of libopcodes.

   This library is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   It is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

/* ??? Eventually more and more of this stuff can go to cpu-independent files.
   Keep that in mind.  */

#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "dis-asm.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "xstormy16-desc.h"
#include "xstormy16-opc.h"
#include "opintl.h"

/* Default text to print if an instruction isn't recognized.  */
#define UNKNOWN_INSN_MSG _("*unknown*")

static void print_normal
  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
static void print_address
  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
static void print_keyword
  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
static void print_insn_normal
  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
static int print_insn
  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
static int default_print_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
static int read_insn
  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
   unsigned long *);
\f
/* -- disassembler routines inserted here.  */


void xstormy16_cgen_print_operand
  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);

/* Main entry point for printing operands.
   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
   of dis-asm.h on cgen.h.

   This function is basically just a big switch statement.  Earlier versions
   used tables to look up the function to use, but
   - if the table contains both assembler and disassembler functions then
     the disassembler contains much of the assembler and vice-versa,
   - there's a lot of inlining possibilities as things grow,
   - using a switch statement avoids the function call overhead.

   This function could be moved into `print_insn_normal', but keeping it
   separate makes clear the interface between `print_insn_normal' and each of
   the handlers.  */

void
xstormy16_cgen_print_operand (CGEN_CPU_DESC cd,
			   int opindex,
			   void * xinfo,
			   CGEN_FIELDS *fields,
			   void const *attrs ATTRIBUTE_UNUSED,
			   bfd_vma pc,
			   int length)
{
  disassemble_info *info = (disassemble_info *) xinfo;

  switch (opindex)
    {
    case XSTORMY16_OPERAND_RB :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0);
      break;
    case XSTORMY16_OPERAND_RBJ :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0);
      break;
    case XSTORMY16_OPERAND_RD :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0);
      break;
    case XSTORMY16_OPERAND_RDM :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0);
      break;
    case XSTORMY16_OPERAND_RM :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0);
      break;
    case XSTORMY16_OPERAND_RS :
      print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0);
      break;
    case XSTORMY16_OPERAND_ABS24 :
      print_normal (cd, info, fields->f_abs24, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
      break;
    case XSTORMY16_OPERAND_BCOND2 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0);
      break;
    case XSTORMY16_OPERAND_BCOND5 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0);
      break;
    case XSTORMY16_OPERAND_HMEM8 :
      print_normal (cd, info, fields->f_hmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM12 :
      print_normal (cd, info, fields->f_imm12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM16 :
      print_normal (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
      break;
    case XSTORMY16_OPERAND_IMM2 :
      print_normal (cd, info, fields->f_imm2, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM3 :
      print_normal (cd, info, fields->f_imm3, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM3B :
      print_normal (cd, info, fields->f_imm3b, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM4 :
      print_normal (cd, info, fields->f_imm4, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM8 :
      print_normal (cd, info, fields->f_imm8, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_IMM8SMALL :
      print_normal (cd, info, fields->f_imm8, 0, pc, length);
      break;
    case XSTORMY16_OPERAND_LMEM8 :
      print_normal (cd, info, fields->f_lmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL12 :
      print_normal (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL12A :
      print_normal (cd, info, fields->f_rel12a, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL8_2 :
      print_normal (cd, info, fields->f_rel8_2, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_REL8_4 :
      print_normal (cd, info, fields->f_rel8_4, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
      break;
    case XSTORMY16_OPERAND_WS2 :
      print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0);
      break;

    default :
      /* xgettext:c-format */
      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
	       opindex);
    abort ();
  }
}

cgen_print_fn * const xstormy16_cgen_print_handlers[] = 
{
  print_insn_normal,
};


void
xstormy16_cgen_init_dis (CGEN_CPU_DESC cd)
{
  xstormy16_cgen_init_opcode_table (cd);
  xstormy16_cgen_init_ibld_table (cd);
  cd->print_handlers = & xstormy16_cgen_print_handlers[0];
  cd->print_operand = xstormy16_cgen_print_operand;
}

\f
/* Default print handler.  */

static void
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	      void *dis_info,
	      long value,
	      unsigned int attrs,
	      bfd_vma pc ATTRIBUTE_UNUSED,
	      int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

#ifdef CGEN_PRINT_NORMAL
  CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
#endif

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* nothing to do */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", value);
}

/* Default address handler.  */

static void
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       bfd_vma value,
	       unsigned int attrs,
	       bfd_vma pc ATTRIBUTE_UNUSED,
	       int length ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;

#ifdef CGEN_PRINT_ADDRESS
  CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
#endif

  /* Print the operand as directed by the attributes.  */
  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
    ; /* Nothing to do.  */
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
    (*info->print_address_func) (value, info);
  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
    (*info->fprintf_func) (info->stream, "%ld", (long) value);
  else
    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
}

/* Keyword print handler.  */

static void
print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	       void *dis_info,
	       CGEN_KEYWORD *keyword_table,
	       long value,
	       unsigned int attrs ATTRIBUTE_UNUSED)
{
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_KEYWORD_ENTRY *ke;

  ke = cgen_keyword_lookup_value (keyword_table, value);
  if (ke != NULL)
    (*info->fprintf_func) (info->stream, "%s", ke->name);
  else
    (*info->fprintf_func) (info->stream, "???");
}
\f
/* Default insn printer.

   DIS_INFO is defined as `void *' so the disassembler needn't know anything
   about disassemble_info.  */

static void
print_insn_normal (CGEN_CPU_DESC cd,
		   void *dis_info,
		   const CGEN_INSN *insn,
		   CGEN_FIELDS *fields,
		   bfd_vma pc,
		   int length)
{
  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
  disassemble_info *info = (disassemble_info *) dis_info;
  const CGEN_SYNTAX_CHAR_TYPE *syn;

  CGEN_INIT_PRINT (cd);

  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
    {
      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	  continue;
	}
      if (CGEN_SYNTAX_CHAR_P (*syn))
	{
	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
	  continue;
	}

      /* We have an operand.  */
      xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
				 fields, CGEN_INSN_ATTRS (insn), pc, length);
    }
}
\f
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
   the extract info.
   Returns 0 if all is well, non-zero otherwise.  */

static int
read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	   bfd_vma pc,
	   disassemble_info *info,
	   bfd_byte *buf,
	   int buflen,
	   CGEN_EXTRACT_INFO *ex_info,
	   unsigned long *insn_value)
{
  int status = (*info->read_memory_func) (pc, buf, buflen, info);

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  ex_info->dis_info = info;
  ex_info->valid = (1 << buflen) - 1;
  ex_info->insn_bytes = buf;

  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
  return 0;
}

/* Utility to print an insn.
   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occurs fetching data (memory_error_func will have
   been called).  */

static int
print_insn (CGEN_CPU_DESC cd,
	    bfd_vma pc,
	    disassemble_info *info,
	    bfd_byte *buf,
	    unsigned int buflen)
{
  CGEN_INSN_INT insn_value;
  const CGEN_INSN_LIST *insn_list;
  CGEN_EXTRACT_INFO ex_info;
  int basesize;

  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
  basesize = cd->base_insn_bitsize < buflen * 8 ?
                                     cd->base_insn_bitsize : buflen * 8;
  insn_value = cgen_get_insn_value (cd, buf, basesize);


  /* Fill in ex_info fields like read_insn would.  Don't actually call
     read_insn, since the incoming buffer is already read (and possibly
     modified a la m32r).  */
  ex_info.valid = (1 << buflen) - 1;
  ex_info.dis_info = info;
  ex_info.insn_bytes = buf;

  /* The instructions are stored in hash lists.
     Pick the first one and keep trying until we find the right one.  */

  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
  while (insn_list != NULL)
    {
      const CGEN_INSN *insn = insn_list->insn;
      CGEN_FIELDS fields;
      int length;
      unsigned long insn_value_cropped;

#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
      /* Not needed as insn shouldn't be in hash lists if not supported.  */
      /* Supported by this cpu?  */
      if (! xstormy16_cgen_insn_supported (cd, insn))
        {
          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	  continue;
        }
#endif

      /* Basic bit mask must be correct.  */
      /* ??? May wish to allow target to defer this check until the extract
	 handler.  */

      /* Base size may exceed this instruction's size.  Extract the
         relevant part from the buffer. */
      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
					   info->endian == BFD_ENDIAN_BIG);
      else
	insn_value_cropped = insn_value;

      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	  == CGEN_INSN_BASE_VALUE (insn))
	{
	  /* Printing is handled in two passes.  The first pass parses the
	     machine insn and extracts the fields.  The second pass prints
	     them.  */

	  /* Make sure the entire insn is loaded into insn_value, if it
	     can fit.  */
	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	    {
	      unsigned long full_insn_value;
	      int rc = read_insn (cd, pc, info, buf,
				  CGEN_INSN_BITSIZE (insn) / 8,
				  & ex_info, & full_insn_value);
	      if (rc != 0)
		return rc;
	      length = CGEN_EXTRACT_FN (cd, insn)
		(cd, insn, &ex_info, full_insn_value, &fields, pc);
	    }
	  else
	    length = CGEN_EXTRACT_FN (cd, insn)
	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);

	  /* Length < 0 -> error.  */
	  if (length < 0)
	    return length;
	  if (length > 0)
	    {
	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
	      /* Length is in bits, result is in bytes.  */
	      return length / 8;
	    }
	}

      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
    }

  return 0;
}

/* Default value for CGEN_PRINT_INSN.
   The result is the size of the insn in bytes or zero for an unknown insn
   or -1 if an error occured fetching bytes.  */

#ifndef CGEN_PRINT_INSN
#define CGEN_PRINT_INSN default_print_insn
#endif

static int
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
  bfd_byte buf[CGEN_MAX_INSN_SIZE];
  int buflen;
  int status;

  /* Attempt to read the base part of the insn.  */
  buflen = cd->base_insn_bitsize / 8;
  status = (*info->read_memory_func) (pc, buf, buflen, info);

  /* Try again with the minimum part, if min < base.  */
  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
    {
      buflen = cd->min_insn_bitsize / 8;
      status = (*info->read_memory_func) (pc, buf, buflen, info);
    }

  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }

  return print_insn (cd, pc, info, buf, buflen);
}

/* Main entry point.
   Print one instruction from PC on INFO->STREAM.
   Return the size of the instruction (in bytes).  */

typedef struct cpu_desc_list
{
  struct cpu_desc_list *next;
  CGEN_BITSET *isa;
  int mach;
  int endian;
  CGEN_CPU_DESC cd;
} cpu_desc_list;

int
print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
		? CGEN_ENDIAN_BIG
		: CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_xstormy16
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
	  || mach != prev_mach
	  || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
	{
	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
	      cl->mach == mach &&
	      cl->endian == endian)
	    {
	      cd = cl->cd;
 	      prev_isa = cd->isas;
	      break;
	    }
	}
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
	abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
				 CGEN_CPU_OPEN_BFDMACH, mach_name,
				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
				 CGEN_CPU_OPEN_END);
      if (!cd)
	abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      xstormy16_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}
Commit	Line	Data
93fbbb04 GK	1	/* Disassembler interface for targets using CGEN. -- C --
	2	CGEN: Cpu tools GENerator
	3
47b0e7ad NC	4	THIS FILE IS MACHINE GENERATED WITH CGEN.
47b0e7ad NC	5	- the resultant file is machine generated, cgen-dis.in isn't
93fbbb04	6
6f3b91a6 AM	7	Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007,
6f3b91a6 AM	8	2008 Free Software Foundation, Inc.
93fbbb04	9
9b201bb5	10	This file is part of libopcodes.
93fbbb04	11
9b201bb5	12	This library is free software; you can redistribute it and/or modify
47b0e7ad	13	it under the terms of the GNU General Public License as published by
9b201bb5	14	the Free Software Foundation; either version 3, or (at your option)
47b0e7ad	15	any later version.
93fbbb04	16
9b201bb5 NC	17	It is distributed in the hope that it will be useful, but WITHOUT
	18	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	19	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	20	License for more details.
93fbbb04	21
47b0e7ad NC	22	You should have received a copy of the GNU General Public License
	23	along with this program; if not, write to the Free Software Foundation, Inc.,
	24	51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
93fbbb04 GK	25
	26	/* ??? Eventually more and more of this stuff can go to cpu-independent files.
	27	Keep that in mind. */
	28
	29	#include "sysdep.h"
	30	#include <stdio.h>
	31	#include "ansidecl.h"
	32	#include "dis-asm.h"
	33	#include "bfd.h"
	34	#include "symcat.h"
98f70fc4	35	#include "libiberty.h"
93fbbb04 GK	36	#include "xstormy16-desc.h"
	37	#include "xstormy16-opc.h"
	38	#include "opintl.h"
	39
	40	/* Default text to print if an instruction isn't recognized. */
	41	#define UNKNOWN_INSN_MSG _("unknown")
	42
	43	static void print_normal
ffead7ae	44	(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
93fbbb04	45	static void print_address
bf143b25	46	(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
93fbbb04	47	static void print_keyword
bf143b25	48	(CGEN_CPU_DESC, void , CGEN_KEYWORD , long, unsigned int) ATTRIBUTE_UNUSED;
93fbbb04	49	static void print_insn_normal
ffead7ae	50	(CGEN_CPU_DESC, void , const CGEN_INSN , CGEN_FIELDS *, bfd_vma, int);
93fbbb04	51	static int print_insn
33b71eeb	52	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , unsigned);
93fbbb04	53	static int default_print_insn
bf143b25	54	(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
93fbbb04	55	static int read_insn
33b71eeb	56	(CGEN_CPU_DESC, bfd_vma, disassemble_info , bfd_byte , int, CGEN_EXTRACT_INFO *,
ffead7ae	57	unsigned long *);
93fbbb04	58	\f
47b0e7ad	59	/* -- disassembler routines inserted here. */
93fbbb04 GK	60
	61
	62	void xstormy16_cgen_print_operand
47b0e7ad	63	(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS , void const , bfd_vma, int);
93fbbb04 GK	64
	65	/* Main entry point for printing operands.
	66	XINFO is a `void ' and not a `disassemble_info ' to not put a requirement
	67	of dis-asm.h on cgen.h.
	68
	69	This function is basically just a big switch statement. Earlier versions
	70	used tables to look up the function to use, but
	71	- if the table contains both assembler and disassembler functions then
	72	the disassembler contains much of the assembler and vice-versa,
	73	- there's a lot of inlining possibilities as things grow,
	74	- using a switch statement avoids the function call overhead.
	75
	76	This function could be moved into `print_insn_normal', but keeping it
	77	separate makes clear the interface between `print_insn_normal' and each of
	78	the handlers. */
	79
	80	void
47b0e7ad NC	81	xstormy16_cgen_print_operand (CGEN_CPU_DESC cd,
	82	int opindex,
	83	void * xinfo,
	84	CGEN_FIELDS *fields,
	85	void const *attrs ATTRIBUTE_UNUSED,
	86	bfd_vma pc,
	87	int length)
93fbbb04	88	{
47b0e7ad	89	disassemble_info info = (disassemble_info ) xinfo;
93fbbb04 GK	90
	91	switch (opindex)
	92	{
	93	case XSTORMY16_OPERAND_RB :
1951c6f7	94	print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0);
93fbbb04 GK	95	break;
93fbbb04 GK	96	case XSTORMY16_OPERAND_RBJ :
1951c6f7	97	print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0);
93fbbb04 GK	98	break;
	99	case XSTORMY16_OPERAND_RD :
	100	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0);
	101	break;
	102	case XSTORMY16_OPERAND_RDM :
	103	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0);
	104	break;
	105	case XSTORMY16_OPERAND_RM :
	106	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0);
	107	break;
	108	case XSTORMY16_OPERAND_RS :
	109	print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0);
	110	break;
	111	case XSTORMY16_OPERAND_ABS24 :
	112	print_normal (cd, info, fields->f_abs24, 0\|(1<<CGEN_OPERAND_ABS_ADDR)\|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
	113	break;
	114	case XSTORMY16_OPERAND_BCOND2 :
	115	print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0);
	116	break;
	117	case XSTORMY16_OPERAND_BCOND5 :
	118	print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0);
	119	break;
	120	case XSTORMY16_OPERAND_HMEM8 :
	121	print_normal (cd, info, fields->f_hmem8, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	122	break;
	123	case XSTORMY16_OPERAND_IMM12 :
	124	print_normal (cd, info, fields->f_imm12, 0\|(1<<CGEN_OPERAND_SIGNED), pc, length);
	125	break;
	126	case XSTORMY16_OPERAND_IMM16 :
	127	print_normal (cd, info, fields->f_imm16, 0\|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
	128	break;
	129	case XSTORMY16_OPERAND_IMM2 :
	130	print_normal (cd, info, fields->f_imm2, 0, pc, length);
	131	break;
	132	case XSTORMY16_OPERAND_IMM3 :
	133	print_normal (cd, info, fields->f_imm3, 0, pc, length);
	134	break;
	135	case XSTORMY16_OPERAND_IMM3B :
	136	print_normal (cd, info, fields->f_imm3b, 0, pc, length);
	137	break;
	138	case XSTORMY16_OPERAND_IMM4 :
	139	print_normal (cd, info, fields->f_imm4, 0, pc, length);
	140	break;
	141	case XSTORMY16_OPERAND_IMM8 :
	142	print_normal (cd, info, fields->f_imm8, 0, pc, length);
	143	break;
	144	case XSTORMY16_OPERAND_IMM8SMALL :
	145	print_normal (cd, info, fields->f_imm8, 0, pc, length);
	146	break;
	147	case XSTORMY16_OPERAND_LMEM8 :
	148	print_normal (cd, info, fields->f_lmem8, 0\|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
	149	break;
	150	case XSTORMY16_OPERAND_REL12 :
	151	print_normal (cd, info, fields->f_rel12, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	152	break;
	153	case XSTORMY16_OPERAND_REL12A :
	154	print_normal (cd, info, fields->f_rel12a, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	155	break;
	156	case XSTORMY16_OPERAND_REL8_2 :
	157	print_normal (cd, info, fields->f_rel8_2, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	158	break;
	159	case XSTORMY16_OPERAND_REL8_4 :
	160	print_normal (cd, info, fields->f_rel8_4, 0\|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
	161	break;
162	case XSTORMY16_OPERAND_WS2 :
163	print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0);
164	break;
165
166	default :
167	/* xgettext:c-format */
168	fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
169	opindex);
170	abort ();
171	}
172	}
173
174	cgen_print_fn * const xstormy16_cgen_print_handlers[] =
175	{
176	print_insn_normal,
177	};
178
179
180	void
47b0e7ad	181	xstormy16_cgen_init_dis (CGEN_CPU_DESC cd)
93fbbb04 GK	182	{
	183	xstormy16_cgen_init_opcode_table (cd);
	184	xstormy16_cgen_init_ibld_table (cd);
	185	cd->print_handlers = & xstormy16_cgen_print_handlers[0];
	186	cd->print_operand = xstormy16_cgen_print_operand;
	187	}
	188
	189	\f
	190	/* Default print handler. */
	191
	192	static void
ffead7ae MM	193	print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	194	void *dis_info,
	195	long value,
	196	unsigned int attrs,
	197	bfd_vma pc ATTRIBUTE_UNUSED,
	198	int length ATTRIBUTE_UNUSED)
93fbbb04 GK	199	{
	200	disassemble_info info = (disassemble_info ) dis_info;
	201
	202	#ifdef CGEN_PRINT_NORMAL
	203	CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
	204	#endif
	205
	206	/* Print the operand as directed by the attributes. */
	207	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
	208	; /* nothing to do */
	209	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	210	(*info->fprintf_func) (info->stream, "%ld", value);
	211	else
	212	(*info->fprintf_func) (info->stream, "0x%lx", value);
	213	}
	214
	215	/* Default address handler. */
	216
	217	static void
ffead7ae MM	218	print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	219	void *dis_info,
	220	bfd_vma value,
	221	unsigned int attrs,
	222	bfd_vma pc ATTRIBUTE_UNUSED,
	223	int length ATTRIBUTE_UNUSED)
93fbbb04 GK	224	{
	225	disassemble_info info = (disassemble_info ) dis_info;
	226
	227	#ifdef CGEN_PRINT_ADDRESS
	228	CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
	229	#endif
	230
	231	/* Print the operand as directed by the attributes. */
	232	if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
47b0e7ad	233	; /* Nothing to do. */
93fbbb04 GK	234	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
	235	(*info->print_address_func) (value, info);
	236	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
	237	(*info->print_address_func) (value, info);
	238	else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
	239	(*info->fprintf_func) (info->stream, "%ld", (long) value);
	240	else
	241	(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
	242	}
	243
	244	/* Keyword print handler. */
	245
	246	static void
ffead7ae MM	247	print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	248	void *dis_info,
	249	CGEN_KEYWORD *keyword_table,
	250	long value,
	251	unsigned int attrs ATTRIBUTE_UNUSED)
93fbbb04 GK	252	{
	253	disassemble_info info = (disassemble_info ) dis_info;
	254	const CGEN_KEYWORD_ENTRY *ke;
	255
	256	ke = cgen_keyword_lookup_value (keyword_table, value);
	257	if (ke != NULL)
	258	(*info->fprintf_func) (info->stream, "%s", ke->name);
	259	else
	260	(*info->fprintf_func) (info->stream, "???");
	261	}
	262	\f
	263	/* Default insn printer.
	264
ffead7ae	265	DIS_INFO is defined as `void *' so the disassembler needn't know anything
93fbbb04 GK	266	about disassemble_info. */
	267
	268	static void
ffead7ae MM	269	print_insn_normal (CGEN_CPU_DESC cd,
	270	void *dis_info,
	271	const CGEN_INSN *insn,
	272	CGEN_FIELDS *fields,
	273	bfd_vma pc,
	274	int length)
93fbbb04 GK	275	{
	276	const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
	277	disassemble_info info = (disassemble_info ) dis_info;
	278	const CGEN_SYNTAX_CHAR_TYPE *syn;
	279
	280	CGEN_INIT_PRINT (cd);
	281
	282	for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
	283	{
	284	if (CGEN_SYNTAX_MNEMONIC_P (*syn))
	285	{
	286	(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
	287	continue;
	288	}
	289	if (CGEN_SYNTAX_CHAR_P (*syn))
	290	{
	291	(info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (syn));
	292	continue;
	293	}
	294
	295	/* We have an operand. */
	296	xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
	297	fields, CGEN_INSN_ATTRS (insn), pc, length);
	298	}
	299	}
	300	\f
	301	/* Subroutine of print_insn. Reads an insn into the given buffers and updates
	302	the extract info.
	303	Returns 0 if all is well, non-zero otherwise. */
	304
	305	static int
ffead7ae MM	306	read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
	307	bfd_vma pc,
	308	disassemble_info *info,
33b71eeb	309	bfd_byte *buf,
ffead7ae MM	310	int buflen,
	311	CGEN_EXTRACT_INFO *ex_info,
	312	unsigned long *insn_value)
93fbbb04 GK	313	{
93fbbb04 GK	314	int status = (*info->read_memory_func) (pc, buf, buflen, info);
47b0e7ad	315
93fbbb04 GK	316	if (status != 0)
	317	{
	318	(*info->memory_error_func) (status, pc, info);
	319	return -1;
	320	}
	321
	322	ex_info->dis_info = info;
	323	ex_info->valid = (1 << buflen) - 1;
	324	ex_info->insn_bytes = buf;
	325
	326	insn_value = bfd_get_bits (buf, buflen 8, info->endian == BFD_ENDIAN_BIG);
	327	return 0;
	328	}
	329
	330	/* Utility to print an insn.
	331	BUF is the base part of the insn, target byte order, BUFLEN bytes long.
	332	The result is the size of the insn in bytes or zero for an unknown insn
	333	or -1 if an error occurs fetching data (memory_error_func will have
	334	been called). */
	335
	336	static int
ffead7ae MM	337	print_insn (CGEN_CPU_DESC cd,
	338	bfd_vma pc,
	339	disassemble_info *info,
33b71eeb	340	bfd_byte *buf,
ffead7ae	341	unsigned int buflen)
93fbbb04 GK	342	{
	343	CGEN_INSN_INT insn_value;
	344	const CGEN_INSN_LIST *insn_list;
	345	CGEN_EXTRACT_INFO ex_info;
1951c6f7	346	int basesize;
93fbbb04 GK	347
93fbbb04 GK	348	/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
1951c6f7 MG	349	basesize = cd->base_insn_bitsize < buflen * 8 ?
	350	cd->base_insn_bitsize : buflen * 8;
	351	insn_value = cgen_get_insn_value (cd, buf, basesize);
	352
93fbbb04 GK	353
	354	/* Fill in ex_info fields like read_insn would. Don't actually call
	355	read_insn, since the incoming buffer is already read (and possibly
	356	modified a la m32r). */
	357	ex_info.valid = (1 << buflen) - 1;
	358	ex_info.dis_info = info;
	359	ex_info.insn_bytes = buf;
	360
	361	/* The instructions are stored in hash lists.
	362	Pick the first one and keep trying until we find the right one. */
	363
33b71eeb	364	insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
93fbbb04 GK	365	while (insn_list != NULL)
	366	{
	367	const CGEN_INSN *insn = insn_list->insn;
	368	CGEN_FIELDS fields;
	369	int length;
	370	unsigned long insn_value_cropped;
	371
	372	#ifdef CGEN_VALIDATE_INSN_SUPPORTED
	373	/* Not needed as insn shouldn't be in hash lists if not supported. */
	374	/* Supported by this cpu? */
	375	if (! xstormy16_cgen_insn_supported (cd, insn))
	376	{
	377	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	378	continue;
	379	}
	380	#endif
	381
	382	/* Basic bit mask must be correct. */
	383	/* ??? May wish to allow target to defer this check until the extract
	384	handler. */
	385
	386	/* Base size may exceed this instruction's size. Extract the
	387	relevant part from the buffer. */
	388	if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
	389	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	390	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
	391	info->endian == BFD_ENDIAN_BIG);
	392	else
	393	insn_value_cropped = insn_value;
	394
	395	if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
	396	== CGEN_INSN_BASE_VALUE (insn))
	397	{
	398	/* Printing is handled in two passes. The first pass parses the
	399	machine insn and extracts the fields. The second pass prints
	400	them. */
	401
	402	/* Make sure the entire insn is loaded into insn_value, if it
	403	can fit. */
	404	if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
	405	(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
	406	{
	407	unsigned long full_insn_value;
	408	int rc = read_insn (cd, pc, info, buf,
	409	CGEN_INSN_BITSIZE (insn) / 8,
	410	& ex_info, & full_insn_value);
	411	if (rc != 0)
	412	return rc;
	413	length = CGEN_EXTRACT_FN (cd, insn)
	414	(cd, insn, &ex_info, full_insn_value, &fields, pc);
	415	}
	416	else
	417	length = CGEN_EXTRACT_FN (cd, insn)
	418	(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
	419
47b0e7ad	420	/* Length < 0 -> error. */
93fbbb04 GK	421	if (length < 0)
	422	return length;
	423	if (length > 0)
	424	{
	425	CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
47b0e7ad	426	/* Length is in bits, result is in bytes. */
93fbbb04 GK	427	return length / 8;
	428	}
	429	}
	430
	431	insn_list = CGEN_DIS_NEXT_INSN (insn_list);
	432	}
	433
	434	return 0;
	435	}
	436
	437	/* Default value for CGEN_PRINT_INSN.
	438	The result is the size of the insn in bytes or zero for an unknown insn
	439	or -1 if an error occured fetching bytes. */
	440
	441	#ifndef CGEN_PRINT_INSN
	442	#define CGEN_PRINT_INSN default_print_insn
	443	#endif
	444
	445	static int
ffead7ae	446	default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
93fbbb04	447	{
33b71eeb	448	bfd_byte buf[CGEN_MAX_INSN_SIZE];
93fbbb04 GK	449	int buflen;
	450	int status;
	451
	452	/* Attempt to read the base part of the insn. */
	453	buflen = cd->base_insn_bitsize / 8;
	454	status = (*info->read_memory_func) (pc, buf, buflen, info);
	455
	456	/* Try again with the minimum part, if min < base. */
	457	if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
	458	{
	459	buflen = cd->min_insn_bitsize / 8;
	460	status = (*info->read_memory_func) (pc, buf, buflen, info);
	461	}
	462
	463	if (status != 0)
	464	{
	465	(*info->memory_error_func) (status, pc, info);
	466	return -1;
	467	}
	468
	469	return print_insn (cd, pc, info, buf, buflen);
	470	}
	471
	472	/* Main entry point.
	473	Print one instruction from PC on INFO->STREAM.
	474	Return the size of the instruction (in bytes). */
	475
47b0e7ad NC	476	typedef struct cpu_desc_list
47b0e7ad NC	477	{
a978a3e5	478	struct cpu_desc_list *next;
fb53f5a8	479	CGEN_BITSET *isa;
a978a3e5 NC	480	int mach;
	481	int endian;
	482	CGEN_CPU_DESC cd;
	483	} cpu_desc_list;
	484
93fbbb04	485	int
ffead7ae	486	print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
93fbbb04	487	{
a978a3e5 NC	488	static cpu_desc_list *cd_list = 0;
a978a3e5 NC	489	cpu_desc_list *cl = 0;
93fbbb04	490	static CGEN_CPU_DESC cd = 0;
fb53f5a8	491	static CGEN_BITSET *prev_isa;
93fbbb04 GK	492	static int prev_mach;
	493	static int prev_endian;
	494	int length;
fb53f5a8 DB	495	CGEN_BITSET *isa;
fb53f5a8 DB	496	int mach;
93fbbb04 GK	497	int endian = (info->endian == BFD_ENDIAN_BIG
	498	? CGEN_ENDIAN_BIG
	499	: CGEN_ENDIAN_LITTLE);
	500	enum bfd_architecture arch;
	501
	502	/* ??? gdb will set mach but leave the architecture as "unknown" */
	503	#ifndef CGEN_BFD_ARCH
	504	#define CGEN_BFD_ARCH bfd_arch_xstormy16
	505	#endif
	506	arch = info->arch;
	507	if (arch == bfd_arch_unknown)
	508	arch = CGEN_BFD_ARCH;
	509
	510	/* There's no standard way to compute the machine or isa number
	511	so we leave it to the target. */
	512	#ifdef CGEN_COMPUTE_MACH
	513	mach = CGEN_COMPUTE_MACH (info);
	514	#else
	515	mach = info->mach;
	516	#endif
	517
	518	#ifdef CGEN_COMPUTE_ISA
fb53f5a8 DB	519	{
	520	static CGEN_BITSET *permanent_isa;
	521
	522	if (!permanent_isa)
	523	permanent_isa = cgen_bitset_create (MAX_ISAS);
	524	isa = permanent_isa;
	525	cgen_bitset_clear (isa);
	526	cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
	527	}
93fbbb04	528	#else
a978a3e5	529	isa = info->insn_sets;
93fbbb04 GK	530	#endif
93fbbb04 GK	531
a978a3e5	532	/* If we've switched cpu's, try to find a handle we've used before */
93fbbb04	533	if (cd
fb53f5a8	534	&& (cgen_bitset_compare (isa, prev_isa) != 0
93fbbb04 GK	535	\|\| mach != prev_mach
	536	\|\| endian != prev_endian))
	537	{
93fbbb04	538	cd = 0;
a978a3e5 NC	539	for (cl = cd_list; cl; cl = cl->next)
a978a3e5 NC	540	{
fb53f5a8	541	if (cgen_bitset_compare (cl->isa, isa) == 0 &&
a978a3e5 NC	542	cl->mach == mach &&
	543	cl->endian == endian)
	544	{
	545	cd = cl->cd;
fb53f5a8	546	prev_isa = cd->isas;
a978a3e5 NC	547	break;
	548	}
	549	}
	550	}
93fbbb04 GK	551
	552	/* If we haven't initialized yet, initialize the opcode table. */
	553	if (! cd)
	554	{
	555	const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
	556	const char *mach_name;
	557
	558	if (!arch_type)
	559	abort ();
	560	mach_name = arch_type->printable_name;
	561
fb53f5a8	562	prev_isa = cgen_bitset_copy (isa);
93fbbb04 GK	563	prev_mach = mach;
	564	prev_endian = endian;
	565	cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
	566	CGEN_CPU_OPEN_BFDMACH, mach_name,
	567	CGEN_CPU_OPEN_ENDIAN, prev_endian,
	568	CGEN_CPU_OPEN_END);
	569	if (!cd)
	570	abort ();
a978a3e5	571
47b0e7ad	572	/* Save this away for future reference. */
a978a3e5 NC	573	cl = xmalloc (sizeof (struct cpu_desc_list));
a978a3e5 NC	574	cl->cd = cd;
fb53f5a8	575	cl->isa = prev_isa;
a978a3e5 NC	576	cl->mach = mach;
	577	cl->endian = endian;
	578	cl->next = cd_list;
	579	cd_list = cl;
	580
93fbbb04 GK	581	xstormy16_cgen_init_dis (cd);
	582	}
	583
	584	/* We try to have as much common code as possible.
	585	But at this point some targets need to take over. */
	586	/* ??? Some targets may need a hook elsewhere. Try to avoid this,
	587	but if not possible try to move this hook elsewhere rather than
	588	have two hooks. */
	589	length = CGEN_PRINT_INSN (cd, pc, info);
	590	if (length > 0)
	591	return length;
	592	if (length < 0)
	593	return -1;
	594
	595	(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
	596	return cd->default_insn_bitsize / 8;
	597	}