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2003-06-22 Andrew Cagney <[email protected]>
[binutils.git] / sim / d30v / cpu.h
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AC		 1/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */
2/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */
3/* OBSOLETE Contributed by Cygnus Support. */
4/* OBSOLETE */
5/* OBSOLETE This file is part of GDB, the GNU debugger. */
6/* OBSOLETE */
7/* OBSOLETE This program is free software; you can redistribute it and/or modify */
8/* OBSOLETE it under the terms of the GNU General Public License as published by */
9/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */
10/* OBSOLETE any later version. */
11/* OBSOLETE */
12/* OBSOLETE This program is distributed in the hope that it will be useful, */
13/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
14/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
15/* OBSOLETE GNU General Public License for more details. */
16/* OBSOLETE */
17/* OBSOLETE You should have received a copy of the GNU General Public License along */
18/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */
19/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */
20/* OBSOLETE */
21/* OBSOLETE */
22/* OBSOLETE #ifndef _CPU_H_ */
23/* OBSOLETE #define _CPU_H_ */
24/* OBSOLETE */
25/* OBSOLETE enum { */
26/* OBSOLETE NR_GENERAL_PURPOSE_REGISTERS = 64, */
27/* OBSOLETE NR_CONTROL_REGISTERS = 64, */
28/* OBSOLETE NR_ACCUMULATORS = 2, */
29/* OBSOLETE STACK_POINTER_GPR = 63, */
30/* OBSOLETE NR_STACK_POINTERS = 2, */
31/* OBSOLETE }; */
32/* OBSOLETE */
33/* OBSOLETE enum { */
34/* OBSOLETE processor_status_word_cr = 0, */
35/* OBSOLETE backup_processor_status_word_cr = 1, */
36/* OBSOLETE program_counter_cr = 2, */
37/* OBSOLETE backup_program_counter_cr = 3, */
38/* OBSOLETE debug_backup_processor_status_word_cr = 4, */
39/* OBSOLETE debug_backup_program_counter_cr = 5, */
40/* OBSOLETE reserved_6_cr = 6, */
41/* OBSOLETE repeat_count_cr = 7, */
42/* OBSOLETE repeat_start_address_cr = 8, */
43/* OBSOLETE repeat_end_address_cr = 9, */
44/* OBSOLETE modulo_start_address_cr = 10, */
45/* OBSOLETE modulo_end_address_cr = 11, */
46/* OBSOLETE instruction_break_address_cr = 14, */
47/* OBSOLETE eit_vector_base_cr = 15, */
48/* OBSOLETE }; */
49/* OBSOLETE */
50/* OBSOLETE */
51/* OBSOLETE enum { */
52/* OBSOLETE PSW_SM = 0, */
53/* OBSOLETE PSW_EA = 2, */
54/* OBSOLETE PSW_DB = 3, */
55/* OBSOLETE PSW_DS = 4, */
56/* OBSOLETE PSW_IE = 5, */
57/* OBSOLETE PSW_RP = 6, */
58/* OBSOLETE PSW_MD = 7, */
59/* OBSOLETE PSW_F0 = 17, */
60/* OBSOLETE PSW_F1 = 19, */
61/* OBSOLETE PSW_F2 = 21, */
62/* OBSOLETE PSW_F3 = 23, */
63/* OBSOLETE PSW_S = 25, */
64/* OBSOLETE PSW_V = 27, */
65/* OBSOLETE PSW_VA = 29, */
66/* OBSOLETE PSW_C = 31, */
67/* OBSOLETE }; */
68/* OBSOLETE */
69/* OBSOLETE /* aliases for PSW flag numbers (F0..F7) */ */
70/* OBSOLETE enum */
71/* OBSOLETE { */
72/* OBSOLETE PSW_S_FLAG = 4, */
73/* OBSOLETE }; */
74/* OBSOLETE */
75/* OBSOLETE typedef struct _registers { */
76/* OBSOLETE unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS]; */
77/* OBSOLETE /* keep track of the stack pointer */ */
78/* OBSOLETE unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */ */
79/* OBSOLETE unsigned32 current_sp; */
80/* OBSOLETE unsigned32 control[NR_CONTROL_REGISTERS]; */
81/* OBSOLETE unsigned64 accumulator[NR_ACCUMULATORS]; */
82/* OBSOLETE } registers; */
83/* OBSOLETE */
84/* OBSOLETE typedef enum _cpu_units { */
85/* OBSOLETE memory_unit, */
86/* OBSOLETE integer_unit, */
87/* OBSOLETE any_unit, */
88/* OBSOLETE } cpu_units; */
89/* OBSOLETE */
90/* OBSOLETE /* In order to support parallel instructions, which one instruction can be */
91/* OBSOLETE writing to a register that is used as input to another, queue up the */
92/* OBSOLETE writes to the end of the instruction boundaries. */ */
93/* OBSOLETE */
94/* OBSOLETE #define MAX_WRITE32 16 */
95/* OBSOLETE #define MAX_WRITE64 2 */
96/* OBSOLETE */
97/* OBSOLETE struct _write32 { */
98/* OBSOLETE int num; /* # of 32-bit writes queued up */ */
99/* OBSOLETE unsigned32 value[MAX_WRITE32]; /* value to write */ */
100/* OBSOLETE unsigned32 mask[MAX_WRITE32]; /* mask to use */ */
101/* OBSOLETE unsigned32 *ptr[MAX_WRITE32]; /* address to write to */ */
102/* OBSOLETE }; */
103/* OBSOLETE */
104/* OBSOLETE struct _write64 { */
105/* OBSOLETE int num; /* # of 64-bit writes queued up */ */
106/* OBSOLETE unsigned64 value[MAX_WRITE64]; /* value to write */ */
107/* OBSOLETE unsigned64 *ptr[MAX_WRITE64]; /* address to write to */ */
108/* OBSOLETE }; */
109/* OBSOLETE */
110/* OBSOLETE struct _sim_cpu { */
111/* OBSOLETE cpu_units unit; */
112/* OBSOLETE registers regs; */
113/* OBSOLETE sim_cpu_base base; */
114/* OBSOLETE int trace_call_p; /* Whether to do call tracing. */ */
115/* OBSOLETE int trace_trap_p; /* If unknown traps dump out the regs */ */
116/* OBSOLETE int trace_action; /* trace bits at end of instructions */ */
117/* OBSOLETE int left_kills_right_p; /* left insn kills insn in right slot of -> */ */
118/* OBSOLETE int mvtsys_left_p; /* left insn was mvtsys */ */
119/* OBSOLETE int did_trap; /* we did a trap & need to finish it */ */
120/* OBSOLETE struct _write32 write32; /* queued up 32-bit writes */ */
121/* OBSOLETE struct _write64 write64; /* queued up 64-bit writes */ */
122/* OBSOLETE }; */
123/* OBSOLETE */
124/* OBSOLETE #define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr]) */
125/* OBSOLETE #define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr]) */
126/* OBSOLETE #define PSWL (*AL2_4(&PSW)) */
127/* OBSOLETE #define PSWH (*AH2_4(&PSW)) */
128/* OBSOLETE #define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr]) */
129/* OBSOLETE #define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr]) */
130/* OBSOLETE #define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr]) */
131/* OBSOLETE #define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr]) */
132/* OBSOLETE #define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr]) */
133/* OBSOLETE #define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr]) */
134/* OBSOLETE #define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr]) */
135/* OBSOLETE #define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr]) */
136/* OBSOLETE #define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr]) */
137/* OBSOLETE #define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr]) */
138/* OBSOLETE #define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr]) */
139/* OBSOLETE #define GPR (STATE_CPU (sd, 0)->regs.general_purpose) */
140/* OBSOLETE #define GPR_CLEAR(N) (GPR[(N)] = 0) */
141/* OBSOLETE #define ACC (STATE_CPU (sd, 0)->regs.accumulator) */
142/* OBSOLETE #define CREG (STATE_CPU (sd, 0)->regs.control) */
143/* OBSOLETE #define SP (GPR[STACK_POINTER_GPR]) */
144/* OBSOLETE #define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p) */
145/* OBSOLETE #define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p) */
146/* OBSOLETE #define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action) */
147/* OBSOLETE #define TRACE_ACTION_CALL 0x00000001 /* call occurred */ */
148/* OBSOLETE #define TRACE_ACTION_RETURN 0x00000002 /* return occurred */ */
149/* OBSOLETE */
150/* OBSOLETE #define WRITE32 (STATE_CPU (sd, 0)->write32) */
151/* OBSOLETE #define WRITE32_NUM (WRITE32.num) */
152/* OBSOLETE #define WRITE32_PTR(N) (WRITE32.ptr[N]) */
153/* OBSOLETE #define WRITE32_MASK(N) (WRITE32.mask[N]) */
154/* OBSOLETE #define WRITE32_VALUE(N) (WRITE32.value[N]) */
155/* OBSOLETE #define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff) */
156/* OBSOLETE */
157/* OBSOLETE #define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \ */
158/* OBSOLETE do { \ */
159/* OBSOLETE int _num = WRITE32_NUM; \ */
160/* OBSOLETE if (_num >= MAX_WRITE32) \ */
161/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */
162/* OBSOLETE "Too many queued 32-bit writes"); \ */
163/* OBSOLETE WRITE32_PTR(_num) = PTR; \ */
164/* OBSOLETE WRITE32_VALUE(_num) = VALUE; \ */
165/* OBSOLETE WRITE32_MASK(_num) = MASK; \ */
166/* OBSOLETE WRITE32_NUM = _num+1; \ */
167/* OBSOLETE } while (0) */
168/* OBSOLETE */
169/* OBSOLETE #define DID_TRAP (STATE_CPU (sd, 0)->did_trap) */
170/* OBSOLETE */
171/* OBSOLETE #define WRITE64 (STATE_CPU (sd, 0)->write64) */
172/* OBSOLETE #define WRITE64_NUM (WRITE64.num) */
173/* OBSOLETE #define WRITE64_PTR(N) (WRITE64.ptr[N]) */
174/* OBSOLETE #define WRITE64_VALUE(N) (WRITE64.value[N]) */
175/* OBSOLETE #define WRITE64_QUEUE(PTR, VALUE) \ */
176/* OBSOLETE do { \ */
177/* OBSOLETE int _num = WRITE64_NUM; \ */
178/* OBSOLETE if (_num >= MAX_WRITE64) \ */
179/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */
180/* OBSOLETE "Too many queued 64-bit writes"); \ */
181/* OBSOLETE WRITE64_PTR(_num) = PTR; \ */
182/* OBSOLETE WRITE64_VALUE(_num) = VALUE; \ */
183/* OBSOLETE WRITE64_NUM = _num+1; \ */
184/* OBSOLETE } while (0) */
185/* OBSOLETE */
186/* OBSOLETE #define DPSW_VALID 0xbf005555 */
187/* OBSOLETE #define PSW_VALID 0xb7005555 */
188/* OBSOLETE #define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */ */
189/* OBSOLETE #define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */ */
190/* OBSOLETE */
191/* OBSOLETE /* Verify that the instruction is in the correct slot */ */
192/* OBSOLETE */
193/* OBSOLETE #define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX) */
194/* OBSOLETE extern int is_wrong_slot */
195/* OBSOLETE (SIM_DESC sd, */
196/* OBSOLETE address_word cia, */
197/* OBSOLETE itable_index index); */
198/* OBSOLETE */
199/* OBSOLETE #define IS_CONDITION_OK is_condition_ok(sd, cia, CCC) */
200/* OBSOLETE extern int is_condition_ok */
201/* OBSOLETE (SIM_DESC sd, */
202/* OBSOLETE address_word cia, */
203/* OBSOLETE int cond); */
204/* OBSOLETE */
205/* OBSOLETE #define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */ */
206/* OBSOLETE */
207/* OBSOLETE /* Internal breakpoint instruction is syscall 5 */ */
208/* OBSOLETE #define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05} */
209/* OBSOLETE #define SIM_BREAKPOINT_SIZE (4) */
210/* OBSOLETE */
211/* OBSOLETE /* Call occurred */ */
212/* OBSOLETE extern void call_occurred */
213/* OBSOLETE (SIM_DESC sd, */
214/* OBSOLETE sim_cpu *cpu, */
215/* OBSOLETE address_word cia, */
216/* OBSOLETE address_word nia); */
217/* OBSOLETE */
218/* OBSOLETE /* Return occurred */ */
219/* OBSOLETE extern void return_occurred */
220/* OBSOLETE (SIM_DESC sd, */
221/* OBSOLETE sim_cpu *cpu, */
222/* OBSOLETE address_word cia, */
223/* OBSOLETE address_word nia); */
224/* OBSOLETE */
225/* OBSOLETE /* Whether to do call tracing. */ */
226/* OBSOLETE extern int d30v_call_trace_p; */
227/* OBSOLETE */
228/* OBSOLETE /* Read/write functions for system call interface. */ */
229/* OBSOLETE extern int d30v_read_mem */
230/* OBSOLETE (host_callback *cb, */
231/* OBSOLETE struct cb_syscall *sc, */
232/* OBSOLETE unsigned long taddr, */
233/* OBSOLETE char *buf, */
234/* OBSOLETE int bytes); */
235/* OBSOLETE */
236/* OBSOLETE extern int d30v_write_mem */
237/* OBSOLETE (host_callback *cb, */
238/* OBSOLETE struct cb_syscall *sc, */
239/* OBSOLETE unsigned long taddr, */
240/* OBSOLETE const char *buf, */
241/* OBSOLETE int bytes); */
242/* OBSOLETE */
243/* OBSOLETE /* Process all of the queued up writes in order now */ */
244/* OBSOLETE void unqueue_writes */
245/* OBSOLETE (SIM_DESC sd, */
246/* OBSOLETE sim_cpu *cpu, */
247/* OBSOLETE address_word cia); */
248/* OBSOLETE */
249/* OBSOLETE #endif /* _CPU_H_ */ */
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