projects / binutils.git / blame
| Commit | Line | Data |
|---|---|---|
| 3372836e FCE |
1 | # Test macro |
| 2 | ||
| 3 | .macro assert reg,value | |
| 4 | cmpeq f0,\reg,\value | |
| 5 | bra/fx fail | |
| 6 | .endm | |
| 7 | ||
| 8 | ||
| 9 | # PR 16993 - a.s | |
| 10 | ||
| 11 | add r8,r0,0x80005555 ; for psw | |
| 12 | add r9,r0,0x80000000 ; for psw | |
| 13 | add r40,r0,0x11111111 ; | |
| 14 | add r41,r0,0x22222222 ; | |
| 15 | add r42,r0,0x00000000 ; | |
| 16 | mvtsys psw,r8 ||nop | |
| 17 | mvtsys psw,r9 ||add r42,r40,r41,; | |
| 18 | ||
| 19 | mvfsys r10,psw | |
| 20 | assert r10, 0x80000000 | |
| 21 | ||
| 22 | ||
| 23 | # PR 16995 - b.s | |
| 24 | ||
| 25 | add r8,r0,0x80000000 ; for psw | |
| 26 | add r9,r0,0x80005555 ; for psw | |
| 27 | add r10,r0,0x00000000 ; | |
| 28 | add r40,r0,0x11111111 ; | |
| 29 | add r41,r0,0x22222222 ; | |
| 30 | add r42,r0,0x00000000 ; | |
| 31 | mvtsys psw,r8 ||nop | |
| 32 | mvtsys psw,r9 ||add r42,r40,r41,; | |
| 33 | ||
| 34 | mvfsys r10,psw | |
| 35 | assert r10, 0x80005544 | |
| 36 | ||
| 37 | ||
| 38 | # PR 17006 - c.s | |
| 39 | ||
| 40 | add r8,r0,0x80005555 ; for psw | |
| 41 | add r9,r0,0x80000000 ; for psw | |
| 42 | add r10,r0,0x00000000 ; | |
| 43 | add r40,r0,0x00000011 ; | |
| 44 | add r41,r0,0x00000011 ; | |
| 45 | mvtsys psw,r8 ||nop | |
| 46 | mvtsys psw,r9 ||cmpeq f5,r40,r41,; | |
| 47 | ||
| 48 | mvfsys r10,psw | |
| 49 | assert r10, 0x80000010 | |
| 50 | ||
| 51 | ||
| 52 | # PR 17006 - d.s | |
| 53 | ||
| 54 | add r9,r0,0x80000000 ; for psw | |
| 55 | add r40,r0,0x00000011 ; | |
| 56 | add r41,r0,0x00000011 ; | |
| 57 | nop ||nop | |
| 58 | mvtsys psw, r9 || nop | |
| 59 | nop ||nop | |
| 60 | nop ||cmpeq f5,r40,r41,; | |
| 61 | ||
| 62 | mvfsys r10,psw | |
| 63 | assert r10, 0x80000010 | |
| 64 | ||
| 65 | ||
| 66 | # PR 17106 - a.s | |
| 67 | ||
| 68 | ; test 000 ; mvtsys(s=0) || sathl(s=0) prallel execution test | |
| 69 | add r8,r0,0x80005555 ; for psw | |
| 70 | add r9,r0,0x80000000 ; for psw | |
| 71 | add r40,r0,0x00000044 ; | |
| 72 | add r41,r0,0x00000008 ; | |
| 73 | mvtsys psw,r8 ||nop | |
| 74 | mvtsys psw,r9 ||sathl r30,r40,r41,; | |
| 75 | mvfsys r20, psw ||nop | |
| 76 | ;------------------------------- | |
| 77 | ; test 001 ; mvtsys(s=0) || sathl(s=1) prallel execution test | |
| 78 | _test_001: | |
| 79 | add r40,r0,0x00004444 ; | |
| 80 | add r41,r0,0x00000008 ; | |
| 81 | mvtsys psw,r8 ||nop | |
| 82 | mvtsys psw,r9 ||sathl r31,r40,r41,; | |
| 83 | mvfsys r21,psw ||nop | |
| 84 | ;------------------------------- | |
| 85 | ; test 002 ; mvtsys(s=1) || sathl(s=0) prallel execution test | |
| 86 | add r8,r0,0x80000000 ; for psw | |
| 87 | add r9,r0,0x80005555 ; for psw | |
| 88 | add r40,r0,0x00000044 ; | |
| 89 | add r41,r0,0x00000008 ; | |
| 90 | mvtsys psw,r8 ||nop | |
| 91 | mvtsys psw,r9 ||sathl r32,r40,r41,; | |
| 92 | mvfsys r22,psw ||nop | |
| 93 | ;------------------------------- | |
| 94 | ; test 003 ; mvtsys(s=1) || sathl(s=1) prallel execution test | |
| 95 | ; init-reg | |
| 96 | add r40,r0,0x00004444 ; | |
| 97 | add r41,r0,0x00000008 ; | |
| 98 | mvtsys psw,r8 ||nop | |
| 99 | mvtsys psw,r9 ||sathl r33,r40,r41,; | |
| 100 | mvfsys r23,psw ||nop | |
| 101 | ||
| 102 | assert r20, 0x80000000 | |
| 103 | assert r21, 0x80000040 | |
| 104 | assert r22, 0x80005555 | |
| 105 | assert r23, 0x80005515 | |
| 106 | ||
| 107 | ||
| 108 | # PR 18288 - a.s | |
| 109 | ||
| 110 | ;------------------------------------------------------------------------ | |
| 111 | ; mvtsys (C =1, V= VA = 0) || addc (C= V= VA =0) | |
| 112 | ;------------------------------------------------------------------------ | |
| 113 | test_000b: | |
| 114 | add r1,r0,1 ||nop ; set C bit | |
| 115 | mvtsys psw r0 ||nop | |
| 116 | mvtsys psw r1 ||addc r20,r0,1 | |
| 117 | mvfsys r10,psw ||nop | |
| 118 | ; C changed in MU is not used in IU. | |
| 119 | ; IU prevail for resulting C. | |
| 120 | ;------------------------------------------------------------------------ | |
| 121 | ; mvtsys (V =1, C = VA = 0) || add (C= V= VA =0) | |
| 122 | ;------------------------------------------------------------------------ | |
| 123 | test_001b: | |
| 124 | add r1,r0,0x10 ||nop ; set V bit | |
| 125 | mvtsys psw r0 ||nop | |
| 126 | mvtsys psw r1 ||add r0,r0,r0 | |
| 127 | mvfsys r11,psw ||nop | |
| 128 | ; IU prevail for resulting V. | |
| 129 | ;------------------------------------------------------------------------ | |
| 130 | ; mvtsys (V = C= VA = 0) || add (C=0,V= VA =1) | |
| 131 | ;------------------------------------------------------------------------ | |
| 132 | test_002b: | |
| 133 | add r1,r0,0x70000000 | |
| 134 | add r2,r0,0x30000000 | |
| 135 | mvtsys psw r0 ||nop | |
| 136 | mvtsys psw r0 ||add r0,r1,r2 | |
| 137 | mvfsys r12,psw ||nop | |
| 138 | ; IU prevail for resulting V. | |
| 139 | ; VA is set(OR'ed) | |
| 140 | ;------------------------------------------------------------------------ | |
| 141 | ; mvtsys (C= 0 V = VA = 1) || add (C= V= VA =0) | |
| 142 | ;------------------------------------------------------------------------ | |
| 143 | test_003b: | |
| 144 | add r1,r0,0x14 ||nop ; set V and VA bit | |
| 145 | mvtsys psw r0 ||nop | |
| 146 | mvtsys psw r1 ||add r0,r0,r0 | |
| 147 | mvfsys r13,psw ||nop | |
| 148 | ; IU prevail for resulging V | |
| 149 | ; VA is set(OR'ed) | |
| 150 | ;------------------------------------------------------------------------ | |
| 151 | ; mvtsys (f3 =1) || orfg (f3) : GROUP_B | |
| 152 | ;------------------------------------------------------------------------ | |
| 153 | test_004b: | |
| 154 | add r1,r0,0x100 ; set f3 | |
| 155 | mvtsys psw r0 ||nop | |
| 156 | mvtsys psw,r1 ||orfg f3,f3,0 | |
| 157 | mvfsys r14,psw ||nop | |
| 158 | ; results of IU prevail. | |
| 159 | ;------------------------------------------------------------------------ | |
| 160 | ; mvtsys (f4 =1) || sathp | |
| 161 | ;------------------------------------------------------------------------ | |
| 162 | test_005b: | |
| 163 | add r1,r0,0x40 ; set f4 | |
| 164 | mvtsys psw r0 ||nop | |
| 165 | mvtsys psw r1 ||sathl r2,r1,3 | |
| 166 | mvfsys r15,psw ||nop | |
| 167 | ; results of MU is used in IU | |
| 168 | ||
| 169 | assert r20, 0x1 | |
| 170 | assert r10, 0x0 | |
| 171 | assert r11, 0x0 | |
| 172 | assert r12, 0x14 | |
| 173 | assert r13, 0x4 | |
| 174 | assert r14, 0x0 | |
| 175 | assert r15, 0x0 | |
| 176 | ||
| 177 | ||
| 178 | # all okay | |
| 179 | ||
| 180 | bra ok | |
| 181 | ||
| 182 | ok: | |
| 183 | add r2, r0, 0 | |
| 184 | .long 0x0e000004 | |
| 185 | nop | |
| 186 | ||
| 187 | fail: | |
| 188 | add r2, r0, 47 | |
| 189 | .long 0x0e000004 | |
| 190 | nop |