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* aout-adobe.c (aout_32_bfd_reloc_name_lookup): Define.
[binutils.git] / bfd / coff-sh.c
CommitLineData
c2dcd04e 1/* BFD back-end for Renesas Super-H COFF binaries.
eea6121a 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
157090f7 3 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <[email protected]>.
6 Relaxing code written by Ian Lance Taylor, <[email protected]>.
7
c2dcd04e 8 This file is part of BFD, the Binary File Descriptor library.
252b5132 9
c2dcd04e
NC		 10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
252b5132 14
c2dcd04e
NC		 15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
252b5132 19
c2dcd04e
NC		 20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
3e110533 22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132
RH		 23
24#include "bfd.h"
25#include "sysdep.h"
993e9275 26#include "libiberty.h"
252b5132
RH		 27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
17505c5c
NC		 31
32#ifdef COFF_WITH_PE
33#include "coff/pe.h"
86033394
NC		 34
35#ifndef COFF_IMAGE_WITH_PE
b34976b6 36static bfd_boolean sh_align_load_span
86033394 37 PARAMS ((bfd *, asection *, bfd_byte *,
b34976b6
AM		 38 bfd_boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
39 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *));
86033394
NC		 40
41#define _bfd_sh_align_load_span sh_align_load_span
42#endif
17505c5c
NC		 43#endif
44
252b5132
RH		 45#include "libcoff.h"
46
47/* Internal functions. */
48static bfd_reloc_status_type sh_reloc
49 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
50static long get_symbol_value PARAMS ((asymbol *));
b34976b6
AM		 51static bfd_boolean sh_relax_section
52 PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *));
53static bfd_boolean sh_relax_delete_bytes
252b5132 54 PARAMS ((bfd *, asection *, bfd_vma, int));
86033394 55#ifndef COFF_IMAGE_WITH_PE
252b5132 56static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
86033394 57#endif
b34976b6
AM		 58static bfd_boolean sh_align_loads
59 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *,
60 bfd_boolean *));
61static bfd_boolean sh_swap_insns
252b5132 62 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
b34976b6 63static bfd_boolean sh_relocate_section
252b5132
RH		 64 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
65 struct internal_reloc *, struct internal_syment *, asection **));
66static bfd_byte *sh_coff_get_relocated_section_contents
67 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
b34976b6 68 bfd_byte *, bfd_boolean, asymbol **));
f4ffd778 69static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
252b5132 70
17505c5c
NC		 71#ifdef COFF_WITH_PE
72/* Can't build import tables with 2**4 alignment. */
73#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
74#else
252b5132 75/* Default section alignment to 2**4. */
17505c5c
NC		 76#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
77#endif
78
79#ifdef COFF_IMAGE_WITH_PE
80/* Align PE executables. */
81#define COFF_PAGE_SIZE 0x1000
82#endif
252b5132
RH		 83
84/* Generate long file names. */
85#define COFF_LONG_FILENAMES
86
17505c5c 87#ifdef COFF_WITH_PE
b34976b6
AM		 88static bfd_boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
89/* Return TRUE if this relocation should
17505c5c 90 appear in the output .reloc section. */
b34976b6 91static bfd_boolean in_reloc_p (abfd, howto)
17505c5c
NC		 92 bfd * abfd ATTRIBUTE_UNUSED;
93 reloc_howto_type * howto;
94{
95 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 96}
17505c5c
NC		 97#endif
98
252b5132
RH		 99/* The supported relocations. There are a lot of relocations defined
100 in coff/internal.h which we do not expect to ever see. */
101static reloc_howto_type sh_coff_howtos[] =
102{
5f771d47
ILT		 103 EMPTY_HOWTO (0),
104 EMPTY_HOWTO (1),
17505c5c
NC		 105#ifdef COFF_WITH_PE
106 /* Windows CE */
107 HOWTO (R_SH_IMM32CE, /* type */
108 0, /* rightshift */
109 2, /* size (0 = byte, 1 = short, 2 = long) */
110 32, /* bitsize */
b34976b6 111 FALSE, /* pc_relative */
17505c5c
NC		 112 0, /* bitpos */
113 complain_overflow_bitfield, /* complain_on_overflow */
114 sh_reloc, /* special_function */
115 "r_imm32ce", /* name */
b34976b6 116 TRUE, /* partial_inplace */
17505c5c
NC		 117 0xffffffff, /* src_mask */
118 0xffffffff, /* dst_mask */
b34976b6 119 FALSE), /* pcrel_offset */
17505c5c 120#else
5f771d47 121 EMPTY_HOWTO (2),
17505c5c 122#endif
5f771d47
ILT		 123 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
124 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
125 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
126 EMPTY_HOWTO (6), /* R_SH_IMM24 */
127 EMPTY_HOWTO (7), /* R_SH_LOW16 */
128 EMPTY_HOWTO (8),
129 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 130
131 HOWTO (R_SH_PCDISP8BY2, /* type */
132 1, /* rightshift */
133 1, /* size (0 = byte, 1 = short, 2 = long) */
134 8, /* bitsize */
b34976b6 135 TRUE, /* pc_relative */
252b5132
RH		 136 0, /* bitpos */
137 complain_overflow_signed, /* complain_on_overflow */
138 sh_reloc, /* special_function */
139 "r_pcdisp8by2", /* name */
b34976b6 140 TRUE, /* partial_inplace */
252b5132
RH		 141 0xff, /* src_mask */
142 0xff, /* dst_mask */
b34976b6 143 TRUE), /* pcrel_offset */
252b5132 144
5f771d47 145 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 146
147 HOWTO (R_SH_PCDISP, /* type */
148 1, /* rightshift */
149 1, /* size (0 = byte, 1 = short, 2 = long) */
150 12, /* bitsize */
b34976b6 151 TRUE, /* pc_relative */
252b5132
RH		 152 0, /* bitpos */
153 complain_overflow_signed, /* complain_on_overflow */
154 sh_reloc, /* special_function */
155 "r_pcdisp12by2", /* name */
b34976b6 156 TRUE, /* partial_inplace */
252b5132
RH		 157 0xfff, /* src_mask */
158 0xfff, /* dst_mask */
b34976b6 159 TRUE), /* pcrel_offset */
252b5132 160
5f771d47 161 EMPTY_HOWTO (13),
252b5132
RH		 162
163 HOWTO (R_SH_IMM32, /* type */
164 0, /* rightshift */
165 2, /* size (0 = byte, 1 = short, 2 = long) */
166 32, /* bitsize */
b34976b6 167 FALSE, /* pc_relative */
252b5132
RH		 168 0, /* bitpos */
169 complain_overflow_bitfield, /* complain_on_overflow */
170 sh_reloc, /* special_function */
171 "r_imm32", /* name */
b34976b6 172 TRUE, /* partial_inplace */
252b5132
RH		 173 0xffffffff, /* src_mask */
174 0xffffffff, /* dst_mask */
b34976b6 175 FALSE), /* pcrel_offset */
252b5132 176
5f771d47 177 EMPTY_HOWTO (15),
17505c5c 178#ifdef COFF_WITH_PE
cbfe05c4
KH		 179 HOWTO (R_SH_IMAGEBASE, /* type */
180 0, /* rightshift */
181 2, /* size (0 = byte, 1 = short, 2 = long) */
182 32, /* bitsize */
b34976b6 183 FALSE, /* pc_relative */
cbfe05c4 184 0, /* bitpos */
17505c5c 185 complain_overflow_bitfield, /* complain_on_overflow */
cbfe05c4
KH		 186 sh_reloc, /* special_function */
187 "rva32", /* name */
b34976b6 188 TRUE, /* partial_inplace */
cbfe05c4
KH		 189 0xffffffff, /* src_mask */
190 0xffffffff, /* dst_mask */
b34976b6 191 FALSE), /* pcrel_offset */
17505c5c 192#else
5f771d47 193 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 194#endif
5f771d47
ILT		 195 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
196 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
197 EMPTY_HOWTO (19), /* R_SH_IMM4 */
198 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
199 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 200
201 HOWTO (R_SH_PCRELIMM8BY2, /* type */
202 1, /* rightshift */
203 1, /* size (0 = byte, 1 = short, 2 = long) */
204 8, /* bitsize */
b34976b6 205 TRUE, /* pc_relative */
252b5132
RH		 206 0, /* bitpos */
207 complain_overflow_unsigned, /* complain_on_overflow */
208 sh_reloc, /* special_function */
209 "r_pcrelimm8by2", /* name */
b34976b6 210 TRUE, /* partial_inplace */
252b5132
RH		 211 0xff, /* src_mask */
212 0xff, /* dst_mask */
b34976b6 213 TRUE), /* pcrel_offset */
252b5132
RH		 214
215 HOWTO (R_SH_PCRELIMM8BY4, /* type */
216 2, /* rightshift */
217 1, /* size (0 = byte, 1 = short, 2 = long) */
218 8, /* bitsize */
b34976b6 219 TRUE, /* pc_relative */
252b5132
RH		 220 0, /* bitpos */
221 complain_overflow_unsigned, /* complain_on_overflow */
222 sh_reloc, /* special_function */
223 "r_pcrelimm8by4", /* name */
b34976b6 224 TRUE, /* partial_inplace */
252b5132
RH		 225 0xff, /* src_mask */
226 0xff, /* dst_mask */
b34976b6 227 TRUE), /* pcrel_offset */
252b5132
RH		 228
229 HOWTO (R_SH_IMM16, /* type */
230 0, /* rightshift */
231 1, /* size (0 = byte, 1 = short, 2 = long) */
232 16, /* bitsize */
b34976b6 233 FALSE, /* pc_relative */
252b5132
RH		 234 0, /* bitpos */
235 complain_overflow_bitfield, /* complain_on_overflow */
236 sh_reloc, /* special_function */
237 "r_imm16", /* name */
b34976b6 238 TRUE, /* partial_inplace */
252b5132
RH		 239 0xffff, /* src_mask */
240 0xffff, /* dst_mask */
b34976b6 241 FALSE), /* pcrel_offset */
252b5132
RH		 242
243 HOWTO (R_SH_SWITCH16, /* type */
244 0, /* rightshift */
245 1, /* size (0 = byte, 1 = short, 2 = long) */
246 16, /* bitsize */
b34976b6 247 FALSE, /* pc_relative */
252b5132
RH		 248 0, /* bitpos */
249 complain_overflow_bitfield, /* complain_on_overflow */
250 sh_reloc, /* special_function */
251 "r_switch16", /* name */
b34976b6 252 TRUE, /* partial_inplace */
252b5132
RH		 253 0xffff, /* src_mask */
254 0xffff, /* dst_mask */
b34976b6 255 FALSE), /* pcrel_offset */
252b5132
RH		 256
257 HOWTO (R_SH_SWITCH32, /* type */
258 0, /* rightshift */
259 2, /* size (0 = byte, 1 = short, 2 = long) */
260 32, /* bitsize */
b34976b6 261 FALSE, /* pc_relative */
252b5132
RH		 262 0, /* bitpos */
263 complain_overflow_bitfield, /* complain_on_overflow */
264 sh_reloc, /* special_function */
265 "r_switch32", /* name */
b34976b6 266 TRUE, /* partial_inplace */
252b5132
RH		 267 0xffffffff, /* src_mask */
268 0xffffffff, /* dst_mask */
b34976b6 269 FALSE), /* pcrel_offset */
252b5132
RH		 270
271 HOWTO (R_SH_USES, /* type */
272 0, /* rightshift */
273 1, /* size (0 = byte, 1 = short, 2 = long) */
274 16, /* bitsize */
b34976b6 275 FALSE, /* pc_relative */
252b5132
RH		 276 0, /* bitpos */
277 complain_overflow_bitfield, /* complain_on_overflow */
278 sh_reloc, /* special_function */
279 "r_uses", /* name */
b34976b6 280 TRUE, /* partial_inplace */
252b5132
RH		 281 0xffff, /* src_mask */
282 0xffff, /* dst_mask */
b34976b6 283 FALSE), /* pcrel_offset */
252b5132
RH		 284
285 HOWTO (R_SH_COUNT, /* type */
286 0, /* rightshift */
287 2, /* size (0 = byte, 1 = short, 2 = long) */
288 32, /* bitsize */
b34976b6 289 FALSE, /* pc_relative */
252b5132
RH		 290 0, /* bitpos */
291 complain_overflow_bitfield, /* complain_on_overflow */
292 sh_reloc, /* special_function */
293 "r_count", /* name */
b34976b6 294 TRUE, /* partial_inplace */
252b5132
RH		 295 0xffffffff, /* src_mask */
296 0xffffffff, /* dst_mask */
b34976b6 297 FALSE), /* pcrel_offset */
252b5132
RH		 298
299 HOWTO (R_SH_ALIGN, /* type */
300 0, /* rightshift */
301 2, /* size (0 = byte, 1 = short, 2 = long) */
302 32, /* bitsize */
b34976b6 303 FALSE, /* pc_relative */
252b5132
RH		 304 0, /* bitpos */
305 complain_overflow_bitfield, /* complain_on_overflow */
306 sh_reloc, /* special_function */
307 "r_align", /* name */
b34976b6 308 TRUE, /* partial_inplace */
252b5132
RH		 309 0xffffffff, /* src_mask */
310 0xffffffff, /* dst_mask */
b34976b6 311 FALSE), /* pcrel_offset */
252b5132
RH		 312
313 HOWTO (R_SH_CODE, /* type */
314 0, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
316 32, /* bitsize */
b34976b6 317 FALSE, /* pc_relative */
252b5132
RH		 318 0, /* bitpos */
319 complain_overflow_bitfield, /* complain_on_overflow */
320 sh_reloc, /* special_function */
321 "r_code", /* name */
b34976b6 322 TRUE, /* partial_inplace */
252b5132
RH		 323 0xffffffff, /* src_mask */
324 0xffffffff, /* dst_mask */
b34976b6 325 FALSE), /* pcrel_offset */
252b5132
RH		 326
327 HOWTO (R_SH_DATA, /* type */
328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
b34976b6 331 FALSE, /* pc_relative */
252b5132
RH		 332 0, /* bitpos */
333 complain_overflow_bitfield, /* complain_on_overflow */
334 sh_reloc, /* special_function */
335 "r_data", /* name */
b34976b6 336 TRUE, /* partial_inplace */
252b5132
RH		 337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
b34976b6 339 FALSE), /* pcrel_offset */
252b5132
RH		 340
341 HOWTO (R_SH_LABEL, /* type */
342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
b34976b6 345 FALSE, /* pc_relative */
252b5132
RH		 346 0, /* bitpos */
347 complain_overflow_bitfield, /* complain_on_overflow */
348 sh_reloc, /* special_function */
349 "r_label", /* name */
b34976b6 350 TRUE, /* partial_inplace */
252b5132
RH		 351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
b34976b6 353 FALSE), /* pcrel_offset */
252b5132
RH		 354
355 HOWTO (R_SH_SWITCH8, /* type */
356 0, /* rightshift */
357 0, /* size (0 = byte, 1 = short, 2 = long) */
358 8, /* bitsize */
b34976b6 359 FALSE, /* pc_relative */
252b5132
RH		 360 0, /* bitpos */
361 complain_overflow_bitfield, /* complain_on_overflow */
362 sh_reloc, /* special_function */
363 "r_switch8", /* name */
b34976b6 364 TRUE, /* partial_inplace */
252b5132
RH		 365 0xff, /* src_mask */
366 0xff, /* dst_mask */
b34976b6 367 FALSE) /* pcrel_offset */
252b5132
RH		 368};
369
370#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
371
372/* Check for a bad magic number. */
373#define BADMAG(x) SHBADMAG(x)
374
375/* Customize coffcode.h (this is not currently used). */
376#define SH 1
377
378/* FIXME: This should not be set here. */
379#define __A_MAGIC_SET__
380
17505c5c 381#ifndef COFF_WITH_PE
252b5132 382/* Swap the r_offset field in and out. */
dc810e39
AM		 383#define SWAP_IN_RELOC_OFFSET H_GET_32
384#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 385
386/* Swap out extra information in the reloc structure. */
387#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
388 do \
389 { \
390 dst->r_stuff[0] = 'S'; \
391 dst->r_stuff[1] = 'C'; \
392 } \
393 while (0)
17505c5c 394#endif
252b5132
RH		 395
396/* Get the value of a symbol, when performing a relocation. */
397
398static long
cbfe05c4 399get_symbol_value (symbol)
252b5132 400 asymbol *symbol;
cbfe05c4 401{
252b5132
RH		 402 bfd_vma relocation;
403
404 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 405 relocation = 0;
406 else
252b5132
RH		 407 relocation = (symbol->value +
408 symbol->section->output_section->vma +
409 symbol->section->output_offset);
410
411 return relocation;
412}
413
17505c5c
NC		 414#ifdef COFF_WITH_PE
415/* Convert an rtype to howto for the COFF backend linker.
416 Copied from coff-i386. */
417#define coff_rtype_to_howto coff_sh_rtype_to_howto
f4ffd778 418static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
17505c5c
NC		 419
420static reloc_howto_type *
421coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
86033394 422 bfd * abfd ATTRIBUTE_UNUSED;
17505c5c
NC		 423 asection * sec;
424 struct internal_reloc * rel;
425 struct coff_link_hash_entry * h;
426 struct internal_syment * sym;
427 bfd_vma * addendp;
428{
429 reloc_howto_type * howto;
430
431 howto = sh_coff_howtos + rel->r_type;
432
433 *addendp = 0;
434
435 if (howto->pc_relative)
436 *addendp += sec->vma;
437
438 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
439 {
440 /* This is a common symbol. The section contents include the
441 size (sym->n_value) as an addend. The relocate_section
442 function will be adding in the final value of the symbol. We
443 need to subtract out the current size in order to get the
444 correct result. */
445 BFD_ASSERT (h != NULL);
446 }
447
448 if (howto->pc_relative)
449 {
450 *addendp -= 4;
451
452 /* If the symbol is defined, then the generic code is going to
453 add back the symbol value in order to cancel out an
454 adjustment it made to the addend. However, we set the addend
455 to 0 at the start of this function. We need to adjust here,
456 to avoid the adjustment the generic code will make. FIXME:
457 This is getting a bit hackish. */
458 if (sym != NULL && sym->n_scnum != 0)
459 *addendp -= sym->n_value;
460 }
461
462 if (rel->r_type == R_SH_IMAGEBASE)
463 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
464
465 return howto;
466}
467
993e9275
NC		 468#endif /* COFF_WITH_PE */
469
17505c5c
NC		 470/* This structure is used to map BFD reloc codes to SH PE relocs. */
471struct shcoff_reloc_map
472{
aa066ac8 473 bfd_reloc_code_real_type bfd_reloc_val;
17505c5c
NC		 474 unsigned char shcoff_reloc_val;
475};
476
a9a32010 477#ifdef COFF_WITH_PE
17505c5c
NC		 478/* An array mapping BFD reloc codes to SH PE relocs. */
479static const struct shcoff_reloc_map sh_reloc_map[] =
480{
481 { BFD_RELOC_32, R_SH_IMM32CE },
482 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
483 { BFD_RELOC_CTOR, R_SH_IMM32CE },
484};
a9a32010
DJ		 485#else
486/* An array mapping BFD reloc codes to SH PE relocs. */
487static const struct shcoff_reloc_map sh_reloc_map[] =
488{
489 { BFD_RELOC_32, R_SH_IMM32 },
490 { BFD_RELOC_CTOR, R_SH_IMM32 },
491};
492#endif
17505c5c
NC		 493
494/* Given a BFD reloc code, return the howto structure for the
495 corresponding SH PE reloc. */
496#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
157090f7 497#define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
17505c5c
NC		 498
499static reloc_howto_type *
500sh_coff_reloc_type_lookup (abfd, code)
501 bfd * abfd ATTRIBUTE_UNUSED;
502 bfd_reloc_code_real_type code;
503{
504 unsigned int i;
505
993e9275
NC		 506 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
507 if (sh_reloc_map[i].bfd_reloc_val == code)
508 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c
NC		 509
510 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
511 return NULL;
512}
17505c5c 513
157090f7
AM		 514static reloc_howto_type *
515sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
516 const char *r_name)
517{
518 unsigned int i;
519
520 for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
521 if (sh_coff_howtos[i].name != NULL
522 && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
523 return &sh_coff_howtos[i];
524
525 return NULL;
526}
527
252b5132
RH		 528/* This macro is used in coffcode.h to get the howto corresponding to
529 an internal reloc. */
530
531#define RTYPE2HOWTO(relent, internal) \
532 ((relent)->howto = \
533 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
534 ? &sh_coff_howtos[(internal)->r_type] \
535 : (reloc_howto_type *) NULL))
536
537/* This is the same as the macro in coffcode.h, except that it copies
538 r_offset into reloc_entry->addend for some relocs. */
539#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
540 { \
541 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
542 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
543 coffsym = (obj_symbols (abfd) \
544 + (cache_ptr->sym_ptr_ptr - symbols)); \
545 else if (ptr) \
546 coffsym = coff_symbol_from (abfd, ptr); \
547 if (coffsym != (coff_symbol_type *) NULL \
548 && coffsym->native->u.syment.n_scnum == 0) \
549 cache_ptr->addend = 0; \
550 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
551 && ptr->section != (asection *) NULL) \
552 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
553 else \
554 cache_ptr->addend = 0; \
555 if ((reloc).r_type == R_SH_SWITCH8 \
556 || (reloc).r_type == R_SH_SWITCH16 \
557 || (reloc).r_type == R_SH_SWITCH32 \
558 || (reloc).r_type == R_SH_USES \
559 || (reloc).r_type == R_SH_COUNT \
560 || (reloc).r_type == R_SH_ALIGN) \
561 cache_ptr->addend = (reloc).r_offset; \
562 }
563
564/* This is the howto function for the SH relocations. */
565
566static bfd_reloc_status_type
567sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
568 error_message)
569 bfd *abfd;
570 arelent *reloc_entry;
571 asymbol *symbol_in;
572 PTR data;
573 asection *input_section;
574 bfd *output_bfd;
5f771d47 575 char **error_message ATTRIBUTE_UNUSED;
252b5132
RH		 576{
577 unsigned long insn;
578 bfd_vma sym_value;
579 unsigned short r_type;
580 bfd_vma addr = reloc_entry->address;
581 bfd_byte *hit_data = addr + (bfd_byte *) data;
582
583 r_type = reloc_entry->howto->type;
584
585 if (output_bfd != NULL)
586 {
587 /* Partial linking--do nothing. */
588 reloc_entry->address += input_section->output_offset;
589 return bfd_reloc_ok;
590 }
591
592 /* Almost all relocs have to do with relaxing. If any work must be
593 done for them, it has been done in sh_relax_section. */
594 if (r_type != R_SH_IMM32
17505c5c
NC		 595#ifdef COFF_WITH_PE
596 && r_type != R_SH_IMM32CE
597 && r_type != R_SH_IMAGEBASE
598#endif
252b5132
RH		 599 && (r_type != R_SH_PCDISP
600 || (symbol_in->flags & BSF_LOCAL) != 0))
601 return bfd_reloc_ok;
602
603 if (symbol_in != NULL
604 && bfd_is_und_section (symbol_in->section))
605 return bfd_reloc_undefined;
606
607 sym_value = get_symbol_value (symbol_in);
608
609 switch (r_type)
610 {
611 case R_SH_IMM32:
17505c5c
NC		 612#ifdef COFF_WITH_PE
613 case R_SH_IMM32CE:
614#endif
252b5132
RH		 615 insn = bfd_get_32 (abfd, hit_data);
616 insn += sym_value + reloc_entry->addend;
dc810e39 617 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
252b5132 618 break;
17505c5c
NC		 619#ifdef COFF_WITH_PE
620 case R_SH_IMAGEBASE:
621 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 622 insn += sym_value + reloc_entry->addend;
623 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
624 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
17505c5c
NC		 625 break;
626#endif
252b5132
RH		 627 case R_SH_PCDISP:
628 insn = bfd_get_16 (abfd, hit_data);
629 sym_value += reloc_entry->addend;
630 sym_value -= (input_section->output_section->vma
631 + input_section->output_offset
632 + addr
633 + 4);
634 sym_value += (insn & 0xfff) << 1;
635 if (insn & 0x800)
636 sym_value -= 0x1000;
637 insn = (insn & 0xf000) | (sym_value & 0xfff);
dc810e39 638 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
252b5132
RH		 639 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
640 return bfd_reloc_overflow;
641 break;
642 default:
643 abort ();
644 break;
645 }
646
647 return bfd_reloc_ok;
648}
649
875f7f69 650#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 651
652/* We can do relaxing. */
653#define coff_bfd_relax_section sh_relax_section
654
655/* We use the special COFF backend linker. */
656#define coff_relocate_section sh_relocate_section
657
658/* When relaxing, we need to use special code to get the relocated
659 section contents. */
660#define coff_bfd_get_relocated_section_contents \
661 sh_coff_get_relocated_section_contents
662
663#include "coffcode.h"
664\f
665/* This function handles relaxing on the SH.
666
667 Function calls on the SH look like this:
668
669 movl L1,r0
670 ...
671 jsr @r0
672 ...
673 L1:
674 .long function
675
676 The compiler and assembler will cooperate to create R_SH_USES
677 relocs on the jsr instructions. The r_offset field of the
678 R_SH_USES reloc is the PC relative offset to the instruction which
679 loads the register (the r_offset field is computed as though it
680 were a jump instruction, so the offset value is actually from four
681 bytes past the instruction). The linker can use this reloc to
682 determine just which function is being called, and thus decide
683 whether it is possible to replace the jsr with a bsr.
684
685 If multiple function calls are all based on a single register load
686 (i.e., the same function is called multiple times), the compiler
687 guarantees that each function call will have an R_SH_USES reloc.
688 Therefore, if the linker is able to convert each R_SH_USES reloc
689 which refers to that address, it can safely eliminate the register
690 load.
691
692 When the assembler creates an R_SH_USES reloc, it examines it to
693 determine which address is being loaded (L1 in the above example).
694 It then counts the number of references to that address, and
695 creates an R_SH_COUNT reloc at that address. The r_offset field of
696 the R_SH_COUNT reloc will be the number of references. If the
697 linker is able to eliminate a register load, it can use the
698 R_SH_COUNT reloc to see whether it can also eliminate the function
699 address.
700
701 SH relaxing also handles another, unrelated, matter. On the SH, if
702 a load or store instruction is not aligned on a four byte boundary,
703 the memory cycle interferes with the 32 bit instruction fetch,
704 causing a one cycle bubble in the pipeline. Therefore, we try to
705 align load and store instructions on four byte boundaries if we
706 can, by swapping them with one of the adjacent instructions. */
707
b34976b6 708static bfd_boolean
252b5132
RH		 709sh_relax_section (abfd, sec, link_info, again)
710 bfd *abfd;
711 asection *sec;
712 struct bfd_link_info *link_info;
b34976b6 713 bfd_boolean *again;
252b5132
RH		 714{
715 struct internal_reloc *internal_relocs;
b34976b6 716 bfd_boolean have_code;
252b5132
RH		 717 struct internal_reloc *irel, *irelend;
718 bfd_byte *contents = NULL;
252b5132 719
b34976b6 720 *again = FALSE;
252b5132 721
1049f94e 722 if (link_info->relocatable
252b5132
RH		 723 || (sec->flags & SEC_RELOC) == 0
724 || sec->reloc_count == 0)
b34976b6 725 return TRUE;
252b5132 726
eea6121a
AM		 727 if (coff_section_data (abfd, sec) == NULL)
728 {
729 bfd_size_type amt = sizeof (struct coff_section_tdata);
730 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
731 if (sec->used_by_bfd == NULL)
732 return FALSE;
733 }
252b5132
RH		 734
735 internal_relocs = (_bfd_coff_read_internal_relocs
736 (abfd, sec, link_info->keep_memory,
b34976b6 737 (bfd_byte *) NULL, FALSE,
252b5132
RH		 738 (struct internal_reloc *) NULL));
739 if (internal_relocs == NULL)
740 goto error_return;
252b5132 741
b34976b6 742 have_code = FALSE;
252b5132
RH		 743
744 irelend = internal_relocs + sec->reloc_count;
745 for (irel = internal_relocs; irel < irelend; irel++)
746 {
747 bfd_vma laddr, paddr, symval;
748 unsigned short insn;
749 struct internal_reloc *irelfn, *irelscan, *irelcount;
750 struct internal_syment sym;
751 bfd_signed_vma foff;
752
753 if (irel->r_type == R_SH_CODE)
b34976b6 754 have_code = TRUE;
252b5132
RH		 755
756 if (irel->r_type != R_SH_USES)
757 continue;
758
759 /* Get the section contents. */
760 if (contents == NULL)
761 {
eea6121a 762 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 763 contents = coff_section_data (abfd, sec)->contents;
764 else
765 {
eea6121a 766 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 767 goto error_return;
768 }
769 }
770
771 /* The r_offset field of the R_SH_USES reloc will point us to
772 the register load. The 4 is because the r_offset field is
773 computed as though it were a jump offset, which are based
774 from 4 bytes after the jump instruction. */
775 laddr = irel->r_vaddr - sec->vma + 4;
776 /* Careful to sign extend the 32-bit offset. */
777 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
eea6121a 778 if (laddr >= sec->size)
252b5132 779 {
d003868e
AM		 780 (*_bfd_error_handler) ("%B: 0x%lx: warning: bad R_SH_USES offset",
781 abfd, (unsigned long) irel->r_vaddr);
252b5132
RH		 782 continue;
783 }
784 insn = bfd_get_16 (abfd, contents + laddr);
785
786 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
787 if ((insn & 0xf000) != 0xd000)
788 {
789 ((*_bfd_error_handler)
d003868e
AM		 790 ("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
791 abfd, (unsigned long) irel->r_vaddr, insn));
252b5132
RH		 792 continue;
793 }
794
795 /* Get the address from which the register is being loaded. The
796 displacement in the mov.l instruction is quadrupled. It is a
797 displacement from four bytes after the movl instruction, but,
798 before adding in the PC address, two least significant bits
799 of the PC are cleared. We assume that the section is aligned
800 on a four byte boundary. */
801 paddr = insn & 0xff;
802 paddr *= 4;
dc810e39 803 paddr += (laddr + 4) &~ (bfd_vma) 3;
eea6121a 804 if (paddr >= sec->size)
252b5132
RH		 805 {
806 ((*_bfd_error_handler)
d003868e
AM		 807 ("%B: 0x%lx: warning: bad R_SH_USES load offset",
808 abfd, (unsigned long) irel->r_vaddr));
252b5132
RH		 809 continue;
810 }
811
812 /* Get the reloc for the address from which the register is
813 being loaded. This reloc will tell us which function is
814 actually being called. */
815 paddr += sec->vma;
816 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
817 if (irelfn->r_vaddr == paddr
17505c5c
NC		 818#ifdef COFF_WITH_PE
819 && (irelfn->r_type == R_SH_IMM32
820 || irelfn->r_type == R_SH_IMM32CE
eea6121a 821 || irelfn->r_type == R_SH_IMAGEBASE)
17505c5c
NC		 822
823#else
eea6121a 824 && irelfn->r_type == R_SH_IMM32
17505c5c 825#endif
eea6121a 826 )
252b5132
RH		 827 break;
828 if (irelfn >= irelend)
829 {
830 ((*_bfd_error_handler)
d003868e
AM		 831 ("%B: 0x%lx: warning: could not find expected reloc",
832 abfd, (unsigned long) paddr));
252b5132
RH		 833 continue;
834 }
835
836 /* Get the value of the symbol referred to by the reloc. */
837 if (! _bfd_coff_get_external_symbols (abfd))
838 goto error_return;
839 bfd_coff_swap_sym_in (abfd,
840 ((bfd_byte *) obj_coff_external_syms (abfd)
841 + (irelfn->r_symndx
842 * bfd_coff_symesz (abfd))),
843 &sym);
844 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
845 {
846 ((*_bfd_error_handler)
d003868e
AM		 847 ("%B: 0x%lx: warning: symbol in unexpected section",
848 abfd, (unsigned long) paddr));
252b5132
RH		 849 continue;
850 }
851
852 if (sym.n_sclass != C_EXT)
853 {
854 symval = (sym.n_value
855 - sec->vma
856 + sec->output_section->vma
857 + sec->output_offset);
858 }
859 else
860 {
861 struct coff_link_hash_entry *h;
862
863 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
864 BFD_ASSERT (h != NULL);
865 if (h->root.type != bfd_link_hash_defined
866 && h->root.type != bfd_link_hash_defweak)
867 {
868 /* This appears to be a reference to an undefined
869 symbol. Just ignore it--it will be caught by the
870 regular reloc processing. */
871 continue;
872 }
873
874 symval = (h->root.u.def.value
875 + h->root.u.def.section->output_section->vma
876 + h->root.u.def.section->output_offset);
877 }
878
879 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
880
881 /* See if this function call can be shortened. */
882 foff = (symval
883 - (irel->r_vaddr
884 - sec->vma
885 + sec->output_section->vma
886 + sec->output_offset
887 + 4));
888 if (foff < -0x1000 || foff >= 0x1000)
889 {
890 /* After all that work, we can't shorten this function call. */
891 continue;
892 }
893
894 /* Shorten the function call. */
895
896 /* For simplicity of coding, we are going to modify the section
897 contents, the section relocs, and the BFD symbol table. We
898 must tell the rest of the code not to free up this
899 information. It would be possible to instead create a table
900 of changes which have to be made, as is done in coff-mips.c;
901 that would be more work, but would require less memory when
902 the linker is run. */
903
252b5132 904 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 905 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 906
907 coff_section_data (abfd, sec)->contents = contents;
b34976b6 908 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 909
b34976b6 910 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 911
912 /* Replace the jsr with a bsr. */
913
914 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
915 replace the jsr with a bsr. */
916 irel->r_type = R_SH_PCDISP;
917 irel->r_symndx = irelfn->r_symndx;
918 if (sym.n_sclass != C_EXT)
919 {
920 /* If this needs to be changed because of future relaxing,
921 it will be handled here like other internal PCDISP
922 relocs. */
923 bfd_put_16 (abfd,
dc810e39 924 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 925 contents + irel->r_vaddr - sec->vma);
926 }
927 else
928 {
929 /* We can't fully resolve this yet, because the external
930 symbol value may be changed by future relaxing. We let
931 the final link phase handle it. */
dc810e39
AM		 932 bfd_put_16 (abfd, (bfd_vma) 0xb000,
933 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 934 }
935
936 /* See if there is another R_SH_USES reloc referring to the same
937 register load. */
938 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
939 if (irelscan->r_type == R_SH_USES
940 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
941 break;
942 if (irelscan < irelend)
943 {
944 /* Some other function call depends upon this register load,
945 and we have not yet converted that function call.
946 Indeed, we may never be able to convert it. There is
947 nothing else we can do at this point. */
948 continue;
949 }
950
951 /* Look for a R_SH_COUNT reloc on the location where the
952 function address is stored. Do this before deleting any
953 bytes, to avoid confusion about the address. */
954 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
955 if (irelcount->r_vaddr == paddr
956 && irelcount->r_type == R_SH_COUNT)
957 break;
958
959 /* Delete the register load. */
960 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
961 goto error_return;
962
963 /* That will change things, so, just in case it permits some
964 other function call to come within range, we should relax
965 again. Note that this is not required, and it may be slow. */
b34976b6 966 *again = TRUE;
252b5132
RH		 967
968 /* Now check whether we got a COUNT reloc. */
969 if (irelcount >= irelend)
970 {
971 ((*_bfd_error_handler)
d003868e
AM		 972 ("%B: 0x%lx: warning: could not find expected COUNT reloc",
973 abfd, (unsigned long) paddr));
252b5132
RH		 974 continue;
975 }
976
977 /* The number of uses is stored in the r_offset field. We've
978 just deleted one. */
979 if (irelcount->r_offset == 0)
980 {
d003868e
AM		 981 ((*_bfd_error_handler) ("%B: 0x%lx: warning: bad count",
982 abfd, (unsigned long) paddr));
252b5132
RH		 983 continue;
984 }
985
986 --irelcount->r_offset;
987
988 /* If there are no more uses, we can delete the address. Reload
989 the address from irelfn, in case it was changed by the
990 previous call to sh_relax_delete_bytes. */
991 if (irelcount->r_offset == 0)
992 {
993 if (! sh_relax_delete_bytes (abfd, sec,
994 irelfn->r_vaddr - sec->vma, 4))
995 goto error_return;
996 }
997
998 /* We've done all we can with that function call. */
999 }
1000
1001 /* Look for load and store instructions that we can align on four
1002 byte boundaries. */
1003 if (have_code)
1004 {
b34976b6 1005 bfd_boolean swapped;
252b5132
RH		 1006
1007 /* Get the section contents. */
1008 if (contents == NULL)
1009 {
eea6121a 1010 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 1011 contents = coff_section_data (abfd, sec)->contents;
1012 else
1013 {
eea6121a 1014 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 1015 goto error_return;
1016 }
1017 }
1018
1019 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1020 goto error_return;
1021
1022 if (swapped)
1023 {
252b5132 1024 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 1025 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 1026
1027 coff_section_data (abfd, sec)->contents = contents;
b34976b6 1028 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 1029
b34976b6 1030 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 1031 }
1032 }
1033
eea6121a
AM		 1034 if (internal_relocs != NULL
1035 && internal_relocs != coff_section_data (abfd, sec)->relocs)
252b5132 1036 {
eea6121a
AM		 1037 if (! link_info->keep_memory)
1038 free (internal_relocs);
1039 else
1040 coff_section_data (abfd, sec)->relocs = internal_relocs;
252b5132
RH		 1041 }
1042
eea6121a 1043 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
252b5132
RH		 1044 {
1045 if (! link_info->keep_memory)
eea6121a 1046 free (contents);
252b5132 1047 else
eea6121a
AM		 1048 /* Cache the section contents for coff_link_input_bfd. */
1049 coff_section_data (abfd, sec)->contents = contents;
252b5132
RH		 1050 }
1051
b34976b6 1052 return TRUE;
252b5132
RH		 1053
1054 error_return:
eea6121a
AM		 1055 if (internal_relocs != NULL
1056 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1057 free (internal_relocs);
1058 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1059 free (contents);
b34976b6 1060 return FALSE;
252b5132
RH		 1061}
1062
1063/* Delete some bytes from a section while relaxing. */
1064
b34976b6 1065static bfd_boolean
252b5132
RH		 1066sh_relax_delete_bytes (abfd, sec, addr, count)
1067 bfd *abfd;
1068 asection *sec;
1069 bfd_vma addr;
1070 int count;
1071{
1072 bfd_byte *contents;
1073 struct internal_reloc *irel, *irelend;
1074 struct internal_reloc *irelalign;
1075 bfd_vma toaddr;
1076 bfd_byte *esym, *esymend;
1077 bfd_size_type symesz;
1078 struct coff_link_hash_entry **sym_hash;
1079 asection *o;
1080
1081 contents = coff_section_data (abfd, sec)->contents;
1082
1083 /* The deletion must stop at the next ALIGN reloc for an aligment
1084 power larger than the number of bytes we are deleting. */
1085
1086 irelalign = NULL;
eea6121a 1087 toaddr = sec->size;
252b5132
RH		 1088
1089 irel = coff_section_data (abfd, sec)->relocs;
1090 irelend = irel + sec->reloc_count;
1091 for (; irel < irelend; irel++)
1092 {
1093 if (irel->r_type == R_SH_ALIGN
1094 && irel->r_vaddr - sec->vma > addr
1095 && count < (1 << irel->r_offset))
1096 {
1097 irelalign = irel;
1098 toaddr = irel->r_vaddr - sec->vma;
1099 break;
1100 }
1101 }
1102
1103 /* Actually delete the bytes. */
dc810e39
AM		 1104 memmove (contents + addr, contents + addr + count,
1105 (size_t) (toaddr - addr - count));
252b5132 1106 if (irelalign == NULL)
eea6121a 1107 sec->size -= count;
252b5132
RH		 1108 else
1109 {
1110 int i;
1111
1112#define NOP_OPCODE (0x0009)
1113
1114 BFD_ASSERT ((count & 1) == 0);
1115 for (i = 0; i < count; i += 2)
dc810e39 1116 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1117 }
1118
1119 /* Adjust all the relocs. */
1120 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1121 {
1122 bfd_vma nraddr, stop;
1123 bfd_vma start = 0;
1124 int insn = 0;
1125 struct internal_syment sym;
1126 int off, adjust, oinsn;
1127 bfd_signed_vma voff = 0;
b34976b6 1128 bfd_boolean overflow;
252b5132
RH		 1129
1130 /* Get the new reloc address. */
1131 nraddr = irel->r_vaddr - sec->vma;
1132 if ((irel->r_vaddr - sec->vma > addr
1133 && irel->r_vaddr - sec->vma < toaddr)
1134 || (irel->r_type == R_SH_ALIGN
1135 && irel->r_vaddr - sec->vma == toaddr))
1136 nraddr -= count;
1137
1138 /* See if this reloc was for the bytes we have deleted, in which
1139 case we no longer care about it. Don't delete relocs which
1140 represent addresses, though. */
1141 if (irel->r_vaddr - sec->vma >= addr
1142 && irel->r_vaddr - sec->vma < addr + count
1143 && irel->r_type != R_SH_ALIGN
1144 && irel->r_type != R_SH_CODE
1145 && irel->r_type != R_SH_DATA
1146 && irel->r_type != R_SH_LABEL)
1147 irel->r_type = R_SH_UNUSED;
1148
1149 /* If this is a PC relative reloc, see if the range it covers
1150 includes the bytes we have deleted. */
1151 switch (irel->r_type)
1152 {
1153 default:
1154 break;
1155
1156 case R_SH_PCDISP8BY2:
1157 case R_SH_PCDISP:
1158 case R_SH_PCRELIMM8BY2:
1159 case R_SH_PCRELIMM8BY4:
1160 start = irel->r_vaddr - sec->vma;
1161 insn = bfd_get_16 (abfd, contents + nraddr);
1162 break;
1163 }
1164
1165 switch (irel->r_type)
1166 {
1167 default:
1168 start = stop = addr;
1169 break;
1170
1171 case R_SH_IMM32:
17505c5c
NC		 1172#ifdef COFF_WITH_PE
1173 case R_SH_IMM32CE:
1174 case R_SH_IMAGEBASE:
1175#endif
252b5132
RH		 1176 /* If this reloc is against a symbol defined in this
1177 section, and the symbol will not be adjusted below, we
1178 must check the addend to see it will put the value in
1179 range to be adjusted, and hence must be changed. */
1180 bfd_coff_swap_sym_in (abfd,
1181 ((bfd_byte *) obj_coff_external_syms (abfd)
1182 + (irel->r_symndx
1183 * bfd_coff_symesz (abfd))),
1184 &sym);
1185 if (sym.n_sclass != C_EXT
1186 && sym.n_scnum == sec->target_index
1187 && ((bfd_vma) sym.n_value <= addr
1188 || (bfd_vma) sym.n_value >= toaddr))
1189 {
1190 bfd_vma val;
1191
1192 val = bfd_get_32 (abfd, contents + nraddr);
1193 val += sym.n_value;
1194 if (val > addr && val < toaddr)
1195 bfd_put_32 (abfd, val - count, contents + nraddr);
1196 }
1197 start = stop = addr;
1198 break;
1199
1200 case R_SH_PCDISP8BY2:
1201 off = insn & 0xff;
1202 if (off & 0x80)
1203 off -= 0x100;
1204 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1205 break;
1206
1207 case R_SH_PCDISP:
1208 bfd_coff_swap_sym_in (abfd,
1209 ((bfd_byte *) obj_coff_external_syms (abfd)
1210 + (irel->r_symndx
1211 * bfd_coff_symesz (abfd))),
1212 &sym);
1213 if (sym.n_sclass == C_EXT)
1214 start = stop = addr;
1215 else
1216 {
1217 off = insn & 0xfff;
1218 if (off & 0x800)
1219 off -= 0x1000;
1220 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1221 }
1222 break;
1223
1224 case R_SH_PCRELIMM8BY2:
1225 off = insn & 0xff;
1226 stop = start + 4 + off * 2;
1227 break;
1228
1229 case R_SH_PCRELIMM8BY4:
1230 off = insn & 0xff;
1231 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1232 break;
1233
1234 case R_SH_SWITCH8:
1235 case R_SH_SWITCH16:
1236 case R_SH_SWITCH32:
1237 /* These relocs types represent
1238 .word L2-L1
1239 The r_offset field holds the difference between the reloc
1240 address and L1. That is the start of the reloc, and
1241 adding in the contents gives us the top. We must adjust
1242 both the r_offset field and the section contents. */
1243
1244 start = irel->r_vaddr - sec->vma;
1245 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1246
1247 if (start > addr
1248 && start < toaddr
1249 && (stop <= addr || stop >= toaddr))
1250 irel->r_offset += count;
1251 else if (stop > addr
1252 && stop < toaddr
1253 && (start <= addr || start >= toaddr))
1254 irel->r_offset -= count;
1255
1256 start = stop;
1257
1258 if (irel->r_type == R_SH_SWITCH16)
1259 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1260 else if (irel->r_type == R_SH_SWITCH8)
1261 voff = bfd_get_8 (abfd, contents + nraddr);
1262 else
1263 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1264 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1265
1266 break;
1267
1268 case R_SH_USES:
1269 start = irel->r_vaddr - sec->vma;
1270 stop = (bfd_vma) ((bfd_signed_vma) start
1271 + (long) irel->r_offset
1272 + 4);
1273 break;
1274 }
1275
1276 if (start > addr
1277 && start < toaddr
1278 && (stop <= addr || stop >= toaddr))
1279 adjust = count;
1280 else if (stop > addr
1281 && stop < toaddr
1282 && (start <= addr || start >= toaddr))
1283 adjust = - count;
1284 else
1285 adjust = 0;
1286
1287 if (adjust != 0)
1288 {
1289 oinsn = insn;
b34976b6 1290 overflow = FALSE;
252b5132
RH		 1291 switch (irel->r_type)
1292 {
1293 default:
1294 abort ();
1295 break;
1296
1297 case R_SH_PCDISP8BY2:
1298 case R_SH_PCRELIMM8BY2:
1299 insn += adjust / 2;
1300 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1301 overflow = TRUE;
dc810e39 1302 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1303 break;
1304
1305 case R_SH_PCDISP:
1306 insn += adjust / 2;
1307 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 1308 overflow = TRUE;
dc810e39 1309 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1310 break;
1311
1312 case R_SH_PCRELIMM8BY4:
1313 BFD_ASSERT (adjust == count || count >= 4);
1314 if (count >= 4)
1315 insn += adjust / 4;
1316 else
1317 {
1318 if ((irel->r_vaddr & 3) == 0)
1319 ++insn;
1320 }
1321 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1322 overflow = TRUE;
dc810e39 1323 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1324 break;
1325
1326 case R_SH_SWITCH8:
1327 voff += adjust;
1328 if (voff < 0 || voff >= 0xff)
b34976b6 1329 overflow = TRUE;
dc810e39 1330 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1331 break;
1332
1333 case R_SH_SWITCH16:
1334 voff += adjust;
1335 if (voff < - 0x8000 || voff >= 0x8000)
b34976b6 1336 overflow = TRUE;
dc810e39 1337 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1338 break;
1339
1340 case R_SH_SWITCH32:
1341 voff += adjust;
dc810e39 1342 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1343 break;
1344
1345 case R_SH_USES:
1346 irel->r_offset += adjust;
1347 break;
1348 }
1349
1350 if (overflow)
1351 {
1352 ((*_bfd_error_handler)
d003868e
AM		 1353 ("%B: 0x%lx: fatal: reloc overflow while relaxing",
1354 abfd, (unsigned long) irel->r_vaddr));
252b5132 1355 bfd_set_error (bfd_error_bad_value);
b34976b6 1356 return FALSE;
252b5132
RH		 1357 }
1358 }
1359
1360 irel->r_vaddr = nraddr + sec->vma;
1361 }
1362
1363 /* Look through all the other sections. If there contain any IMM32
1364 relocs against internal symbols which we are not going to adjust
1365 below, we may need to adjust the addends. */
1366 for (o = abfd->sections; o != NULL; o = o->next)
1367 {
1368 struct internal_reloc *internal_relocs;
1369 struct internal_reloc *irelscan, *irelscanend;
1370 bfd_byte *ocontents;
1371
1372 if (o == sec
1373 || (o->flags & SEC_RELOC) == 0
1374 || o->reloc_count == 0)
1375 continue;
1376
1377 /* We always cache the relocs. Perhaps, if info->keep_memory is
b34976b6 1378 FALSE, we should free them, if we are permitted to, when we
252b5132
RH		 1379 leave sh_coff_relax_section. */
1380 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6 1381 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
252b5132
RH		 1382 (struct internal_reloc *) NULL));
1383 if (internal_relocs == NULL)
b34976b6 1384 return FALSE;
252b5132
RH		 1385
1386 ocontents = NULL;
1387 irelscanend = internal_relocs + o->reloc_count;
1388 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1389 {
1390 struct internal_syment sym;
1391
17505c5c
NC		 1392#ifdef COFF_WITH_PE
1393 if (irelscan->r_type != R_SH_IMM32
1394 && irelscan->r_type != R_SH_IMAGEBASE
1395 && irelscan->r_type != R_SH_IMM32CE)
1396#else
252b5132 1397 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1398#endif
252b5132
RH		 1399 continue;
1400
1401 bfd_coff_swap_sym_in (abfd,
1402 ((bfd_byte *) obj_coff_external_syms (abfd)
1403 + (irelscan->r_symndx
1404 * bfd_coff_symesz (abfd))),
1405 &sym);
1406 if (sym.n_sclass != C_EXT
1407 && sym.n_scnum == sec->target_index
1408 && ((bfd_vma) sym.n_value <= addr
1409 || (bfd_vma) sym.n_value >= toaddr))
1410 {
1411 bfd_vma val;
1412
1413 if (ocontents == NULL)
1414 {
1415 if (coff_section_data (abfd, o)->contents != NULL)
1416 ocontents = coff_section_data (abfd, o)->contents;
1417 else
1418 {
eea6121a
AM		 1419 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1420 return FALSE;
252b5132 1421 /* We always cache the section contents.
b34976b6 1422 Perhaps, if info->keep_memory is FALSE, we
252b5132
RH		 1423 should free them, if we are permitted to,
1424 when we leave sh_coff_relax_section. */
252b5132
RH		 1425 coff_section_data (abfd, o)->contents = ocontents;
1426 }
1427 }
1428
1429 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1430 val += sym.n_value;
1431 if (val > addr && val < toaddr)
1432 bfd_put_32 (abfd, val - count,
1433 ocontents + irelscan->r_vaddr - o->vma);
1434
b34976b6 1435 coff_section_data (abfd, o)->keep_contents = TRUE;
252b5132
RH		 1436 }
1437 }
1438 }
1439
1440 /* Adjusting the internal symbols will not work if something has
1441 already retrieved the generic symbols. It would be possible to
1442 make this work by adjusting the generic symbols at the same time.
1443 However, this case should not arise in normal usage. */
1444 if (obj_symbols (abfd) != NULL
1445 || obj_raw_syments (abfd) != NULL)
1446 {
1447 ((*_bfd_error_handler)
d003868e 1448 ("%B: fatal: generic symbols retrieved before relaxing", abfd));
252b5132 1449 bfd_set_error (bfd_error_invalid_operation);
b34976b6 1450 return FALSE;
252b5132
RH		 1451 }
1452
1453 /* Adjust all the symbols. */
1454 sym_hash = obj_coff_sym_hashes (abfd);
1455 symesz = bfd_coff_symesz (abfd);
1456 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1457 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1458 while (esym < esymend)
1459 {
1460 struct internal_syment isym;
1461
1462 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1463
1464 if (isym.n_scnum == sec->target_index
1465 && (bfd_vma) isym.n_value > addr
1466 && (bfd_vma) isym.n_value < toaddr)
1467 {
1468 isym.n_value -= count;
1469
1470 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1471
1472 if (*sym_hash != NULL)
1473 {
1474 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1475 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1476 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1477 && (*sym_hash)->root.u.def.value < toaddr);
1478 (*sym_hash)->root.u.def.value -= count;
1479 }
1480 }
1481
1482 esym += (isym.n_numaux + 1) * symesz;
1483 sym_hash += isym.n_numaux + 1;
1484 }
1485
1486 /* See if we can move the ALIGN reloc forward. We have adjusted
1487 r_vaddr for it already. */
1488 if (irelalign != NULL)
1489 {
1490 bfd_vma alignto, alignaddr;
1491
1492 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1493 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1494 1 << irelalign->r_offset);
1495 if (alignto != alignaddr)
1496 {
1497 /* Tail recursion. */
1498 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1499 (int) (alignto - alignaddr));
252b5132
RH		 1500 }
1501 }
1502
b34976b6 1503 return TRUE;
252b5132
RH		 1504}
1505\f
1506/* This is yet another version of the SH opcode table, used to rapidly
1507 get information about a particular instruction. */
1508
1509/* The opcode map is represented by an array of these structures. The
1510 array is indexed by the high order four bits in the instruction. */
1511
1512struct sh_major_opcode
1513{
1514 /* A pointer to the instruction list. This is an array which
1515 contains all the instructions with this major opcode. */
1516 const struct sh_minor_opcode *minor_opcodes;
1517 /* The number of elements in minor_opcodes. */
1518 unsigned short count;
1519};
1520
1521/* This structure holds information for a set of SH opcodes. The
1522 instruction code is anded with the mask value, and the resulting
1523 value is used to search the order opcode list. */
1524
1525struct sh_minor_opcode
1526{
1527 /* The sorted opcode list. */
1528 const struct sh_opcode *opcodes;
1529 /* The number of elements in opcodes. */
1530 unsigned short count;
1531 /* The mask value to use when searching the opcode list. */
1532 unsigned short mask;
1533};
1534
1535/* This structure holds information for an SH instruction. An array
1536 of these structures is sorted in order by opcode. */
1537
1538struct sh_opcode
1539{
1540 /* The code for this instruction, after it has been anded with the
1541 mask value in the sh_major_opcode structure. */
1542 unsigned short opcode;
1543 /* Flags for this instruction. */
86033394 1544 unsigned long flags;
252b5132
RH		 1545};
1546
1547/* Flag which appear in the sh_opcode structure. */
1548
1549/* This instruction loads a value from memory. */
1550#define LOAD (0x1)
1551
1552/* This instruction stores a value to memory. */
1553#define STORE (0x2)
1554
1555/* This instruction is a branch. */
1556#define BRANCH (0x4)
1557
1558/* This instruction has a delay slot. */
1559#define DELAY (0x8)
1560
1561/* This instruction uses the value in the register in the field at
1562 mask 0x0f00 of the instruction. */
1563#define USES1 (0x10)
84dcfba7 1564#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1565
1566/* This instruction uses the value in the register in the field at
1567 mask 0x00f0 of the instruction. */
1568#define USES2 (0x20)
84dcfba7 1569#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1570
1571/* This instruction uses the value in register 0. */
1572#define USESR0 (0x40)
1573
1574/* This instruction sets the value in the register in the field at
1575 mask 0x0f00 of the instruction. */
1576#define SETS1 (0x80)
84dcfba7 1577#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1578
1579/* This instruction sets the value in the register in the field at
1580 mask 0x00f0 of the instruction. */
1581#define SETS2 (0x100)
84dcfba7 1582#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1583
1584/* This instruction sets register 0. */
1585#define SETSR0 (0x200)
1586
1587/* This instruction sets a special register. */
1588#define SETSSP (0x400)
1589
1590/* This instruction uses a special register. */
1591#define USESSP (0x800)
1592
1593/* This instruction uses the floating point register in the field at
1594 mask 0x0f00 of the instruction. */
1595#define USESF1 (0x1000)
84dcfba7 1596#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1597
1598/* This instruction uses the floating point register in the field at
1599 mask 0x00f0 of the instruction. */
1600#define USESF2 (0x2000)
84dcfba7 1601#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1602
1603/* This instruction uses floating point register 0. */
1604#define USESF0 (0x4000)
1605
1606/* This instruction sets the floating point register in the field at
1607 mask 0x0f00 of the instruction. */
1608#define SETSF1 (0x8000)
84dcfba7 1609#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1610
d4845d57
JR		 1611#define USESAS (0x10000)
1612#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1613#define USESR8 (0x20000)
1614#define SETSAS (0x40000)
1615#define SETSAS_REG(x) USESAS_REG (x)
1616
8d6ad26e
AM		 1617#define MAP(a) a, sizeof a / sizeof a[0]
1618
86033394 1619#ifndef COFF_IMAGE_WITH_PE
b34976b6 1620static bfd_boolean sh_insn_uses_reg
252b5132 1621 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1622static bfd_boolean sh_insn_sets_reg
84dcfba7 1623 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1624static bfd_boolean sh_insn_uses_or_sets_reg
84dcfba7 1625 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1626static bfd_boolean sh_insn_uses_freg
252b5132 1627 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1628static bfd_boolean sh_insn_sets_freg
84dcfba7 1629 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1630static bfd_boolean sh_insn_uses_or_sets_freg
84dcfba7 1631 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1632static bfd_boolean sh_insns_conflict
252b5132
RH		 1633 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1634 const struct sh_opcode *));
b34976b6 1635static bfd_boolean sh_load_use
252b5132
RH		 1636 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1637 const struct sh_opcode *));
252b5132 1638
8d6ad26e 1639/* The opcode maps. */
252b5132
RH		 1640
1641static const struct sh_opcode sh_opcode00[] =
1642{
1643 { 0x0008, SETSSP }, /* clrt */
1644 { 0x0009, 0 }, /* nop */
1645 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1646 { 0x0018, SETSSP }, /* sett */
1647 { 0x0019, SETSSP }, /* div0u */
1648 { 0x001b, 0 }, /* sleep */
1649 { 0x0028, SETSSP }, /* clrmac */
1650 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1651 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1652 { 0x0048, SETSSP }, /* clrs */
1653 { 0x0058, SETSSP } /* sets */
1654};
1655
1656static const struct sh_opcode sh_opcode01[] =
1657{
252b5132
RH		 1658 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1659 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1660 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1661 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1662 { 0x0029, SETS1 | USESSP }, /* movt rn */
1663 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1664 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1665 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1666 { 0x0083, LOAD | USES1 }, /* pref @rn */
1667 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1668 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1669 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1670 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1671 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1672};
1673
252b5132
RH		 1674static const struct sh_opcode sh_opcode02[] =
1675{
d4845d57 1676 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1677 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1678 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1679 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1680 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1681 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1682 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1683 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1684 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1685};
1686
1687static const struct sh_minor_opcode sh_opcode0[] =
1688{
1689 { MAP (sh_opcode00), 0xffff },
1690 { MAP (sh_opcode01), 0xf0ff },
1691 { MAP (sh_opcode02), 0xf00f }
1692};
1693
1694static const struct sh_opcode sh_opcode10[] =
1695{
1696 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1697};
1698
1699static const struct sh_minor_opcode sh_opcode1[] =
1700{
1701 { MAP (sh_opcode10), 0xf000 }
1702};
1703
1704static const struct sh_opcode sh_opcode20[] =
1705{
1706 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1707 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1708 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1709 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1710 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1711 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1712 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1713 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1714 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1715 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1716 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1717 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1718 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1719 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1720 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1721};
1722
1723static const struct sh_minor_opcode sh_opcode2[] =
1724{
1725 { MAP (sh_opcode20), 0xf00f }
1726};
1727
1728static const struct sh_opcode sh_opcode30[] =
1729{
1730 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1731 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1732 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1733 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1734 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1735 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1736 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1737 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1738 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1739 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1740 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1741 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1742 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1743 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1744};
1745
1746static const struct sh_minor_opcode sh_opcode3[] =
1747{
1748 { MAP (sh_opcode30), 0xf00f }
1749};
1750
1751static const struct sh_opcode sh_opcode40[] =
1752{
1753 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1754 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1755 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1756 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1757 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1758 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1759 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1760 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1761 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1762 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1763 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1764 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1765 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1766 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1767 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1768 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1769 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1770 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1771 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1772 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1773 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1774 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1775 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1776 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1777 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1778 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1779 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1780 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1781 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1782 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1783 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1784 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1785 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1786 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1787 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1788 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1789 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1790 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1791 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1792 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1793 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1794 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1795 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1796 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1797 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1798 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1799 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1800 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1801 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1802 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1803 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
252b5132
RH		 1804};
1805
1806static const struct sh_opcode sh_opcode41[] =
1807{
d4845d57
JR		 1808 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1809 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1810 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1811 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1812 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1813 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1814};
1815
1816static const struct sh_minor_opcode sh_opcode4[] =
1817{
1818 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1819 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1820};
1821
1822static const struct sh_opcode sh_opcode50[] =
1823{
1824 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1825};
1826
1827static const struct sh_minor_opcode sh_opcode5[] =
1828{
1829 { MAP (sh_opcode50), 0xf000 }
1830};
1831
1832static const struct sh_opcode sh_opcode60[] =
1833{
1834 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1835 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1836 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1837 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1838 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1839 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1840 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1841 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1842 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1843 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1844 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1845 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1846 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1847 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1848 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1849 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1850};
1851
1852static const struct sh_minor_opcode sh_opcode6[] =
1853{
1854 { MAP (sh_opcode60), 0xf00f }
1855};
1856
1857static const struct sh_opcode sh_opcode70[] =
1858{
1859 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1860};
1861
1862static const struct sh_minor_opcode sh_opcode7[] =
1863{
1864 { MAP (sh_opcode70), 0xf000 }
1865};
1866
1867static const struct sh_opcode sh_opcode80[] =
1868{
1869 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1870 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1871 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1872 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1873 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1874 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1875 { 0x8900, BRANCH | USESSP }, /* bt label */
1876 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1877 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1878 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1879 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1880 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1881};
1882
1883static const struct sh_minor_opcode sh_opcode8[] =
1884{
1885 { MAP (sh_opcode80), 0xff00 }
1886};
1887
1888static const struct sh_opcode sh_opcode90[] =
1889{
1890 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1891};
1892
1893static const struct sh_minor_opcode sh_opcode9[] =
1894{
1895 { MAP (sh_opcode90), 0xf000 }
1896};
1897
1898static const struct sh_opcode sh_opcodea0[] =
1899{
1900 { 0xa000, BRANCH | DELAY } /* bra label */
1901};
1902
1903static const struct sh_minor_opcode sh_opcodea[] =
1904{
1905 { MAP (sh_opcodea0), 0xf000 }
1906};
1907
1908static const struct sh_opcode sh_opcodeb0[] =
1909{
1910 { 0xb000, BRANCH | DELAY } /* bsr label */
1911};
1912
1913static const struct sh_minor_opcode sh_opcodeb[] =
1914{
1915 { MAP (sh_opcodeb0), 0xf000 }
1916};
1917
1918static const struct sh_opcode sh_opcodec0[] =
1919{
1920 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1921 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1922 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1923 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1924 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1925 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1926 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1927 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1928 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1929 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1930 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1931 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1932 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1933 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1934 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1935 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1936};
1937
1938static const struct sh_minor_opcode sh_opcodec[] =
1939{
1940 { MAP (sh_opcodec0), 0xff00 }
1941};
1942
1943static const struct sh_opcode sh_opcoded0[] =
1944{
1945 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1946};
1947
1948static const struct sh_minor_opcode sh_opcoded[] =
1949{
1950 { MAP (sh_opcoded0), 0xf000 }
1951};
1952
1953static const struct sh_opcode sh_opcodee0[] =
1954{
1955 { 0xe000, SETS1 } /* mov #imm,rn */
1956};
1957
1958static const struct sh_minor_opcode sh_opcodee[] =
1959{
1960 { MAP (sh_opcodee0), 0xf000 }
1961};
1962
1963static const struct sh_opcode sh_opcodef0[] =
1964{
1965 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1966 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1967 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1968 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1969 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1970 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1971 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1972 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1973 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1974 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1975 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1976 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1977 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1978 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1979};
1980
1981static const struct sh_opcode sh_opcodef1[] =
1982{
1983 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1984 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1985 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1986 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1987 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1988 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1989 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1990 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1991 { 0xf08d, SETSF1 }, /* fldi0 fn */
1992 { 0xf09d, SETSF1 } /* fldi1 fn */
1993};
1994
1995static const struct sh_minor_opcode sh_opcodef[] =
1996{
1997 { MAP (sh_opcodef0), 0xf00f },
1998 { MAP (sh_opcodef1), 0xf0ff }
1999};
2000
d4845d57 2001static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 2002{
2003 { MAP (sh_opcode0) },
2004 { MAP (sh_opcode1) },
2005 { MAP (sh_opcode2) },
2006 { MAP (sh_opcode3) },
2007 { MAP (sh_opcode4) },
2008 { MAP (sh_opcode5) },
2009 { MAP (sh_opcode6) },
2010 { MAP (sh_opcode7) },
2011 { MAP (sh_opcode8) },
2012 { MAP (sh_opcode9) },
2013 { MAP (sh_opcodea) },
2014 { MAP (sh_opcodeb) },
2015 { MAP (sh_opcodec) },
2016 { MAP (sh_opcoded) },
2017 { MAP (sh_opcodee) },
2018 { MAP (sh_opcodef) }
2019};
2020
d4845d57
JR		 2021/* The double data transfer / parallel processing insns are not
2022 described here. This will cause sh_align_load_span to leave them alone. */
2023
2024static const struct sh_opcode sh_dsp_opcodef0[] =
2025{
2026 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2027 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2028 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2029 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2030 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2031 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2032 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2033 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2034};
2035
2036static const struct sh_minor_opcode sh_dsp_opcodef[] =
2037{
2038 { MAP (sh_dsp_opcodef0), 0xfc0d }
2039};
2040
252b5132
RH		 2041/* Given an instruction, return a pointer to the corresponding
2042 sh_opcode structure. Return NULL if the instruction is not
2043 recognized. */
2044
2045static const struct sh_opcode *
2046sh_insn_info (insn)
2047 unsigned int insn;
2048{
2049 const struct sh_major_opcode *maj;
2050 const struct sh_minor_opcode *min, *minend;
2051
2052 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2053 min = maj->minor_opcodes;
2054 minend = min + maj->count;
2055 for (; min < minend; min++)
2056 {
2057 unsigned int l;
2058 const struct sh_opcode *op, *opend;
2059
2060 l = insn & min->mask;
2061 op = min->opcodes;
2062 opend = op + min->count;
2063
2064 /* Since the opcodes tables are sorted, we could use a binary
2065 search here if the count were above some cutoff value. */
2066 for (; op < opend; op++)
2067 if (op->opcode == l)
2068 return op;
2069 }
2070
cbfe05c4 2071 return NULL;
252b5132
RH		 2072}
2073
84dcfba7
JR		 2074/* See whether an instruction uses or sets a general purpose register */
2075
b34976b6 2076static bfd_boolean
84dcfba7
JR		 2077sh_insn_uses_or_sets_reg (insn, op, reg)
2078 unsigned int insn;
2079 const struct sh_opcode *op;
2080 unsigned int reg;
2081{
2082 if (sh_insn_uses_reg (insn, op, reg))
b34976b6 2083 return TRUE;
84dcfba7
JR		 2084
2085 return sh_insn_sets_reg (insn, op, reg);
2086}
2087
252b5132
RH		 2088/* See whether an instruction uses a general purpose register. */
2089
b34976b6 2090static bfd_boolean
252b5132
RH		 2091sh_insn_uses_reg (insn, op, reg)
2092 unsigned int insn;
2093 const struct sh_opcode *op;
2094 unsigned int reg;
2095{
2096 unsigned int f;
2097
2098 f = op->flags;
2099
2100 if ((f & USES1) != 0
84dcfba7 2101 && USES1_REG (insn) == reg)
b34976b6 2102 return TRUE;
252b5132 2103 if ((f & USES2) != 0
84dcfba7 2104 && USES2_REG (insn) == reg)
b34976b6 2105 return TRUE;
252b5132
RH		 2106 if ((f & USESR0) != 0
2107 && reg == 0)
b34976b6 2108 return TRUE;
d4845d57 2109 if ((f & USESAS) && reg == USESAS_REG (insn))
b34976b6 2110 return TRUE;
d4845d57 2111 if ((f & USESR8) && reg == 8)
b34976b6 2112 return TRUE;
252b5132 2113
b34976b6 2114 return FALSE;
252b5132 2115}
17505c5c 2116
84dcfba7
JR		 2117/* See whether an instruction sets a general purpose register. */
2118
b34976b6 2119static bfd_boolean
84dcfba7
JR		 2120sh_insn_sets_reg (insn, op, reg)
2121 unsigned int insn;
2122 const struct sh_opcode *op;
2123 unsigned int reg;
2124{
2125 unsigned int f;
2126
2127 f = op->flags;
2128
2129 if ((f & SETS1) != 0
2130 && SETS1_REG (insn) == reg)
b34976b6 2131 return TRUE;
84dcfba7
JR		 2132 if ((f & SETS2) != 0
2133 && SETS2_REG (insn) == reg)
b34976b6 2134 return TRUE;
84dcfba7
JR		 2135 if ((f & SETSR0) != 0
2136 && reg == 0)
b34976b6 2137 return TRUE;
d4845d57 2138 if ((f & SETSAS) && reg == SETSAS_REG (insn))
b34976b6 2139 return TRUE;
84dcfba7 2140
b34976b6 2141 return FALSE;
84dcfba7
JR		 2142}
2143
2144/* See whether an instruction uses or sets a floating point register */
2145
b34976b6 2146static bfd_boolean
84dcfba7
JR		 2147sh_insn_uses_or_sets_freg (insn, op, reg)
2148 unsigned int insn;
2149 const struct sh_opcode *op;
2150 unsigned int reg;
2151{
2152 if (sh_insn_uses_freg (insn, op, reg))
b34976b6 2153 return TRUE;
84dcfba7
JR		 2154
2155 return sh_insn_sets_freg (insn, op, reg);
2156}
252b5132
RH		 2157
2158/* See whether an instruction uses a floating point register. */
2159
b34976b6 2160static bfd_boolean
252b5132
RH		 2161sh_insn_uses_freg (insn, op, freg)
2162 unsigned int insn;
2163 const struct sh_opcode *op;
2164 unsigned int freg;
2165{
2166 unsigned int f;
2167
2168 f = op->flags;
2169
2170 /* We can't tell if this is a double-precision insn, so just play safe
2171 and assume that it might be. So not only have we test FREG against
2172 itself, but also even FREG against FREG+1 - if the using insn uses
2173 just the low part of a double precision value - but also an odd
2174 FREG against FREG-1 - if the setting insn sets just the low part
2175 of a double precision value.
2176 So what this all boils down to is that we have to ignore the lowest
2177 bit of the register number. */
cbfe05c4 2178
252b5132 2179 if ((f & USESF1) != 0
84dcfba7 2180 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2181 return TRUE;
252b5132 2182 if ((f & USESF2) != 0
84dcfba7 2183 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2184 return TRUE;
252b5132
RH		 2185 if ((f & USESF0) != 0
2186 && freg == 0)
b34976b6 2187 return TRUE;
252b5132 2188
b34976b6 2189 return FALSE;
252b5132
RH		 2190}
2191
84dcfba7
JR		 2192/* See whether an instruction sets a floating point register. */
2193
b34976b6 2194static bfd_boolean
84dcfba7
JR		 2195sh_insn_sets_freg (insn, op, freg)
2196 unsigned int insn;
2197 const struct sh_opcode *op;
2198 unsigned int freg;
2199{
2200 unsigned int f;
2201
2202 f = op->flags;
2203
2204 /* We can't tell if this is a double-precision insn, so just play safe
2205 and assume that it might be. So not only have we test FREG against
2206 itself, but also even FREG against FREG+1 - if the using insn uses
2207 just the low part of a double precision value - but also an odd
2208 FREG against FREG-1 - if the setting insn sets just the low part
2209 of a double precision value.
2210 So what this all boils down to is that we have to ignore the lowest
2211 bit of the register number. */
cbfe05c4 2212
84dcfba7
JR		 2213 if ((f & SETSF1) != 0
2214 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2215 return TRUE;
84dcfba7 2216
b34976b6 2217 return FALSE;
84dcfba7
JR		 2218}
2219
252b5132
RH		 2220/* See whether instructions I1 and I2 conflict, assuming I1 comes
2221 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
b34976b6 2222 This should return TRUE if there is a conflict, or FALSE if the
252b5132
RH		 2223 instructions can be swapped safely. */
2224
b34976b6 2225static bfd_boolean
252b5132
RH		 2226sh_insns_conflict (i1, op1, i2, op2)
2227 unsigned int i1;
2228 const struct sh_opcode *op1;
2229 unsigned int i2;
2230 const struct sh_opcode *op2;
2231{
2232 unsigned int f1, f2;
2233
2234 f1 = op1->flags;
2235 f2 = op2->flags;
2236
2237 /* Load of fpscr conflicts with floating point operations.
2238 FIXME: shouldn't test raw opcodes here. */
2239 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2240 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
b34976b6 2241 return TRUE;
252b5132
RH		 2242
2243 if ((f1 & (BRANCH | DELAY)) != 0
2244 || (f2 & (BRANCH | DELAY)) != 0)
b34976b6 2245 return TRUE;
252b5132 2246
84dcfba7
JR		 2247 if (((f1 | f2) & SETSSP)
2248 && (f1 & (SETSSP | USESSP))
2249 && (f2 & (SETSSP | USESSP)))
b34976b6 2250 return TRUE;
252b5132
RH		 2251
2252 if ((f1 & SETS1) != 0
84dcfba7 2253 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
b34976b6 2254 return TRUE;
252b5132 2255 if ((f1 & SETS2) != 0
84dcfba7 2256 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
b34976b6 2257 return TRUE;
252b5132 2258 if ((f1 & SETSR0) != 0
84dcfba7 2259 && sh_insn_uses_or_sets_reg (i2, op2, 0))
b34976b6 2260 return TRUE;
d4845d57
JR		 2261 if ((f1 & SETSAS)
2262 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
b34976b6 2263 return TRUE;
252b5132 2264 if ((f1 & SETSF1) != 0
84dcfba7 2265 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
b34976b6 2266 return TRUE;
252b5132
RH		 2267
2268 if ((f2 & SETS1) != 0
84dcfba7 2269 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
b34976b6 2270 return TRUE;
252b5132 2271 if ((f2 & SETS2) != 0
84dcfba7 2272 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
b34976b6 2273 return TRUE;
252b5132 2274 if ((f2 & SETSR0) != 0
84dcfba7 2275 && sh_insn_uses_or_sets_reg (i1, op1, 0))
b34976b6 2276 return TRUE;
d4845d57
JR		 2277 if ((f2 & SETSAS)
2278 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
b34976b6 2279 return TRUE;
252b5132 2280 if ((f2 & SETSF1) != 0
84dcfba7 2281 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
b34976b6 2282 return TRUE;
252b5132
RH		 2283
2284 /* The instructions do not conflict. */
b34976b6 2285 return FALSE;
252b5132
RH		 2286}
2287
2288/* I1 is a load instruction, and I2 is some other instruction. Return
b34976b6 2289 TRUE if I1 loads a register which I2 uses. */
252b5132 2290
b34976b6 2291static bfd_boolean
252b5132
RH		 2292sh_load_use (i1, op1, i2, op2)
2293 unsigned int i1;
2294 const struct sh_opcode *op1;
2295 unsigned int i2;
2296 const struct sh_opcode *op2;
2297{
2298 unsigned int f1;
2299
2300 f1 = op1->flags;
2301
2302 if ((f1 & LOAD) == 0)
b34976b6 2303 return FALSE;
252b5132
RH		 2304
2305 /* If both SETS1 and SETSSP are set, that means a load to a special
2306 register using postincrement addressing mode, which we don't care
2307 about here. */
2308 if ((f1 & SETS1) != 0
2309 && (f1 & SETSSP) == 0
2310 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2311 return TRUE;
252b5132
RH		 2312
2313 if ((f1 & SETSR0) != 0
2314 && sh_insn_uses_reg (i2, op2, 0))
b34976b6 2315 return TRUE;
252b5132
RH		 2316
2317 if ((f1 & SETSF1) != 0
2318 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2319 return TRUE;
252b5132 2320
b34976b6 2321 return FALSE;
252b5132
RH		 2322}
2323
2324/* Try to align loads and stores within a span of memory. This is
2325 called by both the ELF and the COFF sh targets. ABFD and SEC are
2326 the BFD and section we are examining. CONTENTS is the contents of
2327 the section. SWAP is the routine to call to swap two instructions.
2328 RELOCS is a pointer to the internal relocation information, to be
2329 passed to SWAP. PLABEL is a pointer to the current label in a
2330 sorted list of labels; LABEL_END is the end of the list. START and
2331 STOP are the range of memory to examine. If a swap is made,
b34976b6 2332 *PSWAPPED is set to TRUE. */
252b5132 2333
86033394
NC		 2334#ifdef COFF_WITH_PE
2335static
2336#endif
b34976b6 2337bfd_boolean
252b5132
RH		 2338_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2339 plabel, label_end, start, stop, pswapped)
2340 bfd *abfd;
2341 asection *sec;
2342 bfd_byte *contents;
b34976b6 2343 bfd_boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
252b5132
RH		 2344 PTR relocs;
2345 bfd_vma **plabel;
2346 bfd_vma *label_end;
2347 bfd_vma start;
2348 bfd_vma stop;
b34976b6 2349 bfd_boolean *pswapped;
252b5132 2350{
d4845d57
JR		 2351 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2352 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2353 bfd_vma i;
2354
d4845d57
JR		 2355 /* The SH4 has a Harvard architecture, hence aligning loads is not
2356 desirable. In fact, it is counter-productive, since it interferes
2357 with the schedules generated by the compiler. */
2358 if (abfd->arch_info->mach == bfd_mach_sh4)
b34976b6 2359 return TRUE;
d4845d57
JR		 2360
2361 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2362 instructions. */
2363 if (dsp)
2364 {
2365 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2366 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2367 }
2368
252b5132
RH		 2369 /* Instructions should be aligned on 2 byte boundaries. */
2370 if ((start & 1) == 1)
2371 ++start;
2372
2373 /* Now look through the unaligned addresses. */
2374 i = start;
2375 if ((i & 2) == 0)
2376 i += 2;
2377 for (; i < stop; i += 4)
2378 {
2379 unsigned int insn;
2380 const struct sh_opcode *op;
2381 unsigned int prev_insn = 0;
2382 const struct sh_opcode *prev_op = NULL;
2383
2384 insn = bfd_get_16 (abfd, contents + i);
2385 op = sh_insn_info (insn);
2386 if (op == NULL
2387 || (op->flags & (LOAD | STORE)) == 0)
2388 continue;
2389
2390 /* This is a load or store which is not on a four byte boundary. */
2391
2392 while (*plabel < label_end && **plabel < i)
2393 ++*plabel;
2394
2395 if (i > start)
2396 {
2397 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2398 /* If INSN is the field b of a parallel processing insn, it is not
2399 a load / store after all. Note that the test here might mistake
2400 the field_b of a pcopy insn for the starting code of a parallel
2401 processing insn; this might miss a swapping opportunity, but at
2402 least we're on the safe side. */
2403 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2404 continue;
2405
2406 /* Check if prev_insn is actually the field b of a parallel
2407 processing insn. Again, this can give a spurious match
2408 after a pcopy. */
2409 if (dsp && i - 2 > start)
2410 {
2411 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2412
d4845d57
JR		 2413 if ((pprev_insn & 0xfc00) == 0xf800)
2414 prev_op = NULL;
2415 else
2416 prev_op = sh_insn_info (prev_insn);
2417 }
2418 else
2419 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2420
2421 /* If the load/store instruction is in a delay slot, we
2422 can't swap. */
2423 if (prev_op == NULL
2424 || (prev_op->flags & DELAY) != 0)
2425 continue;
2426 }
2427 if (i > start
2428 && (*plabel >= label_end || **plabel != i)
2429 && prev_op != NULL
2430 && (prev_op->flags & (LOAD | STORE)) == 0
2431 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2432 {
b34976b6 2433 bfd_boolean ok;
252b5132
RH		 2434
2435 /* The load/store instruction does not have a label, and
2436 there is a previous instruction; PREV_INSN is not
2437 itself a load/store instruction, and PREV_INSN and
2438 INSN do not conflict. */
2439
b34976b6 2440 ok = TRUE;
252b5132
RH		 2441
2442 if (i >= start + 4)
2443 {
2444 unsigned int prev2_insn;
2445 const struct sh_opcode *prev2_op;
2446
2447 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2448 prev2_op = sh_insn_info (prev2_insn);
2449
2450 /* If the instruction before PREV_INSN has a delay
2451 slot--that is, PREV_INSN is in a delay slot--we
2452 can not swap. */
2453 if (prev2_op == NULL
2454 || (prev2_op->flags & DELAY) != 0)
b34976b6 2455 ok = FALSE;
252b5132
RH		 2456
2457 /* If the instruction before PREV_INSN is a load,
2458 and it sets a register which INSN uses, then
2459 putting INSN immediately after PREV_INSN will
2460 cause a pipeline bubble, so there is no point to
2461 making the swap. */
2462 if (ok
2463 && (prev2_op->flags & LOAD) != 0
2464 && sh_load_use (prev2_insn, prev2_op, insn, op))
b34976b6 2465 ok = FALSE;
252b5132
RH		 2466 }
2467
2468 if (ok)
2469 {
2470 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
b34976b6
AM		 2471 return FALSE;
2472 *pswapped = TRUE;
252b5132
RH		 2473 continue;
2474 }
2475 }
2476
2477 while (*plabel < label_end && **plabel < i + 2)
2478 ++*plabel;
2479
2480 if (i + 2 < stop
2481 && (*plabel >= label_end || **plabel != i + 2))
2482 {
2483 unsigned int next_insn;
2484 const struct sh_opcode *next_op;
2485
2486 /* There is an instruction after the load/store
2487 instruction, and it does not have a label. */
2488 next_insn = bfd_get_16 (abfd, contents + i + 2);
2489 next_op = sh_insn_info (next_insn);
2490 if (next_op != NULL
2491 && (next_op->flags & (LOAD | STORE)) == 0
2492 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2493 {
b34976b6 2494 bfd_boolean ok;
252b5132
RH		 2495
2496 /* NEXT_INSN is not itself a load/store instruction,
2497 and it does not conflict with INSN. */
2498
b34976b6 2499 ok = TRUE;
252b5132
RH		 2500
2501 /* If PREV_INSN is a load, and it sets a register
2502 which NEXT_INSN uses, then putting NEXT_INSN
2503 immediately after PREV_INSN will cause a pipeline
2504 bubble, so there is no reason to make this swap. */
2505 if (prev_op != NULL
2506 && (prev_op->flags & LOAD) != 0
2507 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
b34976b6 2508 ok = FALSE;
252b5132
RH		 2509
2510 /* If INSN is a load, and it sets a register which
2511 the insn after NEXT_INSN uses, then doing the
2512 swap will cause a pipeline bubble, so there is no
2513 reason to make the swap. However, if the insn
2514 after NEXT_INSN is itself a load or store
2515 instruction, then it is misaligned, so
2516 optimistically hope that it will be swapped
2517 itself, and just live with the pipeline bubble if
2518 it isn't. */
2519 if (ok
2520 && i + 4 < stop
2521 && (op->flags & LOAD) != 0)
2522 {
2523 unsigned int next2_insn;
2524 const struct sh_opcode *next2_op;
2525
2526 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2527 next2_op = sh_insn_info (next2_insn);
230d6d81
NC		 2528 if (next2_op == NULL
2529 || ((next2_op->flags & (LOAD | STORE)) == 0
2530 && sh_load_use (insn, op, next2_insn, next2_op)))
b34976b6 2531 ok = FALSE;
252b5132
RH		 2532 }
2533
2534 if (ok)
2535 {
2536 if (! (*swap) (abfd, sec, relocs, contents, i))
b34976b6
AM		 2537 return FALSE;
2538 *pswapped = TRUE;
252b5132
RH		 2539 continue;
2540 }
2541 }
2542 }
2543 }
2544
b34976b6 2545 return TRUE;
252b5132 2546}
86033394 2547#endif /* not COFF_IMAGE_WITH_PE */
252b5132
RH		 2548
2549/* Look for loads and stores which we can align to four byte
2550 boundaries. See the longer comment above sh_relax_section for why
2551 this is desirable. This sets *PSWAPPED if some instruction was
2552 swapped. */
2553
b34976b6 2554static bfd_boolean
252b5132
RH		 2555sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2556 bfd *abfd;
2557 asection *sec;
2558 struct internal_reloc *internal_relocs;
2559 bfd_byte *contents;
b34976b6 2560 bfd_boolean *pswapped;
252b5132
RH		 2561{
2562 struct internal_reloc *irel, *irelend;
2563 bfd_vma *labels = NULL;
2564 bfd_vma *label, *label_end;
dc810e39 2565 bfd_size_type amt;
252b5132 2566
b34976b6 2567 *pswapped = FALSE;
252b5132
RH		 2568
2569 irelend = internal_relocs + sec->reloc_count;
2570
2571 /* Get all the addresses with labels on them. */
dc810e39
AM		 2572 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2573 labels = (bfd_vma *) bfd_malloc (amt);
252b5132
RH		 2574 if (labels == NULL)
2575 goto error_return;
2576 label_end = labels;
2577 for (irel = internal_relocs; irel < irelend; irel++)
2578 {
2579 if (irel->r_type == R_SH_LABEL)
2580 {
2581 *label_end = irel->r_vaddr - sec->vma;
2582 ++label_end;
2583 }
2584 }
2585
2586 /* Note that the assembler currently always outputs relocs in
2587 address order. If that ever changes, this code will need to sort
2588 the label values and the relocs. */
2589
2590 label = labels;
2591
2592 for (irel = internal_relocs; irel < irelend; irel++)
2593 {
2594 bfd_vma start, stop;
2595
2596 if (irel->r_type != R_SH_CODE)
2597 continue;
2598
2599 start = irel->r_vaddr - sec->vma;
2600
2601 for (irel++; irel < irelend; irel++)
2602 if (irel->r_type == R_SH_DATA)
2603 break;
2604 if (irel < irelend)
2605 stop = irel->r_vaddr - sec->vma;
2606 else
eea6121a 2607 stop = sec->size;
252b5132
RH		 2608
2609 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2610 (PTR) internal_relocs, &label,
2611 label_end, start, stop, pswapped))
2612 goto error_return;
2613 }
2614
2615 free (labels);
2616
b34976b6 2617 return TRUE;
252b5132
RH		 2618
2619 error_return:
2620 if (labels != NULL)
2621 free (labels);
b34976b6 2622 return FALSE;
252b5132
RH		 2623}
2624
2625/* Swap two SH instructions. */
2626
b34976b6 2627static bfd_boolean
252b5132
RH		 2628sh_swap_insns (abfd, sec, relocs, contents, addr)
2629 bfd *abfd;
2630 asection *sec;
2631 PTR relocs;
2632 bfd_byte *contents;
2633 bfd_vma addr;
2634{
2635 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2636 unsigned short i1, i2;
2637 struct internal_reloc *irel, *irelend;
2638
2639 /* Swap the instructions themselves. */
2640 i1 = bfd_get_16 (abfd, contents + addr);
2641 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2642 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2643 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2644
2645 /* Adjust all reloc addresses. */
2646 irelend = internal_relocs + sec->reloc_count;
2647 for (irel = internal_relocs; irel < irelend; irel++)
2648 {
2649 int type, add;
2650
2651 /* There are a few special types of relocs that we don't want to
2652 adjust. These relocs do not apply to the instruction itself,
2653 but are only associated with the address. */
2654 type = irel->r_type;
2655 if (type == R_SH_ALIGN
2656 || type == R_SH_CODE
2657 || type == R_SH_DATA
2658 || type == R_SH_LABEL)
2659 continue;
2660
2661 /* If an R_SH_USES reloc points to one of the addresses being
2662 swapped, we must adjust it. It would be incorrect to do this
2663 for a jump, though, since we want to execute both
2664 instructions after the jump. (We have avoided swapping
2665 around a label, so the jump will not wind up executing an
2666 instruction it shouldn't). */
2667 if (type == R_SH_USES)
2668 {
2669 bfd_vma off;
2670
2671 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2672 if (off == addr)
2673 irel->r_offset += 2;
2674 else if (off == addr + 2)
2675 irel->r_offset -= 2;
2676 }
2677
2678 if (irel->r_vaddr - sec->vma == addr)
2679 {
2680 irel->r_vaddr += 2;
2681 add = -2;
2682 }
2683 else if (irel->r_vaddr - sec->vma == addr + 2)
2684 {
2685 irel->r_vaddr -= 2;
2686 add = 2;
2687 }
2688 else
2689 add = 0;
2690
2691 if (add != 0)
2692 {
2693 bfd_byte *loc;
2694 unsigned short insn, oinsn;
b34976b6 2695 bfd_boolean overflow;
252b5132
RH		 2696
2697 loc = contents + irel->r_vaddr - sec->vma;
b34976b6 2698 overflow = FALSE;
252b5132
RH		 2699 switch (type)
2700 {
2701 default:
2702 break;
2703
2704 case R_SH_PCDISP8BY2:
2705 case R_SH_PCRELIMM8BY2:
2706 insn = bfd_get_16 (abfd, loc);
2707 oinsn = insn;
2708 insn += add / 2;
2709 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2710 overflow = TRUE;
dc810e39 2711 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2712 break;
2713
2714 case R_SH_PCDISP:
2715 insn = bfd_get_16 (abfd, loc);
2716 oinsn = insn;
2717 insn += add / 2;
2718 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 2719 overflow = TRUE;
dc810e39 2720 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2721 break;
2722
2723 case R_SH_PCRELIMM8BY4:
2724 /* This reloc ignores the least significant 3 bits of
2725 the program counter before adding in the offset.
2726 This means that if ADDR is at an even address, the
2727 swap will not affect the offset. If ADDR is an at an
2728 odd address, then the instruction will be crossing a
2729 four byte boundary, and must be adjusted. */
2730 if ((addr & 3) != 0)
2731 {
2732 insn = bfd_get_16 (abfd, loc);
2733 oinsn = insn;
2734 insn += add / 2;
2735 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2736 overflow = TRUE;
dc810e39 2737 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2738 }
2739
2740 break;
2741 }
2742
2743 if (overflow)
2744 {
2745 ((*_bfd_error_handler)
d003868e
AM		 2746 ("%B: 0x%lx: fatal: reloc overflow while relaxing",
2747 abfd, (unsigned long) irel->r_vaddr));
252b5132 2748 bfd_set_error (bfd_error_bad_value);
b34976b6 2749 return FALSE;
252b5132
RH		 2750 }
2751 }
2752 }
2753
b34976b6 2754 return TRUE;
252b5132
RH		 2755}
2756\f
2757/* This is a modification of _bfd_coff_generic_relocate_section, which
2758 will handle SH relaxing. */
2759
b34976b6 2760static bfd_boolean
252b5132
RH		 2761sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2762 relocs, syms, sections)
5f771d47 2763 bfd *output_bfd ATTRIBUTE_UNUSED;
252b5132
RH		 2764 struct bfd_link_info *info;
2765 bfd *input_bfd;
2766 asection *input_section;
2767 bfd_byte *contents;
2768 struct internal_reloc *relocs;
2769 struct internal_syment *syms;
2770 asection **sections;
2771{
2772 struct internal_reloc *rel;
2773 struct internal_reloc *relend;
2774
2775 rel = relocs;
2776 relend = rel + input_section->reloc_count;
2777 for (; rel < relend; rel++)
2778 {
2779 long symndx;
2780 struct coff_link_hash_entry *h;
2781 struct internal_syment *sym;
2782 bfd_vma addend;
2783 bfd_vma val;
2784 reloc_howto_type *howto;
2785 bfd_reloc_status_type rstat;
2786
2787 /* Almost all relocs have to do with relaxing. If any work must
2788 be done for them, it has been done in sh_relax_section. */
2789 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2790#ifdef COFF_WITH_PE
2791 && rel->r_type != R_SH_IMM32CE
2792 && rel->r_type != R_SH_IMAGEBASE
2793#endif
252b5132
RH		 2794 && rel->r_type != R_SH_PCDISP)
2795 continue;
2796
2797 symndx = rel->r_symndx;
2798
2799 if (symndx == -1)
2800 {
2801 h = NULL;
2802 sym = NULL;
2803 }
2804 else
cbfe05c4 2805 {
252b5132
RH		 2806 if (symndx < 0
2807 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2808 {
2809 (*_bfd_error_handler)
d003868e
AM		 2810 ("%B: illegal symbol index %ld in relocs",
2811 input_bfd, symndx);
252b5132 2812 bfd_set_error (bfd_error_bad_value);
b34976b6 2813 return FALSE;
252b5132
RH		 2814 }
2815 h = obj_coff_sym_hashes (input_bfd)[symndx];
2816 sym = syms + symndx;
2817 }
2818
2819 if (sym != NULL && sym->n_scnum != 0)
2820 addend = - sym->n_value;
2821 else
2822 addend = 0;
2823
2824 if (rel->r_type == R_SH_PCDISP)
2825 addend -= 4;
2826
2827 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2828 howto = NULL;
2829 else
2830 howto = &sh_coff_howtos[rel->r_type];
2831
2832 if (howto == NULL)
2833 {
2834 bfd_set_error (bfd_error_bad_value);
b34976b6 2835 return FALSE;
252b5132
RH		 2836 }
2837
17505c5c
NC		 2838#ifdef COFF_WITH_PE
2839 if (rel->r_type == R_SH_IMAGEBASE)
2840 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2841#endif
cbfe05c4 2842
252b5132
RH		 2843 val = 0;
2844
2845 if (h == NULL)
2846 {
2847 asection *sec;
2848
2849 /* There is nothing to do for an internal PCDISP reloc. */
2850 if (rel->r_type == R_SH_PCDISP)
2851 continue;
2852
2853 if (symndx == -1)
2854 {
2855 sec = bfd_abs_section_ptr;
2856 val = 0;
2857 }
2858 else
2859 {
2860 sec = sections[symndx];
2861 val = (sec->output_section->vma
2862 + sec->output_offset
2863 + sym->n_value
2864 - sec->vma);
2865 }
2866 }
2867 else
2868 {
2869 if (h->root.type == bfd_link_hash_defined
2870 || h->root.type == bfd_link_hash_defweak)
2871 {
2872 asection *sec;
2873
2874 sec = h->root.u.def.section;
2875 val = (h->root.u.def.value
2876 + sec->output_section->vma
2877 + sec->output_offset);
2878 }
1049f94e 2879 else if (! info->relocatable)
252b5132
RH		 2880 {
2881 if (! ((*info->callbacks->undefined_symbol)
2882 (info, h->root.root.string, input_bfd, input_section,
b34976b6
AM		 2883 rel->r_vaddr - input_section->vma, TRUE)))
2884 return FALSE;
252b5132
RH		 2885 }
2886 }
2887
2888 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2889 contents,
2890 rel->r_vaddr - input_section->vma,
2891 val, addend);
2892
2893 switch (rstat)
2894 {
2895 default:
2896 abort ();
2897 case bfd_reloc_ok:
2898 break;
2899 case bfd_reloc_overflow:
2900 {
2901 const char *name;
2902 char buf[SYMNMLEN + 1];
2903
2904 if (symndx == -1)
2905 name = "*ABS*";
2906 else if (h != NULL)
dfeffb9f 2907 name = NULL;
252b5132
RH		 2908 else if (sym->_n._n_n._n_zeroes == 0
2909 && sym->_n._n_n._n_offset != 0)
2910 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2911 else
2912 {
2913 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2914 buf[SYMNMLEN] = '\0';
2915 name = buf;
2916 }
2917
2918 if (! ((*info->callbacks->reloc_overflow)
dfeffb9f
L		 2919 (info, (h ? &h->root : NULL), name, howto->name,
2920 (bfd_vma) 0, input_bfd, input_section,
2921 rel->r_vaddr - input_section->vma)))
b34976b6 2922 return FALSE;
252b5132
RH		 2923 }
2924 }
2925 }
2926
b34976b6 2927 return TRUE;
252b5132
RH		 2928}
2929
2930/* This is a version of bfd_generic_get_relocated_section_contents
2931 which uses sh_relocate_section. */
2932
2933static bfd_byte *
2934sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
1049f94e 2935 data, relocatable, symbols)
252b5132
RH		 2936 bfd *output_bfd;
2937 struct bfd_link_info *link_info;
2938 struct bfd_link_order *link_order;
2939 bfd_byte *data;
1049f94e 2940 bfd_boolean relocatable;
252b5132
RH		 2941 asymbol **symbols;
2942{
2943 asection *input_section = link_order->u.indirect.section;
2944 bfd *input_bfd = input_section->owner;
2945 asection **sections = NULL;
2946 struct internal_reloc *internal_relocs = NULL;
2947 struct internal_syment *internal_syms = NULL;
2948
2949 /* We only need to handle the case of relaxing, or of having a
2950 particular set of section contents, specially. */
1049f94e 2951 if (relocatable
252b5132
RH		 2952 || coff_section_data (input_bfd, input_section) == NULL
2953 || coff_section_data (input_bfd, input_section)->contents == NULL)
2954 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2955 link_order, data,
1049f94e 2956 relocatable,
252b5132
RH		 2957 symbols);
2958
2959 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
eea6121a 2960 (size_t) input_section->size);
252b5132
RH		 2961
2962 if ((input_section->flags & SEC_RELOC) != 0
2963 && input_section->reloc_count > 0)
2964 {
2965 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2966 bfd_byte *esym, *esymend;
2967 struct internal_syment *isymp;
2968 asection **secpp;
dc810e39 2969 bfd_size_type amt;
252b5132
RH		 2970
2971 if (! _bfd_coff_get_external_symbols (input_bfd))
2972 goto error_return;
2973
2974 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6
AM		 2975 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
2976 FALSE, (struct internal_reloc *) NULL));
252b5132
RH		 2977 if (internal_relocs == NULL)
2978 goto error_return;
2979
dc810e39
AM		 2980 amt = obj_raw_syment_count (input_bfd);
2981 amt *= sizeof (struct internal_syment);
2982 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 2983 if (internal_syms == NULL)
2984 goto error_return;
2985
dc810e39
AM		 2986 amt = obj_raw_syment_count (input_bfd);
2987 amt *= sizeof (asection *);
2988 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 2989 if (sections == NULL)
2990 goto error_return;
2991
2992 isymp = internal_syms;
2993 secpp = sections;
2994 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2995 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2996 while (esym < esymend)
2997 {
2998 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
2999
3000 if (isymp->n_scnum != 0)
3001 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
3002 else
3003 {
3004 if (isymp->n_value == 0)
3005 *secpp = bfd_und_section_ptr;
3006 else
3007 *secpp = bfd_com_section_ptr;
3008 }
3009
3010 esym += (isymp->n_numaux + 1) * symesz;
3011 secpp += isymp->n_numaux + 1;
3012 isymp += isymp->n_numaux + 1;
3013 }
3014
3015 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3016 input_section, data, internal_relocs,
3017 internal_syms, sections))
3018 goto error_return;
3019
3020 free (sections);
3021 sections = NULL;
3022 free (internal_syms);
3023 internal_syms = NULL;
3024 free (internal_relocs);
3025 internal_relocs = NULL;
3026 }
3027
3028 return data;
3029
3030 error_return:
3031 if (internal_relocs != NULL)
3032 free (internal_relocs);
3033 if (internal_syms != NULL)
3034 free (internal_syms);
3035 if (sections != NULL)
3036 free (sections);
3037 return NULL;
3038}
3039
3040/* The target vectors. */
3041
17505c5c 3042#ifndef TARGET_SHL_SYM
3fa78519 3043CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3044#endif
252b5132 3045
c3c89269
NC		 3046#ifdef TARGET_SHL_SYM
3047#define TARGET_SYM TARGET_SHL_SYM
3048#else
3049#define TARGET_SYM shlcoff_vec
3050#endif
cbfe05c4 3051
c3c89269
NC		 3052#ifndef TARGET_SHL_NAME
3053#define TARGET_SHL_NAME "coff-shl"
3054#endif
252b5132 3055
17505c5c
NC		 3056#ifdef COFF_WITH_PE
3057CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3058 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
17505c5c 3059#else
86033394 3060CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3061 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3062#endif
86033394 3063
17505c5c 3064#ifndef TARGET_SHL_SYM
f4ffd778 3065static const bfd_target * coff_small_object_p PARAMS ((bfd *));
b34976b6 3066static bfd_boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
252b5132
RH		 3067/* Some people want versions of the SH COFF target which do not align
3068 to 16 byte boundaries. We implement that by adding a couple of new
3069 target vectors. These are just like the ones above, but they
3070 change the default section alignment. To generate them in the
3071 assembler, use -small. To use them in the linker, use -b
3072 coff-sh{l}-small and -oformat coff-sh{l}-small.
3073
3074 Yes, this is a horrible hack. A general solution for setting
3075 section alignment in COFF is rather complex. ELF handles this
3076 correctly. */
3077
3078/* Only recognize the small versions if the target was not defaulted.
3079 Otherwise we won't recognize the non default endianness. */
3080
3081static const bfd_target *
3082coff_small_object_p (abfd)
3083 bfd *abfd;
3084{
3085 if (abfd->target_defaulted)
3086 {
3087 bfd_set_error (bfd_error_wrong_format);
3088 return NULL;
3089 }
3090 return coff_object_p (abfd);
3091}
3092
3093/* Set the section alignment for the small versions. */
3094
b34976b6 3095static bfd_boolean
252b5132
RH		 3096coff_small_new_section_hook (abfd, section)
3097 bfd *abfd;
3098 asection *section;
3099{
3100 if (! coff_new_section_hook (abfd, section))
b34976b6 3101 return FALSE;
252b5132
RH		 3102
3103 /* We must align to at least a four byte boundary, because longword
3104 accesses must be on a four byte boundary. */
3105 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3106 section->alignment_power = 2;
3107
b34976b6 3108 return TRUE;
252b5132
RH		 3109}
3110
3111/* This is copied from bfd_coff_std_swap_table so that we can change
3112 the default section alignment power. */
3113
3114static const bfd_coff_backend_data bfd_coff_small_swap_table =
3115{
3116 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3117 coff_swap_aux_out, coff_swap_sym_out,
3118 coff_swap_lineno_out, coff_swap_reloc_out,
3119 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3120 coff_swap_scnhdr_out,
692b7d62 3121 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132 3122#ifdef COFF_LONG_FILENAMES
b34976b6 3123 TRUE,
252b5132 3124#else
b34976b6 3125 FALSE,
252b5132
RH		 3126#endif
3127#ifdef COFF_LONG_SECTION_NAMES
b34976b6 3128 TRUE,
252b5132 3129#else
b34976b6 3130 FALSE,
252b5132
RH		 3131#endif
3132 2,
ecefdb58 3133#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
b34976b6 3134 TRUE,
ecefdb58 3135#else
b34976b6 3136 FALSE,
ecefdb58
CP		 3137#endif
3138#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3139 4,
3140#else
3141 2,
3142#endif
252b5132
RH		 3143 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3144 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3145 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3146 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3147 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3148 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3149 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3150 coff_adjust_symndx, coff_link_add_one_symbol,
3151 coff_link_output_has_begun, coff_final_link_postscript
3152};
3153
3154#define coff_small_close_and_cleanup \
3155 coff_close_and_cleanup
3156#define coff_small_bfd_free_cached_info \
3157 coff_bfd_free_cached_info
3158#define coff_small_get_section_contents \
3159 coff_get_section_contents
3160#define coff_small_get_section_contents_in_window \
3161 coff_get_section_contents_in_window
3162
c3c89269
NC		 3163extern const bfd_target shlcoff_small_vec;
3164
252b5132
RH		 3165const bfd_target shcoff_small_vec =
3166{
3167 "coff-sh-small", /* name */
3168 bfd_target_coff_flavour,
3169 BFD_ENDIAN_BIG, /* data byte order is big */
3170 BFD_ENDIAN_BIG, /* header byte order is big */
3171
3172 (HAS_RELOC | EXEC_P | /* object flags */
3173 HAS_LINENO | HAS_DEBUG |
3174 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3175
3176 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3177 '_', /* leading symbol underscore */
3178 '/', /* ar_pad_char */
3179 15, /* ar_max_namelen */
3180 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3181 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3182 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3183 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3184 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3185 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3186
3187 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3188 bfd_generic_archive_p, _bfd_dummy_target},
3189 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3190 bfd_false},
3191 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3192 _bfd_write_archive_contents, bfd_false},
3193
3194 BFD_JUMP_TABLE_GENERIC (coff_small),
3195 BFD_JUMP_TABLE_COPY (coff),
3196 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3197 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3198 BFD_JUMP_TABLE_SYMBOLS (coff),
3199 BFD_JUMP_TABLE_RELOCS (coff),
3200 BFD_JUMP_TABLE_WRITE (coff),
3201 BFD_JUMP_TABLE_LINK (coff),
3202 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3203
c3c89269 3204 & shlcoff_small_vec,
cbfe05c4 3205
252b5132
RH		 3206 (PTR) &bfd_coff_small_swap_table
3207};
3208
3209const bfd_target shlcoff_small_vec =
3210{
3211 "coff-shl-small", /* name */
3212 bfd_target_coff_flavour,
3213 BFD_ENDIAN_LITTLE, /* data byte order is little */
3214 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3215
3216 (HAS_RELOC | EXEC_P | /* object flags */
3217 HAS_LINENO | HAS_DEBUG |
3218 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3219
3220 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3221 '_', /* leading symbol underscore */
3222 '/', /* ar_pad_char */
3223 15, /* ar_max_namelen */
3224 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3225 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3226 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3227 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3228 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3229 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3230
3231 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
cbfe05c4 3232 bfd_generic_archive_p, _bfd_dummy_target},
252b5132
RH		 3233 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3234 bfd_false},
3235 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3236 _bfd_write_archive_contents, bfd_false},
3237
3238 BFD_JUMP_TABLE_GENERIC (coff_small),
3239 BFD_JUMP_TABLE_COPY (coff),
3240 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3241 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3242 BFD_JUMP_TABLE_SYMBOLS (coff),
3243 BFD_JUMP_TABLE_RELOCS (coff),
3244 BFD_JUMP_TABLE_WRITE (coff),
3245 BFD_JUMP_TABLE_LINK (coff),
3246 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3247
c3c89269 3248 & shcoff_small_vec,
cbfe05c4 3249
252b5132
RH		 3250 (PTR) &bfd_coff_small_swap_table
3251};
17505c5c 3252#endif
Empty description
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