]> Git Repo - binutils.git/blame - opcodes/fr30-desc.h
projects / binutils.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* som.c (som_decode_symclass): Recognize weak symbols.
[binutils.git] / opcodes / fr30-desc.h
CommitLineData
252b5132
RH		 1/* CPU data header for fr30.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#ifndef FR30_CPU_H
26#define FR30_CPU_H
27
28#define CGEN_ARCH fr30
29
30/* Given symbol S, return fr30_cgen_<S>. */
31#define CGEN_SYM(s) CONCAT3 (fr30,_cgen_,s)
32
33/* Selected cpu families. */
34#define HAVE_CPU_FR30BF
35
36#define CGEN_INSN_LSB0_P 0
37
eb1b03df
DE		 38/* Minimum size of any insn (in bytes). */
39#define CGEN_MIN_INSN_SIZE 2
40
252b5132
RH		 41/* Maximum size of any insn (in bytes). */
42#define CGEN_MAX_INSN_SIZE 6
43
44#define CGEN_INT_INSN_P 0
45
46/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
47
48/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
49 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
50 we can't hash on everything up to the space. */
51#define CGEN_MNEMONIC_OPERANDS
1fa60b5d 52
252b5132
RH		 53/* Maximum number of operands any insn or macro-insn has. */
54#define CGEN_MAX_INSN_OPERANDS 16
55
56/* Maximum number of fields in an instruction. */
57#define CGEN_MAX_IFMT_OPERANDS 7
58
59/* Enums. */
60
61/* Enum declaration for insn op1 enums. */
62typedef enum insn_op1 {
63 OP1_0, OP1_1, OP1_2, OP1_3
64 , OP1_4, OP1_5, OP1_6, OP1_7
65 , OP1_8, OP1_9, OP1_A, OP1_B
66 , OP1_C, OP1_D, OP1_E, OP1_F
67} INSN_OP1;
68
69/* Enum declaration for insn op2 enums. */
70typedef enum insn_op2 {
71 OP2_0, OP2_1, OP2_2, OP2_3
72 , OP2_4, OP2_5, OP2_6, OP2_7
73 , OP2_8, OP2_9, OP2_A, OP2_B
74 , OP2_C, OP2_D, OP2_E, OP2_F
75} INSN_OP2;
76
77/* Enum declaration for insn op3 enums. */
78typedef enum insn_op3 {
79 OP3_0, OP3_1, OP3_2, OP3_3
80 , OP3_4, OP3_5, OP3_6, OP3_7
81 , OP3_8, OP3_9, OP3_A, OP3_B
82 , OP3_C, OP3_D, OP3_E, OP3_F
83} INSN_OP3;
84
85/* Enum declaration for insn op4 enums. */
86typedef enum insn_op4 {
87 OP4_0
88} INSN_OP4;
89
90/* Enum declaration for insn op5 enums. */
91typedef enum insn_op5 {
92 OP5_0, OP5_1
93} INSN_OP5;
94
95/* Enum declaration for insn cc enums. */
96typedef enum insn_cc {
97 CC_RA, CC_NO, CC_EQ, CC_NE
98 , CC_C, CC_NC, CC_N, CC_P
99 , CC_V, CC_NV, CC_LT, CC_GE
100 , CC_LE, CC_GT, CC_LS, CC_HI
101} INSN_CC;
102
103/* Enum declaration for . */
104typedef enum gr_names {
105 H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
106 , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
107 , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
108 , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
109 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
110} GR_NAMES;
111
112/* Enum declaration for . */
113typedef enum cr_names {
114 H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
115 , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
116 , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
117 , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
118} CR_NAMES;
119
120/* Enum declaration for . */
121typedef enum dr_names {
122 H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
123 , H_DR_MDH, H_DR_MDL
124} DR_NAMES;
125
126/* Attributes. */
127
128/* Enum declaration for machine type selection. */
129typedef enum mach_attr {
130 MACH_BASE, MACH_FR30, MACH_MAX
131} MACH_ATTR;
132
133/* Enum declaration for instruction set selection. */
134typedef enum isa_attr {
135 ISA_FR30, ISA_MAX
136} ISA_ATTR;
137
138/* Number of architecture variants. */
139#define MAX_ISAS 1
140#define MAX_MACHS ((int) MACH_MAX)
141
142/* Ifield support. */
143
144extern const struct cgen_ifld fr30_cgen_ifld_table[];
145
146/* Ifield attribute indices. */
147
148/* Enum declaration for cgen_ifld attrs. */
149typedef enum cgen_ifld_attr {
150 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
151 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
152 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
153} CGEN_IFLD_ATTR;
154
155/* Number of non-boolean elements in cgen_ifld_attr. */
156#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
157
158/* Enum declaration for fr30 ifield types. */
159typedef enum ifield_type {
160 FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3
161 , FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC
162 , FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2
163 , FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI
164 , FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4
165 , FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16
166 , FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8
167 , FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10
168 , FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10
169 , FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST, FR30_F_REGLIST_HI_LD
170 , FR30_F_REGLIST_LOW_LD, FR30_F_MAX
171} IFIELD_TYPE;
172
173#define MAX_IFLD ((int) FR30_F_MAX)
174
175/* Hardware attribute indices. */
176
177/* Enum declaration for cgen_hw attrs. */
178typedef enum cgen_hw_attr {
179 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
180 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
181} CGEN_HW_ATTR;
182
183/* Number of non-boolean elements in cgen_hw_attr. */
184#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
185
186/* Enum declaration for fr30 hardware types. */
187typedef enum cgen_hw_type {
188 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
189 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
190 , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
191 , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
192 , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
193 , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
194 , HW_H_ILM, HW_MAX
195} CGEN_HW_TYPE;
196
197#define MAX_HW ((int) HW_MAX)
198
199/* Operand attribute indices. */
200
201/* Enum declaration for cgen_operand attrs. */
202typedef enum cgen_operand_attr {
203 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
204 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
205 , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
206 , CGEN_OPERAND_END_NBOOLS
207} CGEN_OPERAND_ATTR;
208
209/* Number of non-boolean elements in cgen_operand_attr. */
210#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
211
212/* Enum declaration for fr30 operand types. */
213typedef enum cgen_operand_type {
214 FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
215 , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
216 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
217 , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
218 , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
219 , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
220 , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
221 , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
222 , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
223 , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
224 , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
225 , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
226 , FR30_OPERAND_ILM, FR30_OPERAND_MAX
227} CGEN_OPERAND_TYPE;
228
229/* Number of operands types. */
230#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
231
232/* Maximum number of operands referenced by any insn. */
233#define MAX_OPERAND_INSTANCES 8
234
235/* Insn attribute indices. */
236
237/* Enum declaration for cgen_insn attrs. */
238typedef enum cgen_insn_attr {
239 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
240 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
241 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
242 , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
243} CGEN_INSN_ATTR;
244
245/* Number of non-boolean elements in cgen_insn_attr. */
246#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
247
248/* cgen.h uses things we just defined. */
249#include "opcode/cgen.h"
250
251/* Attributes. */
252extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[];
253extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[];
254extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
255extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
256
257/* Hardware decls. */
258
259extern CGEN_KEYWORD fr30_cgen_opval_gr_names;
260extern CGEN_KEYWORD fr30_cgen_opval_cr_names;
261extern CGEN_KEYWORD fr30_cgen_opval_dr_names;
262extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
263extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
264extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
265extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
266
267
268
269
270#endif /* FR30_CPU_H */
Empty description
This page took 0.102107 seconds and 4 git commands to generate.