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* emultempl/spu_ovl.S: Don't trash lr on tail call from one
[binutils.git] / bfd / elf32-m68hc11.c
CommitLineData
60bcf0fa 1/* Motorola 68HC11-specific support for 32-bit ELF
157090f7 2 Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
eea6121a 3 Free Software Foundation, Inc.
dae78fb0 4 Contributed by Stephane Carrez ([email protected])
60bcf0fa
NC		 5 (Heavily copied from the D10V port by Martin Hunt ([email protected]))
6
7This file is part of BFD, the Binary File Descriptor library.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2 of the License, or
12(at your option) any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program; if not, write to the Free Software
3e110533 21Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
60bcf0fa 22
60bcf0fa 23#include "sysdep.h"
3db64b00 24#include "bfd.h"
1fd03b5a 25#include "bfdlink.h"
60bcf0fa
NC		 26#include "libbfd.h"
27#include "elf-bfd.h"
3a65329d 28#include "elf32-m68hc1x.h"
60bcf0fa 29#include "elf/m68hc11.h"
3a65329d 30#include "opcode/m68hc11.h"
60bcf0fa 31
3a65329d 32/* Relocation functions. */
60bcf0fa 33static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
0a6a3ebe 34 (bfd *, bfd_reloc_code_real_type);
60bcf0fa 35static void m68hc11_info_to_howto_rel
0a6a3ebe 36 (bfd *, arelent *, Elf_Internal_Rela *);
60bcf0fa 37
3a65329d
SC		 38/* Trampoline generation. */
39static bfd_boolean m68hc11_elf_size_one_stub
0a6a3ebe 40 (struct bfd_hash_entry *gen_entry, void *in_arg);
3a65329d 41static bfd_boolean m68hc11_elf_build_one_stub
0a6a3ebe 42 (struct bfd_hash_entry *gen_entry, void *in_arg);
3a65329d 43static struct bfd_link_hash_table* m68hc11_elf_bfd_link_hash_table_create
0a6a3ebe 44 (bfd* abfd);
3a65329d
SC		 45
46/* Linker relaxation. */
b34976b6 47static bfd_boolean m68hc11_elf_relax_section
0a6a3ebe 48 (bfd *, asection *, struct bfd_link_info *, bfd_boolean *);
1fd03b5a 49static void m68hc11_elf_relax_delete_bytes
0a6a3ebe 50 (bfd *, asection *, bfd_vma, int);
1fd03b5a 51static void m68hc11_relax_group
0a6a3ebe
SC		 52 (bfd *, asection *, bfd_byte *, unsigned, unsigned long, unsigned long);
53static int compare_reloc (const void *, const void *);
1fd03b5a 54
60bcf0fa 55/* Use REL instead of RELA to save space */
acf8aed4 56#define USE_REL 1
60bcf0fa 57
3a65329d
SC		 58/* The Motorola 68HC11 microcontroller only addresses 64Kb but we also
59 support a memory bank switching mechanism similar to 68HC12.
60bcf0fa 60 We must handle 8 and 16-bit relocations. The 32-bit relocation
3a65329d
SC		 61 are used for debugging sections (DWARF2) to represent a virtual
62 address.
60bcf0fa
NC		 63 The 3-bit and 16-bit PC rel relocation is only used by 68HC12. */
64static reloc_howto_type elf_m68hc11_howto_table[] = {
65 /* This reloc does nothing. */
66 HOWTO (R_M68HC11_NONE, /* type */
67 0, /* rightshift */
68 2, /* size (0 = byte, 1 = short, 2 = long) */
69 32, /* bitsize */
b34976b6 70 FALSE, /* pc_relative */
60bcf0fa 71 0, /* bitpos */
7a897be4 72 complain_overflow_dont,/* complain_on_overflow */
60bcf0fa
NC		 73 bfd_elf_generic_reloc, /* special_function */
74 "R_M68HC11_NONE", /* name */
b34976b6 75 FALSE, /* partial_inplace */
60bcf0fa
NC		 76 0, /* src_mask */
77 0, /* dst_mask */
b34976b6 78 FALSE), /* pcrel_offset */
60bcf0fa
NC		 79
80 /* A 8 bit absolute relocation */
81 HOWTO (R_M68HC11_8, /* type */
82 0, /* rightshift */
83 0, /* size (0 = byte, 1 = short, 2 = long) */
84 8, /* bitsize */
b34976b6 85 FALSE, /* pc_relative */
60bcf0fa
NC		 86 0, /* bitpos */
87 complain_overflow_bitfield, /* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_M68HC11_8", /* name */
b34976b6 90 FALSE, /* partial_inplace */
60bcf0fa
NC		 91 0x00ff, /* src_mask */
92 0x00ff, /* dst_mask */
b34976b6 93 FALSE), /* pcrel_offset */
60bcf0fa
NC		 94
95 /* A 8 bit absolute relocation (upper address) */
96 HOWTO (R_M68HC11_HI8, /* type */
97 8, /* rightshift */
98 0, /* size (0 = byte, 1 = short, 2 = long) */
99 8, /* bitsize */
b34976b6 100 FALSE, /* pc_relative */
60bcf0fa
NC		 101 0, /* bitpos */
102 complain_overflow_bitfield, /* complain_on_overflow */
103 bfd_elf_generic_reloc, /* special_function */
104 "R_M68HC11_HI8", /* name */
b34976b6 105 FALSE, /* partial_inplace */
60bcf0fa
NC		 106 0x00ff, /* src_mask */
107 0x00ff, /* dst_mask */
b34976b6 108 FALSE), /* pcrel_offset */
60bcf0fa
NC		 109
110 /* A 8 bit absolute relocation (upper address) */
111 HOWTO (R_M68HC11_LO8, /* type */
112 0, /* rightshift */
113 0, /* size (0 = byte, 1 = short, 2 = long) */
114 8, /* bitsize */
b34976b6 115 FALSE, /* pc_relative */
60bcf0fa
NC		 116 0, /* bitpos */
117 complain_overflow_dont, /* complain_on_overflow */
118 bfd_elf_generic_reloc, /* special_function */
119 "R_M68HC11_LO8", /* name */
b34976b6 120 FALSE, /* partial_inplace */
60bcf0fa
NC		 121 0x00ff, /* src_mask */
122 0x00ff, /* dst_mask */
b34976b6 123 FALSE), /* pcrel_offset */
60bcf0fa
NC		 124
125 /* A 8 bit PC-rel relocation */
126 HOWTO (R_M68HC11_PCREL_8, /* type */
127 0, /* rightshift */
128 0, /* size (0 = byte, 1 = short, 2 = long) */
129 8, /* bitsize */
b34976b6 130 TRUE, /* pc_relative */
60bcf0fa
NC		 131 0, /* bitpos */
132 complain_overflow_bitfield, /* complain_on_overflow */
133 bfd_elf_generic_reloc, /* special_function */
134 "R_M68HC11_PCREL_8", /* name */
b34976b6 135 FALSE, /* partial_inplace */
dae78fb0 136 0x00ff, /* src_mask */
60bcf0fa 137 0x00ff, /* dst_mask */
196486be 138 TRUE), /* pcrel_offset */
60bcf0fa
NC		 139
140 /* A 16 bit absolute relocation */
141 HOWTO (R_M68HC11_16, /* type */
142 0, /* rightshift */
143 1, /* size (0 = byte, 1 = short, 2 = long) */
144 16, /* bitsize */
b34976b6 145 FALSE, /* pc_relative */
60bcf0fa
NC		 146 0, /* bitpos */
147 complain_overflow_dont /*bitfield */ , /* complain_on_overflow */
148 bfd_elf_generic_reloc, /* special_function */
149 "R_M68HC11_16", /* name */
b34976b6 150 FALSE, /* partial_inplace */
60bcf0fa
NC		 151 0xffff, /* src_mask */
152 0xffff, /* dst_mask */
b34976b6 153 FALSE), /* pcrel_offset */
60bcf0fa
NC		 154
155 /* A 32 bit absolute relocation. This one is never used for the
156 code relocation. It's used by gas for -gstabs generation. */
157 HOWTO (R_M68HC11_32, /* type */
158 0, /* rightshift */
159 2, /* size (0 = byte, 1 = short, 2 = long) */
160 32, /* bitsize */
b34976b6 161 FALSE, /* pc_relative */
60bcf0fa
NC		 162 0, /* bitpos */
163 complain_overflow_bitfield, /* complain_on_overflow */
164 bfd_elf_generic_reloc, /* special_function */
165 "R_M68HC11_32", /* name */
b34976b6 166 FALSE, /* partial_inplace */
60bcf0fa
NC		 167 0xffffffff, /* src_mask */
168 0xffffffff, /* dst_mask */
b34976b6 169 FALSE), /* pcrel_offset */
60bcf0fa
NC		 170
171 /* A 3 bit absolute relocation */
172 HOWTO (R_M68HC11_3B, /* type */
173 0, /* rightshift */
174 0, /* size (0 = byte, 1 = short, 2 = long) */
175 3, /* bitsize */
b34976b6 176 FALSE, /* pc_relative */
60bcf0fa
NC		 177 0, /* bitpos */
178 complain_overflow_bitfield, /* complain_on_overflow */
179 bfd_elf_generic_reloc, /* special_function */
180 "R_M68HC11_4B", /* name */
b34976b6 181 FALSE, /* partial_inplace */
60bcf0fa
NC		 182 0x003, /* src_mask */
183 0x003, /* dst_mask */
b34976b6 184 FALSE), /* pcrel_offset */
60bcf0fa
NC		 185
186 /* A 16 bit PC-rel relocation */
187 HOWTO (R_M68HC11_PCREL_16, /* type */
188 0, /* rightshift */
189 1, /* size (0 = byte, 1 = short, 2 = long) */
190 16, /* bitsize */
b34976b6 191 TRUE, /* pc_relative */
60bcf0fa
NC		 192 0, /* bitpos */
193 complain_overflow_dont, /* complain_on_overflow */
194 bfd_elf_generic_reloc, /* special_function */
195 "R_M68HC11_PCREL_16", /* name */
b34976b6 196 FALSE, /* partial_inplace */
dae78fb0 197 0xffff, /* src_mask */
60bcf0fa 198 0xffff, /* dst_mask */
196486be 199 TRUE), /* pcrel_offset */
60bcf0fa
NC		 200
201 /* GNU extension to record C++ vtable hierarchy */
202 HOWTO (R_M68HC11_GNU_VTINHERIT, /* type */
203 0, /* rightshift */
204 1, /* size (0 = byte, 1 = short, 2 = long) */
205 0, /* bitsize */
b34976b6 206 FALSE, /* pc_relative */
60bcf0fa
NC		 207 0, /* bitpos */
208 complain_overflow_dont, /* complain_on_overflow */
209 NULL, /* special_function */
210 "R_M68HC11_GNU_VTINHERIT", /* name */
b34976b6 211 FALSE, /* partial_inplace */
60bcf0fa
NC		 212 0, /* src_mask */
213 0, /* dst_mask */
b34976b6 214 FALSE), /* pcrel_offset */
60bcf0fa
NC		 215
216 /* GNU extension to record C++ vtable member usage */
217 HOWTO (R_M68HC11_GNU_VTENTRY, /* type */
218 0, /* rightshift */
219 1, /* size (0 = byte, 1 = short, 2 = long) */
220 0, /* bitsize */
b34976b6 221 FALSE, /* pc_relative */
60bcf0fa
NC		 222 0, /* bitpos */
223 complain_overflow_dont, /* complain_on_overflow */
224 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
225 "R_M68HC11_GNU_VTENTRY", /* name */
b34976b6 226 FALSE, /* partial_inplace */
60bcf0fa
NC		 227 0, /* src_mask */
228 0, /* dst_mask */
b34976b6 229 FALSE), /* pcrel_offset */
dae78fb0 230
7a897be4
SC		 231 /* A 24 bit relocation */
232 HOWTO (R_M68HC11_24, /* type */
233 0, /* rightshift */
234 1, /* size (0 = byte, 1 = short, 2 = long) */
235 24, /* bitsize */
b34976b6 236 FALSE, /* pc_relative */
7a897be4
SC		 237 0, /* bitpos */
238 complain_overflow_bitfield, /* complain_on_overflow */
239 bfd_elf_generic_reloc, /* special_function */
240 "R_M68HC11_24", /* name */
b34976b6 241 FALSE, /* partial_inplace */
196486be
SC		 242 0xffffff, /* src_mask */
243 0xffffff, /* dst_mask */
b34976b6
AM		 244 FALSE), /* pcrel_offset */
245
7a897be4
SC		 246 /* A 16-bit low relocation */
247 HOWTO (R_M68HC11_LO16, /* type */
248 0, /* rightshift */
249 1, /* size (0 = byte, 1 = short, 2 = long) */
250 16, /* bitsize */
b34976b6 251 FALSE, /* pc_relative */
7a897be4
SC		 252 0, /* bitpos */
253 complain_overflow_bitfield, /* complain_on_overflow */
254 bfd_elf_generic_reloc, /* special_function */
255 "R_M68HC11_LO16", /* name */
b34976b6 256 FALSE, /* partial_inplace */
7a897be4
SC		 257 0xffff, /* src_mask */
258 0xffff, /* dst_mask */
b34976b6 259 FALSE), /* pcrel_offset */
7a897be4
SC		 260
261 /* A page relocation */
262 HOWTO (R_M68HC11_PAGE, /* type */
263 0, /* rightshift */
264 0, /* size (0 = byte, 1 = short, 2 = long) */
265 8, /* bitsize */
b34976b6 266 FALSE, /* pc_relative */
7a897be4
SC		 267 0, /* bitpos */
268 complain_overflow_bitfield, /* complain_on_overflow */
269 bfd_elf_generic_reloc, /* special_function */
270 "R_M68HC11_PAGE", /* name */
b34976b6 271 FALSE, /* partial_inplace */
7a897be4
SC		 272 0x00ff, /* src_mask */
273 0x00ff, /* dst_mask */
b34976b6 274 FALSE), /* pcrel_offset */
7a897be4 275
dae78fb0
SC		 276 EMPTY_HOWTO (14),
277 EMPTY_HOWTO (15),
278 EMPTY_HOWTO (16),
279 EMPTY_HOWTO (17),
280 EMPTY_HOWTO (18),
281 EMPTY_HOWTO (19),
b34976b6 282
dae78fb0
SC		 283 /* Mark beginning of a jump instruction (any form). */
284 HOWTO (R_M68HC11_RL_JUMP, /* type */
285 0, /* rightshift */
286 1, /* size (0 = byte, 1 = short, 2 = long) */
287 0, /* bitsize */
b34976b6 288 FALSE, /* pc_relative */
dae78fb0
SC		 289 0, /* bitpos */
290 complain_overflow_dont, /* complain_on_overflow */
291 m68hc11_elf_ignore_reloc, /* special_function */
292 "R_M68HC11_RL_JUMP", /* name */
b34976b6 293 TRUE, /* partial_inplace */
dae78fb0
SC		 294 0, /* src_mask */
295 0, /* dst_mask */
b34976b6 296 TRUE), /* pcrel_offset */
dae78fb0
SC		 297
298 /* Mark beginning of Gcc relaxation group instruction. */
299 HOWTO (R_M68HC11_RL_GROUP, /* type */
300 0, /* rightshift */
301 1, /* size (0 = byte, 1 = short, 2 = long) */
302 0, /* bitsize */
b34976b6 303 FALSE, /* pc_relative */
dae78fb0
SC		 304 0, /* bitpos */
305 complain_overflow_dont, /* complain_on_overflow */
306 m68hc11_elf_ignore_reloc, /* special_function */
307 "R_M68HC11_RL_GROUP", /* name */
b34976b6 308 TRUE, /* partial_inplace */
dae78fb0
SC		 309 0, /* src_mask */
310 0, /* dst_mask */
b34976b6 311 TRUE), /* pcrel_offset */
60bcf0fa
NC		 312};
313
314/* Map BFD reloc types to M68HC11 ELF reloc types. */
315
316struct m68hc11_reloc_map
317{
318 bfd_reloc_code_real_type bfd_reloc_val;
319 unsigned char elf_reloc_val;
320};
321
322static const struct m68hc11_reloc_map m68hc11_reloc_map[] = {
323 {BFD_RELOC_NONE, R_M68HC11_NONE,},
324 {BFD_RELOC_8, R_M68HC11_8},
325 {BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8},
326 {BFD_RELOC_M68HC11_LO8, R_M68HC11_LO8},
327 {BFD_RELOC_8_PCREL, R_M68HC11_PCREL_8},
328 {BFD_RELOC_16_PCREL, R_M68HC11_PCREL_16},
329 {BFD_RELOC_16, R_M68HC11_16},
330 {BFD_RELOC_32, R_M68HC11_32},
331 {BFD_RELOC_M68HC11_3B, R_M68HC11_3B},
332
60bcf0fa
NC		 333 {BFD_RELOC_VTABLE_INHERIT, R_M68HC11_GNU_VTINHERIT},
334 {BFD_RELOC_VTABLE_ENTRY, R_M68HC11_GNU_VTENTRY},
dae78fb0 335
7a897be4
SC		 336 {BFD_RELOC_M68HC11_LO16, R_M68HC11_LO16},
337 {BFD_RELOC_M68HC11_PAGE, R_M68HC11_PAGE},
338 {BFD_RELOC_M68HC11_24, R_M68HC11_24},
339
dae78fb0
SC		 340 {BFD_RELOC_M68HC11_RL_JUMP, R_M68HC11_RL_JUMP},
341 {BFD_RELOC_M68HC11_RL_GROUP, R_M68HC11_RL_GROUP},
60bcf0fa
NC		 342};
343
344static reloc_howto_type *
0a6a3ebe
SC		 345bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
346 bfd_reloc_code_real_type code)
60bcf0fa
NC		 347{
348 unsigned int i;
349
350 for (i = 0;
351 i < sizeof (m68hc11_reloc_map) / sizeof (struct m68hc11_reloc_map);
352 i++)
353 {
354 if (m68hc11_reloc_map[i].bfd_reloc_val == code)
355 return &elf_m68hc11_howto_table[m68hc11_reloc_map[i].elf_reloc_val];
356 }
357
358 return NULL;
359}
360
157090f7
AM		 361static reloc_howto_type *
362bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
363 const char *r_name)
364{
365 unsigned int i;
366
367 for (i = 0;
368 i < (sizeof (elf_m68hc11_howto_table)
369 / sizeof (elf_m68hc11_howto_table[0]));
370 i++)
371 if (elf_m68hc11_howto_table[i].name != NULL
372 && strcasecmp (elf_m68hc11_howto_table[i].name, r_name) == 0)
373 return &elf_m68hc11_howto_table[i];
374
375 return NULL;
376}
377
60bcf0fa
NC		 378/* Set the howto pointer for an M68HC11 ELF reloc. */
379
380static void
0a6a3ebe
SC		 381m68hc11_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED,
382 arelent *cache_ptr, Elf_Internal_Rela *dst)
60bcf0fa
NC		 383{
384 unsigned int r_type;
385
386 r_type = ELF32_R_TYPE (dst->r_info);
387 BFD_ASSERT (r_type < (unsigned int) R_M68HC11_max);
388 cache_ptr->howto = &elf_m68hc11_howto_table[r_type];
389}
390
3a65329d
SC		 391\f
392/* Far trampoline generation. */
9b701e44 393
3a65329d
SC		 394/* Build a 68HC11 trampoline stub. */
395static bfd_boolean
0a6a3ebe 396m68hc11_elf_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
3a65329d
SC		 397{
398 struct elf32_m68hc11_stub_hash_entry *stub_entry;
399 struct bfd_link_info *info;
400 struct m68hc11_elf_link_hash_table *htab;
401 asection *stub_sec;
402 bfd *stub_bfd;
403 bfd_byte *loc;
404 bfd_vma sym_value, phys_page, phys_addr;
405
406 /* Massage our args to the form they really have. */
407 stub_entry = (struct elf32_m68hc11_stub_hash_entry *) gen_entry;
408 info = (struct bfd_link_info *) in_arg;
409
410 htab = m68hc11_elf_hash_table (info);
411
412 stub_sec = stub_entry->stub_sec;
413
414 /* Make a note of the offset within the stubs for this entry. */
eea6121a
AM		 415 stub_entry->stub_offset = stub_sec->size;
416 stub_sec->size += 10;
3a65329d
SC		 417 loc = stub_sec->contents + stub_entry->stub_offset;
418
419 stub_bfd = stub_sec->owner;
420
421 /* Create the trampoline call stub:
422
423 pshb
424 ldab #%page(symbol)
425 ldy #%addr(symbol)
426 jmp __trampoline
427
428 */
429 sym_value = (stub_entry->target_value
430 + stub_entry->target_section->output_offset
431 + stub_entry->target_section->output_section->vma);
432 phys_addr = m68hc11_phys_addr (&htab->pinfo, sym_value);
433 phys_page = m68hc11_phys_page (&htab->pinfo, sym_value);
434
435 /* pshb; ldab #%page(sym) */
436 bfd_put_8 (stub_bfd, 0x37, loc);
437 bfd_put_8 (stub_bfd, 0xC6, loc + 1);
438 bfd_put_8 (stub_bfd, phys_page, loc + 2);
439 loc += 3;
440
441 /* ldy #%addr(sym) */
442 bfd_put_8 (stub_bfd, 0x18, loc);
443 bfd_put_8 (stub_bfd, 0xCE, loc + 1);
444 bfd_put_16 (stub_bfd, phys_addr, loc + 2);
445 loc += 4;
446
447 /* jmp __trampoline */
448 bfd_put_8 (stub_bfd, 0x7E, loc);
449 bfd_put_16 (stub_bfd, htab->pinfo.trampoline_addr, loc + 1);
56780f18 450
3a65329d 451 return TRUE;
9b701e44
SC		 452}
453
3a65329d
SC		 454/* As above, but don't actually build the stub. Just bump offset so
455 we know stub section sizes. */
456
b34976b6 457static bfd_boolean
0a6a3ebe
SC		 458m68hc11_elf_size_one_stub (struct bfd_hash_entry *gen_entry,
459 void *in_arg ATTRIBUTE_UNUSED)
9b701e44 460{
3a65329d
SC		 461 struct elf32_m68hc11_stub_hash_entry *stub_entry;
462
463 /* Massage our args to the form they really have. */
464 stub_entry = (struct elf32_m68hc11_stub_hash_entry *) gen_entry;
465
eea6121a 466 stub_entry->stub_sec->size += 10;
b34976b6 467 return TRUE;
9b701e44
SC		 468}
469
3a65329d
SC		 470/* Create a 68HC11 ELF linker hash table. */
471
472static struct bfd_link_hash_table *
0a6a3ebe 473m68hc11_elf_bfd_link_hash_table_create (bfd *abfd)
3a65329d
SC		 474{
475 struct m68hc11_elf_link_hash_table *ret;
476
477 ret = m68hc11_elf_hash_table_create (abfd);
478 if (ret == (struct m68hc11_elf_link_hash_table *) NULL)
479 return NULL;
480
481 ret->size_one_stub = m68hc11_elf_size_one_stub;
482 ret->build_one_stub = m68hc11_elf_build_one_stub;
483
484 return &ret->root.root;
485}
486
196486be
SC		 487\f
488/* 68HC11 Linker Relaxation. */
489
b34976b6 490struct m68hc11_direct_relax
1fd03b5a
SC		 491{
492 const char *name;
493 unsigned char code;
494 unsigned char direct_code;
495} m68hc11_direct_relax_table[] = {
496 { "adca", 0xB9, 0x99 },
497 { "adcb", 0xF9, 0xD9 },
498 { "adda", 0xBB, 0x9B },
499 { "addb", 0xFB, 0xDB },
500 { "addd", 0xF3, 0xD3 },
501 { "anda", 0xB4, 0x94 },
502 { "andb", 0xF4, 0xD4 },
503 { "cmpa", 0xB1, 0x91 },
504 { "cmpb", 0xF1, 0xD1 },
505 { "cpd", 0xB3, 0x93 },
506 { "cpxy", 0xBC, 0x9C },
507/* { "cpy", 0xBC, 0x9C }, */
508 { "eora", 0xB8, 0x98 },
509 { "eorb", 0xF8, 0xD8 },
510 { "jsr", 0xBD, 0x9D },
511 { "ldaa", 0xB6, 0x96 },
512 { "ldab", 0xF6, 0xD6 },
513 { "ldd", 0xFC, 0xDC },
514 { "lds", 0xBE, 0x9E },
515 { "ldxy", 0xFE, 0xDE },
516 /* { "ldy", 0xFE, 0xDE },*/
517 { "oraa", 0xBA, 0x9A },
518 { "orab", 0xFA, 0xDA },
519 { "sbca", 0xB2, 0x92 },
520 { "sbcb", 0xF2, 0xD2 },
521 { "staa", 0xB7, 0x97 },
522 { "stab", 0xF7, 0xD7 },
523 { "std", 0xFD, 0xDD },
524 { "sts", 0xBF, 0x9F },
525 { "stxy", 0xFF, 0xDF },
526 /* { "sty", 0xFF, 0xDF },*/
527 { "suba", 0xB0, 0x90 },
528 { "subb", 0xF0, 0xD0 },
529 { "subd", 0xB3, 0x93 },
530 { 0, 0, 0 }
531};
532
533static struct m68hc11_direct_relax *
534find_relaxable_insn (unsigned char code)
535{
536 int i;
537
538 for (i = 0; m68hc11_direct_relax_table[i].name; i++)
539 if (m68hc11_direct_relax_table[i].code == code)
540 return &m68hc11_direct_relax_table[i];
541
542 return 0;
543}
544
545static int
0a6a3ebe 546compare_reloc (const void *e1, const void *e2)
1fd03b5a
SC		 547{
548 const Elf_Internal_Rela *i1 = (const Elf_Internal_Rela *) e1;
549 const Elf_Internal_Rela *i2 = (const Elf_Internal_Rela *) e2;
550
551 if (i1->r_offset == i2->r_offset)
552 return 0;
553 else
554 return i1->r_offset < i2->r_offset ? -1 : 1;
555}
556
557#define M6811_OP_LDX_IMMEDIATE (0xCE)
558
559static void
0a6a3ebe
SC		 560m68hc11_relax_group (bfd *abfd, asection *sec, bfd_byte *contents,
561 unsigned value, unsigned long offset,
562 unsigned long end_group)
1fd03b5a
SC		 563{
564 unsigned char code;
565 unsigned long start_offset;
566 unsigned long ldx_offset = offset;
567 unsigned long ldx_size;
568 int can_delete_ldx;
569 int relax_ldy = 0;
570
571 /* First instruction of the relax group must be a
572 LDX #value or LDY #value. If this is not the case,
573 ignore the relax group. */
574 code = bfd_get_8 (abfd, contents + offset);
575 if (code == 0x18)
576 {
577 relax_ldy++;
578 offset++;
579 code = bfd_get_8 (abfd, contents + offset);
580 }
581 ldx_size = offset - ldx_offset + 3;
582 offset += 3;
583 if (code != M6811_OP_LDX_IMMEDIATE || offset >= end_group)
584 return;
585
586
587 /* We can remove the LDX/LDY only when all bset/brclr instructions
588 of the relax group have been converted to use direct addressing
589 mode. */
590 can_delete_ldx = 1;
591 while (offset < end_group)
592 {
593 unsigned isize;
594 unsigned new_value;
595 int bset_use_y;
596
597 bset_use_y = 0;
598 start_offset = offset;
599 code = bfd_get_8 (abfd, contents + offset);
600 if (code == 0x18)
601 {
602 bset_use_y++;
603 offset++;
604 code = bfd_get_8 (abfd, contents + offset);
605 }
606
607 /* Check the instruction and translate to use direct addressing mode. */
608 switch (code)
609 {
610 /* bset */
611 case 0x1C:
612 code = 0x14;
613 isize = 3;
614 break;
615
616 /* brclr */
617 case 0x1F:
618 code = 0x13;
619 isize = 4;
620 break;
621
622 /* brset */
623 case 0x1E:
624 code = 0x12;
625 isize = 4;
626 break;
627
628 /* bclr */
629 case 0x1D:
630 code = 0x15;
631 isize = 3;
632 break;
633
634 /* This instruction is not recognized and we are not
635 at end of the relax group. Ignore and don't remove
636 the first LDX (we don't know what it is used for...). */
637 default:
638 return;
639 }
640 new_value = (unsigned) bfd_get_8 (abfd, contents + offset + 1);
641 new_value += value;
642 if ((new_value & 0xff00) == 0 && bset_use_y == relax_ldy)
643 {
644 bfd_put_8 (abfd, code, contents + offset);
645 bfd_put_8 (abfd, new_value, contents + offset + 1);
646 if (start_offset != offset)
647 {
648 m68hc11_elf_relax_delete_bytes (abfd, sec, start_offset,
649 offset - start_offset);
650 end_group--;
651 }
652 }
653 else
654 {
655 can_delete_ldx = 0;
656 }
657 offset = start_offset + isize;
658 }
659 if (can_delete_ldx)
660 {
661 /* Remove the move instruction (3 or 4 bytes win). */
662 m68hc11_elf_relax_delete_bytes (abfd, sec, ldx_offset, ldx_size);
663 }
664}
665
666/* This function handles relaxing for the 68HC11.
667
b34976b6 668
1fd03b5a
SC		 669 and somewhat more difficult to support. */
670
b34976b6 671static bfd_boolean
0a6a3ebe
SC		 672m68hc11_elf_relax_section (bfd *abfd, asection *sec,
673 struct bfd_link_info *link_info, bfd_boolean *again)
1fd03b5a
SC		 674{
675 Elf_Internal_Shdr *symtab_hdr;
676 Elf_Internal_Shdr *shndx_hdr;
677 Elf_Internal_Rela *internal_relocs;
678 Elf_Internal_Rela *free_relocs = NULL;
679 Elf_Internal_Rela *irel, *irelend;
680 bfd_byte *contents = NULL;
681 bfd_byte *free_contents = NULL;
1fd03b5a
SC		 682 Elf32_External_Sym *free_extsyms = NULL;
683 Elf_Internal_Rela *prev_insn_branch = NULL;
684 Elf_Internal_Rela *prev_insn_group = NULL;
685 unsigned insn_group_value = 0;
1f4c5b47 686 Elf_Internal_Sym *isymbuf = NULL;
1fd03b5a
SC		 687
688 /* Assume nothing changes. */
b34976b6 689 *again = FALSE;
1fd03b5a 690
1049f94e 691 /* We don't have to do anything for a relocatable link, if
1fd03b5a
SC		 692 this section does not have relocs, or if this is not a
693 code section. */
1049f94e 694 if (link_info->relocatable
1fd03b5a
SC		 695 || (sec->flags & SEC_RELOC) == 0
696 || sec->reloc_count == 0
697 || (sec->flags & SEC_CODE) == 0)
b34976b6 698 return TRUE;
1fd03b5a 699
1fd03b5a
SC		 700 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
701 shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr;
702
703 /* Get a copy of the native relocations. */
45d6a902 704 internal_relocs = (_bfd_elf_link_read_relocs
1fd03b5a
SC		 705 (abfd, sec, (PTR) NULL, (Elf_Internal_Rela *) NULL,
706 link_info->keep_memory));
707 if (internal_relocs == NULL)
708 goto error_return;
709 if (! link_info->keep_memory)
710 free_relocs = internal_relocs;
711
712 /* Checking for branch relaxation relies on the relocations to
713 be sorted on 'r_offset'. This is not guaranteed so we must sort. */
714 qsort (internal_relocs, sec->reloc_count, sizeof (Elf_Internal_Rela),
715 compare_reloc);
716
717 /* Walk through them looking for relaxing opportunities. */
718 irelend = internal_relocs + sec->reloc_count;
719 for (irel = internal_relocs; irel < irelend; irel++)
720 {
721 bfd_vma symval;
722 bfd_vma value;
1f4c5b47 723 Elf_Internal_Sym *isym;
9b691193 724 asection *sym_sec;
196486be 725 int is_far = 0;
1fd03b5a
SC		 726
727 /* If this isn't something that can be relaxed, then ignore
728 this reloc. */
729 if (ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_16
730 && ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_RL_JUMP
731 && ELF32_R_TYPE (irel->r_info) != (int) R_M68HC11_RL_GROUP)
732 {
733 prev_insn_branch = 0;
734 prev_insn_group = 0;
735 continue;
736 }
737
738 /* Get the section contents if we haven't done so already. */
739 if (contents == NULL)
740 {
741 /* Get cached copy if it exists. */
742 if (elf_section_data (sec)->this_hdr.contents != NULL)
743 contents = elf_section_data (sec)->this_hdr.contents;
744 else
745 {
746 /* Go get them off disk. */
eea6121a 747 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1fd03b5a
SC		 748 goto error_return;
749 }
750 }
751
752 /* Try to eliminate an unconditional 8 bit pc-relative branch
753 which immediately follows a conditional 8 bit pc-relative
754 branch around the unconditional branch.
755
756 original: new:
757 bCC lab1 bCC' lab2
758 bra lab2
759 lab1: lab1:
760
761 This happens when the bCC can't reach lab2 at assembly time,
762 but due to other relaxations it can reach at link time. */
763 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_RL_JUMP)
764 {
765 Elf_Internal_Rela *nrel;
766 unsigned char code;
767 unsigned char roffset;
768
769 prev_insn_branch = 0;
770 prev_insn_group = 0;
b34976b6 771
1fd03b5a 772 /* Do nothing if this reloc is the last byte in the section. */
eea6121a 773 if (irel->r_offset + 2 >= sec->size)
1fd03b5a
SC		 774 continue;
775
776 /* See if the next instruction is an unconditional pc-relative
777 branch, more often than not this test will fail, so we
778 test it first to speed things up. */
779 code = bfd_get_8 (abfd, contents + irel->r_offset + 2);
780 if (code != 0x7e)
781 continue;
782
783 /* Also make sure the next relocation applies to the next
784 instruction and that it's a pc-relative 8 bit branch. */
785 nrel = irel + 1;
786 if (nrel == irelend
787 || irel->r_offset + 3 != nrel->r_offset
788 || ELF32_R_TYPE (nrel->r_info) != (int) R_M68HC11_16)
789 continue;
790
791 /* Make sure our destination immediately follows the
792 unconditional branch. */
793 roffset = bfd_get_8 (abfd, contents + irel->r_offset + 1);
794 if (roffset != 3)
795 continue;
796
797 prev_insn_branch = irel;
798 prev_insn_group = 0;
799 continue;
800 }
801
802 /* Read this BFD's symbols if we haven't done so already. */
1f4c5b47 803 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1fd03b5a 804 {
1f4c5b47
SC		 805 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
806 if (isymbuf == NULL)
807 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
808 symtab_hdr->sh_info, 0,
809 NULL, NULL, NULL);
810 if (isymbuf == NULL)
811 goto error_return;
1fd03b5a
SC		 812 }
813
814 /* Get the value of the symbol referred to by the reloc. */
815 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
816 {
1fd03b5a 817 /* A local symbol. */
1f4c5b47 818 isym = isymbuf + ELF32_R_SYM (irel->r_info);
196486be 819 is_far = isym->st_other & STO_M68HC12_FAR;
1f4c5b47
SC		 820 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
821 symval = (isym->st_value
1fd03b5a
SC		 822 + sym_sec->output_section->vma
823 + sym_sec->output_offset);
824 }
825 else
826 {
827 unsigned long indx;
828 struct elf_link_hash_entry *h;
829
830 /* An external symbol. */
831 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
832 h = elf_sym_hashes (abfd)[indx];
833 BFD_ASSERT (h != NULL);
834 if (h->root.type != bfd_link_hash_defined
835 && h->root.type != bfd_link_hash_defweak)
836 {
837 /* This appears to be a reference to an undefined
838 symbol. Just ignore it--it will be caught by the
839 regular reloc processing. */
840 prev_insn_branch = 0;
841 prev_insn_group = 0;
842 continue;
843 }
844
196486be 845 is_far = h->other & STO_M68HC12_FAR;
9b691193
SC		 846 isym = 0;
847 sym_sec = h->root.u.def.section;
1fd03b5a 848 symval = (h->root.u.def.value
9b691193
SC		 849 + sym_sec->output_section->vma
850 + sym_sec->output_offset);
1fd03b5a
SC		 851 }
852
853 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_RL_GROUP)
854 {
855 prev_insn_branch = 0;
856 prev_insn_group = 0;
b34976b6 857
1fd03b5a 858 /* Do nothing if this reloc is the last byte in the section. */
eea6121a 859 if (irel->r_offset == sec->size)
1fd03b5a
SC		 860 continue;
861
862 prev_insn_group = irel;
1f4c5b47 863 insn_group_value = isym->st_value;
1fd03b5a
SC		 864 continue;
865 }
866
9b691193
SC		 867 /* When we relax some bytes, the size of our section changes.
868 This affects the layout of next input sections that go in our
869 output section. When the symbol is part of another section that
870 will go in the same output section as the current one, it's
871 final address may now be incorrect (too far). We must let the
872 linker re-compute all section offsets before processing this
873 reloc. Code example:
874
875 Initial Final
876 .sect .text section size = 6 section size = 4
877 jmp foo
878 jmp bar
879 .sect .text.foo_bar output_offset = 6 output_offset = 4
880 foo: rts
881 bar: rts
882
883 If we process the reloc now, the jmp bar is replaced by a
884 relative branch to the initial bar address (output_offset 6). */
885 if (*again && sym_sec != sec
886 && sym_sec->output_section == sec->output_section)
887 {
888 prev_insn_group = 0;
889 prev_insn_branch = 0;
890 continue;
891 }
b34976b6 892
1fd03b5a
SC		 893 value = symval;
894 /* Try to turn a far branch to a near branch. */
895 if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_16
896 && prev_insn_branch)
897 {
898 bfd_vma offset;
899 unsigned char code;
900
901 offset = value - (prev_insn_branch->r_offset
902 + sec->output_section->vma
903 + sec->output_offset + 2);
904
905 /* If the offset is still out of -128..+127 range,
906 leave that far branch unchanged. */
907 if ((offset & 0xff80) != 0 && (offset & 0xff80) != 0xff80)
908 {
909 prev_insn_branch = 0;
910 continue;
911 }
912
913 /* Shrink the branch. */
914 code = bfd_get_8 (abfd, contents + prev_insn_branch->r_offset);
915 if (code == 0x7e)
916 {
917 code = 0x20;
918 bfd_put_8 (abfd, code, contents + prev_insn_branch->r_offset);
196486be 919 bfd_put_8 (abfd, 0xff,
1fd03b5a 920 contents + prev_insn_branch->r_offset + 1);
196486be 921 irel->r_offset = prev_insn_branch->r_offset + 1;
1fd03b5a 922 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
196486be 923 R_M68HC11_PCREL_8);
1fd03b5a 924 m68hc11_elf_relax_delete_bytes (abfd, sec,
196486be 925 irel->r_offset + 1, 1);
1fd03b5a
SC		 926 }
927 else
928 {
929 code ^= 0x1;
930 bfd_put_8 (abfd, code, contents + prev_insn_branch->r_offset);
196486be 931 bfd_put_8 (abfd, 0xff,
1fd03b5a 932 contents + prev_insn_branch->r_offset + 1);
196486be 933 irel->r_offset = prev_insn_branch->r_offset + 1;
1fd03b5a 934 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
196486be 935 R_M68HC11_PCREL_8);
1fd03b5a 936 m68hc11_elf_relax_delete_bytes (abfd, sec,
196486be 937 irel->r_offset + 1, 3);
1fd03b5a
SC		 938 }
939 prev_insn_branch = 0;
b34976b6 940 *again = TRUE;
1fd03b5a
SC		 941 }
942
943 /* Try to turn a 16 bit address into a 8 bit page0 address. */
944 else if (ELF32_R_TYPE (irel->r_info) == (int) R_M68HC11_16
945 && (value & 0xff00) == 0)
946 {
947 unsigned char code;
948 unsigned short offset;
949 struct m68hc11_direct_relax *rinfo;
950
951 prev_insn_branch = 0;
952 offset = bfd_get_16 (abfd, contents + irel->r_offset);
953 offset += value;
954 if ((offset & 0xff00) != 0)
955 {
956 prev_insn_group = 0;
957 continue;
958 }
959
960 if (prev_insn_group)
961 {
eea6121a 962 unsigned long old_sec_size = sec->size;
b34976b6 963
4cc11e76 964 /* Note that we've changed the relocation contents, etc. */
1fd03b5a
SC		 965 elf_section_data (sec)->relocs = internal_relocs;
966 free_relocs = NULL;
967
968 elf_section_data (sec)->this_hdr.contents = contents;
969 free_contents = NULL;
970
1f4c5b47 971 symtab_hdr->contents = (bfd_byte *) isymbuf;
1fd03b5a
SC		 972 free_extsyms = NULL;
973
974 m68hc11_relax_group (abfd, sec, contents, offset,
975 prev_insn_group->r_offset,
976 insn_group_value);
977 irel = prev_insn_group;
978 prev_insn_group = 0;
979 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
980 R_M68HC11_NONE);
eea6121a 981 if (sec->size != old_sec_size)
b34976b6 982 *again = TRUE;
1fd03b5a
SC		 983 continue;
984 }
b34976b6 985
1fd03b5a
SC		 986 /* Get the opcode. */
987 code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
988 rinfo = find_relaxable_insn (code);
989 if (rinfo == 0)
990 {
991 prev_insn_group = 0;
992 continue;
993 }
994
4cc11e76 995 /* Note that we've changed the relocation contents, etc. */
1fd03b5a
SC		 996 elf_section_data (sec)->relocs = internal_relocs;
997 free_relocs = NULL;
998
999 elf_section_data (sec)->this_hdr.contents = contents;
1000 free_contents = NULL;
1001
1f4c5b47 1002 symtab_hdr->contents = (bfd_byte *) isymbuf;
1fd03b5a
SC		 1003 free_extsyms = NULL;
1004
1005 /* Fix the opcode. */
1006 /* printf ("A relaxable case : 0x%02x (%s)\n",
1007 code, rinfo->name); */
1008 bfd_put_8 (abfd, rinfo->direct_code,
1009 contents + irel->r_offset - 1);
1010
1011 /* Delete one byte of data (upper byte of address). */
1012 m68hc11_elf_relax_delete_bytes (abfd, sec, irel->r_offset, 1);
1013
1014 /* Fix the relocation's type. */
1015 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1016 R_M68HC11_8);
1017
9b691193 1018 /* That will change things, so, we should relax again. */
b34976b6 1019 *again = TRUE;
1fd03b5a 1020 }
196486be 1021 else if (ELF32_R_TYPE (irel->r_info) == R_M68HC11_16 && !is_far)
1fd03b5a
SC		 1022 {
1023 unsigned char code;
1024 bfd_vma offset;
1025
1026 prev_insn_branch = 0;
1027 code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
196486be 1028 if (code == 0x7e || code == 0xbd)
1fd03b5a
SC		 1029 {
1030 offset = value - (irel->r_offset
1031 + sec->output_section->vma
1032 + sec->output_offset + 1);
1033 offset += bfd_get_16 (abfd, contents + irel->r_offset);
1034
1035 /* If the offset is still out of -128..+127 range,
1036 leave that far branch unchanged. */
1037 if ((offset & 0xff80) == 0 || (offset & 0xff80) == 0xff80)
1038 {
1039
4cc11e76 1040 /* Note that we've changed the relocation contents, etc. */
1fd03b5a
SC		 1041 elf_section_data (sec)->relocs = internal_relocs;
1042 free_relocs = NULL;
b34976b6 1043
1fd03b5a
SC		 1044 elf_section_data (sec)->this_hdr.contents = contents;
1045 free_contents = NULL;
b34976b6 1046
1f4c5b47 1047 symtab_hdr->contents = (bfd_byte *) isymbuf;
1fd03b5a
SC		 1048 free_extsyms = NULL;
1049
1050 /* Shrink the branch. */
196486be 1051 code = (code == 0x7e) ? 0x20 : 0x8d;
1fd03b5a
SC		 1052 bfd_put_8 (abfd, code,
1053 contents + irel->r_offset - 1);
196486be 1054 bfd_put_8 (abfd, 0xff,
1fd03b5a
SC		 1055 contents + irel->r_offset);
1056 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
196486be 1057 R_M68HC11_PCREL_8);
1fd03b5a
SC		 1058 m68hc11_elf_relax_delete_bytes (abfd, sec,
1059 irel->r_offset + 1, 1);
9b691193 1060 /* That will change things, so, we should relax again. */
b34976b6 1061 *again = TRUE;
1fd03b5a
SC		 1062 }
1063 }
1064 }
1065 prev_insn_branch = 0;
d204f4c0 1066 prev_insn_group = 0;
1fd03b5a
SC		 1067 }
1068
1069 if (free_relocs != NULL)
1070 {
1071 free (free_relocs);
1072 free_relocs = NULL;
1073 }
1074
1075 if (free_contents != NULL)
1076 {
1077 if (! link_info->keep_memory)
1078 free (free_contents);
1079 else
1080 {
1081 /* Cache the section contents for elf_link_input_bfd. */
1082 elf_section_data (sec)->this_hdr.contents = contents;
1083 }
1084 free_contents = NULL;
1085 }
1086
1087 if (free_extsyms != NULL)
1088 {
1089 if (! link_info->keep_memory)
1090 free (free_extsyms);
1091 else
1092 {
1093 /* Cache the symbols for elf_link_input_bfd. */
1f4c5b47 1094 symtab_hdr->contents = (unsigned char *) isymbuf;
1fd03b5a
SC		 1095 }
1096 free_extsyms = NULL;
1097 }
1098
b34976b6 1099 return TRUE;
1fd03b5a
SC		 1100
1101 error_return:
1102 if (free_relocs != NULL)
1103 free (free_relocs);
1104 if (free_contents != NULL)
1105 free (free_contents);
1106 if (free_extsyms != NULL)
1107 free (free_extsyms);
b34976b6 1108 return FALSE;
1fd03b5a
SC		 1109}
1110
1111/* Delete some bytes from a section while relaxing. */
1112
1113static void
0a6a3ebe
SC		 1114m68hc11_elf_relax_delete_bytes (bfd *abfd, asection *sec,
1115 bfd_vma addr, int count)
1fd03b5a
SC		 1116{
1117 Elf_Internal_Shdr *symtab_hdr;
1fd03b5a 1118 unsigned int sec_shndx;
1fd03b5a
SC		 1119 bfd_byte *contents;
1120 Elf_Internal_Rela *irel, *irelend;
1121 bfd_vma toaddr;
1f4c5b47 1122 Elf_Internal_Sym *isymbuf, *isym, *isymend;
1fd03b5a
SC		 1123 struct elf_link_hash_entry **sym_hashes;
1124 struct elf_link_hash_entry **end_hashes;
1125 unsigned int symcount;
1126
1127 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1f4c5b47 1128 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1fd03b5a
SC		 1129
1130 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1131
1132 contents = elf_section_data (sec)->this_hdr.contents;
1133
eea6121a 1134 toaddr = sec->size;
1fd03b5a
SC		 1135
1136 irel = elf_section_data (sec)->relocs;
1137 irelend = irel + sec->reloc_count;
1138
1139 /* Actually delete the bytes. */
1140 memmove (contents + addr, contents + addr + count,
1141 (size_t) (toaddr - addr - count));
1fd03b5a 1142
eea6121a 1143 sec->size -= count;
b34976b6 1144
1fd03b5a
SC		 1145 /* Adjust all the relocs. */
1146 for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++)
1147 {
1148 unsigned char code;
1149 unsigned char offset;
1150 unsigned short raddr;
1151 unsigned long old_offset;
1152 int branch_pos;
1153
1154 old_offset = irel->r_offset;
1155
1156 /* See if this reloc was for the bytes we have deleted, in which
1157 case we no longer care about it. Don't delete relocs which
1158 represent addresses, though. */
1159 if (ELF32_R_TYPE (irel->r_info) != R_M68HC11_RL_JUMP
1160 && irel->r_offset >= addr && irel->r_offset < addr + count)
1161 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1162 R_M68HC11_NONE);
1163
1164 if (ELF32_R_TYPE (irel->r_info) == R_M68HC11_NONE)
1165 continue;
1166
1167 /* Get the new reloc address. */
1168 if ((irel->r_offset > addr
1169 && irel->r_offset < toaddr))
1170 irel->r_offset -= count;
1171
1172 /* If this is a PC relative reloc, see if the range it covers
1173 includes the bytes we have deleted. */
1174 switch (ELF32_R_TYPE (irel->r_info))
1175 {
1176 default:
1177 break;
1178
1179 case R_M68HC11_RL_JUMP:
1180 code = bfd_get_8 (abfd, contents + irel->r_offset);
1181 switch (code)
1182 {
1183 /* jsr and jmp instruction are also marked with RL_JUMP
1184 relocs but no adjustment must be made. */
1185 case 0x7e:
1186 case 0x9d:
1187 case 0xbd:
1188 continue;
1189
1190 case 0x12:
1191 case 0x13:
1192 branch_pos = 3;
1193 raddr = 4;
1194
1195 /* Special case when we translate a brclr N,y into brclr *<addr>
1196 In this case, the 0x18 page2 prefix is removed.
1197 The reloc offset is not modified but the instruction
1198 size is reduced by 1. */
1199 if (old_offset == addr)
1200 raddr++;
1201 break;
1202
1203 case 0x1e:
1204 case 0x1f:
1205 branch_pos = 3;
1206 raddr = 4;
1207 break;
1208
1209 case 0x18:
1210 branch_pos = 4;
1211 raddr = 5;
1212 break;
1213
1214 default:
1215 branch_pos = 1;
1216 raddr = 2;
1217 break;
1218 }
1219 offset = bfd_get_8 (abfd, contents + irel->r_offset + branch_pos);
1220 raddr += old_offset;
1221 raddr += ((unsigned short) offset | ((offset & 0x80) ? 0xff00 : 0));
30491647 1222 if (irel->r_offset < addr && raddr > addr)
1fd03b5a
SC		 1223 {
1224 offset -= count;
1225 bfd_put_8 (abfd, offset, contents + irel->r_offset + branch_pos);
1226 }
1227 else if (irel->r_offset >= addr && raddr <= addr)
1228 {
1229 offset += count;
1230 bfd_put_8 (abfd, offset, contents + irel->r_offset + branch_pos);
1231 }
1232 else
1233 {
1234 /*printf ("Not adjusted 0x%04x [0x%4x 0x%4x]\n", raddr,
1235 irel->r_offset, addr);*/
1236 }
b34976b6 1237
1fd03b5a
SC		 1238 break;
1239 }
1240 }
1241
1242 /* Adjust the local symbols defined in this section. */
1f4c5b47
SC		 1243 isymend = isymbuf + symtab_hdr->sh_info;
1244 for (isym = isymbuf; isym < isymend; isym++)
1fd03b5a 1245 {
1f4c5b47
SC		 1246 if (isym->st_shndx == sec_shndx
1247 && isym->st_value > addr
196486be 1248 && isym->st_value <= toaddr)
1f4c5b47 1249 isym->st_value -= count;
1fd03b5a
SC		 1250 }
1251
1252 /* Now adjust the global symbols defined in this section. */
1253 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1254 - symtab_hdr->sh_info);
1255 sym_hashes = elf_sym_hashes (abfd);
1256 end_hashes = sym_hashes + symcount;
1257 for (; sym_hashes < end_hashes; sym_hashes++)
1258 {
1259 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1260 if ((sym_hash->root.type == bfd_link_hash_defined
1261 || sym_hash->root.type == bfd_link_hash_defweak)
1262 && sym_hash->root.u.def.section == sec
1263 && sym_hash->root.u.def.value > addr
196486be 1264 && sym_hash->root.u.def.value <= toaddr)
1fd03b5a
SC		 1265 {
1266 sym_hash->root.u.def.value -= count;
1267 }
1268 }
1269}
1270
2f89ff8d
L		 1271/* Specific sections:
1272 - The .page0 is a data section that is mapped in [0x0000..0x00FF].
1273 Page0 accesses are faster on the M68HC11. Soft registers used by GCC-m6811
1274 are located in .page0.
3f533aa9 1275 - The .vectors is the section that represents the interrupt
2f89ff8d 1276 vectors. */
b35d266b 1277static const struct bfd_elf_special_section elf32_m68hc11_special_sections[] =
2f89ff8d 1278{
0112cd26
NC		 1279 { STRING_COMMA_LEN (".eeprom"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
1280 { STRING_COMMA_LEN (".page0"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
1281 { STRING_COMMA_LEN (".softregs"), 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
1282 { STRING_COMMA_LEN (".vectors"), 0, SHT_PROGBITS, SHF_ALLOC },
1283 { NULL, 0, 0, 0, 0 }
7f4d3958 1284};
96405e3c 1285\f
60bcf0fa
NC		 1286#define ELF_ARCH bfd_arch_m68hc11
1287#define ELF_MACHINE_CODE EM_68HC11
1288#define ELF_MAXPAGESIZE 0x1000
1289
1290#define TARGET_BIG_SYM bfd_elf32_m68hc11_vec
1291#define TARGET_BIG_NAME "elf32-m68hc11"
1292
1293#define elf_info_to_howto 0
1294#define elf_info_to_howto_rel m68hc11_info_to_howto_rel
1fd03b5a 1295#define bfd_elf32_bfd_relax_section m68hc11_elf_relax_section
1fd03b5a
SC		 1296#define elf_backend_check_relocs elf32_m68hc11_check_relocs
1297#define elf_backend_relocate_section elf32_m68hc11_relocate_section
3a65329d 1298#define elf_backend_add_symbol_hook elf32_m68hc11_add_symbol_hook
60bcf0fa
NC		 1299#define elf_backend_object_p 0
1300#define elf_backend_final_write_processing 0
9b701e44 1301#define elf_backend_can_gc_sections 1
29ef7005 1302#define elf_backend_special_sections elf32_m68hc11_special_sections
3a65329d
SC		 1303
1304#define bfd_elf32_bfd_link_hash_table_create \
1305 m68hc11_elf_bfd_link_hash_table_create
1306#define bfd_elf32_bfd_link_hash_table_free \
1307 m68hc11_elf_bfd_link_hash_table_free
96405e3c
SC		 1308#define bfd_elf32_bfd_merge_private_bfd_data \
1309 _bfd_m68hc11_elf_merge_private_bfd_data
1310#define bfd_elf32_bfd_set_private_flags _bfd_m68hc11_elf_set_private_flags
1311#define bfd_elf32_bfd_print_private_bfd_data \
1312 _bfd_m68hc11_elf_print_private_bfd_data
1313
60bcf0fa 1314#include "elf32-target.h"
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